6867a56a59cf0baec09f6a634e72a2ab7e8d80d8
1 /**
2 * \file sbl_slave_core_boot.c
3 *
4 * \brief This file contain functions related to slave core boot-up.
5 *
6 */
8 /*
9 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include <stdint.h>
46 #include <string.h>
47 #include <ti/csl/csl_types.h>
48 #include <ti/csl/cslr_device.h>
49 #include <ti/csl/hw_types.h>
50 #include <ti/csl/arch/csl_arch.h>
51 #include <ti/drv/uart/UART_stdio.h>
53 #include "sbl_soc.h"
54 #include "sbl_log.h"
55 #include "sbl_soc_cfg.h"
56 #include "sbl_profile.h"
57 #include "sbl_err_trap.h"
58 #include "sbl_sci_client.h"
59 #include "sbl_slave_core_boot.h"
61 #if defined(BOOT_OSPI)
62 #include "sbl_ospi.h"
63 #endif
65 #if defined(BOOT_MMCSD)
66 #include "sbl_mmcsd.h"
67 #endif
69 #if defined(BOOT_UART)
70 #include "sbl_uart.h"
71 #endif
73 #if defined(BOOT_HYPERFLASH)
74 #include "sbl_hyperflash.h"
75 #endif
76 /* ========================================================================== */
77 /* Macros & Typedefs */
78 /* ========================================================================== */
79 #define SBL_DISABLE_MCU_LOCKSTEP (0)
80 #define SBL_ENABLE_MCU_LOCKSTEP (1)
82 /* Don't forget to update parameter OPP of the AVS */
83 /* setup function in SBL_SocLateInit if the CPU freq */
84 /* are changed to a higher or lower operating point */
85 static const sblSlaveCoreInfo_t sbl_slave_core_info[] =
86 {
87 /* MPU1_CPU0 info */
88 {
89 SBL_PROC_ID_MPU1_CPU0,
90 SBL_DEV_ID_MPU1_CPU0,
91 SBL_CLK_ID_MPU1_CPU0,
92 SBL_MPU1_CPU0_FREQ_HZ,
93 },
94 /* MPU1_CPU1 info */
95 {
96 SBL_PROC_ID_MPU1_CPU1,
97 SBL_DEV_ID_MPU1_CPU1,
98 SBL_CLK_ID_MPU1_CPU1,
99 SBL_MPU1_CPU1_FREQ_HZ,
100 },
101 /* MPU2_CPU0 info */
102 {
103 SBL_PROC_ID_MPU2_CPU0,
104 SBL_DEV_ID_MPU2_CPU0,
105 SBL_CLK_ID_MPU2_CPU0,
106 SBL_MPU2_CPU0_FREQ_HZ,
107 },
108 /* MPU2_CPU1 info */
109 {
110 SBL_PROC_ID_MPU2_CPU1,
111 SBL_DEV_ID_MPU2_CPU1,
112 SBL_CLK_ID_MPU2_CPU1,
113 SBL_MPU2_CPU1_FREQ_HZ,
114 },
115 /* MCU1_CPU0 info */
116 {
117 SBL_PROC_ID_MCU1_CPU0,
118 SBL_DEV_ID_MCU1_CPU0,
119 SBL_CLK_ID_MCU1_CPU0,
120 SBL_MCU1_CPU0_FREQ_HZ,
121 },
122 /* MCU1_CPU1 info */
123 {
124 SBL_PROC_ID_MCU1_CPU1,
125 SBL_DEV_ID_MCU1_CPU1,
126 SBL_CLK_ID_MCU1_CPU1,
127 SBL_MCU1_CPU1_FREQ_HZ,
128 },
129 /* MCU2_CPU0 info */
130 {
131 SBL_PROC_ID_MCU2_CPU0,
132 SBL_DEV_ID_MCU2_CPU0,
133 SBL_CLK_ID_MCU2_CPU0,
134 SBL_MCU2_CPU0_FREQ_HZ,
135 },
136 /* MCU2_CPU1 info */
137 {
138 SBL_PROC_ID_MCU2_CPU1,
139 SBL_DEV_ID_MCU2_CPU1,
140 SBL_CLK_ID_MCU2_CPU1,
141 SBL_MCU2_CPU1_FREQ_HZ,
142 },
143 /* MCU3_CPU0 info */
144 {
145 SBL_PROC_ID_MCU3_CPU0,
146 SBL_DEV_ID_MCU3_CPU0,
147 SBL_CLK_ID_MCU3_CPU0,
148 SBL_MCU3_CPU0_FREQ_HZ,
149 },
150 /* MCU3_CPU1 info */
151 {
152 SBL_PROC_ID_MCU3_CPU1,
153 SBL_DEV_ID_MCU3_CPU1,
154 SBL_CLK_ID_MCU3_CPU1,
155 SBL_MCU3_CPU1_FREQ_HZ,
156 },
157 /* DSP1_C66X info */
158 {
159 SBL_PROC_ID_DSP1_C66X,
160 SBL_DEV_ID_DSP1_C66X,
161 SBL_CLK_ID_DSP1_C66X,
162 SBL_DSP1_C66X_FREQ_HZ,
163 },
164 /* DSP2_C66X info */
165 {
166 SBL_PROC_ID_DSP2_C66X,
167 SBL_DEV_ID_DSP2_C66X,
168 SBL_CLK_ID_DSP2_C66X,
169 SBL_DSP2_C66X_FREQ_HZ,
170 },
171 /* DSP1_C7X info */
172 {
173 SBL_PROC_ID_DSP1_C7X,
174 SBL_DEV_ID_DSP1_C7X,
175 SBL_CLK_ID_DSP1_C7X,
176 SBL_DSP1_C7X_FREQ_HZ,
177 },
178 /* DSP2_C7X info */
179 {
180 SBL_PROC_ID_DSP2_C7X,
181 SBL_DEV_ID_DSP2_C7X,
182 SBL_CLK_ID_DSP2_C7X,
183 SBL_DSP2_C7X_FREQ_HZ,
184 },
185 /* M4F Core0 info*/
186 {
187 SBL_PROC_ID_M4F_CPU0,
188 SBL_DEV_ID_M4F_CPU0,
189 SBL_CLK_ID_M4F_CPU0,
190 SBL_M4F_CPU0_FREQ_HZ,
191 }
192 };
194 static const uint32_t SblAtcmAddr[] =
195 {
196 SBL_MCU_ATCM_BASE,
197 SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC,
198 SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC,
199 SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC,
200 SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC,
201 SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
202 };
204 #if !defined(SOC_AM65XX)
205 static const uint32_t SblBtcmAddr[] =
206 {
207 SBL_MCU_BTCM_BASE,
208 SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC,
209 SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC,
210 SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC,
211 SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
212 SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
213 };
214 #endif
215 /* ========================================================================== */
216 /* Internal Functions */
217 /* ========================================================================== */
219 static void SBL_RequestCore(cpu_core_id_t core_id)
220 {
221 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
222 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
223 int32_t status = CSL_EFAIL;
225 #if defined(SOC_AM64X)
226 /* Do not touch the M4 if reset isolation is enabled */
227 uint32_t mmrMagicRegister;
228 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
229 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
230 {
231 return;
232 }
233 #endif
235 if (proc_id != 0xBAD00000)
236 {
237 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
239 status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
240 if (status != CSL_PASS)
241 {
242 SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
243 SblErrLoop(__FILE__, __LINE__);
244 }
245 }
246 #endif
248 return;
249 }
251 static void SBL_RequestAllCores(void)
252 {
253 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
254 cpu_core_id_t core_id;
255 uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
257 SBL_ADD_PROFILE_POINT;
259 for (core_id = 0; core_id < num_cores; core_id++)
260 {
261 SBL_RequestCore(core_id);
262 }
264 SBL_ADD_PROFILE_POINT;
265 #endif
267 return;
268 }
270 static void SBL_ReleaseCore (cpu_core_id_t core_id, uint32_t reqFlag)
271 {
272 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
273 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
274 int32_t status = CSL_EFAIL;
276 #if defined(SOC_AM64X)
277 /* Do not touch the M4 if reset isolation is enabled */
278 uint32_t mmrMagicRegister;
279 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
280 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
281 {
282 return;
283 }
284 #endif
286 if(proc_id != 0xBAD00000)
287 {
288 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
289 status = Sciclient_procBootReleaseProcessor(proc_id, reqFlag, SCICLIENT_SERVICE_WAIT_FOREVER);
291 if (status != CSL_PASS)
292 {
293 SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
294 SblErrLoop(__FILE__, __LINE__);
295 }
296 }
297 #endif
299 return;
300 }
302 static void SBL_ReleaseAllCores(void)
303 {
304 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
305 cpu_core_id_t core_id;
306 uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
308 SBL_ADD_PROFILE_POINT;
310 for (core_id = 0; core_id < num_cores; core_id++)
311 {
312 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
313 }
315 SBL_ADD_PROFILE_POINT;
316 #endif
318 return;
319 }
321 static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo_t *sblCoreInfoPtr)
322 {
323 int32_t status = CSL_EFAIL;
324 struct tisci_msg_proc_get_status_resp cpuStatus;
325 struct tisci_msg_proc_set_config_req proc_set_config_req;
327 SBL_ADD_PROFILE_POINT;
329 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblCoreInfoPtr->tisci_proc_id);
330 status = Sciclient_procBootGetProcessorState(sblCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
331 if (status != CSL_PASS)
332 {
333 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
334 SblErrLoop(__FILE__, __LINE__);
335 }
337 proc_set_config_req.processor_id = cpuStatus.processor_id;
338 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
339 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
340 proc_set_config_req.config_flags_1_set = 0;
341 proc_set_config_req.config_flags_1_clear = 0;
343 if (enableLockStep)
344 {
345 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
346 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
347 }
348 else
349 {
350 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
351 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
352 }
354 SBL_ADD_PROFILE_POINT;
356 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
357 if (status != CSL_PASS)
358 {
359 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
360 }
362 SBL_ADD_PROFILE_POINT;
364 return;
365 }
367 int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
368 {
369 int32_t retval = 0;
370 cpu_core_id_t core_id;
372 SBL_ADD_PROFILE_POINT;
374 /* Initialize the entry point array to 0. */
375 for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
376 pEntry->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
378 /* Request SYSW for control of all cores */
379 SBL_RequestAllCores();
381 SBL_ADD_PROFILE_POINT;
383 #if defined(BOOT_MMCSD)
384 /* MMCSD Boot Mode Image Copy function. */
385 if (SBL_MMCBootImage(pEntry) != E_PASS)
386 #elif defined(BOOT_OSPI)
387 if (SBL_OSPIBootImage(pEntry) != E_PASS)
388 #elif defined(BOOT_UART)
389 if (SBL_UARTBootImage(pEntry) != E_PASS)
390 #elif defined(BOOT_HYPERFLASH)
391 if (SBL_HYPERFLASHBootImage(pEntry) != E_PASS)
392 #endif
393 {
394 retval = E_FAIL;
395 }
397 SBL_ADD_PROFILE_POINT;
399 #if defined(SBL_ENABLE_HLOS_BOOT)
400 /* Ensure all the key MMCSD & Flash memory interfaces are handed off properly, for HLOS control */
401 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MMCSD0);
402 Sciclient_pmSetModuleState(TISCI_DEV_MMCSD0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
403 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MMCSD1);
404 Sciclient_pmSetModuleState(TISCI_DEV_MMCSD1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
405 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_OSPI_0);
406 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_OSPI_0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
407 #if defined(SOC_J721E)
408 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_OSPI_1);
409 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_OSPI_1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
410 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0);
411 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
412 #endif
413 #endif
415 /* Release control of all cores */
416 SBL_ReleaseAllCores();
418 SBL_ADD_PROFILE_POINT;
420 return retval;
421 }
423 /**
424 * \brief SBL_SetupCoreMem function sets up the CPUs internal memory
425 *
426 * \param[in] core_id - CPU ID
427 * \param[in] pAppEntry - Core info struct
428 *
429 * \return none
430 */
431 void SBL_SetupCoreMem(uint32_t core_id)
432 {
433 int32_t status = CSL_EFAIL;
434 uint8_t runLockStep = 0;
435 uint8_t mcuModeConfigured = 0;
436 struct tisci_msg_proc_get_status_resp cpuStatus;
437 struct tisci_msg_proc_set_config_req proc_set_config_req;
438 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
440 SBL_ADD_PROFILE_POINT;
442 #if defined(SOC_AM64X)
443 /* Do not touch the M4 if reset isolation is enabled */
444 uint32_t mmrMagicRegister;
445 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
446 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
447 {
448 return;
449 }
450 #endif
452 /* Remap virtual core-ids if needed */
453 switch (core_id)
454 {
455 case MCU1_SMP_ID:
456 runLockStep = 1;
457 core_id = MCU1_CPU0_ID;
458 break;
459 case MCU2_SMP_ID:
460 runLockStep = 1;
461 core_id = MCU2_CPU0_ID;
462 break;
463 case MCU3_SMP_ID:
464 runLockStep = 1;
465 core_id = MCU3_CPU0_ID;
466 break;
467 default:
468 break;
469 }
471 sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
473 if(runLockStep)
474 {
475 SBL_log(SBL_LOG_MAX, "Detected lockstep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
476 SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
477 mcuModeConfigured = 1;
478 }
480 switch (core_id)
481 {
483 case DSP1_C66X_ID:
484 break;
485 case DSP2_C66X_ID:
486 break;
487 case DSP1_C7X_ID:
488 break;
489 case DSP2_C7X_ID:
490 break;
492 case MCU1_CPU1_ID:
493 case MCU2_CPU1_ID:
494 case MCU3_CPU1_ID:
495 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
496 /* Image for second MCU core present, disable lock step for the cluster */
497 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
498 mcuModeConfigured = 1;
499 /* DOnt break, fall through for enabling TCMs */
500 case MCU1_CPU0_ID:
501 case MCU2_CPU0_ID:
502 case MCU3_CPU0_ID:
503 if (!mcuModeConfigured)
504 {
505 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id, sbl_slave_core_info[core_id].tisci_proc_id);
506 /* Non-SMP image used, disable lock step for the cluster */
507 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id]));
508 }
510 /* Ensure Power is OFF for each core before configuring TCMs */
511 /* SBL running on MCU0, don't fool around with its power */
512 if (core_id != MCU1_CPU0_ID)
513 {
514 if (runLockStep)
515 {
516 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
517 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
518 }
519 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
520 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
521 }
523 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
524 status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
525 if (status != CSL_PASS)
526 {
527 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
528 SblErrLoop(__FILE__, __LINE__);
529 }
531 proc_set_config_req.processor_id = cpuStatus.processor_id;
532 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
533 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
534 proc_set_config_req.config_flags_1_set = 0;
535 proc_set_config_req.config_flags_1_clear = 0;
536 #if defined(SOC_AM65XX)
537 SBL_log(SBL_LOG_MAX, "Restore TCM defaults (ATCM disabled), after reset, for core %d\n", core_id);
538 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
539 #else
540 SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
541 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
542 #endif
543 proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
544 TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
546 #if defined(SOC_J7200) || defined(SOC_AM64X)
547 /* Only need to set mem_init disable bit for MCU1_0 or MCU2_0 (for each cluster) */
548 if ((core_id == MCU1_CPU0_ID) || (core_id == MCU2_CPU0_ID))
549 {
550 SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
551 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
552 }
553 #endif
555 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
556 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
557 if (status != CSL_PASS)
558 {
559 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
560 SblErrLoop(__FILE__, __LINE__);
561 }
563 #if !defined(SOC_AM65XX)
564 /* Only initialize TCMs for Non-AM65xx SoCs. For AM65xx, TCMs must be initialized by the app itself. */
566 /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
567 if (core_id != MCU1_CPU0_ID)
568 {
569 SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
570 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
571 if (status != CSL_PASS)
572 {
573 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
574 SblErrLoop(__FILE__, __LINE__);
575 }
576 }
578 /* SBL running on MCU0, don't fool around with its power & TCMs */
579 if (core_id != MCU1_CPU0_ID)
580 {
581 if (runLockStep)
582 {
583 /* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
584 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
585 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
586 }
587 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
588 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
590 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
591 #if defined(SOC_J7200)
592 /* J7200: ATCM in lock-step is the combined size of both the split-mode ATCMs */
593 if (runLockStep)
594 {
595 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
596 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
597 }
598 else
599 /* Clear the normal size of ATCM for non-lockstep cores */
600 #endif
601 {
602 SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
603 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
604 }
606 #ifndef VLAB_SIM
607 #if defined(SOC_J7200)
608 /* J7200: BTCM in lock-step is the combined size of both the split-mode BTCMs */
609 if (runLockStep)
610 {
611 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
612 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
613 }
614 else
615 /* Clear the normal size of BTCM for non-lockstep cores */
616 #endif
617 {
618 SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
619 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
620 }
621 #else
622 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
623 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
624 #endif
625 }
626 #endif /* #if !defined(SOC_AM65XX) */
627 break;
628 case MPU1_SMP_ID:
629 case MPU1_CPU0_ID:
630 case MPU1_CPU1_ID:
631 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
632 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
633 break;
634 case MPU2_SMP_ID:
635 case MPU2_CPU0_ID:
636 case MPU2_CPU1_ID:
637 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
638 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
639 break;
640 case M4F_CPU0_ID:
641 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
642 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
643 if (status != CSL_PASS)
644 {
645 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
646 SblErrLoop(__FILE__, __LINE__);
647 }
648 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
649 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
650 if (status != CSL_PASS)
651 {
652 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
653 SblErrLoop(__FILE__, __LINE__);
654 }
656 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
657 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
658 if (status != CSL_PASS)
659 {
660 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
661 SblErrLoop(__FILE__, __LINE__);
662 }
663 break;
664 case MPU_SMP_ID:
665 /* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
666 if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
667 {
668 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
669 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
670 }
671 if (SBL_DEV_ID_MPU_CLUSTER1 != 0xBAD00000)
672 {
673 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
674 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
675 }
676 break;
677 default:
678 /* No special memory setup needed */
679 break;
680 }
682 SBL_ADD_PROFILE_POINT;
684 return;
685 }
687 /**
688 * \brief SBL_SlaveCoreBoot function sets the entry point, sets up clocks
689 * and enable to core to start executing from entry point.
690 *
691 * \param core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
692 * freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
693 * pAppEntry = SBL entry point struct
694 * requestCoresFlag = Specify whether cores should be requested/released
695 * from within SBL_SlaveCoreBoot. Accepts the values SBL_REQUEST_CORE
696 * and SBL_DONT_REQUEST_CORE.
697 *
698 **/
699 void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
700 {
701 int32_t status = CSL_EFAIL;
702 struct tisci_msg_proc_set_config_req proc_set_config_req;
703 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
705 SBL_ADD_PROFILE_POINT;
707 #if defined(SOC_AM64X)
708 /* Do not touch the M4 if reset isolation is enabled */
709 uint32_t mmrMagicRegister;
710 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
711 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
712 {
713 return;
714 }
715 #endif
717 #if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
718 /* Skip copy if R5 app entry point is already 0 */
719 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
720 if ((core_id == MCU1_CPU0_ID) &&
721 (pAppEntry->CpuEntryPoint[core_id]) &&
722 (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
723 {
724 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
725 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
726 return;
727 }
728 #endif
730 /* Finished processing images for all cores, start MCU_0 */
731 if ((core_id == MCU1_CPU1_ID) &&
732 (pAppEntry->CpuEntryPoint[core_id] >= SBL_INVALID_ENTRY_ADDR))
733 {
734 /* Display profile logs */
735 SBL_printProfileLog();
737 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
738 /* Branch to start of ATCM */
739 ((void(*)(void))0x0)();
740 }
741 #endif
743 /* Request core */
744 if (requestCoresFlag == SBL_REQUEST_CORE)
745 {
746 SBL_RequestCore(core_id);
747 }
749 /* Set entry point as boot vector */
750 proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
751 proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
752 proc_set_config_req.bootvector_hi = 0x0;
753 proc_set_config_req.config_flags_1_set = 0;
754 proc_set_config_req.config_flags_1_clear = 0;
756 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
757 {
758 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
759 SBL_ADD_PROFILE_POINT;
760 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
761 if (status != CSL_PASS)
762 {
763 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
764 SblErrLoop(__FILE__, __LINE__);
765 }
767 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
768 SBL_ADD_PROFILE_POINT;
769 Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
770 sblSlaveCoreInfoPtr->tisci_clk_id,
771 sblSlaveCoreInfoPtr->slave_clk_freq_hz,
772 TISCI_MSG_FLAG_AOP,
773 SCICLIENT_SERVICE_WAIT_FOREVER);
774 SBL_ADD_PROFILE_POINT;
775 }
776 else
777 {
778 SBL_log(SBL_LOG_MAX, "Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
779 }
780 /* Power down and then power up each core*/
781 switch (core_id)
782 {
783 case MCU1_CPU1_ID:
784 /* Display profile logs */
785 SBL_printProfileLog();
787 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
788 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
789 {
790 /* Skip copy if R5 app entry point is already 0 */
791 if (pAppEntry->CpuEntryPoint[core_id])
792 {
793 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
794 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
795 }
796 }
797 #endif
799 #ifdef SBL_SKIP_MCU_RESET
800 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
801 {
802 #if !defined(SOC_AM65XX)
803 /* Un-halt MCU1_1 core */
804 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
805 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
806 #endif
807 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
808 }
810 /* Release the CPU and branch to app */
811 if (requestCoresFlag == SBL_REQUEST_CORE)
812 {
813 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
814 }
816 /* Start the App - Branch to start of ATCM (0x0) */
817 ((void(*)(void))0x0)();
818 #else
819 /* Request MCU1_0 */
820 if (requestCoresFlag == SBL_REQUEST_CORE)
821 {
822 SBL_RequestCore(core_id - 1);
823 }
825 /**
826 * Reset sequence for cluster running SBL
827 *
828 * The reset sequence for the cluster running SBL has to be done differently from
829 * that of other clusters. More detail is described in comments below, but a high-
830 * level overview of the reset sequence is as follows:
831 *
832 * 1. Processor Boot Wait (holds the queue)
833 * 2. MCU1_1 Enter Reset - (AM65x case: already powered OFF)
834 * 3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
835 * 4. Un-halt MCU1_1 - (AM65x case: Not necessary)
836 * 5. Release control of MCU1_0
837 * 6. Release control of MCU1_1
838 * 7. MCU1_0 Leave Reset - (AM65x case: Power ON)
839 * 8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
840 */
842 /**
843 * Processor Boot Wait
844 *
845 * DMSC will block until a WFI is issued, thus allowing the following commands
846 * to be queued so this cluster may be reset by DMSC (queue length is defined in
847 * "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
848 * were to be issued and executed prior to WFI, the cluster would enter reset and
849 * SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
850 */
851 /* SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0); */
852 status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
853 if (status != CSL_PASS)
854 {
855 SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
856 SblErrLoop(__FILE__, __LINE__);
857 }
859 /**
860 * Both cores enter reset
861 *
862 * It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
863 * MCU1_1 may never ben in a higher functional state than MCU1_0.
864 */
865 #if !defined(SOC_AM65XX)
866 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
867 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
869 /**
870 * Un-halt MCU1_1 (MCU1_0 is not halted)
871 */
872 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
873 #else
874 /* AM65x case (can't use local reset flags): Power down core running SBL */
875 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
876 #endif
878 /**
879 * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
880 */
881 #if !defined(SOC_J721E) && !defined(SOC_J7200)
882 if (requestCoresFlag == SBL_REQUEST_CORE)
883 {
884 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
885 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
886 }
887 #endif
888 /**
889 * MCU1_0 and (optionally) MCU1_1 leave reset
890 *
891 * Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
892 * shall leave reset. Only take MCU1_1 out of reset if an application will be running
893 * on it.
894 */
895 #if !defined(SOC_AM65XX)
896 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
897 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
898 {
899 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
900 }
901 #else
902 /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
903 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
904 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
905 {
906 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
907 }
908 #endif
910 #if defined(SOC_J721E) || defined(SOC_J7200)
911 /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
912 /* This is done at the end as the PM set module state relies on the fact the SBL is the owner of MCU1_0 and MCU1_1 */
913 if (requestCoresFlag == SBL_REQUEST_CORE)
914 {
915 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
916 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
917 }
918 #endif
919 /* Execute a WFI */
920 asm volatile (" wfi");
921 #endif
922 break;
924 case MCU1_CPU0_ID:
925 /* Skip copy if R5 app entry point is already 0 */
926 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
927 if (pAppEntry->CpuEntryPoint[core_id])
928 {
929 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
930 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
931 }
932 #endif
933 break;
934 case MCU2_CPU0_ID:
935 case MCU2_CPU1_ID:
936 case MCU3_CPU0_ID:
937 case MCU3_CPU1_ID:
938 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
939 {
940 /* Skip copy if R5 app entry point is already 0 */
941 if (pAppEntry->CpuEntryPoint[core_id])
942 {
943 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
944 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
945 }
946 SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
947 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
948 if (status != CSL_PASS)
949 {
950 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
951 SblErrLoop(__FILE__, __LINE__);
952 }
953 }
955 /* Release core */
956 if (requestCoresFlag == SBL_REQUEST_CORE)
957 {
958 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
959 }
961 SBL_ADD_PROFILE_POINT;
962 break;
963 case M4F_CPU0_ID:
964 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
965 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
966 if (status != CSL_PASS)
967 {
968 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
969 SblErrLoop(__FILE__, __LINE__);
970 }
972 /* Release core */
973 if (requestCoresFlag == SBL_REQUEST_CORE)
974 {
975 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
976 }
978 SBL_ADD_PROFILE_POINT;
979 break;
980 default:
981 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
982 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
983 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
984 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
986 /* Release core */
987 if (requestCoresFlag == SBL_REQUEST_CORE)
988 {
989 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
990 }
992 SBL_ADD_PROFILE_POINT;
993 break;
994 }
995 }