a468ea7230f1b0b3381b4168ce47abd30f284392
1 /**
2 * \file sbl_slave_core_boot.c
3 *
4 * \brief This file contain functions related to slave core boot-up.
5 *
6 */
8 /*
9 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include <stdint.h>
46 #include <string.h>
47 #include <ti/csl/csl_types.h>
48 #include <ti/csl/cslr_device.h>
49 #include <ti/csl/hw_types.h>
50 #include <ti/csl/arch/csl_arch.h>
51 #include <ti/drv/uart/UART_stdio.h>
53 #include "sbl_soc.h"
54 #include "sbl_log.h"
55 #include "sbl_soc_cfg.h"
56 #include "sbl_profile.h"
57 #include "sbl_err_trap.h"
58 #include "sbl_sci_client.h"
59 #include "sbl_slave_core_boot.h"
61 #if defined(BOOT_OSPI)
62 #include "sbl_ospi.h"
63 #endif
65 #if defined(BOOT_MMCSD)
66 #include "sbl_mmcsd.h"
67 #endif
69 #if defined(BOOT_UART)
70 #include "sbl_uart.h"
71 #endif
73 #if defined(BOOT_HYPERFLASH)
74 #include "sbl_hyperflash.h"
75 #endif
76 /* ========================================================================== */
77 /* Macros & Typedefs */
78 /* ========================================================================== */
79 #define SBL_DISABLE_MCU_LOCKSTEP (0)
80 #define SBL_ENABLE_MCU_LOCKSTEP (1)
82 /* Don't forget to update parameter OPP of the AVS */
83 /* setup function in SBL_SocLateInit if the CPU freq */
84 /* are changed to a higher or lower operating point */
85 static const sblSlaveCoreInfo_t sbl_slave_core_info[] =
86 {
87 /* MPU1_CPU0 info */
88 {
89 SBL_PROC_ID_MPU1_CPU0,
90 SBL_DEV_ID_MPU1_CPU0,
91 SBL_CLK_ID_MPU1_CPU0,
92 SBL_MPU1_CPU0_FREQ_HZ,
93 },
94 /* MPU1_CPU1 info */
95 {
96 SBL_PROC_ID_MPU1_CPU1,
97 SBL_DEV_ID_MPU1_CPU1,
98 SBL_CLK_ID_MPU1_CPU1,
99 SBL_MPU1_CPU1_FREQ_HZ,
100 },
101 /* MPU2_CPU0 info */
102 {
103 SBL_PROC_ID_MPU2_CPU0,
104 SBL_DEV_ID_MPU2_CPU0,
105 SBL_CLK_ID_MPU2_CPU0,
106 SBL_MPU2_CPU0_FREQ_HZ,
107 },
108 /* MPU2_CPU1 info */
109 {
110 SBL_PROC_ID_MPU2_CPU1,
111 SBL_DEV_ID_MPU2_CPU1,
112 SBL_CLK_ID_MPU2_CPU1,
113 SBL_MPU2_CPU1_FREQ_HZ,
114 },
115 /* MCU1_CPU0 info */
116 {
117 SBL_PROC_ID_MCU1_CPU0,
118 SBL_DEV_ID_MCU1_CPU0,
119 SBL_CLK_ID_MCU1_CPU0,
120 SBL_MCU1_CPU0_FREQ_HZ,
121 },
122 /* MCU1_CPU1 info */
123 {
124 SBL_PROC_ID_MCU1_CPU1,
125 SBL_DEV_ID_MCU1_CPU1,
126 SBL_CLK_ID_MCU1_CPU1,
127 SBL_MCU1_CPU1_FREQ_HZ,
128 },
129 /* MCU2_CPU0 info */
130 {
131 SBL_PROC_ID_MCU2_CPU0,
132 SBL_DEV_ID_MCU2_CPU0,
133 SBL_CLK_ID_MCU2_CPU0,
134 SBL_MCU2_CPU0_FREQ_HZ,
135 },
136 /* MCU2_CPU1 info */
137 {
138 SBL_PROC_ID_MCU2_CPU1,
139 SBL_DEV_ID_MCU2_CPU1,
140 SBL_CLK_ID_MCU2_CPU1,
141 SBL_MCU2_CPU1_FREQ_HZ,
142 },
143 /* MCU3_CPU0 info */
144 {
145 SBL_PROC_ID_MCU3_CPU0,
146 SBL_DEV_ID_MCU3_CPU0,
147 SBL_CLK_ID_MCU3_CPU0,
148 SBL_MCU3_CPU0_FREQ_HZ,
149 },
150 /* MCU3_CPU1 info */
151 {
152 SBL_PROC_ID_MCU3_CPU1,
153 SBL_DEV_ID_MCU3_CPU1,
154 SBL_CLK_ID_MCU3_CPU1,
155 SBL_MCU3_CPU1_FREQ_HZ,
156 },
157 /* DSP1_C66X info */
158 {
159 SBL_PROC_ID_DSP1_C66X,
160 SBL_DEV_ID_DSP1_C66X,
161 SBL_CLK_ID_DSP1_C66X,
162 SBL_DSP1_C66X_FREQ_HZ,
163 },
164 /* DSP2_C66X info */
165 {
166 SBL_PROC_ID_DSP2_C66X,
167 SBL_DEV_ID_DSP2_C66X,
168 SBL_CLK_ID_DSP2_C66X,
169 SBL_DSP2_C66X_FREQ_HZ,
170 },
171 /* DSP1_C7X info */
172 {
173 SBL_PROC_ID_DSP1_C7X,
174 SBL_DEV_ID_DSP1_C7X,
175 SBL_CLK_ID_DSP1_C7X,
176 SBL_DSP1_C7X_FREQ_HZ,
177 },
178 /* DSP2_C7X info */
179 {
180 SBL_PROC_ID_DSP2_C7X,
181 SBL_DEV_ID_DSP2_C7X,
182 SBL_CLK_ID_DSP2_C7X,
183 SBL_DSP2_C7X_FREQ_HZ,
184 },
185 /* M4F Core0 info*/
186 {
187 SBL_PROC_ID_M4F_CPU0,
188 SBL_DEV_ID_M4F_CPU0,
189 SBL_CLK_ID_M4F_CPU0,
190 SBL_M4F_CPU0_FREQ_HZ,
191 }
192 };
194 static const uint32_t SblAtcmAddr[] =
195 {
196 SBL_MCU_ATCM_BASE,
197 SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC,
198 SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC,
199 SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC,
200 SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC,
201 SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
202 };
204 static const uint32_t SblBtcmAddr[] =
205 {
206 SBL_MCU_BTCM_BASE,
207 SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC,
208 SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC,
209 SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC,
210 SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
211 SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
212 };
213 /* ========================================================================== */
214 /* Internal Functions */
215 /* ========================================================================== */
217 static void SBL_RequestCore(cpu_core_id_t core_id)
218 {
219 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
220 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
221 int32_t status = CSL_EFAIL;
223 #if defined(SOC_AM64X)
224 /* Do not touch the M4 if reset isolation is enabled */
225 uint32_t mmrMagicRegister;
226 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
227 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
228 {
229 return;
230 }
231 #endif
233 if (proc_id != 0xBAD00000)
234 {
235 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
237 status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
238 if (status != CSL_PASS)
239 {
240 SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
241 SblErrLoop(__FILE__, __LINE__);
242 }
243 }
244 #endif
246 return;
247 }
249 static void SBL_RequestAllCores(void)
250 {
251 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
252 cpu_core_id_t core_id;
253 uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
255 SBL_ADD_PROFILE_POINT;
257 for (core_id = 0; core_id < num_cores; core_id++)
258 {
259 SBL_RequestCore(core_id);
260 }
262 SBL_ADD_PROFILE_POINT;
263 #endif
265 return;
266 }
268 static void SBL_ReleaseCore(cpu_core_id_t core_id)
269 {
270 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
271 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
272 int32_t status = CSL_EFAIL;
274 #if defined(SOC_AM64X)
275 /* Do not touch the M4 if reset isolation is enabled */
276 uint32_t mmrMagicRegister;
277 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
278 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
279 {
280 return;
281 }
282 #endif
284 if(proc_id != 0xBAD00000)
285 {
286 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
287 status = Sciclient_procBootReleaseProcessor(proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
289 if (status != CSL_PASS)
290 {
291 SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
292 SblErrLoop(__FILE__, __LINE__);
293 }
294 }
295 #endif
297 return;
298 }
300 static void SBL_ReleaseAllCores(void)
301 {
302 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
303 cpu_core_id_t core_id;
304 uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
306 SBL_ADD_PROFILE_POINT;
308 for (core_id = 0; core_id < num_cores; core_id++)
309 {
310 SBL_ReleaseCore(core_id);
311 }
313 SBL_ADD_PROFILE_POINT;
314 #endif
316 return;
317 }
319 static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo_t *sblCoreInfoPtr)
320 {
321 int32_t status = CSL_EFAIL;
322 struct tisci_msg_proc_get_status_resp cpuStatus;
323 struct tisci_msg_proc_set_config_req proc_set_config_req;
325 SBL_ADD_PROFILE_POINT;
327 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblCoreInfoPtr->tisci_proc_id);
328 status = Sciclient_procBootGetProcessorState(sblCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
329 if (status != CSL_PASS)
330 {
331 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
332 SblErrLoop(__FILE__, __LINE__);
333 }
335 proc_set_config_req.processor_id = cpuStatus.processor_id;
336 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
337 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
338 proc_set_config_req.config_flags_1_set = 0;
339 proc_set_config_req.config_flags_1_clear = 0;
341 if (enableLockStep)
342 {
343 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
344 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
345 }
346 else
347 {
348 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
349 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
350 }
352 SBL_ADD_PROFILE_POINT;
354 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
355 if (status != CSL_PASS)
356 {
357 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
358 }
360 SBL_ADD_PROFILE_POINT;
362 return;
363 }
365 int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
366 {
367 int32_t retval = 0;
368 cpu_core_id_t core_id;
370 SBL_ADD_PROFILE_POINT;
372 /* Initialize the entry point array to 0. */
373 for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
374 pEntry->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
376 /* Request SYSW for control of all cores */
377 SBL_RequestAllCores();
379 SBL_ADD_PROFILE_POINT;
381 #if defined(BOOT_MMCSD)
382 /* MMCSD Boot Mode Image Copy function. */
383 if (SBL_MMCBootImage(pEntry) != E_PASS)
384 #elif defined(BOOT_OSPI)
385 if (SBL_OSPIBootImage(pEntry) != E_PASS)
386 #elif defined(BOOT_UART)
387 if (SBL_UARTBootImage(pEntry) != E_PASS)
388 #elif defined(BOOT_HYPERFLASH)
389 if (SBL_HYPERFLASHBootImage(pEntry) != E_PASS)
390 #endif
391 {
392 retval = E_FAIL;
393 }
395 SBL_ADD_PROFILE_POINT;
397 #if defined(SBL_ENABLE_HLOS_BOOT)
398 /* Ensure all the key MMCSD & Flash memory interfaces are handed off properly, for HLOS control */
399 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MMCSD0);
400 Sciclient_pmSetModuleState(TISCI_DEV_MMCSD0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
401 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MMCSD1);
402 Sciclient_pmSetModuleState(TISCI_DEV_MMCSD1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
404 #if defined(SOC_J721E)
405 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_OSPI_0);
406 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_OSPI_0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
407 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_OSPI_1);
408 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_OSPI_1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
409 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId: %d \n", TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0);
410 Sciclient_pmSetModuleState(TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
411 #endif
412 #endif
414 /* Release control of all cores */
415 SBL_ReleaseAllCores();
417 SBL_ADD_PROFILE_POINT;
419 return retval;
420 }
422 /**
423 * \brief SBL_SetupCoreMem function sets up the CPUs internal memory
424 *
425 * \param[in] core_id - CPU ID
426 * \param[in] pAppEntry - Core info struct
427 *
428 * \return none
429 */
430 void SBL_SetupCoreMem(uint32_t core_id)
431 {
432 int32_t status = CSL_EFAIL;
433 uint8_t runLockStep = 0;
434 uint8_t mcuModeConfigured = 0;
435 struct tisci_msg_proc_get_status_resp cpuStatus;
436 struct tisci_msg_proc_set_config_req proc_set_config_req;
437 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
439 SBL_ADD_PROFILE_POINT;
441 #if defined(SOC_AM64X)
442 /* Do not touch the M4 if reset isolation is enabled */
443 uint32_t mmrMagicRegister;
444 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
445 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
446 {
447 return;
448 }
449 #endif
451 /* Remap virtual core-ids if needed */
452 switch (core_id)
453 {
454 case MCU1_SMP_ID:
455 runLockStep = 1;
456 core_id = MCU1_CPU0_ID;
457 break;
458 case MCU2_SMP_ID:
459 runLockStep = 1;
460 core_id = MCU2_CPU0_ID;
461 break;
462 case MCU3_SMP_ID:
463 runLockStep = 1;
464 core_id = MCU3_CPU0_ID;
465 break;
466 default:
467 break;
468 }
470 sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
472 if(runLockStep)
473 {
474 SBL_log(SBL_LOG_MAX, "Detected lockstep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
475 SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
476 mcuModeConfigured = 1;
477 }
479 switch (core_id)
480 {
482 case DSP1_C66X_ID:
483 break;
484 case DSP2_C66X_ID:
485 break;
486 case DSP1_C7X_ID:
487 break;
488 case DSP2_C7X_ID:
489 break;
491 case MCU1_CPU1_ID:
492 case MCU2_CPU1_ID:
493 case MCU3_CPU1_ID:
494 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
495 /* Image for second MCU core present, disable lock step for the cluster */
496 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
497 mcuModeConfigured = 1;
498 /* DOnt break, fall through for enabling TCMs */
499 case MCU1_CPU0_ID:
500 case MCU2_CPU0_ID:
501 case MCU3_CPU0_ID:
502 if (!mcuModeConfigured)
503 {
504 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id, sbl_slave_core_info[core_id].tisci_proc_id);
505 /* Non-SMP image used, disable lock step for the cluster */
506 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id]));
507 }
509 /* Ensure Power is OFF for each core before configuring TCMs */
510 /* SBL running on MCU0, don't fool around with its power */
511 if (core_id != MCU1_CPU0_ID)
512 {
513 if (runLockStep)
514 {
515 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
516 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
517 }
518 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
519 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
520 }
522 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
523 status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
524 if (status != CSL_PASS)
525 {
526 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
527 SblErrLoop(__FILE__, __LINE__);
528 }
530 proc_set_config_req.processor_id = cpuStatus.processor_id;
531 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
532 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
533 proc_set_config_req.config_flags_1_set = 0;
534 proc_set_config_req.config_flags_1_clear = 0;
535 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
537 SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
538 proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
539 TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
541 #if defined(SOC_J7200) || defined(SOC_AM64X)
542 /* Only need to set mem_init disable bit for MCU1_0 or MCU2_0 (for each cluster) */
543 if ((core_id == MCU1_CPU0_ID) || (core_id == MCU2_CPU0_ID))
544 {
545 SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
546 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
547 }
548 #endif
550 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
551 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
552 if (status != CSL_PASS)
553 {
554 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
555 SblErrLoop(__FILE__, __LINE__);
556 }
558 /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
559 if (core_id != MCU1_CPU0_ID)
560 {
561 SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
562 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
563 if (status != CSL_PASS)
564 {
565 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
566 SblErrLoop(__FILE__, __LINE__);
567 }
568 }
570 /* SBL running on MCU0, don't fool around with its power & TCMs */
571 if (core_id != MCU1_CPU0_ID)
572 {
573 if (runLockStep)
574 {
575 /* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
576 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
577 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
578 }
579 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
580 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
582 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
583 #if defined(SOC_J7200)
584 /* J7200: ATCM in lock-step is the combined size of both the split-mode ATCMs */
585 if (runLockStep)
586 {
587 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
588 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
589 }
590 else
591 /* Clear the normal size of ATCM for non-lockstep cores */
592 #endif
593 {
594 SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
595 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
596 }
598 #ifndef VLAB_SIM
599 #if defined(SOC_J7200)
600 /* J7200: BTCM in lock-step is the combined size of both the split-mode BTCMs */
601 if (runLockStep)
602 {
603 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
604 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
605 }
606 else
607 /* Clear the normal size of BTCM for non-lockstep cores */
608 #endif
609 {
610 SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
611 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
612 }
613 #else
614 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
615 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
616 #endif
617 }
618 break;
619 case MPU1_SMP_ID:
620 case MPU1_CPU0_ID:
621 case MPU1_CPU1_ID:
622 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
623 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
624 break;
625 case MPU2_SMP_ID:
626 case MPU2_CPU0_ID:
627 case MPU2_CPU1_ID:
628 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
629 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
630 break;
631 case M4F_CPU0_ID:
632 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
633 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
634 if (status != CSL_PASS)
635 {
636 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
637 SblErrLoop(__FILE__, __LINE__);
638 }
639 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
640 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
641 if (status != CSL_PASS)
642 {
643 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
644 SblErrLoop(__FILE__, __LINE__);
645 }
647 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
648 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
649 if (status != CSL_PASS)
650 {
651 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
652 SblErrLoop(__FILE__, __LINE__);
653 }
654 break;
655 case MPU_SMP_ID:
656 /* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
657 if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
658 {
659 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
660 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
661 }
662 if (SBL_DEV_ID_MPU_CLUSTER1 != 0xBAD00000)
663 {
664 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
665 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
666 }
667 break;
668 default:
669 /* No special memory setup needed */
670 break;
671 }
673 SBL_ADD_PROFILE_POINT;
675 return;
676 }
678 /**
679 * \brief SBL_SlaveCoreBoot function sets the entry point, sets up clocks
680 * and enable to core to start executing from entry point.
681 *
682 * \param core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
683 * freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
684 * pAppEntry = SBL entry point struct
685 * requestCoresFlag = Specify whether cores should be requested/released
686 * from within SBL_SlaveCoreBoot. Accepts the values SBL_REQUEST_CORE
687 * and SBL_DONT_REQUEST_CORE.
688 *
689 **/
690 void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
691 {
692 int32_t status = CSL_EFAIL;
693 struct tisci_msg_proc_set_config_req proc_set_config_req;
694 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
696 SBL_ADD_PROFILE_POINT;
698 #if defined(SOC_AM64X)
699 /* Do not touch the M4 if reset isolation is enabled */
700 uint32_t mmrMagicRegister;
701 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
702 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
703 {
704 return;
705 }
706 #endif
708 #if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
709 /* Skip copy if R5 app entry point is already 0 */
710 if ((core_id == MCU1_CPU0_ID) &&
711 (pAppEntry->CpuEntryPoint[core_id]) &&
712 (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
713 {
714 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
715 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
716 return;
717 }
719 /* Finished processing images for all cores, start MCU_0 */
720 if ((core_id == MCU1_CPU1_ID) &&
721 (pAppEntry->CpuEntryPoint[core_id] >= SBL_INVALID_ENTRY_ADDR))
722 {
723 /* Display profile logs */
724 SBL_printProfileLog();
726 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
727 /* Branch to start of ATCM */
728 ((void(*)(void))0x0)();
729 }
730 #endif
732 /* Request core */
733 if (requestCoresFlag == SBL_REQUEST_CORE)
734 {
735 SBL_RequestCore(core_id);
736 }
738 /* Set entry point as boot vector */
739 proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
740 proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
741 proc_set_config_req.bootvector_hi = 0x0;
742 proc_set_config_req.config_flags_1_set = 0;
743 proc_set_config_req.config_flags_1_clear = 0;
745 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
746 {
747 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
748 SBL_ADD_PROFILE_POINT;
749 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
750 if (status != CSL_PASS)
751 {
752 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
753 SblErrLoop(__FILE__, __LINE__);
754 }
756 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
757 SBL_ADD_PROFILE_POINT;
758 Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
759 sblSlaveCoreInfoPtr->tisci_clk_id,
760 sblSlaveCoreInfoPtr->slave_clk_freq_hz,
761 TISCI_MSG_FLAG_AOP,
762 SCICLIENT_SERVICE_WAIT_FOREVER);
763 SBL_ADD_PROFILE_POINT;
764 }
765 else
766 {
767 SBL_log(SBL_LOG_MAX, "Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
768 }
769 /* Power down and then power up each core*/
770 switch (core_id)
771 {
772 case MCU1_CPU1_ID:
773 /* Display profile logs */
774 SBL_printProfileLog();
776 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
777 {
778 /* Skip copy if R5 app entry point is already 0 */
779 if (pAppEntry->CpuEntryPoint[core_id])
780 {
781 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
782 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
783 }
784 }
786 #ifdef SBL_SKIP_MCU_RESET
787 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
788 {
789 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
790 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
791 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
792 }
794 /* Release the CPU and branch to app */
795 if (requestCoresFlag == SBL_REQUEST_CORE)
796 {
797 SBL_ReleaseCore(core_id);
798 }
800 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
801 /* Branch to start of ATCM */
802 ((void(*)(void))0x0)();
803 #else
804 /* Request MCU1_0 */
805 if (requestCoresFlag == SBL_REQUEST_CORE)
806 {
807 SBL_RequestCore(core_id - 1);
808 }
810 #if defined(SOC_AM65XX)
811 /**
812 * AM65x special case: Un-halt MCU1_1 early and let it run to "wfi" so that SYSFW can power down the cluster (once MCU1_0 is also in "wfi")
813 * NOTE: if MCU1_1 doesn't get to wfi/wfe before powering down the core, then R5 cluster won't do proper power down & up.
814 */
815 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
816 #endif
817 /**
818 * Reset sequence for cluster running SBL
819 *
820 * The reset sequence for the cluster running SBL has to be done differently from
821 * that of other clusters. More detail is described in comments below, but a high-
822 * level overview of the reset sequence is as follows:
823 *
824 * 1. Processor Boot Wait (holds the queue)
825 * 2. MCU1_1 Enter Reset - (AM65x case: Power OFF)
826 * 3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
827 * 4. Un-halt MCU1_1 - (AM65x case: already did this earlier)
828 * 5. Release control of MCU1_0
829 * 6. Release control of MCU1_1
830 * 7. MCU1_0 Leave Reset - (AM65x case: Power ON)
831 * 8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
832 */
834 /**
835 * Processor Boot Wait
836 *
837 * DMSC will block until a WFI is issued, thus allowing the following commands
838 * to be queued so this cluster may be reset by DMSC (queue length is defined in
839 * "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
840 * were to be issued and executed prior to WFI, the cluster would enter reset and
841 * SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
842 */
843 SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0);
844 status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
845 if (status != CSL_PASS)
846 {
847 SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
848 SblErrLoop(__FILE__, __LINE__);
849 }
851 /**
852 * Both cores enter reset
853 *
854 * It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
855 * MCU1_1 may never ben in a higher functional state than MCU1_0.
856 */
857 #if !defined(SOC_AM65XX)
858 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
859 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
861 /**
862 * Un-halt MCU1_1 (MCU1_0 is not halted)
863 */
864 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
865 #else
866 /* AM65x case (can't use local reset flags): Power down both cores */
867 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
868 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
869 #endif
871 /**
872 * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
873 */
874 if (requestCoresFlag == SBL_REQUEST_CORE)
875 {
876 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
877 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
878 }
880 /**
881 * MCU1_0 and (optionally) MCU1_1 leave reset
882 *
883 * Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
884 * shall leave reset. Only take MCU1_1 out of reset if an application will be running
885 * on it.
886 */
887 #if !defined(SOC_AM65XX)
888 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
889 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
890 {
891 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
892 }
893 #else
894 /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
895 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
896 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
897 {
898 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
899 }
900 #endif
902 /* Execute a WFI */
903 asm volatile (" wfi");
904 #endif
905 break;
907 case MCU1_CPU0_ID:
908 /* Skip copy if R5 app entry point is already 0 */
909 if (pAppEntry->CpuEntryPoint[core_id])
910 {
911 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
912 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
913 }
914 break;
915 case MCU2_CPU0_ID:
916 case MCU2_CPU1_ID:
917 case MCU3_CPU0_ID:
918 case MCU3_CPU1_ID:
919 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
920 {
921 /* Skip copy if R5 app entry point is already 0 */
922 if (pAppEntry->CpuEntryPoint[core_id])
923 {
924 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
925 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
926 }
927 SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
928 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
929 if (status != CSL_PASS)
930 {
931 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
932 SblErrLoop(__FILE__, __LINE__);
933 }
934 }
936 /* Release core */
937 if (requestCoresFlag == SBL_REQUEST_CORE)
938 {
939 SBL_ReleaseCore(core_id);
940 }
942 SBL_ADD_PROFILE_POINT;
943 break;
944 case M4F_CPU0_ID:
945 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
946 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
947 if (status != CSL_PASS)
948 {
949 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
950 SblErrLoop(__FILE__, __LINE__);
951 }
953 /* Release core */
954 if (requestCoresFlag == SBL_REQUEST_CORE)
955 {
956 SBL_ReleaseCore(core_id);
957 }
959 SBL_ADD_PROFILE_POINT;
960 break;
961 default:
962 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
963 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
964 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
965 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
967 /* Release core */
968 if (requestCoresFlag == SBL_REQUEST_CORE)
969 {
970 SBL_ReleaseCore(core_id);
971 }
973 SBL_ADD_PROFILE_POINT;
974 break;
975 }
976 }