b7d5773b12ebbb88ce41b3576958563b457a59d9
1 /**
2 * \file sbl_slave_core_boot.c
3 *
4 * \brief This file contain functions related to slave core boot-up.
5 *
6 */
8 /*
9 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include <stdint.h>
46 #include <string.h>
47 #include <ti/csl/csl_types.h>
48 #include <ti/csl/cslr_device.h>
49 #include <ti/csl/hw_types.h>
50 #include <ti/csl/arch/csl_arch.h>
51 #include <ti/drv/uart/UART_stdio.h>
53 #include "sbl_soc.h"
54 #include "sbl_log.h"
55 #include "sbl_soc_cfg.h"
56 #include "sbl_profile.h"
57 #include "sbl_err_trap.h"
58 #include "sbl_sci_client.h"
59 #include "sbl_slave_core_boot.h"
61 #if defined(BOOT_OSPI)
62 #include "sbl_ospi.h"
63 #endif
65 #if defined(BOOT_MMCSD)
66 #include "sbl_mmcsd.h"
67 #endif
69 #if defined(BOOT_UART)
70 #include "sbl_uart.h"
71 #endif
73 #if defined(BOOT_HYPERFLASH)
74 #include "sbl_hyperflash.h"
75 #endif
76 /* ========================================================================== */
77 /* Macros & Typedefs */
78 /* ========================================================================== */
79 #define SBL_DISABLE_MCU_LOCKSTEP (0)
80 #define SBL_ENABLE_MCU_LOCKSTEP (1)
82 /* Don't forget to update parameter OPP of the AVS */
83 /* setup function in SBL_SocLateInit if the CPU freq */
84 /* are changed to a higher or lower operating point */
85 static const sblSlaveCoreInfo_t sbl_slave_core_info[] =
86 {
87 /* MPU1_CPU0 info */
88 {
89 SBL_PROC_ID_MPU1_CPU0,
90 SBL_DEV_ID_MPU1_CPU0,
91 SBL_CLK_ID_MPU1_CPU0,
92 SBL_MPU1_CPU0_FREQ_HZ,
93 },
94 /* MPU1_CPU1 info */
95 {
96 SBL_PROC_ID_MPU1_CPU1,
97 SBL_DEV_ID_MPU1_CPU1,
98 SBL_CLK_ID_MPU1_CPU1,
99 SBL_MPU1_CPU1_FREQ_HZ,
100 },
101 /* MPU2_CPU0 info */
102 {
103 SBL_PROC_ID_MPU2_CPU0,
104 SBL_DEV_ID_MPU2_CPU0,
105 SBL_CLK_ID_MPU2_CPU0,
106 SBL_MPU2_CPU0_FREQ_HZ,
107 },
108 /* MPU2_CPU1 info */
109 {
110 SBL_PROC_ID_MPU2_CPU1,
111 SBL_DEV_ID_MPU2_CPU1,
112 SBL_CLK_ID_MPU2_CPU1,
113 SBL_MPU2_CPU1_FREQ_HZ,
114 },
115 /* MCU1_CPU0 info */
116 {
117 SBL_PROC_ID_MCU1_CPU0,
118 SBL_DEV_ID_MCU1_CPU0,
119 SBL_CLK_ID_MCU1_CPU0,
120 SBL_MCU1_CPU0_FREQ_HZ,
121 },
122 /* MCU1_CPU1 info */
123 {
124 SBL_PROC_ID_MCU1_CPU1,
125 SBL_DEV_ID_MCU1_CPU1,
126 SBL_CLK_ID_MCU1_CPU1,
127 SBL_MCU1_CPU1_FREQ_HZ,
128 },
129 /* MCU2_CPU0 info */
130 {
131 SBL_PROC_ID_MCU2_CPU0,
132 SBL_DEV_ID_MCU2_CPU0,
133 SBL_CLK_ID_MCU2_CPU0,
134 SBL_MCU2_CPU0_FREQ_HZ,
135 },
136 /* MCU2_CPU1 info */
137 {
138 SBL_PROC_ID_MCU2_CPU1,
139 SBL_DEV_ID_MCU2_CPU1,
140 SBL_CLK_ID_MCU2_CPU1,
141 SBL_MCU2_CPU1_FREQ_HZ,
142 },
143 /* MCU3_CPU0 info */
144 {
145 SBL_PROC_ID_MCU3_CPU0,
146 SBL_DEV_ID_MCU3_CPU0,
147 SBL_CLK_ID_MCU3_CPU0,
148 SBL_MCU3_CPU0_FREQ_HZ,
149 },
150 /* MCU3_CPU1 info */
151 {
152 SBL_PROC_ID_MCU3_CPU1,
153 SBL_DEV_ID_MCU3_CPU1,
154 SBL_CLK_ID_MCU3_CPU1,
155 SBL_MCU3_CPU1_FREQ_HZ,
156 },
157 /* DSP1_C66X info */
158 {
159 SBL_PROC_ID_DSP1_C66X,
160 SBL_DEV_ID_DSP1_C66X,
161 SBL_CLK_ID_DSP1_C66X,
162 SBL_DSP1_C66X_FREQ_HZ,
163 },
164 /* DSP2_C66X info */
165 {
166 SBL_PROC_ID_DSP2_C66X,
167 SBL_DEV_ID_DSP2_C66X,
168 SBL_CLK_ID_DSP2_C66X,
169 SBL_DSP2_C66X_FREQ_HZ,
170 },
171 /* DSP1_C7X info */
172 {
173 SBL_PROC_ID_DSP1_C7X,
174 SBL_DEV_ID_DSP1_C7X,
175 SBL_CLK_ID_DSP1_C7X,
176 SBL_DSP1_C7X_FREQ_HZ,
177 },
178 /* DSP2_C7X info */
179 {
180 SBL_PROC_ID_DSP2_C7X,
181 SBL_DEV_ID_DSP2_C7X,
182 SBL_CLK_ID_DSP2_C7X,
183 SBL_DSP2_C7X_FREQ_HZ,
184 },
185 /* M4F Core0 info*/
186 {
187 SBL_PROC_ID_M4F_CPU0,
188 SBL_DEV_ID_M4F_CPU0,
189 SBL_CLK_ID_M4F_CPU0,
190 SBL_M4F_CPU0_FREQ_HZ,
191 }
192 };
194 static const uint32_t SblAtcmAddr[] =
195 {
196 SBL_MCU_ATCM_BASE,
197 SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC,
198 SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC,
199 SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC,
200 SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC,
201 SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
202 };
204 #if !defined(SOC_AM65XX)
205 static const uint32_t SblBtcmAddr[] =
206 {
207 SBL_MCU_BTCM_BASE,
208 SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC,
209 SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC,
210 SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC,
211 SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
212 SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
213 };
214 #endif
215 /* ========================================================================== */
216 /* Internal Functions */
217 /* ========================================================================== */
219 static void SBL_RequestCore(cpu_core_id_t core_id)
220 {
221 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
222 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
223 int32_t status = CSL_EFAIL;
225 #if defined(SOC_AM64X)
226 /* Do not touch the M4 if reset isolation is enabled */
227 uint32_t mmrMagicRegister;
228 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
229 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
230 {
231 return;
232 }
233 #endif
235 if (proc_id != 0xBAD00000)
236 {
237 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
239 status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
240 if (status != CSL_PASS)
241 {
242 SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
243 SblErrLoop(__FILE__, __LINE__);
244 }
245 }
246 #endif
248 return;
249 }
251 static void SBL_RequestAllCores(void)
252 {
253 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
254 cpu_core_id_t core_id;
255 uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
257 SBL_ADD_PROFILE_POINT;
259 for (core_id = 0; core_id < num_cores; core_id++)
260 {
261 SBL_RequestCore(core_id);
262 }
264 SBL_ADD_PROFILE_POINT;
265 #endif
267 return;
268 }
270 static void SBL_ReleaseCore (cpu_core_id_t core_id, uint32_t reqFlag)
271 {
272 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
273 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
274 int32_t status = CSL_EFAIL;
276 #if defined(SOC_AM64X)
277 /* Do not touch the M4 if reset isolation is enabled */
278 uint32_t mmrMagicRegister;
279 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
280 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
281 {
282 return;
283 }
284 #endif
286 if(proc_id != 0xBAD00000)
287 {
288 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
289 status = Sciclient_procBootReleaseProcessor(proc_id, reqFlag, SCICLIENT_SERVICE_WAIT_FOREVER);
291 if (status != CSL_PASS)
292 {
293 SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
294 SblErrLoop(__FILE__, __LINE__);
295 }
296 }
297 #endif
299 return;
300 }
302 static void SBL_ReleaseAllCores(void)
303 {
304 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
305 cpu_core_id_t core_id;
306 uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
308 SBL_ADD_PROFILE_POINT;
310 for (core_id = 0; core_id < num_cores; core_id++)
311 {
312 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
313 }
315 SBL_ADD_PROFILE_POINT;
316 #endif
318 return;
319 }
321 static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo_t *sblCoreInfoPtr)
322 {
323 int32_t status = CSL_EFAIL;
324 struct tisci_msg_proc_get_status_resp cpuStatus;
325 struct tisci_msg_proc_set_config_req proc_set_config_req;
327 SBL_ADD_PROFILE_POINT;
329 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblCoreInfoPtr->tisci_proc_id);
330 status = Sciclient_procBootGetProcessorState(sblCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
331 if (status != CSL_PASS)
332 {
333 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
334 SblErrLoop(__FILE__, __LINE__);
335 }
337 proc_set_config_req.processor_id = cpuStatus.processor_id;
338 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
339 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
340 proc_set_config_req.config_flags_1_set = 0;
341 proc_set_config_req.config_flags_1_clear = 0;
343 if (enableLockStep)
344 {
345 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
346 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
347 }
348 else
349 {
350 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
351 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
352 }
354 SBL_ADD_PROFILE_POINT;
356 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
357 if (status != CSL_PASS)
358 {
359 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
360 }
362 SBL_ADD_PROFILE_POINT;
364 return;
365 }
367 int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
368 {
369 int32_t retval = 0;
370 cpu_core_id_t core_id;
372 SBL_ADD_PROFILE_POINT;
374 /* Initialize the entry point array to 0. */
375 for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
376 pEntry->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
378 /* Request SYSW for control of all cores */
379 SBL_RequestAllCores();
381 SBL_ADD_PROFILE_POINT;
383 #if defined(BOOT_MMCSD)
384 /* MMCSD Boot Mode Image Copy function. */
385 if (SBL_MMCBootImage(pEntry) != E_PASS)
386 #elif defined(BOOT_OSPI)
387 if (SBL_OSPIBootImage(pEntry) != E_PASS)
388 #elif defined(BOOT_UART)
389 if (SBL_UARTBootImage(pEntry) != E_PASS)
390 #elif defined(BOOT_HYPERFLASH)
391 if (SBL_HYPERFLASHBootImage(pEntry) != E_PASS)
392 #endif
393 {
394 retval = E_FAIL;
395 }
397 SBL_ADD_PROFILE_POINT;
399 /* Release control of all cores */
400 SBL_ReleaseAllCores();
402 SBL_ADD_PROFILE_POINT;
404 return retval;
405 }
407 /**
408 * \brief SBL_SetupCoreMem function sets up the CPUs internal memory
409 *
410 * \param[in] core_id - CPU ID
411 * \param[in] pAppEntry - Core info struct
412 *
413 * \return none
414 */
415 void SBL_SetupCoreMem(uint32_t core_id)
416 {
417 int32_t status = CSL_EFAIL;
418 uint8_t runLockStep = 0;
419 uint8_t mcuModeConfigured = 0;
420 struct tisci_msg_proc_get_status_resp cpuStatus;
421 struct tisci_msg_proc_set_config_req proc_set_config_req;
422 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
424 SBL_ADD_PROFILE_POINT;
426 #if defined(SOC_AM64X)
427 /* Do not touch the M4 if reset isolation is enabled */
428 uint32_t mmrMagicRegister;
429 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
430 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
431 {
432 return;
433 }
434 #endif
436 /* Remap virtual core-ids if needed */
437 switch (core_id)
438 {
439 case MCU1_SMP_ID:
440 runLockStep = 1;
441 core_id = MCU1_CPU0_ID;
442 break;
443 case MCU2_SMP_ID:
444 runLockStep = 1;
445 core_id = MCU2_CPU0_ID;
446 break;
447 case MCU3_SMP_ID:
448 runLockStep = 1;
449 core_id = MCU3_CPU0_ID;
450 break;
451 default:
452 break;
453 }
455 sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
457 if(runLockStep)
458 {
459 SBL_log(SBL_LOG_MAX, "Detected lockstep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
460 SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
461 mcuModeConfigured = 1;
462 }
464 switch (core_id)
465 {
467 case DSP1_C66X_ID:
468 break;
469 case DSP2_C66X_ID:
470 break;
471 case DSP1_C7X_ID:
472 break;
473 case DSP2_C7X_ID:
474 break;
476 case MCU1_CPU1_ID:
477 case MCU2_CPU1_ID:
478 case MCU3_CPU1_ID:
479 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
480 /* Image for second MCU core present, disable lock step for the cluster */
481 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
482 mcuModeConfigured = 1;
483 /* DOnt break, fall through for enabling TCMs */
484 case MCU1_CPU0_ID:
485 case MCU2_CPU0_ID:
486 case MCU3_CPU0_ID:
487 if (!mcuModeConfigured)
488 {
489 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id, sbl_slave_core_info[core_id].tisci_proc_id);
490 /* Non-SMP image used, disable lock step for the cluster */
491 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id]));
492 }
494 /* Ensure Power is OFF for each core before configuring TCMs */
495 /* SBL running on MCU0, don't fool around with its power */
496 if (core_id != MCU1_CPU0_ID)
497 {
498 if (runLockStep)
499 {
500 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
501 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
502 }
503 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
504 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
505 }
507 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
508 status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
509 if (status != CSL_PASS)
510 {
511 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
512 SblErrLoop(__FILE__, __LINE__);
513 }
515 proc_set_config_req.processor_id = cpuStatus.processor_id;
516 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
517 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
518 proc_set_config_req.config_flags_1_set = 0;
519 proc_set_config_req.config_flags_1_clear = 0;
520 #if defined(SOC_AM65XX)
521 SBL_log(SBL_LOG_MAX, "Restore TCM defaults (ATCM disabled), after reset, for core %d\n", core_id);
522 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
523 #else
524 SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
525 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
526 #endif
527 proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
528 TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
530 #if defined(SOC_J7200) || defined(SOC_AM64X)
531 /* Only need to set mem_init disable bit for MCU1_0 or MCU2_0 (for each cluster) */
532 if ((core_id == MCU1_CPU0_ID) || (core_id == MCU2_CPU0_ID))
533 {
534 SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
535 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
536 }
537 #endif
539 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
540 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
541 if (status != CSL_PASS)
542 {
543 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
544 SblErrLoop(__FILE__, __LINE__);
545 }
547 #if !defined(SOC_AM65XX)
548 /* Only initialize TCMs for Non-AM65xx SoCs. For AM65xx, TCMs must be initialized by the app itself. */
550 /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
551 if (core_id != MCU1_CPU0_ID)
552 {
553 SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
554 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
555 if (status != CSL_PASS)
556 {
557 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
558 SblErrLoop(__FILE__, __LINE__);
559 }
560 }
562 /* SBL running on MCU0, don't fool around with its power & TCMs */
563 if (core_id != MCU1_CPU0_ID)
564 {
565 uint32_t atcm_size = sblAtcmSize();
566 uint32_t btcm_size = sblBtcmSize();
568 if (runLockStep)
569 {
570 /* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
571 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
572 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
573 }
574 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
575 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
577 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
578 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
579 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, atcm_size);
581 #ifndef VLAB_SIM
582 SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
583 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, btcm_size);
584 #else
585 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
586 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
587 #endif
588 }
589 #endif /* #if !defined(SOC_AM65XX) */
590 break;
591 case MPU1_SMP_ID:
592 case MPU1_CPU0_ID:
593 case MPU1_CPU1_ID:
594 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
595 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
596 break;
597 case MPU2_SMP_ID:
598 case MPU2_CPU0_ID:
599 case MPU2_CPU1_ID:
600 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
601 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
602 break;
603 case M4F_CPU0_ID:
604 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
605 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
606 if (status != CSL_PASS)
607 {
608 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
609 SblErrLoop(__FILE__, __LINE__);
610 }
611 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
612 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
613 if (status != CSL_PASS)
614 {
615 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
616 SblErrLoop(__FILE__, __LINE__);
617 }
619 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
620 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
621 if (status != CSL_PASS)
622 {
623 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
624 SblErrLoop(__FILE__, __LINE__);
625 }
626 break;
627 case MPU_SMP_ID:
628 /* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
629 if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
630 {
631 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
632 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
633 }
634 if (SBL_DEV_ID_MPU_CLUSTER1 != 0xBAD00000)
635 {
636 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
637 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
638 }
639 break;
640 default:
641 /* No special memory setup needed */
642 break;
643 }
645 SBL_ADD_PROFILE_POINT;
647 return;
648 }
650 /**
651 * \brief SBL_SlaveCoreBoot function sets the entry point, sets up clocks
652 * and enable to core to start executing from entry point.
653 *
654 * \param core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
655 * freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
656 * pAppEntry = SBL entry point struct
657 * requestCoresFlag = Specify whether cores should be requested/released
658 * from within SBL_SlaveCoreBoot. Accepts the values SBL_REQUEST_CORE
659 * and SBL_DONT_REQUEST_CORE.
660 *
661 **/
662 void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
663 {
664 int32_t status = CSL_EFAIL;
665 struct tisci_msg_proc_set_config_req proc_set_config_req;
666 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
668 SBL_ADD_PROFILE_POINT;
670 #if defined(SOC_AM64X)
671 /* Do not touch the M4 if reset isolation is enabled */
672 uint32_t mmrMagicRegister;
673 mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
674 if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
675 {
676 return;
677 }
678 #endif
680 #if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
681 /* Skip copy if R5 app entry point is already 0 */
682 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
683 if ((core_id == MCU1_CPU0_ID) &&
684 (pAppEntry->CpuEntryPoint[core_id]) &&
685 (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
686 {
687 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
688 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
689 return;
690 }
691 #endif
693 /* Finished processing images for all cores, start MCU_0 */
694 if ((core_id == MCU1_CPU1_ID) &&
695 (pAppEntry->CpuEntryPoint[core_id] >= SBL_INVALID_ENTRY_ADDR))
696 {
697 /* Display profile logs */
698 SBL_printProfileLog();
700 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
701 /* Branch to start of ATCM */
702 ((void(*)(void))0x0)();
703 }
704 #endif
706 /* Request core */
707 if (requestCoresFlag == SBL_REQUEST_CORE)
708 {
709 SBL_RequestCore(core_id);
710 }
712 /* Set entry point as boot vector */
713 proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
714 proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
715 proc_set_config_req.bootvector_hi = 0x0;
716 proc_set_config_req.config_flags_1_set = 0;
717 proc_set_config_req.config_flags_1_clear = 0;
719 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
720 {
721 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
722 SBL_ADD_PROFILE_POINT;
723 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
724 if (status != CSL_PASS)
725 {
726 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
727 SblErrLoop(__FILE__, __LINE__);
728 }
730 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
731 SBL_ADD_PROFILE_POINT;
732 Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
733 sblSlaveCoreInfoPtr->tisci_clk_id,
734 sblSlaveCoreInfoPtr->slave_clk_freq_hz,
735 TISCI_MSG_FLAG_AOP,
736 SCICLIENT_SERVICE_WAIT_FOREVER);
737 SBL_ADD_PROFILE_POINT;
738 }
739 else
740 {
741 SBL_log(SBL_LOG_MAX, "Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
742 }
743 /* Power down and then power up each core*/
744 switch (core_id)
745 {
746 case MCU1_CPU1_ID:
747 /* Display profile logs */
748 SBL_printProfileLog();
750 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
751 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
752 {
753 /* Skip copy if R5 app entry point is already 0 */
754 if (pAppEntry->CpuEntryPoint[core_id])
755 {
756 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
757 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
758 }
759 }
760 #endif
762 #ifdef SBL_SKIP_MCU_RESET
763 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
764 {
765 #if !defined(SOC_AM65XX)
766 /* Un-halt MCU1_1 core */
767 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
768 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
769 #endif
770 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
771 }
773 /* Release the CPU and branch to app */
774 if (requestCoresFlag == SBL_REQUEST_CORE)
775 {
776 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
777 }
779 /* Start the App - Branch to start of ATCM (0x0) */
780 ((void(*)(void))0x0)();
781 #else
782 /* Request MCU1_0 */
783 if (requestCoresFlag == SBL_REQUEST_CORE)
784 {
785 SBL_RequestCore(core_id - 1);
786 }
788 /**
789 * Reset sequence for cluster running SBL
790 *
791 * The reset sequence for the cluster running SBL has to be done differently from
792 * that of other clusters. More detail is described in comments below, but a high-
793 * level overview of the reset sequence is as follows:
794 *
795 * 1. Processor Boot Wait (holds the queue)
796 * 2. MCU1_1 Enter Reset - (AM65x case: already powered OFF)
797 * 3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
798 * 4. Un-halt MCU1_1 - (AM65x case: Not necessary)
799 * 5. Release control of MCU1_0
800 * 6. Release control of MCU1_1
801 * 7. MCU1_0 Leave Reset - (AM65x case: Power ON)
802 * 8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
803 */
805 /**
806 * Processor Boot Wait
807 *
808 * DMSC will block until a WFI is issued, thus allowing the following commands
809 * to be queued so this cluster may be reset by DMSC (queue length is defined in
810 * "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
811 * were to be issued and executed prior to WFI, the cluster would enter reset and
812 * SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
813 */
814 /* SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0); */
815 status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
816 if (status != CSL_PASS)
817 {
818 SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
819 SblErrLoop(__FILE__, __LINE__);
820 }
822 /**
823 * Both cores enter reset
824 *
825 * It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
826 * MCU1_1 may never ben in a higher functional state than MCU1_0.
827 */
828 #if !defined(SOC_AM65XX)
829 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
830 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
832 /**
833 * Un-halt MCU1_1 (MCU1_0 is not halted)
834 */
835 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
836 #else
837 /* AM65x case (can't use local reset flags): Power down core running SBL */
838 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
839 #endif
841 /**
842 * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
843 */
844 #if !defined(SOC_J721E) && !defined(SOC_J7200)
845 if (requestCoresFlag == SBL_REQUEST_CORE)
846 {
847 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
848 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
849 }
850 #endif
851 /**
852 * MCU1_0 and (optionally) MCU1_1 leave reset
853 *
854 * Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
855 * shall leave reset. Only take MCU1_1 out of reset if an application will be running
856 * on it.
857 */
858 #if !defined(SOC_AM65XX)
859 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
860 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
861 {
862 Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
863 }
864 #else
865 /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
866 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
867 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
868 {
869 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
870 }
871 #endif
873 #if defined(SOC_J721E) || defined(SOC_J7200)
874 /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
875 /* This is done at the end as the PM set module state relies on the fact the SBL is the owner of MCU1_0 and MCU1_1 */
876 if (requestCoresFlag == SBL_REQUEST_CORE)
877 {
878 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
879 Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
880 }
881 #endif
882 /* Execute a WFI */
883 asm volatile (" wfi");
884 #endif
885 break;
887 case MCU1_CPU0_ID:
888 /* Skip copy if R5 app entry point is already 0 */
889 #if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
890 if (pAppEntry->CpuEntryPoint[core_id])
891 {
892 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
893 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
894 }
895 #endif
896 break;
897 case MCU2_CPU0_ID:
898 case MCU2_CPU1_ID:
899 case MCU3_CPU0_ID:
900 case MCU3_CPU1_ID:
901 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
902 {
903 /* Skip copy if R5 app entry point is already 0 */
904 if (pAppEntry->CpuEntryPoint[core_id])
905 {
906 SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
907 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
908 }
909 SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
910 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
911 if (status != CSL_PASS)
912 {
913 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
914 SblErrLoop(__FILE__, __LINE__);
915 }
916 }
918 /* Release core */
919 if (requestCoresFlag == SBL_REQUEST_CORE)
920 {
921 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
922 }
924 SBL_ADD_PROFILE_POINT;
925 break;
926 case M4F_CPU0_ID:
927 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
928 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
929 if (status != CSL_PASS)
930 {
931 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
932 SblErrLoop(__FILE__, __LINE__);
933 }
935 /* Release core */
936 if (requestCoresFlag == SBL_REQUEST_CORE)
937 {
938 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
939 }
941 SBL_ADD_PROFILE_POINT;
942 break;
943 default:
944 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
945 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
946 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
947 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
949 /* Release core */
950 if (requestCoresFlag == SBL_REQUEST_CORE)
951 {
952 SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
953 }
955 SBL_ADD_PROFILE_POINT;
956 break;
957 }
958 }