1 /**
2 * \file sbl_slave_core_boot.c
3 *
4 * \brief This file contain functions related to slave core boot-up.
5 *
6 */
8 /*
9 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include <stdint.h>
46 #include <string.h>
47 #include <ti/csl/csl_types.h>
48 #include <ti/csl/cslr_device.h>
49 #include <ti/csl/hw_types.h>
50 #include <ti/csl/arch/csl_arch.h>
51 #include <ti/drv/uart/UART_stdio.h>
53 #include "sbl_soc.h"
54 #include "sbl_log.h"
55 #include "sbl_soc_cfg.h"
56 #include "sbl_profile.h"
57 #include "sbl_err_trap.h"
58 #include "sbl_sci_client.h"
59 #include "sbl_slave_core_boot.h"
61 #if defined(BOOT_OSPI)
62 #include "sbl_ospi.h"
63 #endif
65 #if defined(BOOT_MMCSD)
66 #include "sbl_mmcsd.h"
67 #endif
69 #if defined(BOOT_UART)
70 #include "sbl_uart.h"
71 #endif
73 #if defined(BOOT_HYPERFLASH)
74 #include "sbl_hyperflash.h"
75 #endif
76 /* ========================================================================== */
77 /* Macros & Typedefs */
78 /* ========================================================================== */
79 #define SBL_DISABLE_MCU_LOCKSTEP (0)
80 #define SBL_ENABLE_MCU_LOCKSTEP (1)
82 /* Don't forget to update parameter OPP of the AVS */
83 /* setup function in SBL_SocLateInit if the CPU freq */
84 /* are changed to a higher or lower operating point */
85 static const sblSlaveCoreInfo_t sbl_slave_core_info[] =
86 {
87 /* MPU1_CPU0 info */
88 {
89 SBL_PROC_ID_MPU1_CPU0,
90 SBL_DEV_ID_MPU1_CPU0,
91 SBL_CLK_ID_MPU1_CPU0,
92 SBL_MPU1_CPU0_FREQ_HZ,
93 },
94 /* MPU1_CPU1 info */
95 {
96 SBL_PROC_ID_MPU1_CPU1,
97 SBL_DEV_ID_MPU1_CPU1,
98 SBL_CLK_ID_MPU1_CPU1,
99 SBL_MPU1_CPU1_FREQ_HZ,
100 },
101 /* MPU2_CPU0 info */
102 {
103 SBL_PROC_ID_MPU2_CPU0,
104 SBL_DEV_ID_MPU2_CPU0,
105 SBL_CLK_ID_MPU2_CPU0,
106 SBL_MPU2_CPU0_FREQ_HZ,
107 },
108 /* MPU2_CPU1 info */
109 {
110 SBL_PROC_ID_MPU2_CPU1,
111 SBL_DEV_ID_MPU2_CPU1,
112 SBL_CLK_ID_MPU2_CPU1,
113 SBL_MPU2_CPU1_FREQ_HZ,
114 },
115 /* MCU1_CPU0 info */
116 {
117 SBL_PROC_ID_MCU1_CPU0,
118 SBL_DEV_ID_MCU1_CPU0,
119 SBL_CLK_ID_MCU1_CPU0,
120 SBL_MCU1_CPU0_FREQ_HZ,
121 },
122 /* MCU1_CPU1 info */
123 {
124 SBL_PROC_ID_MCU1_CPU1,
125 SBL_DEV_ID_MCU1_CPU1,
126 SBL_CLK_ID_MCU1_CPU1,
127 SBL_MCU1_CPU1_FREQ_HZ,
128 },
129 /* MCU2_CPU0 info */
130 {
131 SBL_PROC_ID_MCU2_CPU0,
132 SBL_DEV_ID_MCU2_CPU0,
133 SBL_CLK_ID_MCU2_CPU0,
134 SBL_MCU2_CPU0_FREQ_HZ,
135 },
136 /* MCU2_CPU1 info */
137 {
138 SBL_PROC_ID_MCU2_CPU1,
139 SBL_DEV_ID_MCU2_CPU1,
140 SBL_CLK_ID_MCU2_CPU1,
141 SBL_MCU2_CPU1_FREQ_HZ,
142 },
143 /* MCU3_CPU0 info */
144 {
145 SBL_PROC_ID_MCU3_CPU0,
146 SBL_DEV_ID_MCU3_CPU0,
147 SBL_CLK_ID_MCU3_CPU0,
148 SBL_MCU3_CPU0_FREQ_HZ,
149 },
150 /* MCU3_CPU1 info */
151 {
152 SBL_PROC_ID_MCU3_CPU1,
153 SBL_DEV_ID_MCU3_CPU1,
154 SBL_CLK_ID_MCU3_CPU1,
155 SBL_MCU3_CPU1_FREQ_HZ,
156 },
157 /* DSP1_C66X info */
158 {
159 SBL_PROC_ID_DSP1_C66X,
160 SBL_DEV_ID_DSP1_C66X,
161 SBL_CLK_ID_DSP1_C66X,
162 SBL_DSP1_C66X_FREQ_HZ,
163 },
164 /* DSP2_C66X info */
165 {
166 SBL_PROC_ID_DSP2_C66X,
167 SBL_DEV_ID_DSP2_C66X,
168 SBL_CLK_ID_DSP2_C66X,
169 SBL_DSP2_C66X_FREQ_HZ,
170 },
171 /* DSP1_C7X info */
172 {
173 SBL_PROC_ID_DSP1_C7X,
174 SBL_DEV_ID_DSP1_C7X,
175 SBL_CLK_ID_DSP1_C7X,
176 SBL_DSP1_C7X_FREQ_HZ,
177 },
178 /* DSP2_C7X info */
179 {
180 SBL_PROC_ID_DSP2_C7X,
181 SBL_DEV_ID_DSP2_C7X,
182 SBL_CLK_ID_DSP2_C7X,
183 SBL_DSP2_C7X_FREQ_HZ,
184 },
185 /* M4F Core0 info*/
186 {
187 SBL_PROC_ID_M4F_CPU0,
188 SBL_DEV_ID_M4F_CPU0,
189 SBL_CLK_ID_M4F_CPU0,
190 SBL_M4F_CPU0_FREQ_HZ,
191 }
192 };
194 #ifndef DISABLE_ATCM
195 static const uint32_t SblAtcmAddr[] =
196 {
197 SBL_MCU_ATCM_BASE,
198 SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC,
199 SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC,
200 SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC,
201 SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC,
202 SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
203 };
204 #else
205 static const uint32_t SblBtcmAddr[] =
206 {
207 SBL_MCU_BTCM_BASE,
208 SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC,
209 SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC,
210 SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC,
211 SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
212 SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
213 };
214 #endif
215 /* ========================================================================== */
216 /* Internal Functions */
217 /* ========================================================================== */
219 void SBL_RequestCoreProcId(int32_t proc_id) {
220 int32_t status = CSL_EFAIL;
222 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
224 status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
225 if (status != CSL_PASS)
226 {
227 SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
228 SblErrLoop(__FILE__, __LINE__);
229 }
230 }
232 void SBL_RequestCore(cpu_core_id_t core_id)
233 {
234 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
235 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
237 if(proc_id != 0xBAD00000)
238 {
239 SBL_RequestCoreProcId(proc_id);
240 }
241 #endif
243 return;
244 }
246 void SBL_RequestAllCores(void)
247 {
248 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
249 cpu_core_id_t core_id;
250 uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
252 SBL_ADD_PROFILE_POINT;
254 for (core_id = 0; core_id < num_cores; core_id++)
255 {
256 if(sbl_slave_core_info[core_id].tisci_proc_id != 0xBAD00000)
257 {
258 SBL_RequestCore(core_id);
259 }
260 }
262 SBL_ADD_PROFILE_POINT;
263 #endif
265 return;
266 }
268 void SBL_ReleaseCoreProcId(int32_t proc_id)
269 {
270 int32_t status = CSL_EFAIL;
272 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
273 status = Sciclient_procBootReleaseProcessor(proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
274 if (status != CSL_PASS)
275 {
276 SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
277 SblErrLoop(__FILE__, __LINE__);
278 }
279 }
281 void SBL_ReleaseCore(cpu_core_id_t core_id)
282 {
283 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
284 int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
286 if(proc_id != 0xBAD00000)
287 {
288 SBL_ReleaseCoreProcId(proc_id);
289 }
290 #endif
292 return;
293 }
295 void SBL_ReleaseAllCores(void)
296 {
297 #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
298 cpu_core_id_t core_id;
299 uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
301 SBL_ADD_PROFILE_POINT;
303 for (core_id = 0; core_id < num_cores; core_id++)
304 {
305 SBL_ReleaseCore(core_id);
306 }
308 SBL_ADD_PROFILE_POINT;
309 #endif
311 return;
312 }
314 static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo_t *sblCoreInfoPtr)
315 {
316 int32_t status = CSL_EFAIL;
317 struct tisci_msg_proc_get_status_resp cpuStatus;
318 struct tisci_msg_proc_set_config_req proc_set_config_req;
320 SBL_ADD_PROFILE_POINT;
322 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblCoreInfoPtr->tisci_proc_id);
323 status = Sciclient_procBootGetProcessorState(sblCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
324 if (status != CSL_PASS)
325 {
326 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
327 SblErrLoop(__FILE__, __LINE__);
328 }
330 proc_set_config_req.processor_id = cpuStatus.processor_id;
331 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
332 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
333 proc_set_config_req.config_flags_1_set = 0;
334 proc_set_config_req.config_flags_1_clear = 0;
336 if (enableLockStep)
337 {
338 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
339 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
340 }
341 else
342 {
343 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
344 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
345 }
347 SBL_ADD_PROFILE_POINT;
349 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
350 if (status != CSL_PASS)
351 {
352 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
353 }
355 SBL_ADD_PROFILE_POINT;
357 return;
358 }
360 int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
361 {
362 int32_t retval = 0;
363 cpu_core_id_t core_id;
365 SBL_ADD_PROFILE_POINT;
367 /* Initialize the entry point array to 0. */
368 for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
369 pEntry->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
371 /* Request SYSW for control of all cores */
372 SBL_RequestAllCores();
374 SBL_ADD_PROFILE_POINT;
376 #if defined(BOOT_MMCSD)
377 /* MMCSD Boot Mode Image Copy function. */
378 if (SBL_MMCBootImage(pEntry) != E_PASS)
379 #elif defined(BOOT_OSPI)
380 if (SBL_OSPIBootImage(pEntry) != E_PASS)
381 #elif defined(BOOT_UART)
382 if (SBL_UARTBootImage(pEntry) != E_PASS)
383 #elif defined(BOOT_HYPERFLASH)
384 if (SBL_HYPERFLASHBootImage(pEntry) != E_PASS)
385 #endif
386 {
387 retval = E_FAIL;
388 }
390 SBL_ADD_PROFILE_POINT;
392 /* Release control of all cores */
393 SBL_ReleaseAllCores();
395 SBL_ADD_PROFILE_POINT;
397 return retval;
398 }
400 /**
401 * \brief SBL_SetupCoreMem function sets up the CPUs internal memory
402 *
403 * \param[in] core_id - CPU ID
404 * \param[in] pAppEntry - Core info struct
405 *
406 * \return none
407 */
408 void SBL_SetupCoreMem(uint32_t core_id)
409 {
410 int32_t status = CSL_EFAIL;
411 uint8_t runLockStep = 0;
412 struct tisci_msg_proc_get_status_resp cpuStatus;
413 struct tisci_msg_proc_set_config_req proc_set_config_req;
414 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
416 SBL_ADD_PROFILE_POINT;
418 /* Remap virtual core-ids if needed */
419 switch (core_id)
420 {
421 case MCU1_SMP_ID:
422 runLockStep = 1;
423 core_id = MCU1_CPU0_ID;
424 break;
425 case MCU2_SMP_ID:
426 runLockStep = 1;
427 core_id = MCU2_CPU0_ID;
428 break;
429 case MCU3_SMP_ID:
430 runLockStep = 1;
431 core_id = MCU3_CPU0_ID;
432 break;
433 default:
434 break;
435 }
437 sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
439 if(runLockStep)
440 {
441 SBL_log(SBL_LOG_MAX, "Detected locktep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
442 SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
443 }
445 switch (core_id)
446 {
448 case DSP1_C66X_ID:
449 break;
450 case DSP2_C66X_ID:
451 break;
452 case DSP1_C7X_ID:
453 break;
454 case DSP2_C7X_ID:
455 break;
457 case MCU1_CPU1_ID:
458 case MCU2_CPU1_ID:
459 case MCU3_CPU1_ID:
460 SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
461 /* Image for second MCU core present, disable lock step for the cluster */
462 SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
463 /* DOnt break, fall through for enabling TCMs */
464 case MCU1_CPU0_ID:
465 case MCU2_CPU0_ID:
466 case MCU3_CPU0_ID:
467 SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
468 status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
469 if (status != CSL_PASS)
470 {
471 SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
472 SblErrLoop(__FILE__, __LINE__);
473 }
475 proc_set_config_req.processor_id = cpuStatus.processor_id;
476 proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
477 proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
478 proc_set_config_req.config_flags_1_set = 0;
479 proc_set_config_req.config_flags_1_clear = 0;
480 SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
481 #ifdef DISABLE_ATCM
482 proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
483 proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
484 TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
485 #else
486 /* When ATCM is enabled, then BTCM_EN & RSTBASE flags should be cleared (BTCM disabled and BTCM is at 0x0) */
487 proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
488 proc_set_config_req.config_flags_1_clear |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
489 TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
490 #endif
492 #if defined(SOC_J7200)
493 //SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
494 //proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
495 #endif
497 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
498 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
499 if (status != CSL_PASS)
500 {
501 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
502 SblErrLoop(__FILE__, __LINE__);
503 }
504 /* SBL running on MCU0, don't fool around with its power */
505 if (core_id != MCU1_CPU0_ID)
506 {
507 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
508 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
510 #ifdef VLAB_SIM
511 /* HALT issue on VLAB causes the core to a immediate halt. ASTC Ticket #*/
512 SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
513 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
514 if (status != CSL_PASS)
515 {
516 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
517 SblErrLoop(__FILE__, __LINE__);
518 }
519 #endif
520 }
522 #ifndef VLAB_SIM
523 /* In case of VLAB_SIM, the below step is done only for all but mcu1_0 shown above */
524 SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
525 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
526 if (status != CSL_PASS)
527 {
528 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
529 SblErrLoop(__FILE__, __LINE__);
530 }
531 #endif
533 /* SBL running on MCU0, don't fool around with its power & TCMs */
534 if (core_id != MCU1_CPU0_ID)
535 {
536 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
537 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
539 #if !defined(SOC_J7200)
540 /* Currently using HW-based TCM mem init for J7200 */
542 #ifndef DISABLE_ATCM
543 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
544 SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
545 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
546 #else
548 #ifndef VLAB_SIM
549 SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
550 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
551 #else
552 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
553 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
554 #endif
555 #endif /* ifndef DISABLE_ATCM */
556 #endif /* if !defined(SOC_J7200) */
557 }
558 break;
559 case MPU1_SMP_ID:
560 case MPU1_CPU0_ID:
561 case MPU1_CPU1_ID:
562 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
563 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
564 break;
565 case MPU2_SMP_ID:
566 case MPU2_CPU0_ID:
567 case MPU2_CPU1_ID:
568 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
569 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
570 break;
571 case M4F_CPU0_ID:
572 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
573 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
574 if (status != CSL_PASS)
575 {
576 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
577 SblErrLoop(__FILE__, __LINE__);
578 }
579 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
580 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id,1,SCICLIENT_SERVICE_WAIT_FOREVER);
581 if (status != CSL_PASS)
582 {
583 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
584 SblErrLoop(__FILE__, __LINE__);
585 }
587 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
588 status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
589 if (status != CSL_PASS)
590 {
591 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
592 SblErrLoop(__FILE__, __LINE__);
593 }
594 break;
595 case MPU_SMP_ID:
596 /* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
597 if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
598 {
599 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
600 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
601 }
602 if (SBL_DEV_ID_MPU_CLUSTER1 != 0xBAD00000)
603 {
604 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
605 Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
606 }
607 break;
608 default:
609 /* No special memory setup needed */
610 break;
611 }
613 SBL_ADD_PROFILE_POINT;
615 return;
616 }
618 /**
619 * \brief SBL_SlaveCoreBoot function sets the entry point, sets up clocks
620 * and enable to core to start executing from entry point.
621 *
622 * \param core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
623 * freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
624 * pAppEntry = SBL entry point struct
625 *
626 **/
627 void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry)
628 {
629 int32_t status = CSL_EFAIL;
630 struct tisci_msg_proc_set_config_req proc_set_config_req;
631 const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
633 SBL_ADD_PROFILE_POINT;
635 #if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
636 /* Skip copy if R5 app entry point is already 0 */
637 if ((core_id == MCU1_CPU0_ID) &&
638 (pAppEntry->CpuEntryPoint[core_id]) &&
639 (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
640 {
641 #ifndef DISABLE_ATCM
642 SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
643 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
644 #endif
645 return;
646 }
648 /* Finished processing images for all cores, start MCU_0 */
649 if ((core_id == MCU1_CPU1_ID) &&
650 (pAppEntry->CpuEntryPoint[core_id] >= SBL_INVALID_ENTRY_ADDR))
651 {
652 /* Display profile logs */
653 SBL_printProfileLog();
655 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
656 /* Branch to start of ATCM */
657 ((void(*)(void))0x0)();
658 }
659 #endif
661 SBL_RequestCoreProcId(sblSlaveCoreInfoPtr->tisci_proc_id);
663 proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
664 proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
665 proc_set_config_req.bootvector_hi = 0x0;
666 proc_set_config_req.config_flags_1_set = 0;
667 proc_set_config_req.config_flags_1_clear = 0;
670 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
671 {
672 SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
673 SBL_ADD_PROFILE_POINT;
674 status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
675 if (status != CSL_PASS)
676 {
677 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
678 SblErrLoop(__FILE__, __LINE__);
679 }
681 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
682 SBL_ADD_PROFILE_POINT;
683 Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
684 sblSlaveCoreInfoPtr->tisci_clk_id,
685 sblSlaveCoreInfoPtr->slave_clk_freq_hz,
686 TISCI_MSG_FLAG_AOP,
687 SCICLIENT_SERVICE_WAIT_FOREVER);
688 SBL_ADD_PROFILE_POINT;
689 }
690 else
691 {
692 SBL_log(SBL_LOG_MAX, "Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
693 }
694 /* Power down and then power up each core*/
695 switch (core_id)
696 {
697 case MCU1_CPU1_ID:
698 /* Display profile logs */
699 SBL_printProfileLog();
701 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
702 {
703 #if defined(SOC_J7200)
704 Osal_delay(300U);
705 #ifndef DISABLE_ATCM
706 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
707 SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
708 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
709 #else
711 #ifndef VLAB_SIM
712 SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
713 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
714 #else
715 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
716 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
717 #endif
718 #endif /* ifndef DISABLE_ATCM */
719 #endif /* if defined(SOC_J7200) */
721 /* Skip copy if R5 app entry point is already 0 */
722 if (pAppEntry->CpuEntryPoint[core_id])
723 {
724 #ifndef DISABLE_ATCM
725 SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
726 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
727 #endif
728 }
729 }
731 #ifdef SBL_SKIP_MCU_RESET
732 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
733 {
734 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
735 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
736 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
737 }
739 /* Release the CPU and branch to app */
740 SBL_ReleaseCoreProcId(sblSlaveCoreInfoPtr->tisci_proc_id);
742 SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
743 /* Branch to start of ATCM */
744 ((void(*)(void))0x0)();
745 #else
746 /* Request DMSC CPU */
747 SBL_RequestCoreProcId(SBL_PROC_ID_MCU1_CPU0);
749 /* Setting up DMSC to wait for WFI */
750 SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0);
751 status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
752 if (status != CSL_PASS)
753 {
754 SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
755 SblErrLoop(__FILE__, __LINE__);
756 }
758 /* Power down core running SBL */
759 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
761 /* Both cores halted at this point. Now un-halt them as needed */
762 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU0, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
763 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
764 {
765 Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
766 }
768 /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
769 status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
770 status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
772 /* Power up cores as needed */
773 #if defined(SOC_AM64X) || defined(SOC_J7200)
774 /* AM64X & J7200 have a different Power on sequence than other K3 SOCs.
775 * We must ensure that CPU1 is powered off, first, before turning on CPU0 (and then CPU1) */
776 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
777 {
778 /* Multicore image has valid images for both core 0 and core 1 */
779 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
780 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
781 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
782 }
783 else
784 {
785 /* Multicore image has valid images for core 0 and no image for core 1 */
786 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
787 }
788 #else
789 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
790 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
791 {
792 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
793 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
794 }
795 #endif
797 /* Execute a WFI */
798 asm volatile (" wfi");
799 #endif
800 break;
802 case MCU1_CPU0_ID:
803 /* Skip copy if R5 app entry point is already 0 */
804 if (pAppEntry->CpuEntryPoint[core_id])
805 {
806 #ifndef DISABLE_ATCM
807 SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
808 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
809 #endif
810 }
811 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
812 break;
813 case MCU2_CPU0_ID:
814 case MCU2_CPU1_ID:
815 case MCU3_CPU0_ID:
816 case MCU3_CPU1_ID:
817 if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
818 {
819 #if defined(SOC_J7200)
820 Osal_delay(300U);
821 #ifndef DISABLE_ATCM
822 /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
823 SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
824 memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
825 #else
827 #ifndef VLAB_SIM
828 SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
829 memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
830 #else
831 /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
832 SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
833 #endif
834 #endif /* ifndef DISABLE_ATCM */
835 #endif /* if defined(SOC_J7200) */
837 /* Skip copy if R5 app entry point is already 0 */
838 if (pAppEntry->CpuEntryPoint[core_id])
839 {
840 #ifndef DISABLE_ATCM
841 SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
842 memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
843 #endif
844 }
845 SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
846 status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
847 if (status != CSL_PASS)
848 {
849 SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
850 SblErrLoop(__FILE__, __LINE__);
851 }
852 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
853 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
854 }
855 SBL_ADD_PROFILE_POINT;
856 break;
857 case M4F_CPU0_ID:
858 SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
859 status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id,0,SCICLIENT_SERVICE_WAIT_FOREVER);
860 if (status != CSL_PASS)
861 {
862 SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
863 SblErrLoop(__FILE__, __LINE__);
864 }
866 SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
867 status = Sciclient_procBootReleaseProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
868 if (status != CSL_PASS)
869 {
870 SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sblSlaveCoreInfoPtr->tisci_proc_id);
871 SblErrLoop(__FILE__, __LINE__);
872 }
874 SBL_ADD_PROFILE_POINT;
875 break;
876 default:
877 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
878 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
879 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
880 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
881 SBL_ADD_PROFILE_POINT;
882 break;
883 }
884 }