1 ; General settings that can be overwritten in the host code
2 ; that calls the AISGen library.
3 [General]
5 ; Can be 8 or 16 - used in emifa
6 busWidth=8
8 ; EMIFA,NONE
9 ; EMIFA required for NOR boot modes, along with busWidth field
10 BootMode=none
12 ; NO_CRC,SECTION_CRC,SINGLE_CRC
13 crcCheckType=NO_CRC
16 ; Enable sequential read mode for boot modes that support it.
17 ; Does not impact boot modes that don't use it.
18 [AIS_SeqReadEnable]
21 ; This section allows setting the PLL system clock with a
22 ; specified multiplier and divider as shown. The clock source
23 ; can also be chosen for internal or external.
24 ; |------24|------16|-------8|-------0|
25 ; PLLCFG0: | PLLM| POSTDIV| PLLDIV3| PLLDIV5|
26 ; PLLCFG1: | CLKMODE| PLLDIV7|PLL_LOCK_TIME_CNT|
27 [PLLCONFIG]
28 PLLCFG0 = 0x18010202
29 PLLCFG1 = 0x00050800
31 ; This section lets us configure the peripheral interface
32 ; of the current booting peripheral (I2C, SPI, or UART).
33 ; Use with caution. The format of the PERIPHCLKCFG field
34 ; is as follows:
35 ; SPI: |------24|------16|-------8|-------0|
36 ; | RSVD |PRESCALE|
37 ;
38 ; I2C: |------24|------16|-------8|-------0|
39 ; | RSVD |PRESCALE| CLKL | CLKH |
40 ;
41 ; UART: |------24|------16|-------8|-------0|
42 ; | RSVD | OSR | DLH | DLL |
43 ;[PERIPHCLKCFG]
44 ;PERIPHCLKCFG = 0x00000000
46 ; This section can be used to configure the PLL1 and the EMIF3a registers
47 ; for starting the DDR2 interface.
48 ; See PLL1CONFIG section for the format of the PLL1CFG fields.
49 ; |------24|------16|-------8|-------0|
50 ; SDCR: | SDCR |
51 ; SDTIMR: | SDTIMR |
52 ; SDTIMR2: | SDTIMR2 |
53 ; SDRCR: | SDRCR |
54 ;[EMIF3SDRAM]
55 ;SDCR = 0x00008621
56 ;SDTIMR = 0x0A492148
57 ;SDTIMR2 = 0x70060004
58 ;SDRCR = 0x0000030E
60 ; This section can be used to configure the EMIFA to use
61 ; CS0 as an SDRAM interface. The fields required to do this
62 ; are given below.
63 ; |------24|------16|-------8|-------0|
64 ; SDBCR: | SDBCR |
65 ; SDTIMR: | SDTIMR |
66 ; SDRSRPDEXIT: | SDRSRPDEXIT |
67 ; SDRCR: | SDRCR |
68 ;[EMIF25SDRAM]
69 ;SDBCR = 0x00004721
70 ;SDTIMR = 0x29114510
71 ;SDRSRPDEXIT = 0x00000006
72 ;SDRCR = 0x0000030E
74 ; This section can be used to configure the async chip selects
75 ; of the EMIFA (CS2-CS5). The fields required to do this
76 ; are given below.
77 ; |------24|------16|-------8|-------0|
78 ; A1CR: | A1CR |
79 ; A2CR: | A2CR |
80 ; A3CR: | A3CR |
81 ; A4CR: | A4CR |
82 ;[EMIF25ASYNC]
83 ;A1CR = 0x00000000
84 ;A2CR = 0x00000000
85 ;A3CR = 0x00000000
86 ;A4CR = 0x00000000
88 ; This section should be used in place of PLL0CONFIG when
89 ; the I2C, SPI, or UART modes are being used. This ensures that
90 ; the system PLL and the peripheral's clocks are changed together.
91 ; See PLL0CONFIG section for the format of the PLL0CFG fields.
92 ; See PERIPHCLKCFG section for the format of the CLKCFG field.
93 ; |------24|------16|-------8|-------0|
94 ; PLLCFG0: | PLL0CFG |
95 ; PLLCFG1: | PLL0CFG |
96 ; PERIPHCLKCFG: | CLKCFG |
97 ;[PLLANDCLOCKCONFIG]
98 ;PLLCFG0 = 0x00000000
99 ;PLLCFG1 = 0x00000000
100 ;PERIPHCLKCFG = 0x00000000
102 ; This section should be used to setup the power state of modules
103 ; of the two PSCs. This section can be included multiple times to
104 ; allow the configuration of any or all of the device modules.
105 ; |------24|------16|-------8|-------0|
106 ; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
107 ;[PSCCONFIG]
108 ;LPSCCFG = 0x01030003
110 ; This section allows setting of a single PINMUX register.
111 ; This section can be included multiple times to allow setting
112 ; as many PINMUX registers as needed.
113 ; |------24|------16|-------8|-------0|
114 ; REGNUM: | regNum |
115 ; MASK: | mask |
116 ; VALUE: | value |
117 ;[PINMUX]
118 ;REGNUM = 5
119 ;MASK = 0x00FF0000
120 ;VALUE = 0x00880000
122 ; No Params required - simply include this section for the fast boot function to be called
123 ;[FASTBOOT]