[processor-sdk/pdk.git] / packages / ti / boot / sbl / src / sbl_eve / sbl_lib / src / am57xx / sbl_lib_prcm_dpll.c
1 /*
2 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file sbl_lib_am57xx_prcm_dpll.c
36 *
37 * \brief This file contains the structure for all DPLL Divider elements for
38 * am57xx SOC family. This also contains some related macros.
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include <stdint.h>
46 #include <ti/csl/csl_types.h>
47 #include <ti/csl/soc.h>
48 #include <sbl_lib.h>
49 #include <sbl_lib_board.h>
50 #include <sbl_lib_config.h>
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
56 /* ========================================================================== */
57 /* Macros & Typedefs */
58 /* ========================================================================== */
60 /* None */
62 /* ========================================================================== */
63 /* Structures and Enums */
64 /* ========================================================================== */
66 /* None */
68 /* ========================================================================== */
69 /* Internal Function Declarations */
70 /* ========================================================================== */
72 /* None */
74 /* ========================================================================== */
75 /* Global Variables */
76 /* ========================================================================== */
78 /* Arrays given below are defined for 20 MHz */
79 static pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppNom_20[] =
80 {
81 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
82 };
83 #if defined (SOC_AM572x) || defined (SOC_AM574x)
84 static pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppOd_20[] =
85 {
86 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
87 };
88 #endif
89 static pmhalPrcmPllPostDivValue_t dpllCorePostDivCfgOppNom_20[] =
90 {
91 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2 }, /* Div_m2_clkcfg */
92 {PMHAL_PRCM_DPLL_POST_DIV_H12, 4 }, /* Div_h12_clkcfg */
93 {PMHAL_PRCM_DPLL_POST_DIV_H13, 62}, /* Div_h13_clkcfg */
94 {PMHAL_PRCM_DPLL_POST_DIV_H14, 5 }, /* Div_h14_clkcfg */
95 {PMHAL_PRCM_DPLL_POST_DIV_H22, 5 }, /* Div_h22_clkcfg */
96 {PMHAL_PRCM_DPLL_POST_DIV_H23, 4 }, /* Div_h23_clkcfg */
97 {PMHAL_PRCM_DPLL_POST_DIV_H24, 1 } /* Div_h24_clkcfg */
98 };
100 static pmhalPrcmPllPostDivValue_t dpllPerPostDivCfgOppNom_20[] =
101 {
102 {PMHAL_PRCM_DPLL_POST_DIV_M2, 4}, /* Div_m2_clkcfg */
103 {PMHAL_PRCM_DPLL_POST_DIV_M3, 1}, /* Div_m3_clkcfg */
104 {PMHAL_PRCM_DPLL_POST_DIV_H11, 3}, /* Div_h11_clkcfg */
105 {PMHAL_PRCM_DPLL_POST_DIV_H12, 4}, /* Div_h12_clkcfg */
106 {PMHAL_PRCM_DPLL_POST_DIV_H13, 4}, /* Div_h13_clkcfg */
107 {PMHAL_PRCM_DPLL_POST_DIV_H14, 2} /* Div_h14_clkcfg */
108 };
110 static pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppNom_20[] =
111 {
112 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
113 {PMHAL_PRCM_DPLL_POST_DIV_M3, 3} /* Div_m3_clkcfg */
114 };
116 static pmhalPrcmPllPostDivValue_t dpllEvePostDivCfgOppNom_20[] =
117 {
118 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */
119 };
121 static pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppNom_20[] =
122 {
123 {PMHAL_PRCM_DPLL_POST_DIV_M2, 3} /* Div_m2_clkcfg */
124 };
126 static pmhalPrcmPllPostDivValue_t dpllGpuPostDivCfgOppNom_20[] =
127 {
128 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */
129 };
131 static pmhalPrcmPllPostDivValue_t dpllDdrPostDivCfgOppNom_20[] =
132 {
133 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */
134 {PMHAL_PRCM_DPLL_POST_DIV_H11, 8} /* Div_h11_clkcfg */
135 };
137 static pmhalPrcmPllPostDivValue_t dpllGmacPostDivCfgOppNom_20[] =
138 {
139 {PMHAL_PRCM_DPLL_POST_DIV_M2, 4 }, /* Div_m2_clkcfg */
140 {PMHAL_PRCM_DPLL_POST_DIV_M3, 10}, /* Div_m3_clkcfg */
141 {PMHAL_PRCM_DPLL_POST_DIV_H11, 40}, /* Div_h11_clkcfg */
142 {PMHAL_PRCM_DPLL_POST_DIV_H12, 8 }, /* Div_h12_clkcfg */
143 {PMHAL_PRCM_DPLL_POST_DIV_H13, 10} /* Div_h13_clkcfg */
144 };
146 static pmhalPrcmPllPostDivValue_t dpllAbePostDivCfgAllOpp_20[] =
147 {
148 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
149 {PMHAL_PRCM_DPLL_POST_DIV_M3, 1} /* Div_m3_clkcfg */
150 };
152 static pmhalPrcmPllPostDivValue_t dpllUsbPostDivCfgAllOpp_20[] =
153 {
154 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */
155 };
157 static pmhalPrcmPllPostDivValue_t dpllPcieRefPostDivCfgOppNom_20[] =
158 {
159 {PMHAL_PRCM_DPLL_POST_DIV_M2, 15}, /* Div_m2_clkcfg */
160 };
162 static pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppOd_20[] =
163 {
164 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
165 {PMHAL_PRCM_DPLL_POST_DIV_M3, 3} /* Div_m3_clkcfg */
166 };
168 static pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppOd_20[] =
169 {
170 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */
171 };
173 static pmhalPrcmPllPostDivValue_t dpllGpuPostDivCfgOppOd_20[] =
174 {
175 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */
176 };
178 static pmhalPrcmPllPostDivValue_t dpllEvePostDivCfgOppHigh_20[] =
179 {
180 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */
181 };
183 static pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppHigh_20[] =
184 {
185 {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */
186 };
188 static pmhalPrcmPllPostDivValue_t dpllVideo1PostDivCfgOppNom_20[] =
189 {
190 {PMHAL_PRCM_DPLL_POST_DIV_H11, 13} /* Div_h11_clkcfg */
191 };
193 static pmhalPrcmPllPostDivValue_t dpllHdmiPostDivCfgOppNom_20[] =
194 {
195 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1} /* Div_m2_clkcfg */
196 };
198 #if defined (SOC_AM572x) || defined (SOC_AM574x)
199 static pmhalPrcmPllPostDivValue_t dpllVideo2PostDivCfgOppNom_20[] =
200 {
201 {PMHAL_PRCM_DPLL_POST_DIV_M2, 5 }, /* Div_m2_clkcfg */
202 {PMHAL_PRCM_DPLL_POST_DIV_H11, 10}, /* Div_h11_clkcfg */
203 {PMHAL_PRCM_DPLL_POST_DIV_H12, 10}, /* Div_h12_clkcfg */
204 {PMHAL_PRCM_DPLL_POST_DIV_H13, 10}, /* Div_h13_clkcfg */
205 {PMHAL_PRCM_DPLL_POST_DIV_H14, 10} /* Div_h14_clkcfg */
206 };
208 static pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppLow_20[] =
209 {
210 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
211 };
213 static pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppHigh_20[] =
214 {
215 {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */
216 {PMHAL_PRCM_DPLL_POST_DIV_M3, 3} /* Div_m3_clkcfg */
217 };
218 #endif
220 static pmhalPrcmDpllConfig_t dpllCoreCfgOppNom_20 =
221 {
222 266,
223 4,
224 0,
225 dpllCorePostDivCfgOppNom_20,
226 (sizeof (dpllCorePostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
227 0
228 };
230 static pmhalPrcmDpllConfig_t dpllPerCfgOppNom_20 =
231 {
232 96,
233 4,
234 0,
235 dpllPerPostDivCfgOppNom_20,
236 (sizeof (dpllPerPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
237 0
238 };
240 static pmhalPrcmDpllConfig_t dpllDspCfgOppNom_20 =
241 {
242 150,
243 4,
244 0,
245 dpllDspPostDivCfgOppNom_20,
246 (sizeof (dpllDspPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
247 0
248 };
250 static pmhalPrcmDpllConfig_t dpllEveCfgOppNom_20 =
251 {
252 214,
253 3,
254 0,
255 dpllEvePostDivCfgOppNom_20,
256 (sizeof (dpllEvePostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
257 0
258 };
260 static pmhalPrcmDpllConfig_t dpllIvaCfgOppNom_20 =
261 {
262 233,
263 3,
264 0,
265 dpllIvaPostDivCfgOppNom_20,
266 (sizeof (dpllIvaPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
267 0
268 };
270 static pmhalPrcmDpllConfig_t dpllGpuCfgOppNom_20 =
271 {
272 170,
273 3,
274 0,
275 dpllGpuPostDivCfgOppNom_20,
276 (sizeof (dpllGpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
277 0
278 };
280 static pmhalPrcmDpllConfig_t dpllGmacCfgOppNom_20 =
281 {
282 250,
283 4,
284 0,
285 dpllGmacPostDivCfgOppNom_20,
286 (sizeof (dpllGmacPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
287 0
288 };
290 static pmhalPrcmDpllConfig_t dpllAbeCfgAllOpp_20 =
291 {
292 200,
293 9,
294 0,
295 dpllAbePostDivCfgAllOpp_20,
296 (sizeof (dpllAbePostDivCfgAllOpp_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
297 0
298 };
300 static pmhalPrcmDpllConfig_t dpllUsbCfgAllOpp_20 =
301 {
302 27,
303 0,
304 0,
305 dpllUsbPostDivCfgAllOpp_20,
306 (sizeof (dpllUsbPostDivCfgAllOpp_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
307 0
308 };
310 static pmhalPrcmDpllConfig_t dpllPcieRefCfgOppNom_20 =
311 {
312 750, /* Multiplier */
313 9, /* Divider */
314 0, /* DutyCycleCorrector */
315 dpllPcieRefPostDivCfgOppNom_20,
316 (sizeof (dpllPcieRefPostDivCfgOppNom_20) /
317 sizeof (pmhalPrcmPllPostDivValue_t)),
318 0
319 };
321 static pmhalPrcmDpllConfig_t dpllDspCfgOppOd_20 =
322 {
323 175,
324 4,
325 0,
326 dpllDspPostDivCfgOppOd_20,
327 (sizeof (dpllDspPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
328 0
329 };
331 static pmhalPrcmDpllConfig_t dpllIvaCfgOppOd_20 =
332 {
333 172,
334 3,
335 0,
336 dpllIvaPostDivCfgOppOd_20,
337 (sizeof (dpllIvaPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
338 0
339 };
341 static pmhalPrcmDpllConfig_t dpllGpuCfgOppOd_20 =
342 {
343 200,
344 3,
345 0,
346 dpllGpuPostDivCfgOppOd_20,
347 (sizeof (dpllGpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
348 0
349 };
351 static pmhalPrcmDpllConfig_t dpllEveCfgOppHigh_20 =
352 {
353 260,
354 3,
355 0,
356 dpllEvePostDivCfgOppHigh_20,
357 (sizeof (dpllEvePostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
358 0
359 };
361 static pmhalPrcmDpllConfig_t dpllIvaCfgOppHigh_20 =
362 {
363 266,
364 4,
365 0,
366 dpllIvaPostDivCfgOppHigh_20,
367 (sizeof (dpllIvaPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
368 0
369 };
371 static pmhalPrcmDpllConfig_t dpllVideo1CfgOppNom_20 =
372 {
373 1637, /* Multiplier */
374 39, /* Divider */
375 0, /* DutyCycleCorrector */
376 dpllVideo1PostDivCfgOppNom_20,
377 (sizeof (dpllVideo1PostDivCfgOppNom_20) /
378 sizeof (pmhalPrcmPllPostDivValue_t)),
379 0
380 };
382 static pmhalPrcmDpllConfig_t dpllHdmiCfgOppNom_20 =
383 {
384 1188,
385 15,
386 0,
387 dpllHdmiPostDivCfgOppNom_20,
388 (sizeof (dpllHdmiPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
389 0
390 };
392 #if defined (SOC_AM572x) || defined (SOC_AM574x)
393 static pmhalPrcmDpllConfig_t dpllVideo2CfgOppNom_20 =
394 {
395 297, /* Multiplier */
396 7, /* Divider */
397 0, /* DutyCycleCorrector */
398 dpllVideo2PostDivCfgOppNom_20,
399 (sizeof (dpllVideo2PostDivCfgOppNom_20) /
400 sizeof (pmhalPrcmPllPostDivValue_t)),
401 0
402 };
404 static pmhalPrcmDpllConfig_t dpllDspCfgOppHigh_20 =
405 {
406 187,
407 4,
408 0,
409 dpllDspPostDivCfgOppHigh_20,
410 (sizeof (dpllDspPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
411 0
412 };
414 static pmhalPrcmDpllConfig_t dpllMpuCfgOppLow_20 =
415 {
416 250,
417 9,
418 0,
419 dpllMpuPostDivCfgOppLow_20,
420 (sizeof (dpllMpuPostDivCfgOppLow_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
421 0
422 };
423 #endif
425 #if defined (SOC_AM572x) || defined (SOC_AM574x)
426 static pmhalPrcmDpllConfig_t dpllDdrCfgOppNom_20 =
427 {
428 266,
429 4,
430 0,
431 dpllDdrPostDivCfgOppNom_20,
432 (sizeof (dpllDdrPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
433 0
434 };
436 static pmhalPrcmDpllConfig_t dpllMpuCfgOppNom_20 =
437 {
438 375,
439 9,
440 0,
441 dpllMpuPostDivCfgOppNom_20,
442 (sizeof (dpllMpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
443 0
444 };
446 static pmhalPrcmDpllConfig_t dpllMpuCfgOppOd_20 =
447 {
448 294,
449 4,
450 0,
451 dpllMpuPostDivCfgOppOd_20,
452 (sizeof (dpllMpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
453 0
454 };
455 #else
456 static pmhalPrcmDpllConfig_t dpllDdrCfgOppNom_20 =
457 {
458 333,
459 4,
460 0,
461 dpllDdrPostDivCfgOppNom_20,
462 (sizeof (dpllDdrPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
463 0
464 };
466 static pmhalPrcmDpllConfig_t dpllMpuCfgOppNom_20 =
467 {
468 400,
469 9,
470 0,
471 dpllMpuPostDivCfgOppNom_20,
472 (sizeof (dpllMpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),
473 0
474 };
475 #endif
477 static pmhalPrcmDpllConfig_t *pDpllAbeCfg_20[] =
478 {
479 &dpllAbeCfgAllOpp_20,
480 &dpllAbeCfgAllOpp_20,
481 &dpllAbeCfgAllOpp_20,
482 &dpllAbeCfgAllOpp_20
483 };
485 static pmhalPrcmDpllConfig_t *pDpllCoreCfg_20[] =
486 {
487 &dpllCoreCfgOppNom_20,
488 &dpllCoreCfgOppNom_20,
489 &dpllCoreCfgOppNom_20,
490 &dpllCoreCfgOppNom_20
491 };
493 static pmhalPrcmDpllConfig_t *pDpllDdrCfg_20[] =
494 {
495 &dpllDdrCfgOppNom_20,
496 &dpllDdrCfgOppNom_20,
497 &dpllDdrCfgOppNom_20,
498 &dpllDdrCfgOppNom_20
499 };
501 static pmhalPrcmDpllConfig_t *pDpllGmacCfg_20[] =
502 {
503 &dpllGmacCfgOppNom_20,
504 &dpllGmacCfgOppNom_20,
505 &dpllGmacCfgOppNom_20,
506 &dpllGmacCfgOppNom_20
507 };
509 static pmhalPrcmDpllConfig_t *pDpllIvaCfg_20[] =
510 {
511 &dpllIvaCfgOppNom_20,
512 &dpllIvaCfgOppNom_20,
513 &dpllIvaCfgOppOd_20,
514 &dpllIvaCfgOppHigh_20
515 };
517 static pmhalPrcmDpllConfig_t *pDpllPcieRefCfg_20[] =
518 {
519 &dpllPcieRefCfgOppNom_20,
520 &dpllPcieRefCfgOppNom_20,
521 &dpllPcieRefCfgOppNom_20,
522 &dpllPcieRefCfgOppNom_20
523 };
525 static pmhalPrcmDpllConfig_t *pDpllPerCfg_20[] =
526 {
527 &dpllPerCfgOppNom_20,
528 &dpllPerCfgOppNom_20,
529 &dpllPerCfgOppNom_20,
530 &dpllPerCfgOppNom_20
531 };
533 static pmhalPrcmDpllConfig_t *pDpllUsbCfg_20[] =
534 {
535 &dpllUsbCfgAllOpp_20,
536 &dpllUsbCfgAllOpp_20,
537 &dpllUsbCfgAllOpp_20,
538 &dpllUsbCfgAllOpp_20
539 };
541 static pmhalPrcmDpllConfig_t *pDpllEveCfg_20[] =
542 {
543 &dpllEveCfgOppNom_20,
544 &dpllEveCfgOppNom_20,
545 &dpllEveCfgOppHigh_20,
546 &dpllEveCfgOppHigh_20
547 };
549 static pmhalPrcmDpllConfig_t *pDpllVideo1Cfg_20[] =
550 {
551 &dpllVideo1CfgOppNom_20,
552 &dpllVideo1CfgOppNom_20,
553 &dpllVideo1CfgOppNom_20,
554 &dpllVideo1CfgOppNom_20
555 };
557 #if defined (SOC_AM572x) || defined (SOC_AM574x)
558 static pmhalPrcmDpllConfig_t *pDpllVideo2Cfg_20[] =
559 {
560 &dpllVideo2CfgOppNom_20,
561 &dpllVideo2CfgOppNom_20,
562 &dpllVideo2CfgOppNom_20,
563 &dpllVideo2CfgOppNom_20
564 };
565 #endif
567 static pmhalPrcmDpllConfig_t *pDpllHdmiCfg_20[] =
568 {
569 &dpllHdmiCfgOppNom_20,
570 &dpllHdmiCfgOppNom_20,
571 &dpllHdmiCfgOppNom_20,
572 &dpllHdmiCfgOppNom_20
573 };
575 #if defined (SOC_AM572x) || defined (SOC_AM574x)
576 static pmhalPrcmDpllConfig_t *pDpllDspCfg_20[] =
577 {
578 &dpllDspCfgOppNom_20,
579 &dpllDspCfgOppNom_20,
580 &dpllDspCfgOppOd_20,
581 &dpllDspCfgOppHigh_20
582 };
584 static pmhalPrcmDpllConfig_t *pDpllGpuCfg_20[] =
585 {
586 &dpllGpuCfgOppNom_20,
587 &dpllGpuCfgOppNom_20,
588 &dpllGpuCfgOppOd_20,
589 &dpllGpuCfgOppOd_20
590 };
592 static pmhalPrcmDpllConfig_t *pDpllMpuCfg_23x23Package_20[] =
593 {
594 &dpllMpuCfgOppLow_20,
595 &dpllMpuCfgOppNom_20,
596 &dpllMpuCfgOppOd_20,
597 &dpllMpuCfgOppOd_20
598 };
599 static pmhalPrcmDpllConfig_t *pDpllMpuCfg_17x17Package_20[] =
600 {
601 &dpllMpuCfgOppLow_20,
602 &dpllMpuCfgOppNom_20,
603 &dpllMpuCfgOppNom_20,
604 &dpllMpuCfgOppNom_20
605 };
606 #endif
608 /* ========================================================================== */
609 /* Function Declarations */
610 /* ========================================================================== */
612 int32_t SBLLibGetDpllStructure(uint32_t dpllId,
613 uint32_t sysClk,
614 uint32_t opp,
615 pmhalPrcmDpllConfig_t **dpllCfg)
616 {
617 #if defined (SOC_AM572x) || defined (SOC_AM574x)
618 uint32_t siliconPackageType;
619 #endif
620 int32_t retVal = STW_SOK;
622 if (PMHAL_PRCM_SYSCLK_20_MHZ == sysClk)
623 {
624 switch (dpllId)
625 {
626 case PMHAL_PRCM_DPLL_ABE:
627 *dpllCfg = pDpllAbeCfg_20[opp];
628 break;
629 case PMHAL_PRCM_DPLL_CORE:
630 *dpllCfg = pDpllCoreCfg_20[opp];
631 break;
632 case PMHAL_PRCM_DPLL_DDR:
633 *dpllCfg = pDpllDdrCfg_20[opp];
634 break;
635 case PMHAL_PRCM_DPLL_GMAC:
636 *dpllCfg = pDpllGmacCfg_20[opp];
637 break;
638 case PMHAL_PRCM_DPLL_GPU:
639 *dpllCfg = pDpllGpuCfg_20[opp];
640 break;
641 case PMHAL_PRCM_DPLL_IVA:
642 *dpllCfg = pDpllIvaCfg_20[opp];
643 break;
644 case PMHAL_PRCM_DPLL_PCIE_REF:
645 *dpllCfg = pDpllPcieRefCfg_20[opp];
646 break;
647 case PMHAL_PRCM_DPLL_PER:
648 *dpllCfg = pDpllPerCfg_20[opp];
649 break;
650 case PMHAL_PRCM_DPLL_USB:
651 *dpllCfg = pDpllUsbCfg_20[opp];
652 break;
653 case PMHAL_PRCM_DPLL_DSP:
654 *dpllCfg = pDpllDspCfg_20[opp];
655 break;
656 case PMHAL_PRCM_DPLL_EVE:
657 *dpllCfg = pDpllEveCfg_20[opp];
658 break;
659 case PMHAL_PRCM_DPLL_MPU:
660 #if defined (SOC_AM572x) || defined (SOC_AM574x)
661 siliconPackageType = SBLLibGetSiliconPackageType();
662 if (siliconPackageType == SBLLIB_SILICON_PACKAGE_TYPE_17X17)
663 {
664 *dpllCfg = pDpllMpuCfg_17x17Package_20[opp];
665 }
666 else
667 {
668 *dpllCfg = pDpllMpuCfg_23x23Package_20[opp];
669 }
670 #else
671 *dpllCfg = pDpllMpuCfg_23x23Package_20[opp];
672 #endif
673 break;
674 case PMHAL_PRCM_VIDEOPLL_VIDEO1:
675 *dpllCfg = pDpllVideo1Cfg_20[opp];
676 break;
677 #if defined (SOC_AM572x) || defined (SOC_AM574x)
678 case PMHAL_PRCM_VIDEOPLL_VIDEO2:
679 *dpllCfg = pDpllVideo2Cfg_20[opp];
680 break;
681 #endif
682 case PMHAL_PRCM_VIDEOPLL_HDMI:
683 *dpllCfg = pDpllHdmiCfg_20[opp];
684 break;
685 default:
686 retVal = STW_EFAIL;
687 break;
688 }
689 }
690 else
691 {
692 retVal = STW_EFAIL;
693 }
695 return retVal;
696 }
698 #ifdef __cplusplus
699 }
700 #endif