[processor-sdk/pdk.git] / packages / ti / boot / sbl / tools / omapl13x_boot_utils / OMAP-L137 / Common / include / device.h
1 /*
2 * device.h
3 */
5 /*
6 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
7 */
8 /*
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
38 /* --------------------------------------------------------------------------
39 FILE : device.h
40 PROJECT : TI Booting and Flashing Utilities for OMAP-L137
41 AUTHOR : Daniel Allred
42 DESC : Provides device differentiation for the project files. This
43 file MUST be modified to match the device specifics.
44 ----------------------------------------------------------------------------- */
46 #ifndef _DEVICE_H_
47 #define _DEVICE_H_
49 #include "tistdtypes.h"
51 // Prevent C++ name mangling
52 #ifdef __cplusplus
53 extern far "c" {
54 #endif
56 /***********************************************************
57 * Global Macro Declarations *
58 ***********************************************************/
61 /************************************************************
62 * Global Variable Declarations *
63 ************************************************************/
65 extern const char devString[];
68 /******************************************************
69 * Global Typedef declarations *
70 ******************************************************/
72 typedef enum _DEVICE_CacheType_
73 {
74 DEVICE_CACHETYPE_L1P = 0x0,
75 DEVICE_CACHETYPE_L1D = 0x1,
76 DEVICE_CACHETYPE_L2 = 0x2
77 }
78 DEVICE_CacheType;
80 // Supported buswidth
81 typedef enum _DEVICE_BUSWIDTH_
82 {
83 DEVICE_BUSWIDTH_8BIT = BUS_8BIT,
84 DEVICE_BUSWIDTH_16BIT = BUS_16BIT
85 }
86 DEVICE_BusWidth;
88 typedef enum _DEVICE_CHIPREVID_TYPE_
89 {
90 DEVICE_CHIPREVID_TYPE_DSPONLY = 0x0,
91 DEVICE_CHIPREVID_TYPE_ARMONLY = 0x1,
92 DEVICE_CHIPREVID_TYPE_DSPBOOT = 0x2,
93 DEVICE_CHIPREVID_TYPE_ARMBOOT = 0x3
94 }
95 DEVICE_ChipRevIDType;
97 typedef enum _DEVICE_BOOTPERIPHERAL_
98 {
99 DEVICE_BOOTPERIPHERAL_NONE = 0,
100 DEVICE_BOOTPERIPHERAL_NOR,
101 DEVICE_BOOTPERIPHERAL_UHPI,
102 DEVICE_BOOTPERIPHERAL_SPI,
103 DEVICE_BOOTPERIPHERAL_I2C,
104 DEVICE_BOOTPERIPHERAL_NAND,
105 DEVICE_BOOTPERIPHERAL_USB,
106 DEVICE_BOOTPERIPHERAL_UART,
107 DEVICE_BOOTPERIPHERAL_RMII,
108 DEVICE_BOOTPERIPHERAL_ESF
109 }
110 DEVICE_BootPeripheral;
112 typedef enum _DEVICE_BOOTMODE_
113 {
114 DEVICE_BOOTMODE_NONE = 0,
115 DEVICE_BOOTMODE_EMU_DEBUG,
116 DEVICE_BOOTMODE_NOR_EMIFA,
117 DEVICE_BOOTMODE_NAND_EMIFA_8BIT,
118 DEVICE_BOOTMODE_NAND_EMIFA_16BIT,
119 DEVICE_BOOTMODE_UHPI, // 16 bit
120 DEVICE_BOOTMODE_SPI0_FLASH, // 24 bit address
121 DEVICE_BOOTMODE_SPI0_EEPROM, // 16 bit address
122 DEVICE_BOOTMODE_SPI0_SLAVE, // 16 bit data
123 DEVICE_BOOTMODE_SPI1_FLASH, // 24 bit address
124 DEVICE_BOOTMODE_SPI1_EEPROM, // 16 bit address
125 DEVICE_BOOTMODE_SPI1_SLAVE, // 16 bit data
126 DEVICE_BOOTMODE_I2C0_MASTER, // 16 bit address
127 DEVICE_BOOTMODE_I2C0_SLAVE, // 16 bit data
128 DEVICE_BOOTMODE_I2C1_MASTER, // 16 bit address
129 DEVICE_BOOTMODE_I2C1_SLAVE, // 16 bit data
130 DEVICE_BOOTMODE_UART0,
131 DEVICE_BOOTMODE_UART1,
132 DEVICE_BOOTMODE_UART2,
133 DEVICE_BOOTMODE_ESF,
134 DEVICE_BOOTMODE_MMC, // Not supported
135 DEVICE_BOOTMODE_RMII, // Not supported
136 DEVICE_BOOTMODE_USB11, // Not supported
137 DEVICE_BOOTMODE_USB20, // Not supported
138 DEVICE_BOOTMODE_THB = 0xAA
139 }
140 DEVICE_BootMode;
142 // C6740 Megamodule Power Down Controller
143 typedef struct _DEVICE_C6740_PDC_
144 {
145 VUint32 PDCCMD;
146 }
147 DEVICE_C6740_PDCRegs;
149 #define PDC ((DEVICE_C6740_PDCRegs *) 0x01810000)
151 // C6740 IDMA
152 typedef struct _DEVICE_C6740_IDMA_
153 {
154 VUint32 STAT;
155 VUint32 MASK;
156 VUint32 SOURCE;
157 VUint32 DEST;
158 VUint32 CNT;
159 }
160 DEVICE_C6740_IDMARegs;
162 #define IDMA0 ((DEVICE_C6740_IDMARegs *) 0x01820000)
163 #define IDMA1 ((DEVICE_C6740_IDMARegs *) 0x01820100)
165 // C6740 L1P Control
166 typedef struct _DEVICE_C6740_L1P_
167 {
168 VUint8 RSVD0[0x20]; // 0x0000
169 VUint32 L1PCFG; // 0x0020
170 VUint32 L1PCC; // 0x0024
171 VUint8 RSVD1[0x3FF8]; // 0x0028
172 VUint32 L1PIBAR; // 0x4020
173 VUint32 L1PIWC; // 0x4024
174 VUint8 RSVD2[0x1000]; // 0x4028
175 VUint32 L1PINV; // 0x5028
176 }
177 DEVICE_C6740_L1PRegs;
179 #define L1PCTL ((DEVICE_C6740_L1PRegs *) 0x01840000)
181 // C6740 L1D Control
182 typedef struct _DEVICE_C6740_L1D_
183 {
184 VUint8 RSVD0[0x40]; // 0x0000
185 VUint32 L1DCFG; // 0x0040
186 VUint32 L1DCC; // 0x0044
187 VUint8 RSVD1[0x3FE8]; // 0x0048
188 VUint32 L1DWIBAR; // 0x4030
189 VUint32 L1DWIWC; // 0x4034
190 VUint8 RSVD2[0x08]; // 0x4038
191 VUint32 L1DWBAR; // 0x4040
192 VUint32 L1DWWC; // 0x4044
193 VUint32 L1DIBAR; // 0x4048
194 VUint32 L1DIWC; // 0x404C
195 VUint8 RSVD3[0xFF0]; // 0x4050
196 VUint32 L1DWB; // 0x5040
197 VUint32 L1DWBINV; // 0x5044
198 VUint32 L1DINV; // 0x5048
199 }
200 DEVICE_C6740_L1DRegs;
202 #define L1DCTL ((DEVICE_C6740_L1DRegs *) 0x01840000)
205 // C6740 L2 Control
206 typedef struct _DEVICE_C6740_L2_
207 {
208 VUint32 L2CFG; // 0x0000
209 VUint8 RSVD0[0x3FFC]; // 0x0004
210 VUint32 L2WBAR; // 0x4000
211 VUint32 L2WWC; // 0x4004
212 VUint8 RSVD1[0x08]; // 0x4008
213 VUint32 L2WIBAR; // 0x4010
214 VUint32 L2WIWC; // 0x4014
215 VUint32 L2IBAR; // 0x4018
216 VUint32 L2IWC; // 0x401C
217 VUint8 RSVD2[0xFE0]; // 0x4020
218 VUint32 L2WB; // 0x5000
219 VUint32 L2WBINV; // 0x5004
220 VUint32 L2INV; // 0x5008
221 }
222 DEVICE_C6740_L2Regs;
224 #define L2CTL ((DEVICE_C6740_L2Regs *) 0x01840000)
227 // C6740 Megamodule memory error controller
228 typedef struct _DEVICE_C6740_EDC_
229 {
230 VUint8 RSVD0[4]; // 0x000
231 VUint32 L2EDSTAT; // 0x004
232 VUint32 L2EDCMD; // 0x008
233 VUint32 L2EDADDR; // 0x00C
234 VUint32 L2EDPEN0; // 0x010
235 VUint32 L2EDPEN1; // 0x014
236 VUint32 L2EDCPEC; // 0x018
237 VUint32 L2EDNPEC; // 0x01C
238 VUint8 RSVD1[0x3E4]; // 0x020
239 VUint32 L1PEDSTAT; // 0x404
240 VUint32 L1PEDCMD; // 0x408
241 VUint32 L1PEDADDR; // 0x40C
242 }
243 DEVICE_C6740_EDCRegs;
245 #define DSP_EDC ((DEVICE_C6740_EDCRegs *) 0x01846000)
248 // C6740 Megamodule Interrupt Controller
249 typedef struct _DEVICE_C6740_INTC_
250 {
251 VUint32 EVTFLAG[4]; // 0x000
252 VUint8 RSVD0[16]; // 0x010
253 VUint32 EVTSET[4]; // 0x020
254 VUint8 RSVD1[16]; // 0x030
255 VUint32 EVTCLR[4]; // 0x040
256 VUint8 RSVD2[48]; // 0x050
257 VUint32 EVTMASK[4]; // 0x080
258 VUint8 RSVD3[16]; // 0x090
259 VUint32 MEVTFLAG[4]; // 0x0A0
260 VUint8 RSVD4[16]; // 0x0B0
261 VUint32 EXPMASK[4]; // 0x0C0
262 VUint8 RSVD5[16];
263 VUint32 MEXPFLAG[4];
264 VUint8 RSVD6[20];
265 VUint32 INTMUX1;
266 VUint32 INTMUX2;
267 VUint32 INTMUX3;
268 VUint8 RSVD7[48];
269 VUint32 AEGMUX0;
270 VUint32 AEGMUX1;
271 VUint8 RSVD8[56];
272 VUint32 INTXSTAT;
273 VUint32 INTXCLR;
274 VUint32 INTDMASK;
275 VUint8 RSVD9[52];
276 VUint32 EVTASRT;
277 }
278 DEVICE_C6740_INTCRegs;
280 #define DSP_INTC ((DEVICE_C6740_INTCRegs *) 0x01800000)
283 // System Control Module register structure
284 typedef struct _DEVICE_SYS_MODULE_REGS_
285 {
286 VUint32 REVID; //0x00
287 VUint8 RSVD0[4]; //0x04
288 VUint32 DIEIDR[4]; //0x08
289 VUint32 DEVIDD[2]; //0x18
290 VUint32 BOOTCFG; //0x20
291 VUint32 CHIPREVID; //0x24
292 VUint32 FEATURE_ENA; //0x28
293 VUint32 L2ROMDIV; //0x2C
294 VUint8 RSVD1[8]; //0x30
295 VUint32 KICKR[2]; //0x38
296 VUint32 HOSTCFG[2]; //0x40
297 VUint8 RSVD2[152]; //0x48
298 VUint32 IRAWSTRAT; //0xE0
299 VUint32 IENSTAT; //0xE4
300 VUint32 IENSET; //0xE8
301 VUint32 IENCLR; //0xEC
302 VUint32 EOI; //0xF0
303 VUint32 FLTADDRR; //0xF4
304 VUint32 FLTSTAT; //0xF8
305 VUint32 FLTCLR; //0xFC
306 VUint8 RSVD3[16]; //0x100
307 VUint32 MSTPRI[3]; //0x110
308 VUint8 RSVD4[4]; //0x11C
309 VUint32 PINMUX[20]; //0x120
310 VUint32 SUSPSRC; //0x170
311 VUint32 CHIPSIG; //0x174
312 VUint32 CHIPSIG_CLR; //0x178
313 VUint32 CFGCHIP[5]; //0x17C
314 VUint8 RSVD5[5]; //0x190
315 VUint32 ROMCHECKSUM[2]; //0x1A0
316 }
317 DEVICE_SysModuleRegs;
319 #define SYSTEM ((DEVICE_SysModuleRegs*) 0x01C14000)
321 #define DEVICE_BOOTCFG_BOOTMODE_MASK (0x000000FF)
322 #define DEVICE_BOOTCFG_BOOTMODE_SHIFT (0)
324 #define DEVICE_CHIPREVID_TYPE_MASK (0x00000030u)
325 #define DEVICE_CHIPREVID_TYPE_SHIFT (4)
329 // ARM Interrupt Controller register structure
330 typedef struct _DEVICE_AINTC_REGS_
331 {
332 VUint32 FIQ0;
333 VUint32 FIQ1;
334 VUint32 IRQ0;
335 VUint32 IRQ1;
336 VUint32 FIQENTRY;
337 VUint32 IRQENTRY;
338 VUint32 EINT0;
339 VUint32 EINT1;
340 VUint32 INTCTL;
341 VUint32 EABASE;
342 VUint8 RSVD0[8];
343 VUint32 INTPRI0;
344 VUint32 INTPRI1;
345 VUint32 INTPRI2;
346 VUint32 INTPRI3;
347 VUint32 INTPRI4;
348 VUint32 INTPRI5;
349 VUint32 INTPRI6;
350 VUint32 INTPRI7;
351 }
352 DEVICE_AIntcRegs;
354 #define AINTC ((DEVICE_AIntcRegs*) 0xFFFEE000)
357 // PRU Control register structure
358 typedef struct _DEVICE_PRU_CTRL_REGS_
359 {
360 VUint32 CONTROL;
361 VUint32 STATUS;
362 VUint32 WAKEUP;
363 VUint32 CYCLECNT;
364 VUint32 STALLCNT;
365 VUint8 RSVD0[12];
366 VUint32 CONTABBLKIDX0;
367 VUint32 CONTABBLKIDX1;
368 VUint32 CONTABPROPTR0;
369 VUint32 CONTABPROPTR1;
370 VUint8 RSVD1[976];
371 VUint32 INTGPR0;
372 VUint32 INTGPR1;
373 VUint32 INTGPR2;
374 VUint32 INTGPR3;
375 VUint32 INTGPR4;
376 VUint32 INTGPR5;
377 VUint32 INTGPR6;
378 VUint32 INTGPR7;
379 VUint32 INTGPR8;
380 VUint32 INTGPR9;
381 VUint32 INTGPR10;
382 VUint32 INTGPR11;
383 VUint32 INTGPR12;
384 VUint32 INTGPR13;
385 VUint32 INTGPR14;
386 VUint32 INTGPR15;
387 VUint32 INTGPR16;
388 VUint32 INTGPR17;
389 VUint32 INTGPR18;
390 VUint32 INTGPR19;
391 VUint32 INTGPR20;
392 VUint32 INTGPR21;
393 VUint32 INTGPR22;
394 VUint32 INTGPR23;
395 VUint32 INTGPR24;
396 VUint32 INTGPR25;
397 VUint32 INTGPR26;
398 VUint32 INTGPR27;
399 VUint32 INTGPR28;
400 VUint32 INTGPR29;
401 VUint32 INTGPR30;
402 VUint32 INTGPR31;
403 VUint32 INTCTER0;
404 VUint32 INTCTER1;
405 VUint32 INTCTER2;
406 VUint32 INTCTER3;
407 VUint32 INTCTER4;
408 VUint32 INTCTER5;
409 VUint32 INTCTER6;
410 VUint32 INTCTER7;
411 VUint32 INTCTER8;
412 VUint32 INTCTER9;
413 VUint32 INTCTER10;
414 VUint32 INTCTER11;
415 VUint32 INTCTER12;
416 VUint32 INTCTER13;
417 VUint32 INTCTER14;
418 VUint32 INTCTER15;
419 VUint32 INTCTER16;
420 VUint32 INTCTER17;
421 VUint32 INTCTER18;
422 VUint32 INTCTER19;
423 VUint32 INTCTER20;
424 VUint32 INTCTER21;
425 VUint32 INTCTER22;
426 VUint32 INTCTER23;
427 VUint32 INTCTER24;
428 VUint32 INTCTER25;
429 VUint32 INTCTER26;
430 VUint32 INTCTER27;
431 VUint32 INTCTER28;
432 VUint32 INTCTER29;
433 VUint32 INTCTER30;
434 VUint32 INTCTER31;
435 }
436 DEVICE_PRUCtrlRegs;
438 #define PRU0 ((DEVICE_PRUCtrlRegs *) 0x01C37000)
439 #define PRU1 ((DEVICE_PRUCtrlRegs *) 0x01C37800)
441 #define DEVICE_PRU_CONTROL_COUNTENABLE_MASK (0x00000008u)
442 #define DEVICE_PRU_CONTROL_COUNTENABLE_SHIFT (3)
443 #define DEVICE_PRU_CONTROL_ENABLE_MASK (0x00000002u)
444 #define DEVICE_PRU_CONTROL_ENABLE_SHIFT (1)
445 #define DEVICE_PRU_CONTROL_SOFTRESET_MASK (0x00000001u)
446 #define DEVICE_PRU_CONTROL_SOFTRESET_SHIFT (0)
447 #define DEVICE_PRU_CONTROL_RUNSTATE_MASK (0x00008000u)
448 #define DEVICE_PRU_CONTROL_RUNSTATE_SHIFT (15)
451 // PLL Register structure
452 typedef struct _DEVICE_PLL_REGS_
453 {
454 VUint32 PID; // 0x000
455 VUint8 RSVD0[204]; // 0x004
456 VUint32 SHIFTDIV; // 0x0D0
457 VUint32 CS0; // 0x0D4
458 VUint32 DFTCNTR; // 0x0D8
459 VUint32 DFTCNTRCTRL; // 0x0DC
460 VUint32 FUSERR; // 0x0E0
461 VUint32 RSTYPE; // 0x0E4
462 VUint32 RSTCTRL; // 0x0E8
463 VUint32 RSTCFG; // 0x0EC
464 VUint32 RSISO; // 0x0F0
465 VUint8 RSVD1[12]; // 0x0F4
466 VUint32 PLLCTL; // 0x100
467 VUint32 OCSEL; // 0x104
468 VUint32 SECCTL; // 0x108
469 VUint8 RSVD2[4]; // 0x10C
470 VUint32 PLLM; // 0x110
471 VUint32 PREDIV;
472 VUint32 PLLDIV1;
473 VUint32 PLLDIV2;
474 VUint32 PLLDIV3;
475 VUint32 OSCDIV1;
476 VUint32 POSTDIV;
477 VUint32 BPDIV;
478 VUint32 WAKEUP;
479 VUint8 RSVD3[4];
480 VUint32 PLLCMD;
481 VUint32 PLLSTAT;
482 VUint32 ALNCTL;
483 VUint32 DCHANGE;
484 VUint32 CKEN;
485 VUint32 CKSTAT;
486 VUint32 SYSTAT;
487 VUint8 RSVD4[12];
488 VUint32 PLLDIV4;
489 VUint32 PLLDIV5;
490 VUint32 PLLDIV6;
491 VUint32 PLLDIV7;
492 VUint32 PLLDIV8;
493 VUint32 PLLDIV9;
494 VUint32 PLLDIV10;
495 VUint32 PLLDIV11;
496 VUint32 PLLDIV12;
497 VUint32 PLLDIV13;
498 VUint32 PLLDIV14;
499 VUint8 RSVD5[4];
500 VUint32 PLLDIV15;
501 VUint8 RSVD6[88];
502 VUint32 PLLHDIVEN;
503 VUint32 EMUCNT0;
504 VUint32 EMUCNT1;
505 }
506 DEVICE_PLLRegs;
508 #define PLL0 ((DEVICE_PLLRegs*) 0x01C11000)
510 #define DEVICE_PLLCTL_PLLEN_MASK (0x00000001)
511 #define DEVICE_PLLCTL_PLLPWRDN_MASK (0x00000002)
512 #define DEVICE_PLLCTL_PLLRST_MASK (0x00000008)
513 #define DEVICE_PLLCTL_PLLDIS_MASK (0x00000010)
514 #define DEVICE_PLLCTL_PLLENSRC_MASK (0x00000020)
515 #define DEVICE_PLLCTL_CLKMODE_MASK (0x00000100)
517 #define DEVICE_PLLCMD_GOSET_MASK (0x00000001)
518 #define DEVICE_PLLSTAT_GOSTAT_MASK (0x00000001)
519 #define DEVICE_PLLDIV_EN_MASK (0x00008000)
521 // Power/Sleep Ctrl Register structure
522 typedef struct _DEVICE_PSC_REGS_
523 {
524 VUint32 PID; // 0x000
525 VUint8 RSVD0[16]; // 0x004
526 VUint8 RSVD1[4]; // 0x014
527 VUint32 INTEVAL; // 0x018
528 VUint8 RSVD2[36]; // 0x01C
529 VUint32 MERRPR0; // 0x040
530 VUint32 MERRPR1; // 0x044
531 VUint8 RSVD3[8]; // 0x048
532 VUint32 MERRCR0; // 0x050
533 VUint32 MERRCR1; // 0x054
534 VUint8 RSVD4[8]; // 0x058
535 VUint32 PERRPR; // 0x060
536 VUint8 RSVD5[4]; // 0x064
537 VUint32 PERRCR; // 0x068
538 VUint8 RSVD6[4]; // 0x06C
539 VUint32 EPCPR; // 0x070
540 VUint8 RSVD7[4]; // 0x074
541 VUint32 EPCCR; // 0x078
542 VUint8 RSVD8[144]; // 0x07C
543 VUint8 RSVD9[20]; // 0x10C
544 VUint32 PTCMD; // 0x120
545 VUint8 RSVD10[4]; // 0x124
546 VUint32 PTSTAT; // 0x128
547 VUint8 RSVD11[212]; // 0x12C
548 VUint32 PDSTAT0; // 0x200
549 VUint32 PDSTAT1; // 0x204
550 VUint8 RSVD12[248]; // 0x208
551 VUint32 PDCTL0; // 0x300
552 VUint32 PDCTL1; // 0x304
553 VUint8 RSVD13[536]; // 0x308
554 VUint32 MCKOUT0; // 0x520
555 VUint32 MCKOUT1; // 0x524
556 VUint8 RSVD14[728]; // 0x528
557 VUint32 MDSTAT[41]; // 0x800
558 VUint8 RSVD15[348]; // 0x8A4
559 VUint32 MDCTL[41]; // 0xA00
560 }
561 DEVICE_PSCRegs;
563 #define PSC0 ((DEVICE_PSCRegs*) 0x01C10000)
564 #define PSC1 ((DEVICE_PSCRegs*) 0x01E27000)
566 #define EMURSTIE_MASK (0x00000200)
568 #define PSC_ENABLE (0x3)
569 #define PSC_DISABLE (0x2)
570 #define PSC_SYNCRESET (0x1)
571 #define PSC_SWRSTDISABLE (0x0)
573 #define PSC_MDCTL_LRSTZ_MASK (0x00000100u)
574 #define PSC_MDCTL_LRSTZ_SHIFT (0x00000008u)
576 #define PSCNUM0 (0x0)
577 #define PSCNUM1 (0x1)
579 #define PD0 (0x0)
580 #define PD1 (0x1)
582 // PSC0 (Matrix) defines
583 #define LPSC_TPCC (0)
584 #define LPSC_TPTC0 (1)
585 #define LPSC_TPTC1 (2)
586 #define LPSC_EMIFA (3)
587 #define LPSC_SPI0 (4)
588 #define LPSC_MMCSD0 (5)
589 #define LPSC_ARMINTC (6)
590 #define LPSC_ARMRAM (7)
591 #define LPSC_SCnKM (8)
592 #define LPSC_UART0 (9)
593 #define LPSC_PRU (13)
594 #define LPSC_ARM (14)
595 #define LPSC_DSP (15)
597 // PSC1 (Subchip) defines
598 #define LPSC_USB0 (1)
599 #define LPSC_USB1 (2)
600 #define LPSC_GPIO (3)
601 #define LPSC_UHPI0 (4)
602 #define LPSC_EMAC (5)
603 #define LPSC_EMIFB (6)
604 #define LPSC_McASP0 (7)
605 #define LPSC_McASP1 (8)
606 #define LPSC_McASP2 (9)
607 #define LPSC_SPI1 (10)
608 #define LPSC_I2C1 (11)
609 #define LPSC_UART1 (12)
610 #define LPSC_UART2 (13)
611 #define LPSC_L3CBA (31)
612 // AEMIF Register structure - From EMIF 2.5 Spec
613 typedef struct _DEVICE_EMIF25_REGS_
614 {
615 VUint32 ERCSR; // 0x00
616 VUint32 AWCCR; // 0x04
617 VUint32 SDBCR; // 0x08
618 VUint32 SDRCR; // 0x0C
620 VUint32 A1CR; // 0x10
621 VUint32 A2CR; // 0x14
622 VUint32 A3CR; // 0x18
623 VUint32 A4CR; // 0x1C
625 VUint32 SDTIMR; // 0x20
626 VUint32 SDRSTAT; // 0x24
627 VUint32 DDRPHYCR; // 0x28
628 VUint32 DDRPHYSR; // 0x2C
630 VUint32 SDRACCR; // 0x30
631 VUint32 SDRACT; // 0x34
632 VUint32 DDRPHYREV; // 0x38
633 VUint32 SDRSRPDEXIT; // 0x3C
635 VUint32 EIRR; // 0x40
636 VUint32 EIMR; // 0x44
637 VUint32 EIMSR; // 0x48
638 VUint32 EIMCR; // 0x4C
640 VUint32 IOCR; // 0x50
641 VUint32 IOSR; // 0x54
642 VUint8 RSVD0[4]; // 0x58
643 VUint32 ONENANDCTL; // 0x5C
645 VUint32 NANDFCR; // 0x60
646 VUint32 NANDFSR; // 0x64
647 VUint32 PMCR; // 0x68
648 VUint8 RSVD1[4]; // 0x6C
650 VUint32 NANDF1ECC; // 0x70
651 VUint32 NANDF2ECC; // 0x74
652 VUint32 NANDF3ECC; // 0x78
653 VUint32 NANDF4ECC; // 0x7C
655 VUint8 RSVD2[4]; // 0x80
656 VUint32 IODFTEXECNT; // 0x84
657 VUint32 IODFTGBLCTRL; // 0x88
658 VUint8 RSVD3[4]; // 0x8C
660 VUint32 IODFTMISRLSB; // 0x90
661 VUint32 IODFTMISRMID; // 0x94
662 VUint32 IODFTMISRMSB; // 0x98
663 VUint8 RSVD4[20]; // 0x9C
665 VUint32 MODRELNUM; // 0xB0
666 VUint8 RSVD5[8]; // 0xB4
667 VUint32 NAND4BITECCLOAD; // 0xBC
669 VUint32 NAND4BITECC1; // 0xC0
670 VUint32 NAND4BITECC2; // 0xC4
671 VUint32 NAND4BITECC3; // 0xC8
672 VUint32 NAND4BITECC4; // 0xCC
674 VUint32 NANDERRADD1; // 0xD0
675 VUint32 NANDERRADD2; // 0xD4
676 VUint32 NANDERRVAL1; // 0xD8
677 VUint32 NANDERRVAL2; // 0xDC
678 }
679 DEVICE_Emif25Regs;
681 #define AEMIF ((DEVICE_Emif25Regs*) 0x68000000u)
683 #define DEVICE_EMIF_NUMBER_CE_REGION (4)
684 #define DEVICE_EMIF_FIRST_CE_START_ADDR (0x60000000u)
685 #define DEVICE_EMIF_INTER_CE_REGION_SIZE (0x02000000u)
686 #define DEVICE_EMIF_NAND_BOOT_BASE (0x62000000u)
687 #define DEVICE_EMIF_NOR_BOOT_BASE (0x60000000u)
689 #define DEVICE_EMIF_AxCR_SS_MASK (0x80000000u)
690 #define DEVICE_EMIF_AxCR_SS_SHIFT (31)
691 #define DEVICE_EMIF_AxCR_EW_MASK (0x40000000u)
692 #define DEVICE_EMIF_AxCR_EW_SHIFT (30)
693 #define DEVICE_EMIF_AxCR_WSETUP_MASK (0x3C000000u)
694 #define DEVICE_EMIF_AxCR_WSETUP_SHIFT (26)
695 #define DEVICE_EMIF_AxCR_WSTROBE_MASK (0x03F00000u)
696 #define DEVICE_EMIF_AxCR_WSTROBE_SHIFT (20)
697 #define DEVICE_EMIF_AxCR_WHOLD_MASK (0x000E0000u)
698 #define DEVICE_EMIF_AxCR_WHOLD_SHIFT (17)
699 #define DEVICE_EMIF_AxCR_RSETUP_MASK (0x0001E000u)
700 #define DEVICE_EMIF_AxCR_RSETUP_SHIFT (13)
701 #define DEVICE_EMIF_AxCR_RSTROBE_MASK (0x00001F80u)
702 #define DEVICE_EMIF_AxCR_RSTROBE_SHIFT (7)
703 #define DEVICE_EMIF_AxCR_RHOLD_MASK (0x00000070u)
704 #define DEVICE_EMIF_AxCR_RHOLD_SHIFT (4)
705 #define DEVICE_EMIF_AxCR_TA_MASK (0x0000000Cu)
706 #define DEVICE_EMIF_AxCR_TA_SHIFT (2)
707 #define DEVICE_EMIF_AxCR_ASIZE_MASK (0x00000003u)
708 #define DEVICE_EMIF_AxCR_ASIZE_SHIFT (0)
710 #define DEVICE_EMIF_AWCC_WAITSTATE_MASK (0x000000FF)
712 #define DEVICE_EMIF_NANDFCR_4BITECC_SEL_MASK (0x00000030)
713 #define DEVICE_EMIF_NANDFCR_4BITECC_SEL_SHIFT (4)
715 #define DEVICE_EMIF_NANDFCR_4BITECC_START_MASK (0x00001000)
716 #define DEVICE_EMIF_NANDFCR_4BITECC_START_SHIFT (12)
717 #define DEVICE_EMIF_NANDFCR_4BITECC_ADD_CALC_START_MASK (0x00002000)
718 #define DEVICE_EMIF_NANDFCR_4BITECC_ADD_CALC_START_SHIFT (13)
720 #define DEVICE_EMIF_NANDFSR_READY_MASK (0x00000001)
721 #define DEVICE_EMIF_NANDFSR_READY_SHIFT (0)
723 #define DEVICE_EMIF_NANDFSR_ECC_STATE_MASK (0x00000F00)
724 #define DEVICE_EMIF_NANDFSR_ECC_STATE_SHIFT (8)
725 #define DEVICE_EMIF_NANDFSR_ECC_ERRNUM_MASK (0x00030000)
726 #define DEVICE_EMIF_NANDFSR_ECC_ERRNUM_SHIFT (16)
729 typedef struct _DEVICE_EMIF3C_REGS_
730 {
731 VUint32 ERCSR;
732 VUint32 SDRSTAT;
733 VUint32 SDCR;
734 VUint32 SDRCR;
735 VUint32 SDTIMR;
736 VUint32 SDTIMR2;
737 VUint8 RSVD0[4];
738 VUint32 SDCR2;
739 VUint32 PBBPR;
740 VUint8 RSVD1[4];
741 VUint32 VBCFG1;
742 VUint32 VBCFG2;
743 VUint8 RSVD2[16];
744 VUint32 PERFC1R;
745 VUint32 PERFC2R;
746 VUint32 PCCR;
747 VUint32 PCMRSR;
748 VUint32 PCTR;
749 VUint8 RSVD3[12];
750 VUint32 IODFTGBLCTRL;
751 VUint32 IODFTMISRR;
752 VUint32 IODFTMISADDRRR;
753 VUint32 IODFTMISR1R;
754 VUint32 IODFTMISR2R;
755 VUint32 IODFTMISR3R;
756 VUint8 RSVD4[8];
757 VUint32 ASYNCCS2CR;
758 VUint32 ASYNCCS3CR;
759 VUint32 ASYNCCS4CR;
760 VUint32 ASYNCCS5CR;
761 VUint8 RSVD5[16];
762 VUint32 AWCCR;
763 VUint8 RSVD6[28];
764 VUint32 IRR;
765 VUint32 IMR;
766 VUint32 IMSR;
767 VUint32 IMCR;
768 VUint8 RSVD7[16];
769 VUint32 DDRPHYREV;
770 VUint32 DDRPHYC1R;
771 VUint32 DDRPHYC2R;
772 VUint32 DDRPHYC3R;
773 }
774 DEVICE_Emif3Regs;
776 #define EMIF3C ((DEVICE_Emif3Regs*) 0xB0000000u)
778 #define DEVICE_SDCR_NM_MASK (0x00004000u)
779 #define DEVICE_SDCR_NM_SHIFT (14)
784 // UART Register structure - See sprued9b.pdf for more details.
785 typedef struct _DEVICE_UART_REGS_
786 {
787 VUint32 RBR;
788 VUint32 IER;
789 VUint32 IIR;
790 VUint32 LCR;
791 VUint32 MCR;
792 VUint32 LSR;
793 VUint32 MSR;
794 VUint32 SCR;
795 VUint8 DLL;
796 VUint8 RSVD1[3];
797 VUint8 DLH;
798 VUint8 RSVD2[3];
799 VUint32 PID1;
800 VUint32 PID2;
801 VUint32 PWREMU_MGMT;
802 VUint32 MDR;
803 }
804 DEVICE_UARTRegs;
806 #define THR RBR
807 #define FCR IIR
809 #define UART_PERIPHERAL_CNT (3)
811 #define UART0 ((DEVICE_UARTRegs*) 0x01C42000)
812 #define UART1 ((DEVICE_UARTRegs*) 0x01D0C000)
813 #define UART2 ((DEVICE_UARTRegs*) 0x01D0D000)
815 #define DEVICE_UART0_DESIRED_BAUD (115200)
816 #define DEVICE_UART0_OVERSAMPLE_CNT (16)
818 #define DEVICE_UART_DLL_MASK (0x000000FFu)
819 #define DEVICE_UART_DLL_SHIFT (0)
820 #define DEVICE_UART_DLH_MASK (0x000000FFu)
821 #define DEVICE_UART_DLH_SHIFT (0)
823 #define DEVICE_UART_PWREMU_MGMT_URST_MASK (0x00008000u)
824 #define DEVICE_UART_PWREMU_MGMT_URST_SHIFT (15)
825 #define DEVICE_UART_PWREMU_MGMT_UTRST_MASK (0x00004000u)
826 #define DEVICE_UART_PWREMU_MGMT_UTRST_SHIFT (14)
827 #define DEVICE_UART_PWREMU_MGMT_URRST_MASK (0x00002000u)
828 #define DEVICE_UART_PWREMU_MGMT_URRST_SHIFT (13)
830 #define DEVICE_UART_FCR_RXFIFTL_MASK (0x000000C0u)
831 #define DEVICE_UART_FCR_RXFIFTL_SHIFT (6)
832 #define DEVICE_UART_FCR_DMAMODE1_MASK (0x00000008u)
833 #define DEVICE_UART_FCR_DMAMODE1_SHIFT (3)
834 #define DEVICE_UART_FCR_TXCLR_MASK (0x00000004u)
835 #define DEVICE_UART_FCR_TXCLR_SHIFT (2)
836 #define DEVICE_UART_FCR_RXCLR_MASK (0x00000002u)
837 #define DEVICE_UART_FCR_RXCLR_SHIFT (1)
838 #define DEVICE_UART_FCR_FIFOEN_MASK (0x00000001u)
839 #define DEVICE_UART_FCR_FIFOEN_SHIFT (0)
841 #define DEVICE_UART_LSR_RXFIFOE_MASK (0x00000080u)
842 #define DEVICE_UART_LSR_RXFIFOE_SHIFT (7)
843 #define DEVICE_UART_LSR_TEMT_MASK (0x00000040u)
844 #define DEVICE_UART_LSR_TEMT_SHIFT (6)
845 #define DEVICE_UART_LSR_THRE_MASK (0x00000020u)
846 #define DEVICE_UART_LSR_THRE_SHIFT (5)
847 #define DEVICE_UART_LSR_BI_MASK (0x00000010u)
848 #define DEVICE_UART_LSR_BI_SHIFT (4)
849 #define DEVICE_UART_LSR_FE_MASK (0x00000008u)
850 #define DEVICE_UART_LSR_FE_SHIFT (3)
851 #define DEVICE_UART_LSR_PE_MASK (0x00000004u)
852 #define DEVICE_UART_LSR_PE_SHIFT (2)
853 #define DEVICE_UART_LSR_OE_MASK (0x00000002u)
854 #define DEVICE_UART_LSR_OE_SHIFT (1)
855 #define DEVICE_UART_LSR_DR_MASK (0x00000001u)
856 #define DEVICE_UART_LSR_DR_SHIFT (0)
859 // Timer Register structure - See spruee5a.pdf for more details.
860 typedef struct _DEVICE_TIMER_REGS_
861 {
862 VUint32 PID12; // 0x00
863 VUint32 EMUMGT_CLKSPD; // 0x04
864 VUint8 RSVD0[8]; // 0x08
865 VUint32 TIM12; // 0x10
866 VUint32 TIM34; // 0x14
867 VUint32 PRD12; // 0x18
868 VUint32 PRD34; // 0x1C
869 VUint32 TCR; // 0x20
870 VUint32 TGCR; // 0x24
871 VUint32 WDTCR; // 0x28
872 VUint8 RSVD1[12]; // 0x2C
873 VUint32 REL12; // 0x34
874 VUint32 REL34; // 0x38
875 VUint32 CAP12; // 0x3C
876 VUint32 CAP34; // 0x40
877 VUint32 INTCTL_STAT; // 0x44
878 }
879 DEVICE_TimerRegs;
881 #define TIMER0 ((DEVICE_TimerRegs*) 0x01C21400)
883 // I2C Register structure - See spruee0a.pdf for more details.
884 typedef struct _DEVICE_I2C_REGS_
885 {
886 VUint32 ICOAR; // 0x00
887 VUint32 ICIMR; // 0x04
888 VUint32 ICSTR; // 0x08
889 VUint32 ICCLKL; // 0x0C
890 VUint32 ICCLKH; // 0x10
891 VUint32 ICCNT; // 0x14
892 VUint32 ICDRR; // 0x18
893 VUint32 ICSAR; // 0x1C
894 VUint32 ICDXR; // 0x20
895 VUint32 ICMDR; // 0x24
896 VUint32 ICIVR; // 0x28
897 VUint32 ICEMDR; // 0x2C
898 VUint32 ICPSC; // 0x30
899 VUint32 ICPID1; // 0x34
900 VUint32 ICPID2; // 0x38
901 }
902 DEVICE_I2CRegs;
904 #define I2C0 ((DEVICE_I2CRegs*) 0x01C22000u)
905 #define I2C1 ((DEVICE_I2CRegs*) 0x01E28000u)
907 #define I2C_PERIPHERAL_CNT (2)
909 #define DEVICE_I2C_TARGET_FREQ (200000u)
910 #define DEVICE_I2C_OWN_ADDRESS (0x10)
912 #define I2C_ICMDR_NACKMOD (0x00008000)
913 #define I2C_ICMDR_FRE (0x00004000)
914 #define I2C_ICMDR_STT (0x00002000)
915 #define I2C_ICMDR_STP (0x00000800)
916 #define I2C_ICMDR_MST (0x00000400)
917 #define I2C_ICMDR_TRX (0x00000200)
918 #define I2C_ICMDR_XA (0x00000100)
919 #define I2C_ICMDR_RM (0x00000080)
920 #define I2C_ICMDR_DLB (0x00000040)
921 #define I2C_ICMDR_IRS (0x00000020)
922 #define I2C_ICMDR_STB (0x00000010)
923 #define I2C_ICMDR_FDF (0x00000008)
924 #define I2C_ICMDR_BC8 (0x00000007)
926 #define I2C_ICSTR_AL_MSK (0x00000001)
927 #define I2C_ICSTR_NACK_MSK (0x00000002)
928 #define I2C_ICSTR_ARDY_MSK (0x00000004)
929 #define I2C_ICSTR_ICRRDY_MSK (0x00000008)
930 #define I2C_ICSTR_ICXRDY_MSK (0x00000010)
931 #define I2C_ICSTR_SCD_MSK (0x00000020)
932 #define I2C_ICSTR_BB_MSK (0x00001000)
934 #define I2C_ICEMDR_EXTMODE (0x00000000)
936 // SPI Register structure
937 typedef struct _DEVICE_SPI_REGS_
938 {
939 VUint32 SPIGCR0; // 0x00
940 VUint32 SPIGCR1; // 0x04
941 VUint32 SPIINT; // 0x08
942 VUint32 SPILVL; // 0x0C
943 VUint32 SPIFLG; // 0x10
944 VUint32 SPIPC0; // 0x14
945 VUint32 SPIPC1; // 0x18
946 VUint32 SPIPC2; // 0x1C
947 VUint32 SPIPC3; // 0x20
948 VUint32 SPIPC4; // 0x24
949 VUint32 SPIPC5; // 0x28
950 VUint32 SPIPC6; // 0x2C
951 VUint32 SPIPC7; // 0x30
952 VUint32 SPIPC8; // 0x34
953 VUint32 SPIDAT[2]; // 0x38
954 VUint32 SPIBUF; // 0x40
955 VUint32 SPIEMU; // 0x44
956 VUint32 SPIDELAY; // 0x48
957 VUint32 SPIDEF; // 0x4C
958 VUint32 SPIFMT[4]; // 0x50
959 VUint32 TGINTVEC[2]; // 0x60
960 VUint32 RSVD0[2]; // 0x68
961 VUint32 MIBSPIE; // 0x70
962 }
963 DEVICE_SPIRegs;
965 #define SPI0 ((DEVICE_SPIRegs *) 0x01C41000u)
966 #define SPI1 ((DEVICE_SPIRegs *) 0x01E12000u)
968 #define SPI_PERIPHERAL_CNT (2)
970 #define DEVICE_SPI_SPIGCR1_SPIEN_MASK (0x01000000u)
971 #define DEVICE_SPI_SPIGCR1_SPIEN_SHIFT (24)
973 typedef struct _DEVICE_SDMMC_REGS_
974 {
975 VUint32 MMCCTL;
976 VUint32 MMCCLK;
977 VUint32 MMCST0;
978 VUint32 MMCST1;
979 VUint32 MMCIM;
980 VUint32 MMCTOR;
981 VUint32 MMCTOD;
982 VUint32 MMCBLEN;
983 VUint32 MMCNBLK;
984 VUint32 MMCNBLC;
985 VUint32 MMCDRR;
986 VUint32 MMCDXR;
987 VUint32 MMCCMD;
988 VUint32 MMCARGHL;
989 VUint32 MMCRSP01;
990 VUint32 MMCRSP23;
991 VUint32 MMCRSP45;
992 VUint32 MMCRSP67;
993 VUint32 MMCDRSP;
994 VUint8 RSVD0[4];
995 VUint32 MMCCIDX;
996 VUint8 RSVD1[16];
997 VUint32 SDIOCTL;
998 VUint32 SDIOST0;
999 VUint32 SDIOIEN;
1000 VUint32 SDIOIST;
1001 VUint32 MMCFIFOCTL;
1002 }
1003 DEVICE_SDMMCRegs;
1005 #define SDMMC0 ((DEVICE_SDMMCRegs *) 0x01C40000)
1006 #define SDMMC1 ((DEVICE_SDMMCRegs *) 0x01E1B000)
1008 #define SDMMC_PERIPHERAL_CNT (2)
1011 // GPIO Register structures
1012 typedef struct _DEVICE_GPIO_BANK_REGS_
1013 {
1014 VUint16 DIR[2];
1015 VUint16 OUT_DATA[2];
1016 VUint16 SET_DATA[2];
1017 VUint16 CLR_DATA[2];
1018 VUint16 IN_DATA[2];
1019 VUint16 SET_RIS_TRIG[2];
1020 VUint16 CLR_RIS_TRIG[2];
1021 VUint16 SET_FAL_TRIG[2];
1022 VUint16 CLR_FAL_TRIG[2];
1023 VUint16 INTSTAT[2];
1024 }
1025 DEVICE_GPIOBankRegs;
1027 typedef struct _DEVICE_GPIO_REGS_
1028 {
1029 VUint32 PID;
1030 VUint32 PCR;
1031 VUint32 BINTEN;
1032 VUint8 RSVD0[4];
1033 DEVICE_GPIOBankRegs BANKPAIR[4];
1034 } DEVICE_GPIORegs;
1036 #define GPIO ((DEVICE_GPIORegs *) 0x01E26000u)
1040 /***********************************************************
1041 * Global Function Declarations *
1042 ***********************************************************/
1044 // Execute LPSC state transition
1045 extern __FAR__ void DEVICE_LPSCTransition(Uint8 pscnum, Uint8 module, Uint8 domain, Uint8 state);
1047 // Pinmux control function
1048 extern __FAR__ void DEVICE_pinmuxControl(Uint32 regOffset, Uint32 mask, Uint32 value);
1050 // Kick register lock/unlock functions
1051 extern __FAR__ void DEVICE_kickUnlock(void);
1052 extern __FAR__ void DEVICE_kickLock(void);
1054 // Initialization prototypes
1055 extern __FAR__ Uint32 DEVICE_init(void);
1056 extern __FAR__ void DEVICE_PSCInit();
1057 extern __FAR__ Uint32 DEVICE_PLL0Init(Uint8 clk_src,Uint8 pllm, Uint8 postdiv, Uint8 div3, Uint8 div5, Uint8 div7, Uint16 lock_time );
1058 extern __FAR__ Uint32 DEVICE_ExternalMemInit(Uint32 sdcr, Uint32 sdtimr1, Uint32 sdtimr2, Uint32 sdrcr, Bool use45Div);
1060 // Peripheral Initialization prototypes
1061 extern __FAR__ Uint32 DEVICE_UARTInit(Uint8 periphNum);
1062 extern __FAR__ Uint32 DEVICE_SPIInit(Uint8 periphNum);
1063 extern __FAR__ Uint32 DEVICE_I2CInit(Uint8 periphNum);
1064 extern __FAR__ Uint32 DEVICE_AsyncMemInit(Uint8 interfaceNum);
1065 extern __FAR__ Uint32 DEVICE_TIMER0Init(void);
1067 // Device boot status functions
1068 extern __FAR__ DEVICE_BootMode DEVICE_bootMode( void );
1069 extern __FAR__ DEVICE_BootPeripheral DEVICE_bootPeripheral(void);
1070 extern __FAR__ DEVICE_BusWidth DEVICE_emifBusWidth( void );
1071 extern __FAR__ DEVICE_ChipRevIDType DEVICE_chipRevIDType( void );
1073 extern __FAR__ void DEVICE_TIMER0Start(void);
1074 extern __FAR__ void DEVICE_TIMER0Stop(void);
1075 extern __FAR__ Uint32 DEVICE_TIMER0Status(void);
1078 /***********************************************************
1079 * End file *
1080 ***********************************************************/
1082 #ifdef __cplusplus
1083 }
1084 #endif
1086 #endif // End _DEVICE_H_