[processor-sdk/pdk.git] / packages / ti / boot / sbl / tools / omapl13x_boot_utils / OMAP-L138 / Common / include / device.h
1 /* --------------------------------------------------------------------------
2 FILE : device.h
3 PROJECT : DA8xx/OMAP-L138 ROM Boot Loader
4 AUTHOR : Daniel Allred
5 DESC : Provides device differentiation for the project files. This
6 file MUST be modified to match the device specifics.
7 ----------------------------------------------------------------------------- */
9 #ifndef _DEVICE_H_
10 #define _DEVICE_H_
12 #include "tistdtypes.h"
14 // Prevent C++ name mangling
15 #ifdef __cplusplus
16 extern far "c" {
17 #endif
19 /***********************************************************
20 * Global Macro Declarations *
21 ***********************************************************/
24 /************************************************************
25 * Global Variable Declarations *
26 ************************************************************/
28 extern const char devString[];
31 /******************************************************
32 * Global Typedef declarations *
33 ******************************************************/
35 typedef enum _DEVICE_CacheType_
36 {
37 DEVICE_CACHETYPE_L1P = 0x0,
38 DEVICE_CACHETYPE_L1D = 0x1,
39 DEVICE_CACHETYPE_L2 = 0x2
40 }
41 DEVICE_CacheType;
43 // Supported buswidth
44 typedef enum _DEVICE_BUSWIDTH_
45 {
46 DEVICE_BUSWIDTH_8BIT = BUS_8BIT,
47 DEVICE_BUSWIDTH_16BIT = BUS_16BIT
48 }
49 DEVICE_BusWidth;
51 typedef enum _DEVICE_CHIPREVID_TYPE_
52 {
53 DEVICE_CHIPREVID_TYPE_DSPONLY = 0x0,
54 DEVICE_CHIPREVID_TYPE_ARMONLY = 0x1,
55 DEVICE_CHIPREVID_TYPE_DSPBOOT = 0x2,
56 DEVICE_CHIPREVID_TYPE_ARMBOOT = 0x3
57 }
58 DEVICE_ChipRevIDType;
60 typedef enum _DEVICE_BOOTPERIPHERAL_
61 {
62 DEVICE_BOOTPERIPHERAL_NONE = 0,
63 DEVICE_BOOTPERIPHERAL_NOR,
64 DEVICE_BOOTPERIPHERAL_UHPI,
65 DEVICE_BOOTPERIPHERAL_SPI,
66 DEVICE_BOOTPERIPHERAL_I2C,
67 DEVICE_BOOTPERIPHERAL_NAND,
68 DEVICE_BOOTPERIPHERAL_USB,
69 DEVICE_BOOTPERIPHERAL_UART,
70 DEVICE_BOOTPERIPHERAL_SDMMC,
71 DEVICE_BOOTPERIPHERAL_RMII,
72 DEVICE_BOOTPERIPHERAL_ESF
73 }
74 DEVICE_BootPeripheral;
76 typedef enum _DEVICE_BOOTMODE_
77 {
78 DEVICE_BOOTMODE_NONE = 0,
79 DEVICE_BOOTMODE_EMU_DEBUG,
80 DEVICE_BOOTMODE_NOR_EMIFA,
81 DEVICE_BOOTMODE_NAND_EMIFA_8BIT,
82 DEVICE_BOOTMODE_NAND_EMIFA_16BIT,
83 DEVICE_BOOTMODE_UHPI, // 16 bit
84 DEVICE_BOOTMODE_SPI0_FLASH, // 24 bit address
85 DEVICE_BOOTMODE_SPI0_EEPROM, // 16 bit address
86 DEVICE_BOOTMODE_SPI0_SLAVE, // 16 bit data
87 DEVICE_BOOTMODE_SPI1_FLASH, // 24 bit address
88 DEVICE_BOOTMODE_SPI1_EEPROM, // 16 bit address
89 DEVICE_BOOTMODE_SPI1_SLAVE, // 16 bit data
90 DEVICE_BOOTMODE_I2C0_MASTER, // 16 bit address
91 DEVICE_BOOTMODE_I2C0_SLAVE, // 16 bit data
92 DEVICE_BOOTMODE_I2C1_MASTER, // 16 bit address
93 DEVICE_BOOTMODE_I2C1_SLAVE, // 16 bit data
94 DEVICE_BOOTMODE_UART0,
95 DEVICE_BOOTMODE_UART1,
96 DEVICE_BOOTMODE_UART2,
97 DEVICE_BOOTMODE_ESF,
98 DEVICE_BOOTMODE_SDMMC0,
99 DEVICE_BOOTMODE_SDMMC1,
100 DEVICE_BOOTMODE_USB11, // Not supported
101 DEVICE_BOOTMODE_USB20, // Not supported
102 DEVICE_BOOTMODE_THB = 0xAA
103 }
104 DEVICE_BootMode;
106 // C6740 Megamodule Power Down Controller
107 typedef struct _DEVICE_C6740_PDC_
108 {
109 VUint32 PDCCMD;
110 }
111 DEVICE_C6740_PDCRegs;
113 #define PDC ((DEVICE_C6740_PDCRegs *) 0x01810000)
115 // C6740 IDMA
116 typedef struct _DEVICE_C6740_IDMA_
117 {
118 VUint32 STAT;
119 VUint32 MASK;
120 VUint32 SOURCE;
121 VUint32 DEST;
122 VUint32 CNT;
123 }
124 DEVICE_C6740_IDMARegs;
126 #define IDMA0 ((DEVICE_C6740_IDMARegs *) 0x01820000)
127 #define IDMA1 ((DEVICE_C6740_IDMARegs *) 0x01820100)
129 // C6740 L1P Control
130 typedef struct _DEVICE_C6740_L1P_
131 {
132 VUint8 RSVD0[0x20]; // 0x0000
133 VUint32 L1PCFG; // 0x0020
134 VUint32 L1PCC; // 0x0024
135 VUint8 RSVD1[0x3FF8]; // 0x0028
136 VUint32 L1PIBAR; // 0x4020
137 VUint32 L1PIWC; // 0x4024
138 VUint8 RSVD2[0x1000]; // 0x4028
139 VUint32 L1PINV; // 0x5028
140 }
141 DEVICE_C6740_L1PRegs;
143 #define L1PCTL ((DEVICE_C6740_L1PRegs *) 0x01840000)
145 // C6740 L1D Control
146 typedef struct _DEVICE_C6740_L1D_
147 {
148 VUint8 RSVD0[0x40]; // 0x0000
149 VUint32 L1DCFG; // 0x0040
150 VUint32 L1DCC; // 0x0044
151 VUint8 RSVD1[0x3FE8]; // 0x0048
152 VUint32 L1DWIBAR; // 0x4030
153 VUint32 L1DWIWC; // 0x4034
154 VUint8 RSVD2[0x08]; // 0x4038
155 VUint32 L1DWBAR; // 0x4040
156 VUint32 L1DWWC; // 0x4044
157 VUint32 L1DIBAR; // 0x4048
158 VUint32 L1DIWC; // 0x404C
159 VUint8 RSVD3[0xFF0]; // 0x4050
160 VUint32 L1DWB; // 0x5040
161 VUint32 L1DWBINV; // 0x5044
162 VUint32 L1DINV; // 0x5048
163 }
164 DEVICE_C6740_L1DRegs;
166 #define L1DCTL ((DEVICE_C6740_L1DRegs *) 0x01840000)
169 // C6740 L2 Control
170 typedef struct _DEVICE_C6740_L2_
171 {
172 VUint32 L2CFG; // 0x0000
173 VUint8 RSVD0[0x3FFC]; // 0x0004
174 VUint32 L2WBAR; // 0x4000
175 VUint32 L2WWC; // 0x4004
176 VUint8 RSVD1[0x08]; // 0x4008
177 VUint32 L2WIBAR; // 0x4010
178 VUint32 L2WIWC; // 0x4014
179 VUint32 L2IBAR; // 0x4018
180 VUint32 L2IWC; // 0x401C
181 VUint8 RSVD2[0xFE0]; // 0x4020
182 VUint32 L2WB; // 0x5000
183 VUint32 L2WBINV; // 0x5004
184 VUint32 L2INV; // 0x5008
185 }
186 DEVICE_C6740_L2Regs;
188 #define L2CTL ((DEVICE_C6740_L2Regs *) 0x01840000)
191 // C6740 Megamodule memory error controller
192 typedef struct _DEVICE_C6740_EDC_
193 {
194 VUint8 RSVD0[4]; // 0x000
195 VUint32 L2EDSTAT; // 0x004
196 VUint32 L2EDCMD; // 0x008
197 VUint32 L2EDADDR; // 0x00C
198 VUint32 L2EDPEN0; // 0x010
199 VUint32 L2EDPEN1; // 0x014
200 VUint32 L2EDCPEC; // 0x018
201 VUint32 L2EDNPEC; // 0x01C
202 VUint8 RSVD1[0x3E4]; // 0x020
203 VUint32 L1PEDSTAT; // 0x404
204 VUint32 L1PEDCMD; // 0x408
205 VUint32 L1PEDADDR; // 0x40C
206 }
207 DEVICE_C6740_EDCRegs;
209 #define DSP_EDC ((DEVICE_C6740_EDCRegs *) 0x01846000)
212 // C6740 Megamodule Interrupt Controller
213 typedef struct _DEVICE_C6740_INTC_
214 {
215 VUint32 EVTFLAG[4]; // 0x000
216 VUint8 RSVD0[16]; // 0x010
217 VUint32 EVTSET[4]; // 0x020
218 VUint8 RSVD1[16]; // 0x030
219 VUint32 EVTCLR[4]; // 0x040
220 VUint8 RSVD2[48]; // 0x050
221 VUint32 EVTMASK[4]; // 0x080
222 VUint8 RSVD3[16]; // 0x090
223 VUint32 MEVTFLAG[4]; // 0x0A0
224 VUint8 RSVD4[16]; // 0x0B0
225 VUint32 EXPMASK[4]; // 0x0C0
226 VUint8 RSVD5[16];
227 VUint32 MEXPFLAG[4];
228 VUint8 RSVD6[20];
229 VUint32 INTMUX1;
230 VUint32 INTMUX2;
231 VUint32 INTMUX3;
232 VUint8 RSVD7[48];
233 VUint32 AEGMUX0;
234 VUint32 AEGMUX1;
235 VUint8 RSVD8[56];
236 VUint32 INTXSTAT;
237 VUint32 INTXCLR;
238 VUint32 INTDMASK;
239 VUint8 RSVD9[52];
240 VUint32 EVTASRT;
241 }
242 DEVICE_C6740_INTCRegs;
244 #define DSP_INTC ((DEVICE_C6740_INTCRegs *) 0x01800000)
247 // System Control Module register structure
248 typedef struct _DEVICE_SYS_MODULE_REGS_
249 {
250 VUint32 REVID; //0x00
251 VUint8 RSVD0[4]; //0x04
252 VUint32 DIEIDR[4]; //0x08
253 VUint32 DEVIDD[2]; //0x18
254 VUint32 BOOTCFG; //0x20
255 VUint32 CHIPREVID; //0x24
256 VUint32 FEATURE_ENA; //0x28
257 VUint32 L2ROMDIV; //0x2C
258 VUint8 RSVD1[8]; //0x30
259 VUint32 KICKR[2]; //0x38
260 VUint32 HOSTCFG[2]; //0x40
261 VUint8 RSVD2[152]; //0x48
262 VUint32 IRAWSTRAT; //0xE0
263 VUint32 IENSTAT; //0xE4
264 VUint32 IENSET; //0xE8
265 VUint32 IENCLR; //0xEC
266 VUint32 EOI; //0xF0
267 VUint32 FLTADDRR; //0xF4
268 VUint32 FLTSTAT; //0xF8
269 VUint32 FLTCLR; //0xFC
270 VUint8 RSVD3[16]; //0x100
271 VUint32 MSTPRI[3]; //0x110
272 VUint8 RSVD4[4]; //0x11C
273 VUint32 PINMUX[20]; //0x120
274 VUint32 SUSPSRC; //0x170
275 VUint32 CHIPSIG; //0x174
276 VUint32 CHIPSIG_CLR; //0x178
277 VUint32 CFGCHIP[5]; //0x17C
278 VUint8 RSVD5[5]; //0x190
279 VUint32 ROMCHECKSUM[2]; //0x1A0
280 }
281 DEVICE_SysModuleRegs;
283 #define SYSTEM ((DEVICE_SysModuleRegs*) 0x01C14000)
285 #define DEVICE_BOOTCFG_BOOTMODE_MASK (0x000000FFu)
286 #define DEVICE_BOOTCFG_BOOTMODE_SHIFT (0)
288 #define DEVICE_CHIPREVID_TYPE_MASK (0x00000030u)
289 #define DEVICE_CHIPREVID_TYPE_SHIFT (4)
291 #define DEVICE_CFGCHIP0_PLL0MASTERLOCK_MASK (0x00000010u)
292 #define DEVICE_CFGCHIP0_PLL0MASTERLOCK_SHIFT (4)
294 #define DEVICE_CFGCHIP1_HPIBYTEAD_MASK (0x00010000u)
295 #define DEVICE_CFGCHIP1_HPIBYTEAD_SHIFT (16)
296 #define DEVICE_CFGCHIP1_HPIENA_MASK (0x00008000u)
297 #define DEVICE_CFGCHIP1_HPIENA_SHIFT (15)
299 #define DEVICE_CFGCHIP3_RMII_MODE_MASK (0x00000100u)
300 #define DEVICE_CFGCHIP3_RMII_MODE_SHIFT (8)
301 #define DEVICE_CFGCHIP3_EMB_2XCLKSRC_MASK (0x00000080u)
302 #define DEVICE_CFGCHIP3_EMB_2XCLKSRC_SHIFT (7)
303 #define DEVICE_CFGCHIP3_RPI_TXCLKSRC_MASK (0x00000040u)
304 #define DEVICE_CFGCHIP3_RPI_TXCLKSRC_SHIFT (6)
305 #define DEVICE_CFGCHIP3_PLL1MASTERLOCK_MASK (0x00000020u)
306 #define DEVICE_CFGCHIP3_PLL1MASTERLOCK_SHIFT (5)
307 #define DEVICE_CFGCHIP3_ASYNC3_CLKSRC_MASK (0x00000010u)
308 #define DEVICE_CFGCHIP3_ASYNC3_CLKSRC_SHIFT (4)
309 #define DEVICE_CFGCHIP3_PRUEVTSEL_MASK (0x00000008u)
310 #define DEVICE_CFGCHIP3_PRUEVTSEL_SHIFT (3)
311 #define DEVICE_CFGCHIP3_DIV4p5ENA_MASK (0x00000004u)
312 #define DEVICE_CFGCHIP3_DIV4p5ENA_SHIFT (2)
313 #define DEVICE_CFGCHIP3_EMA_CLKSRC_MASK (0x00000002u)
314 #define DEVICE_CFGCHIP3_EMA_CLKSRC_SHIFT (1)
316 #define DEVICE_L2ROMDIV_ADDRLINE_MASK (0x000003FFu)
317 #define DEVICE_L2ROMDIV_ADDRLINE_SHIFT (0)
319 typedef struct _DEVICE_SUBSCHIP_CONFIG_REGS_
320 {
321 VUint32 VTPIO_CTL;
322 VUint32 DDR_SLEW;
323 VUint32 DEEPSLEEP;
324 VUint32 PUPD_ENA;
325 VUint32 PUPD_SEL;
326 VUint32 RXACTIVE;
327 VUint32 RSVD0[2];
328 }
329 DEVICE_SubchipConfigRegs;
331 #define SUBCHIPCFG ((DEVICE_SubchipConfigRegs*) 0x01E2C000)
333 #define DEVICE_VTPIO_CTL_READY_MASK (0x00008000u)
334 #define DEVICE_VTPIO_CTL_READY_SHIFT (15)
335 #define DEVICE_VTPIO_CTL_IOPWRDN_MASK (0x00004000u)
336 #define DEVICE_VTPIO_CTL_IOPWRDN_SHIFT (14)
337 #define DEVICE_VTPIO_CTL_CLKRZ_MASK (0x00002000u)
338 #define DEVICE_VTPIO_CTL_CLKRZ_SHIFT (13)
339 #define DEVICE_VTPIO_CTL_PWRSAVE_MASK (0x00000100u)
340 #define DEVICE_VTPIO_CTL_PWRSAVE_SHIFT (8)
341 #define DEVICE_VTPIO_CTL_LOCK_MASK (0x00000080u)
342 #define DEVICE_VTPIO_CTL_LOCK_SHIFT (7)
343 #define DEVICE_VTPIO_CTL_POWERDN_MASK (0x00000040u)
344 #define DEVICE_VTPIO_CTL_POWERDN_SHIFT (6)
347 // ARM Interrupt Controller register structure
348 typedef struct _DEVICE_AINTC_REGS_
349 {
350 VUint32 FIQ0;
351 VUint32 FIQ1;
352 VUint32 IRQ0;
353 VUint32 IRQ1;
354 VUint32 FIQENTRY;
355 VUint32 IRQENTRY;
356 VUint32 EINT0;
357 VUint32 EINT1;
358 VUint32 INTCTL;
359 VUint32 EABASE;
360 VUint8 RSVD0[8];
361 VUint32 INTPRI0;
362 VUint32 INTPRI1;
363 VUint32 INTPRI2;
364 VUint32 INTPRI3;
365 VUint32 INTPRI4;
366 VUint32 INTPRI5;
367 VUint32 INTPRI6;
368 VUint32 INTPRI7;
369 }
370 DEVICE_AIntcRegs;
372 #define AINTC ((DEVICE_AIntcRegs*) 0xFFFEE000)
375 // PRU Control register structure
376 typedef struct _DEVICE_PRU_CTRL_REGS_
377 {
378 VUint32 CONTROL;
379 VUint32 STATUS;
380 VUint32 WAKEUP;
381 VUint32 CYCLECNT;
382 VUint32 STALLCNT;
383 VUint8 RSVD0[12];
384 VUint32 CONTABBLKIDX0;
385 VUint32 CONTABBLKIDX1;
386 VUint32 CONTABPROPTR0;
387 VUint32 CONTABPROPTR1;
388 VUint8 RSVD1[976];
389 VUint32 INTGPR0;
390 VUint32 INTGPR1;
391 VUint32 INTGPR2;
392 VUint32 INTGPR3;
393 VUint32 INTGPR4;
394 VUint32 INTGPR5;
395 VUint32 INTGPR6;
396 VUint32 INTGPR7;
397 VUint32 INTGPR8;
398 VUint32 INTGPR9;
399 VUint32 INTGPR10;
400 VUint32 INTGPR11;
401 VUint32 INTGPR12;
402 VUint32 INTGPR13;
403 VUint32 INTGPR14;
404 VUint32 INTGPR15;
405 VUint32 INTGPR16;
406 VUint32 INTGPR17;
407 VUint32 INTGPR18;
408 VUint32 INTGPR19;
409 VUint32 INTGPR20;
410 VUint32 INTGPR21;
411 VUint32 INTGPR22;
412 VUint32 INTGPR23;
413 VUint32 INTGPR24;
414 VUint32 INTGPR25;
415 VUint32 INTGPR26;
416 VUint32 INTGPR27;
417 VUint32 INTGPR28;
418 VUint32 INTGPR29;
419 VUint32 INTGPR30;
420 VUint32 INTGPR31;
421 VUint32 INTCTER0;
422 VUint32 INTCTER1;
423 VUint32 INTCTER2;
424 VUint32 INTCTER3;
425 VUint32 INTCTER4;
426 VUint32 INTCTER5;
427 VUint32 INTCTER6;
428 VUint32 INTCTER7;
429 VUint32 INTCTER8;
430 VUint32 INTCTER9;
431 VUint32 INTCTER10;
432 VUint32 INTCTER11;
433 VUint32 INTCTER12;
434 VUint32 INTCTER13;
435 VUint32 INTCTER14;
436 VUint32 INTCTER15;
437 VUint32 INTCTER16;
438 VUint32 INTCTER17;
439 VUint32 INTCTER18;
440 VUint32 INTCTER19;
441 VUint32 INTCTER20;
442 VUint32 INTCTER21;
443 VUint32 INTCTER22;
444 VUint32 INTCTER23;
445 VUint32 INTCTER24;
446 VUint32 INTCTER25;
447 VUint32 INTCTER26;
448 VUint32 INTCTER27;
449 VUint32 INTCTER28;
450 VUint32 INTCTER29;
451 VUint32 INTCTER30;
452 VUint32 INTCTER31;
453 }
454 DEVICE_PRUCtrlRegs;
456 #define PRU0 ((DEVICE_PRUCtrlRegs *) 0x01C37000)
457 #define PRU1 ((DEVICE_PRUCtrlRegs *) 0x01C37800)
459 #define DEVICE_PRU_CONTROL_COUNTENABLE_MASK (0x00000008u)
460 #define DEVICE_PRU_CONTROL_COUNTENABLE_SHIFT (3)
461 #define DEVICE_PRU_CONTROL_ENABLE_MASK (0x00000002u)
462 #define DEVICE_PRU_CONTROL_ENABLE_SHIFT (1)
463 #define DEVICE_PRU_CONTROL_SOFTRESET_MASK (0x00000001u)
464 #define DEVICE_PRU_CONTROL_SOFTRESET_SHIFT (0)
465 #define DEVICE_PRU_CONTROL_RUNSTATE_MASK (0x00008000u)
466 #define DEVICE_PRU_CONTROL_RUNSTATE_SHIFT (15)
469 // PLL Register structure
470 typedef struct _DEVICE_PLL_REGS_
471 {
472 VUint32 PID; // 0x000
473 VUint8 RSVD0[204]; // 0x004
474 VUint32 SHIFTDIV; // 0x0D0
475 VUint32 CS0; // 0x0D4
476 VUint32 DFTCNTR; // 0x0D8
477 VUint32 DFTCNTRCTRL; // 0x0DC
478 VUint32 FUSERR; // 0x0E0
479 VUint32 RSTYPE; // 0x0E4
480 VUint32 RSTCTRL; // 0x0E8
481 VUint32 RSTCFG; // 0x0EC
482 VUint32 RSISO; // 0x0F0
483 VUint8 RSVD1[12]; // 0x0F4
484 VUint32 PLLCTL; // 0x100
485 VUint32 OCSEL; // 0x104
486 VUint32 SECCTL; // 0x108
487 VUint8 RSVD2[4]; // 0x10C
488 VUint32 PLLM; // 0x110
489 VUint32 PREDIV;
490 VUint32 PLLDIV1;
491 VUint32 PLLDIV2;
492 VUint32 PLLDIV3;
493 VUint32 OSCDIV1;
494 VUint32 POSTDIV;
495 VUint32 BPDIV;
496 VUint32 WAKEUP;
497 VUint8 RSVD3[4];
498 VUint32 PLLCMD;
499 VUint32 PLLSTAT;
500 VUint32 ALNCTL;
501 VUint32 DCHANGE;
502 VUint32 CKEN;
503 VUint32 CKSTAT;
504 VUint32 SYSTAT;
505 VUint8 RSVD4[12];
506 VUint32 PLLDIV4;
507 VUint32 PLLDIV5;
508 VUint32 PLLDIV6;
509 VUint32 PLLDIV7;
510 VUint32 PLLDIV8;
511 VUint32 PLLDIV9;
512 VUint32 PLLDIV10;
513 VUint32 PLLDIV11;
514 VUint32 PLLDIV12;
515 VUint32 PLLDIV13;
516 VUint32 PLLDIV14;
517 VUint8 RSVD5[4];
518 VUint32 PLLDIV15;
519 VUint8 RSVD6[88];
520 VUint32 PLLHDIVEN;
521 VUint32 EMUCNT0;
522 VUint32 EMUCNT1;
523 }
524 DEVICE_PLLRegs;
526 #define PLL0 ((DEVICE_PLLRegs*) 0x01C11000)
527 #define PLL1 ((DEVICE_PLLRegs*) 0x01E1A000)
529 #define DEVICE_PLLCTL_PLLEN_MASK (0x00000001)
530 #define DEVICE_PLLCTL_PLLPWRDN_MASK (0x00000002)
531 #define DEVICE_PLLCTL_PLLRST_MASK (0x00000008)
532 #define DEVICE_PLLCTL_PLLDIS_MASK (0x00000010)
533 #define DEVICE_PLLCTL_PLLENSRC_MASK (0x00000020)
534 #define DEVICE_PLLCTL_EXTCLKSRC_MASK (0x00000200)
535 #define DEVICE_PLLCTL_CLKMODE_MASK (0x00000100)
537 #define DEVICE_PLLCMD_GOSET_MASK (0x00000001)
538 #define DEVICE_PLLSTAT_GOSTAT_MASK (0x00000001)
539 #define DEVICE_PLLDIV_EN_MASK (0x00008000)
541 // Power/Sleep Ctrl Register structure
542 typedef struct _DEVICE_PSC_REGS_
543 {
544 VUint32 PID; // 0x000
545 VUint8 RSVD0[16]; // 0x004
546 VUint8 RSVD1[4]; // 0x014
547 VUint32 INTEVAL; // 0x018
548 VUint8 RSVD2[36]; // 0x01C
549 VUint32 MERRPR0; // 0x040
550 VUint32 MERRPR1; // 0x044
551 VUint8 RSVD3[8]; // 0x048
552 VUint32 MERRCR0; // 0x050
553 VUint32 MERRCR1; // 0x054
554 VUint8 RSVD4[8]; // 0x058
555 VUint32 PERRPR; // 0x060
556 VUint8 RSVD5[4]; // 0x064
557 VUint32 PERRCR; // 0x068
558 VUint8 RSVD6[4]; // 0x06C
559 VUint32 EPCPR; // 0x070
560 VUint8 RSVD7[4]; // 0x074
561 VUint32 EPCCR; // 0x078
562 VUint8 RSVD8[144]; // 0x07C
563 VUint8 RSVD9[20]; // 0x10C
564 VUint32 PTCMD; // 0x120
565 VUint8 RSVD10[4]; // 0x124
566 VUint32 PTSTAT; // 0x128
567 VUint8 RSVD11[212]; // 0x12C
568 VUint32 PDSTAT0; // 0x200
569 VUint32 PDSTAT1; // 0x204
570 VUint8 RSVD12[248]; // 0x208
571 VUint32 PDCTL0; // 0x300
572 VUint32 PDCTL1; // 0x304
573 VUint8 RSVD13[536]; // 0x308
574 VUint32 MCKOUT0; // 0x520
575 VUint32 MCKOUT1; // 0x524
576 VUint8 RSVD14[728]; // 0x528
577 VUint32 MDSTAT[41]; // 0x800
578 VUint8 RSVD15[348]; // 0x8A4
579 VUint32 MDCTL[41]; // 0xA00
580 }
581 DEVICE_PSCRegs;
583 #define PSC0 ((DEVICE_PSCRegs*) 0x01C10000)
584 #define PSC1 ((DEVICE_PSCRegs*) 0x01E27000)
586 #define EMURSTIE_MASK (0x00000200)
588 #define PSC_ENABLE (0x3)
589 #define PSC_DISABLE (0x2)
590 #define PSC_SYNCRESET (0x1)
591 #define PSC_SWRSTDISABLE (0x0)
593 #define PSC_MDCTL_LRSTZ_MASK (0x00000100u)
594 #define PSC_MDCTL_LRSTZ_SHIFT (0x00000008u)
596 #define PSCNUM0 (0x0)
597 #define PSCNUM1 (0x1)
599 #define PD0 (0x0)
600 #define PD1 (0x1)
602 // PSC0 (Matrix) defines
603 #define LPSC_TPCC (0)
604 #define LPSC_TPTC0 (1)
605 #define LPSC_TPTC1 (2)
606 #define LPSC_EMIFA (3)
607 #define LPSC_SPI0 (4)
608 #define LPSC_SDMMC0 (5)
609 #define LPSC_ARMINTC (6)
610 #define LPSC_ARMRAM (7)
611 #define LPSC_SCnKM (8)
612 #define LPSC_UART0 (9)
613 #define LPSC_PRU (13)
614 #define LPSC_ARM (14)
615 #define LPSC_DSP (15)
617 // PSC1 (Subchip) defines
618 #define LPSC_TPCC1 (0)
619 #define LPSC_USB0 (1)
620 #define LPSC_USB1 (2)
621 #define LPSC_GPIO (3)
622 #define LPSC_UHPI0 (4)
623 #define LPSC_EMAC (5)
624 #define LPSC_EMIFB (6)
625 #define LPSC_McASP0 (7)
626 #define LPSC_SATA (8)
627 #define LPSC_VPIF (9)
628 #define LPSC_SPI1 (10)
629 #define LPSC_I2C1 (11)
630 #define LPSC_UART1 (12)
631 #define LPSC_UART2 (13)
632 #define LPSC_McBSP0 (14)
633 #define LPSC_McBSP1 (15)
634 #define LPSC_LCDC (16)
635 #define LPSC_HR_EPWM (17)
636 #define LPSC_SDMMC1 (18)
637 #define LPSC_UPP (19)
638 #define LPSC_ECAP (20)
639 #define LPSC_TPTC2 (21)
640 #define LPSC_L3CBA (31)
643 // AEMIF Register structure - From EMIF 2.5 Spec
644 typedef struct _DEVICE_EMIF25_REGS_
645 {
646 VUint32 ERCSR; // 0x00
647 VUint32 AWCCR; // 0x04
648 VUint32 SDBCR; // 0x08
649 VUint32 SDRCR; // 0x0C
651 VUint32 A1CR; // 0x10
652 VUint32 A2CR; // 0x14
653 VUint32 A3CR; // 0x18
654 VUint32 A4CR; // 0x1C
656 VUint32 SDTIMR; // 0x20
657 VUint32 SDRSTAT; // 0x24
658 VUint32 DDRPHYCR; // 0x28
659 VUint32 DDRPHYSR; // 0x2C
661 VUint32 SDRACCR; // 0x30
662 VUint32 SDRACT; // 0x34
663 VUint32 DDRPHYREV; // 0x38
664 VUint32 SDRSRPDEXIT; // 0x3C
666 VUint32 EIRR; // 0x40
667 VUint32 EIMR; // 0x44
668 VUint32 EIMSR; // 0x48
669 VUint32 EIMCR; // 0x4C
671 VUint32 IOCR; // 0x50
672 VUint32 IOSR; // 0x54
673 VUint8 RSVD0[4]; // 0x58
674 VUint32 ONENANDCTL; // 0x5C
676 VUint32 NANDFCR; // 0x60
677 VUint32 NANDFSR; // 0x64
678 VUint32 PMCR; // 0x68
679 VUint8 RSVD1[4]; // 0x6C
681 VUint32 NANDF1ECC; // 0x70
682 VUint32 NANDF2ECC; // 0x74
683 VUint32 NANDF3ECC; // 0x78
684 VUint32 NANDF4ECC; // 0x7C
686 VUint8 RSVD2[4]; // 0x80
687 VUint32 IODFTEXECNT; // 0x84
688 VUint32 IODFTGBLCTRL; // 0x88
689 VUint8 RSVD3[4]; // 0x8C
691 VUint32 IODFTMISRLSB; // 0x90
692 VUint32 IODFTMISRMID; // 0x94
693 VUint32 IODFTMISRMSB; // 0x98
694 VUint8 RSVD4[20]; // 0x9C
696 VUint32 MODRELNUM; // 0xB0
697 VUint8 RSVD5[8]; // 0xB4
698 VUint32 NAND4BITECCLOAD; // 0xBC
700 VUint32 NAND4BITECC1; // 0xC0
701 VUint32 NAND4BITECC2; // 0xC4
702 VUint32 NAND4BITECC3; // 0xC8
703 VUint32 NAND4BITECC4; // 0xCC
705 VUint32 NANDERRADD1; // 0xD0
706 VUint32 NANDERRADD2; // 0xD4
707 VUint32 NANDERRVAL1; // 0xD8
708 VUint32 NANDERRVAL2; // 0xDC
709 }
710 DEVICE_Emif25Regs;
712 #define AEMIF ((DEVICE_Emif25Regs*) 0x68000000u)
714 #define DEVICE_EMIF_NUMBER_CE_REGION (4)
715 #define DEVICE_EMIF_FIRST_CE_START_ADDR (0x60000000u)
716 #define DEVICE_EMIF_INTER_CE_REGION_SIZE (0x02000000u)
717 #define DEVICE_EMIF_NAND_BUS_WIDTH DEVICE_BUSWIDTH_8BIT
718 #define DEVICE_EMIF_NAND_BOOT_BASE (0X62000000u)
719 #define DEVICE_EMIF_NAND_BOOT_CE (3)
720 #define DEVICE_EMIF_NOR_BOOT_CE (0x60000000u)
722 #define DEVICE_EMIF_AxCR_SS_MASK (0x80000000u)
723 #define DEVICE_EMIF_AxCR_SS_SHIFT (31)
724 #define DEVICE_EMIF_AxCR_EW_MASK (0x40000000u)
725 #define DEVICE_EMIF_AxCR_EW_SHIFT (30)
726 #define DEVICE_EMIF_AxCR_WSETUP_MASK (0x3C000000u)
727 #define DEVICE_EMIF_AxCR_WSETUP_SHIFT (26)
728 #define DEVICE_EMIF_AxCR_WSTROBE_MASK (0x03F00000u)
729 #define DEVICE_EMIF_AxCR_WSTROBE_SHIFT (20)
730 #define DEVICE_EMIF_AxCR_WHOLD_MASK (0x000E0000u)
731 #define DEVICE_EMIF_AxCR_WHOLD_SHIFT (17)
732 #define DEVICE_EMIF_AxCR_RSETUP_MASK (0x0001E000u)
733 #define DEVICE_EMIF_AxCR_RSETUP_SHIFT (13)
734 #define DEVICE_EMIF_AxCR_RSTROBE_MASK (0x00001F80u)
735 #define DEVICE_EMIF_AxCR_RSTROBE_SHIFT (7)
736 #define DEVICE_EMIF_AxCR_RHOLD_MASK (0x00000070u)
737 #define DEVICE_EMIF_AxCR_RHOLD_SHIFT (4)
738 #define DEVICE_EMIF_AxCR_TA_MASK (0x0000000Cu)
739 #define DEVICE_EMIF_AxCR_TA_SHIFT (2)
740 #define DEVICE_EMIF_AxCR_ASIZE_MASK (0x00000003u)
741 #define DEVICE_EMIF_AxCR_ASIZE_SHIFT (0)
743 #define DEVICE_EMIF_AWCC_WAITSTATE_MASK (0x000000FF)
745 #define DEVICE_EMIF_NANDFCR_4BITECC_SEL_MASK (0x00000030)
746 #define DEVICE_EMIF_NANDFCR_4BITECC_SEL_SHIFT (4)
748 #define DEVICE_EMIF_NANDFCR_4BITECC_START_MASK (0x00001000)
749 #define DEVICE_EMIF_NANDFCR_4BITECC_START_SHIFT (12)
750 #define DEVICE_EMIF_NANDFCR_4BITECC_ADD_CALC_START_MASK (0x00002000)
751 #define DEVICE_EMIF_NANDFCR_4BITECC_ADD_CALC_START_SHIFT (13)
753 #define DEVICE_EMIF_NANDFSR_READY_MASK (0x00000001)
754 #define DEVICE_EMIF_NANDFSR_READY_SHIFT (0)
756 #define DEVICE_EMIF_NANDFSR_ECC_STATE_MASK (0x00000F00)
757 #define DEVICE_EMIF_NANDFSR_ECC_STATE_SHIFT (8)
758 #define DEVICE_EMIF_NANDFSR_ECC_ERRNUM_MASK (0x00030000)
759 #define DEVICE_EMIF_NANDFSR_ECC_ERRNUM_SHIFT (16)
762 typedef struct _DEVICE_EMIF3A_REGS_
763 {
764 VUint32 ERCSR;
765 VUint32 SDRSTAT;
766 VUint32 SDCR;
767 VUint32 SDRCR;
768 VUint32 SDTIMR;
769 VUint32 SDTIMR2;
770 VUint8 RSVD0[4];
771 VUint32 SDCR2;
772 VUint32 PBBPR;
773 VUint8 RSVD1[4];
774 VUint32 VBCFG1;
775 VUint32 VBCFG2;
776 VUint8 RSVD2[16];
777 VUint32 PERFC1R;
778 VUint32 PERFC2R;
779 VUint32 PCCR;
780 VUint32 PCMRSR;
781 VUint32 PCTR;
782 VUint8 RSVD3[12];
783 VUint32 IODFTGBLCTRL;
784 VUint32 IODFTMISRR;
785 VUint32 IODFTMISADDRRR;
786 VUint32 IODFTMISR1R;
787 VUint32 IODFTMISR2R;
788 VUint32 IODFTMISR3R;
789 VUint8 RSVD4[8];
790 VUint32 ASYNCCS2CR;
791 VUint32 ASYNCCS3CR;
792 VUint32 ASYNCCS4CR;
793 VUint32 ASYNCCS5CR;
794 VUint8 RSVD5[16];
795 VUint32 AWCCR;
796 VUint8 RSVD6[28];
797 VUint32 IRR;
798 VUint32 IMR;
799 VUint32 IMSR;
800 VUint32 IMCR;
801 VUint8 RSVD7[16];
802 VUint32 DDRPHYREV;
803 VUint32 DDRPHYC1R;
804 VUint32 DDRPHYC2R;
805 VUint32 DDRPHYC3R;
806 }
807 DEVICE_Emif3Regs;
809 #define EMIF3A ((DEVICE_Emif3Regs*) 0xB0000000u)
811 #define DEVICE_SDCR_MSDRAMEN_MASK (0x02000000u)
812 #define DEVICE_SDCR_MSDRAMEN_SHIFT (25)
813 #define DEVICE_SDCR_BOOTUNLOCK_MASK (0x00800000u)
814 #define DEVICE_SDCR_BOOTUNLOCK_SHIFT (23)
815 #define DEVICE_SDCR_TIMUNLOCK_MASK (0x00008000u)
816 #define DEVICE_SDCR_TIMUNLOCK_SHIFT (15)
817 #define DEVICE_SDCR_NM_SHIFT (14)
818 #define DEVICE_SDCR_NM_MASK (0x00004000u)
821 typedef struct _DEVICE_UHPI_REGS
822 {
823 VUint32 PID; // 0x00
824 VUint32 PWREMU_MGMT; // 0x04
825 VUint32 GPIOINT; // 0x08
826 VUint32 GPIOEN; // 0x0C
827 VUint32 GPIODIR1; // 0x10
828 VUint32 GPIODAT1; // 0x14
829 VUint32 GPIODIR2; // 0x18
830 VUint32 GPIODAT2; // 0x1C
831 VUint32 GPIODIR3; // 0x20
832 VUint32 GPIODAT3; // 0x24
833 VUint32 RSVD0[2]; // 0x28
834 VUint32 HPIC; // 0x30
835 VUint32 HPIAW; // 0x34
836 VUint32 HPIAR; // 0x38
837 VUint32 XHPIAW; // 0x3C
838 VUint32 XHPIAR; // 0x40
839 }
840 DEVICE_UHPIRegs;
842 #define UHPI ((DEVICE_UHPIRegs*) 0x01E10000u)
844 #define DEVICE_HPIC_HPIRST_MASK (0x00000080u)
845 #define DEVICE_HPIC_HPIRST_SHIFT (7)
847 #define DEVICE_HPIC_HINT_MASK (0x00000004u)
848 #define DEVICE_HPIC_HINT_SHIFT (2)
850 #define DEVICE_HPIC_DSPINT_MASK (0x00000002u)
851 #define DEVICE_HPIC_DSPINT_SHIFT (1)
855 // UART Register structure - See sprued9b.pdf for more details.
856 typedef struct _DEVICE_UART_REGS_
857 {
858 VUint32 RBR;
859 VUint32 IER;
860 VUint32 IIR;
861 VUint32 LCR;
862 VUint32 MCR;
863 VUint32 LSR;
864 VUint32 MSR;
865 VUint32 SCR;
866 VUint8 DLL;
867 VUint8 RSVD1[3];
868 VUint8 DLH;
869 VUint8 RSVD2[3];
870 VUint32 PID1;
871 VUint32 PID2;
872 VUint32 PWREMU_MGMT;
873 VUint32 MDR;
874 }
875 DEVICE_UARTRegs;
877 #define THR RBR
878 #define FCR IIR
880 #define UART_PERIPHERAL_CNT (3)
882 #define UART0 ((DEVICE_UARTRegs*) 0x01C42000)
883 #define UART1 ((DEVICE_UARTRegs*) 0x01D0C000)
884 #define UART2 ((DEVICE_UARTRegs*) 0x01D0D000)
886 #define DEVICE_UART0_DESIRED_BAUD (115200)
887 #define DEVICE_UART0_OVERSAMPLE_CNT (16)
889 #define DEVICE_UART_DLL_MASK (0x000000FFu)
890 #define DEVICE_UART_DLL_SHIFT (0)
891 #define DEVICE_UART_DLH_MASK (0x000000FFu)
892 #define DEVICE_UART_DLH_SHIFT (0)
894 #define DEVICE_UART_PWREMU_MGMT_URST_MASK (0x00008000u)
895 #define DEVICE_UART_PWREMU_MGMT_URST_SHIFT (15)
896 #define DEVICE_UART_PWREMU_MGMT_UTRST_MASK (0x00004000u)
897 #define DEVICE_UART_PWREMU_MGMT_UTRST_SHIFT (14)
898 #define DEVICE_UART_PWREMU_MGMT_URRST_MASK (0x00002000u)
899 #define DEVICE_UART_PWREMU_MGMT_URRST_SHIFT (13)
901 #define DEVICE_UART_FCR_RXFIFTL_MASK (0x000000C0u)
902 #define DEVICE_UART_FCR_RXFIFTL_SHIFT (6)
903 #define DEVICE_UART_FCR_DMAMODE1_MASK (0x00000008u)
904 #define DEVICE_UART_FCR_DMAMODE1_SHIFT (3)
905 #define DEVICE_UART_FCR_TXCLR_MASK (0x00000004u)
906 #define DEVICE_UART_FCR_TXCLR_SHIFT (2)
907 #define DEVICE_UART_FCR_RXCLR_MASK (0x00000002u)
908 #define DEVICE_UART_FCR_RXCLR_SHIFT (1)
909 #define DEVICE_UART_FCR_FIFOEN_MASK (0x00000001u)
910 #define DEVICE_UART_FCR_FIFOEN_SHIFT (0)
912 #define DEVICE_UART_LSR_RXFIFOE_MASK (0x00000080u)
913 #define DEVICE_UART_LSR_RXFIFOE_SHIFT (7)
914 #define DEVICE_UART_LSR_TEMT_MASK (0x00000040u)
915 #define DEVICE_UART_LSR_TEMT_SHIFT (6)
916 #define DEVICE_UART_LSR_THRE_MASK (0x00000020u)
917 #define DEVICE_UART_LSR_THRE_SHIFT (5)
918 #define DEVICE_UART_LSR_BI_MASK (0x00000010u)
919 #define DEVICE_UART_LSR_BI_SHIFT (4)
920 #define DEVICE_UART_LSR_FE_MASK (0x00000008u)
921 #define DEVICE_UART_LSR_FE_SHIFT (3)
922 #define DEVICE_UART_LSR_PE_MASK (0x00000004u)
923 #define DEVICE_UART_LSR_PE_SHIFT (2)
924 #define DEVICE_UART_LSR_OE_MASK (0x00000002u)
925 #define DEVICE_UART_LSR_OE_SHIFT (1)
926 #define DEVICE_UART_LSR_DR_MASK (0x00000001u)
927 #define DEVICE_UART_LSR_DR_SHIFT (0)
930 // Timer Register structure - See spruee5a.pdf for more details.
931 typedef struct _DEVICE_TIMER_REGS_
932 {
933 VUint32 PID12; // 0x00
934 VUint32 EMUMGT_CLKSPD; // 0x04
935 VUint8 RSVD0[8]; // 0x08
936 VUint32 TIM12; // 0x10
937 VUint32 TIM34; // 0x14
938 VUint32 PRD12; // 0x18
939 VUint32 PRD34; // 0x1C
940 VUint32 TCR; // 0x20
941 VUint32 TGCR; // 0x24
942 VUint32 WDTCR; // 0x28
943 VUint8 RSVD1[12]; // 0x2C
944 VUint32 REL12; // 0x34
945 VUint32 REL34; // 0x38
946 VUint32 CAP12; // 0x3C
947 VUint32 CAP34; // 0x40
948 VUint32 INTCTL_STAT; // 0x44
949 }
950 DEVICE_TimerRegs;
952 #define TIMER0 ((DEVICE_TimerRegs*) 0x01C21400)
954 // I2C Register structure
955 typedef struct _DEVICE_I2C_REGS_
956 {
957 VUint32 ICOAR; // 0x00
958 VUint32 ICIMR; // 0x04
959 VUint32 ICSTR; // 0x08
960 VUint32 ICCLKL; // 0x0C
961 VUint32 ICCLKH; // 0x10
962 VUint32 ICCNT; // 0x14
963 VUint32 ICDRR; // 0x18
964 VUint32 ICSAR; // 0x1C
965 VUint32 ICDXR; // 0x20
966 VUint32 ICMDR; // 0x24
967 VUint32 ICIVR; // 0x28
968 VUint32 ICEMDR; // 0x2C
969 VUint32 ICPSC; // 0x30
970 VUint32 ICPID1; // 0x34
971 VUint32 ICPID2; // 0x38
972 }
973 DEVICE_I2CRegs;
975 #define I2C0 ((DEVICE_I2CRegs*) 0x01C22000u)
976 #define I2C1 ((DEVICE_I2CRegs*) 0x01E28000u)
978 #define I2C_PERIPHERAL_CNT (2)
980 #define DEVICE_I2C_TARGET_FREQ (200000u)
981 #define DEVICE_I2C_OWN_ADDRESS (0x10)
983 #define I2C_ICMDR_NACKMOD (0x00008000)
984 #define I2C_ICMDR_FRE (0x00004000)
985 #define I2C_ICMDR_STT (0x00002000)
986 #define I2C_ICMDR_STP (0x00000800)
987 #define I2C_ICMDR_MST (0x00000400)
988 #define I2C_ICMDR_TRX (0x00000200)
989 #define I2C_ICMDR_XA (0x00000100)
990 #define I2C_ICMDR_RM (0x00000080)
991 #define I2C_ICMDR_DLB (0x00000040)
992 #define I2C_ICMDR_IRS (0x00000020)
993 #define I2C_ICMDR_STB (0x00000010)
994 #define I2C_ICMDR_FDF (0x00000008)
995 #define I2C_ICMDR_BC8 (0x00000007)
997 #define I2C_ICSTR_AL_MSK (0x00000001)
998 #define I2C_ICSTR_NACK_MSK (0x00000002)
999 #define I2C_ICSTR_ARDY_MSK (0x00000004)
1000 #define I2C_ICSTR_ICRRDY_MSK (0x00000008)
1001 #define I2C_ICSTR_ICXRDY_MSK (0x00000010)
1002 #define I2C_ICSTR_SCD_MSK (0x00000020)
1003 #define I2C_ICSTR_BB_MSK (0x00001000)
1005 #define I2C_ICEMDR_EXTMODE (0x00000000)
1007 // SPI Register structure
1008 typedef struct _DEVICE_SPI_REGS_
1009 {
1010 VUint32 SPIGCR0; // 0x00
1011 VUint32 SPIGCR1; // 0x04
1012 VUint32 SPIINT; // 0x08
1013 VUint32 SPILVL; // 0x0C
1014 VUint32 SPIFLG; // 0x10
1015 VUint32 SPIPC0; // 0x14
1016 VUint32 SPIPC1; // 0x18
1017 VUint32 SPIPC2; // 0x1C
1018 VUint32 SPIPC3; // 0x20
1019 VUint32 SPIPC4; // 0x24
1020 VUint32 SPIPC5; // 0x28
1021 VUint32 SPIPC6; // 0x2C
1022 VUint32 SPIPC7; // 0x30
1023 VUint32 SPIPC8; // 0x34
1024 VUint32 SPIDAT[2]; // 0x38
1025 VUint32 SPIBUF; // 0x40
1026 VUint32 SPIEMU; // 0x44
1027 VUint32 SPIDELAY; // 0x48
1028 VUint32 SPIDEF; // 0x4C
1029 VUint32 SPIFMT[4]; // 0x50
1030 VUint32 TGINTVEC[2]; // 0x60
1031 VUint32 SPIDUMMY[51];
1032 VUint32 SPIIOLPBK;
1033 }
1034 DEVICE_SPIRegs;
1036 #define SPI0 ((DEVICE_SPIRegs *) 0x01C41000u)
1037 #define SPI1 ((DEVICE_SPIRegs *) 0x01F0E000u)
1039 #define SPI_PERIPHERAL_CNT (2)
1041 #define DEVICE_SPI_SPIGCR1_SPIEN_MASK (0x01000000u)
1042 #define DEVICE_SPI_SPIGCR1_SPIEN_SHIFT (24)
1044 typedef struct _DEVICE_SDMMC_REGS_
1045 {
1046 VUint32 MMCCTL;
1047 VUint32 MMCCLK;
1048 VUint32 MMCST0;
1049 VUint32 MMCST1;
1050 VUint32 MMCIM;
1051 VUint32 MMCTOR;
1052 VUint32 MMCTOD;
1053 VUint32 MMCBLEN;
1054 VUint32 MMCNBLK;
1055 VUint32 MMCNBLC;
1056 VUint32 MMCDRR;
1057 VUint32 MMCDXR;
1058 VUint32 MMCCMD;
1059 VUint32 MMCARGHL;
1060 VUint32 MMCRSP01;
1061 VUint32 MMCRSP23;
1062 VUint32 MMCRSP45;
1063 VUint32 MMCRSP67;
1064 VUint32 MMCDRSP;
1065 VUint8 RSVD0[4];
1066 VUint32 MMCCIDX;
1067 VUint8 RSVD1[16];
1068 VUint32 SDIOCTL;
1069 VUint32 SDIOST0;
1070 VUint32 SDIOIEN;
1071 VUint32 SDIOIST;
1072 VUint32 MMCFIFOCTL;
1073 }
1074 DEVICE_SDMMCRegs;
1076 #define SDMMC0 ((DEVICE_SDMMCRegs*) 0x01C40000)
1077 #define SDMMC1 ((DEVICE_SDMMCRegs*) 0x01E1B000)
1078 #define SDMMC_PERIPHERAL_CNT (2)
1080 #define SDMMC_MMCCTL_DATRST_MASK (0x00000001u)
1081 #define SDMMC_MMCCTL_DATRST_SHIFT (0)
1082 #define SDMMC_MMCCTL_CMDRST_MASK (0x00000002u)
1083 #define SDMMC_MMCCTL_CMDRST_SHIFT (1)
1084 #define SDMMC_MMCCTL_WIDTH0_MASK (0x00000004u)
1085 #define SDMMC_MMCCTL_WIDTH0_SHIFT (2)
1086 #define SDMMC_MMCCTL_DATEG_MASK (0x00000C0u)
1087 #define SDMMC_MMCCTL_DATEG_SHIFT (6)
1088 #define SDMMC_MMCCTL_WIDTH1_MASK (0x00000100u)
1089 #define SDMMC_MMCCTL_WIDTH1_SHIFT (8)
1090 #define SDMMC_MMCCTL_PERMDR_MASK (0x00000200u)
1091 #define SDMMC_MMCCTL_PERMDR_SHIFT (9)
1092 #define SDMMC_MMCCTL_PERMDX_MASK (0x00000400u)
1093 #define SDMMC_MMCCTL_PERMDX_SHIFT (10)
1095 #define SDMMC_MMCCLK_CLKEN_MASK (0x00000100u)
1096 #define SDMMC_MMCCLK_CLKEN_SHIFT (8)
1097 #define SDMMC_MMCCLK_CLKRT_MASK (0x000000FFu)
1098 #define SDMMC_MMCCLK_CLKRT_SHIFT (0)
1100 #define SDMMC_MMCTOR_TOR_MASK (0x000000FFu)
1101 #define SDMMC_MMCTOR_TOR_SHIFT (0)
1102 #define SDMMC_MMCTOR_TOD_25_16_MASK (0x0003FF00u)
1103 #define SDMMC_MMCTOR_TOD_25_16_SHIFT (8)
1105 #define SDMMC_MMCTOD_TOD_15_0_MASK (0x0000FFFFu)
1106 #define SDMMC_MMCTOD_TOD_15_0_SHIFT (0)
1108 #define SDMMC_MMCBLEN_BLEN_MASK (0x00000FFFu)
1109 #define SDMMC_MMCBLEN_BLEN_SHIFT (0)
1111 #define SDMMC_MMCNBLK_NBLK_MASK (0x0000FFFFu)
1112 #define SDMMC_MMCNBLK_NBLK_SHIFT (0)
1114 #define SDMMC_MMCST0_DATDNE_MASK (0x00000001u)
1115 #define SDMMC_MMCST0_DATDNE_SHIFT (0)
1116 #define SDMMC_MMCST0_BSYDNE_MASK (0x00000002u)
1117 #define SDMMC_MMCST0_BSYDNE_SHIFT (1)
1118 #define SDMMC_MMCST0_RSPDNE_MASK (0x00000004u)
1119 #define SDMMC_MMCST0_RSPDNE_SHIFT (2)
1120 #define SDMMC_MMCST0_TOUTRD_MASK (0x00000008u)
1121 #define SDMMC_MMCST0_TOUTRD_SHIFT (3)
1122 #define SDMMC_MMCST0_TOUTRS_MASK (0x00000010u)
1123 #define SDMMC_MMCST0_TOUTRS_SHIFT (4)
1124 #define SDMMC_MMCST0_CRCWR_MASK (0x00000020u)
1125 #define SDMMC_MMCST0_CRCWR_SHIFT (5)
1126 #define SDMMC_MMCST0_CRCRD_MASK (0x00000040u)
1127 #define SDMMC_MMCST0_CRCRD_SHIFT (6)
1128 #define SDMMC_MMCST0_CRCRS_MASK (0x00000080u)
1129 #define SDMMC_MMCST0_CRCRS_SHIFT (7)
1130 #define SDMMC_MMCST0_DXRDY_MASK (0x00000200u)
1131 #define SDMMC_MMCST0_DXRDY_SHIFT (9)
1132 #define SDMMC_MMCST0_DRRDY_MASK (0x00000400u)
1133 #define SDMMC_MMCST0_DRRDY_SHIFT (10)
1136 #define SDMMC_MMCCMD_DMATRIG_MASK (0x00010000u)
1137 #define SDMMC_MMCCMD_DMATRIG_SHIFT (16)
1138 #define SDMMC_MMCCMD_DCLR_MASK (0x00008000u)
1139 #define SDMMC_MMCCMD_DCLR_SHIFT (15)
1140 #define SDMMC_MMCCMD_INITCK_MASK (0x00004000u)
1141 #define SDMMC_MMCCMD_INITCK_SHIFT (14)
1142 #define SDMMC_MMCCMD_WDATX_MASK (0x00002000u)
1143 #define SDMMC_MMCCMD_WDATX_SHIFT (13)
1144 #define SDMMC_MMCCMD_STRMTP_MASK (0x00001000u)
1145 #define SDMMC_MMCCMD_STRMTP_SHIFT (12)
1146 #define SDMMC_MMCCMD_DTRW_MASK (0x00000800u)
1147 #define SDMMC_MMCCMD_DTRW_SHIFT (11)
1148 #define SDMMC_MMCCMD_RSPFMT_MASK (0x00000600u)
1149 #define SDMMC_MMCCMD_RSPFMT_SHIFT (9)
1150 #define SDMMC_MMCCMD_RSPFMT_NONE (0)
1151 #define SDMMC_MMCCMD_RSPFMT_R1 (1)
1152 #define SDMMC_MMCCMD_RSPFMT_R2 (2)
1153 #define SDMMC_MMCCMD_RSPFMT_R3 (3)
1154 #define SDMMC_MMCCMD_RSPFMT_R4 SDMMC_MMCCMD_RSPFMT_R1
1155 #define SDMMC_MMCCMD_RSPFMT_R5 SDMMC_MMCCMD_RSPFMT_R1
1156 #define SDMMC_MMCCMD_RSPFMT_R6 SDMMC_MMCCMD_RSPFMT_R1
1157 #define SDMMC_MMCCMD_BSYEXP_MASK (0x00000100u)
1158 #define SDMMC_MMCCMD_BSYEXP_SHIFT (8)
1159 #define SDMMC_MMCCMD_PPLEN_MASK (0x00000080u)
1160 #define SDMMC_MMCCMD_PPLEN_SHIFT (7)
1161 #define SDMMC_MMCCMD_CMD_MASK (0x0000003Fu)
1162 #define SDMMC_MMCCMD_CMD_SHIFT (0)
1164 #define SDMMC_MMCFIFOCTL_FIFORST_MASK (0x00000001u)
1165 #define SDMMC_MMCFIFOCTL_FIFORST_SHIFT (0)
1166 #define SDMMC_MMCFIFOCTL_FIFODIR_MASK (0x00000002u)
1167 #define SDMMC_MMCFIFOCTL_FIFODIR_SHIFT (1)
1168 #define SDMMC_MMCFIFOCTL_FIFOLEV_MASK (0x00000004u)
1169 #define SDMMC_MMCFIFOCTL_FIFOLEV_SHIFT (2)
1170 #define SDMMC_MMCFIFOCTL_ACCWD_MASK (0x00000018u)
1171 #define SDMMC_MMCFIFOCTL_ACCWD_SHIFT (3)
1175 // GPIO Register structures
1176 typedef struct _DEVICE_GPIO_BANK_REGS_
1177 {
1178 VUint16 DIR[2];
1179 VUint16 OUT_DATA[2];
1180 VUint16 SET_DATA[2];
1181 VUint16 CLR_DATA[2];
1182 VUint16 IN_DATA[2];
1183 VUint16 SET_RIS_TRIG[2];
1184 VUint16 CLR_RIS_TRIG[2];
1185 VUint16 SET_FAL_TRIG[2];
1186 VUint16 CLR_FAL_TRIG[2];
1187 VUint16 INTSTAT[2];
1188 }
1189 DEVICE_GPIOBankRegs;
1191 typedef struct _DEVICE_GPIO_REGS_
1192 {
1193 VUint32 PID;
1194 VUint32 PCR;
1195 VUint32 BINTEN;
1196 VUint8 RSVD0[4];
1197 DEVICE_GPIOBankRegs BANKPAIR[4];
1198 } DEVICE_GPIORegs;
1200 #define GPIO ((DEVICE_GPIORegs *) 0x01E26000u)
1204 /***********************************************************
1205 * Global Function Declarations *
1206 ***********************************************************/
1208 // Execute LPSC state transition
1209 extern __FAR__ void DEVICE_LPSCTransition(Uint8 pscnum, Uint8 module, Uint8 domain, Uint8 state);
1211 // Pinmux control function
1212 extern __FAR__ void DEVICE_pinmuxControl(Uint32 regOffset, Uint32 mask, Uint32 value);
1214 // Kick register lock/unlock functions
1215 extern __FAR__ void DEVICE_kickUnlock(void);
1216 extern __FAR__ void DEVICE_kickLock(void);
1218 // System Initialization prototypes
1219 extern __FAR__ Uint32 DEVICE_init(void);
1220 extern __FAR__ void DEVICE_PSCInit();
1221 extern __FAR__ Uint32 DEVICE_PLL0Init(Uint8 clk_src, Uint8 pllm, Uint8 prediv, Uint8 postdiv, Uint8 div1 ,Uint8 div3, Uint8 div7);
1222 extern __FAR__ Uint32 DEVICE_PLL1Init(Uint8 pllm, Uint8 postdiv, Uint8 div1, Uint8 div2, Uint8 div3);
1223 extern __FAR__ Uint32 DEVICE_ExternalMemInit(Uint32 ddrphycr, Uint32 sdcr, Uint32 sdtimr, Uint32 sdtimr2, Uint32 sdrcr, Uint32 sdcr2);
1225 // Peripheral Initialization prototypes
1226 extern __FAR__ Uint32 DEVICE_UARTInit(Uint8 periphNum);
1227 extern __FAR__ Uint32 DEVICE_SPIInit(Uint8 periphNum);
1228 extern __FAR__ Uint32 DEVICE_I2CInit(Uint8 periphNum);
1229 extern __FAR__ Uint32 DEVICE_AsyncMemInit(Uint8 interfaceNum);
1230 extern __FAR__ Uint32 DEVICE_TIMER0Init(void);
1232 // Device boot status functions
1233 extern __FAR__ DEVICE_BootMode DEVICE_bootMode( void );
1234 extern __FAR__ DEVICE_BootPeripheral DEVICE_bootPeripheral(void);
1235 extern __FAR__ DEVICE_BusWidth DEVICE_emifBusWidth( void );
1236 extern __FAR__ DEVICE_ChipRevIDType DEVICE_chipRevIDType( void );
1238 extern __FAR__ void DEVICE_TIMER0Start(void);
1239 extern __FAR__ void DEVICE_TIMER0Stop(void);
1240 extern __FAR__ Uint32 DEVICE_TIMER0Status(void);
1243 /***********************************************************
1244 * End file *
1245 ***********************************************************/
1247 #ifdef __cplusplus
1248 }
1249 #endif
1251 #endif // End _DEVICE_H_