676abf8ad2c7629651bb079115af45c6a2bdcec3
1 /*
2 * ECC Example
3 *
4 * Error Correcting Code (ECC) Example Application
5 *
6 * Copyright (c) 2020 Texas Instruments Incorporated
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 */
37 /**
38 * \file ecc_inject.c
39 *
40 * \brief This file contains functions that provide input ECC event triggers
41 * for the Error Correcting Code Module (ECC) application.
42 */
44 /* ========================================================================== */
45 /* Include Files */
46 /* ========================================================================== */
47 #include <stdint.h>
48 #include <diag_utils.h>
49 #include <sdr_ecc.h>
51 #include "ecc_trigger_func.h"
52 #include "ecc_inject.h"
55 /* ========================================================================== */
56 /* Macros & Typedefs */
57 /* ========================================================================== */
59 /* None */
61 /* ========================================================================== */
62 /* Structure Declarations */
63 /* ========================================================================== */
65 /* Use case definition structure */
66 typedef struct diag_ecc_use_case_s
67 {
68 SDR_ECC_MemType eccAggrId; /* ECC Aggregator ID */
69 SDR_ECC_MemSubType eccRamId; /* ECC RAM ID */
70 SDR_ECC_InjectErrorType secInjErrType; /* SEC Inject Error Type */
71 uint32_t secFlipMask; /* SEC Error injection bitmask */
72 SDR_ECC_InjectErrorType dedInjErrType; /* DED Inject Error Type */
73 uint32_t dedFlipMask; /* DED Error injection bitmask */
74 SDR_ECC_RamIdType ramIdType; /* ECC RAM ID Type - Wrapper or Interconnect */
75 SDR_ECC_MemSubSubType chkGrp; /* ECC Checker Group - Only for Interconnect Type */
76 uint32_t testAddressTrigLoc; /* Memory location to read for event trigger.
77 For accessible Wrapper types only. */
78 int32_t (*testTrigFunc)(void); /* Function to run for event trigger.
79 For inaccessible Wrapper types only. */
80 } diag_ecc_use_case_t;
82 /* ========================================================================== */
83 /* Function Declarations */
84 /* ========================================================================== */
86 static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
87 SDR_ECC_MemSubType eccRamId,
88 SDR_ECC_InjectErrorType injErrType,
89 uint32_t flipMask,
90 uint32_t ramIdType,
91 SDR_ECC_MemSubSubType chkGrp,
92 uint32_t testAddressTrigLoc,
93 int32_t (*testTrigFunc)(void) );
95 static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
96 SDR_ECC_MemSubType eccRamId,
97 SDR_ECC_InjectErrorType injErrType,
98 uint32_t flipMask,
99 uint32_t ramIdType,
100 SDR_ECC_MemSubSubType chkGrp,
101 uint32_t testAddressTrigLoc,
102 int32_t (*testTrigFunc)(void) );
104 /* ========================================================================== */
105 /* Global Variables */
106 /* ========================================================================== */
109 /* List all needed values/ID's for all the use cases */
110 diag_ecc_use_case_t useCaseArray[6] =
111 {
112 /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Interconnect ECC Type */
113 {SDR_ECC_MEMTYPE_MCU_R5F0_CORE, /* eccAggrId of type SDR_ECC_MemType */
114 SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* RAM ID = 28 */
115 SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE, /* SEC Inject Error Type */
116 0x10, /* secFlipMask of type uint32_t */
117 SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE, /* DED Inject Error Type */
118 0x101, /* dedFlipMask of type uint32_t */
119 SDR_ECC_RAM_ID_TYPE_INTERCONNECT, /* ramIdType of type SDR_ECC_RamIdType */
120 SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0, /* EDC Group Type */
121 0x0, /* testAddressTrigLoc of type uint32_t,
122 * not used for Interconnect Type */
123 NULL /* testTrigFunc filled in initialization function */
124 },
125 /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Wrapper ECC Type */
126 {SDR_ECC_MEMTYPE_MCU_R5F0_CORE, /* eccAggrId of type SDR_ECC_MemType */
127 SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID, /* eccRamId of type SDR_ECC_MemSubType - CSL_ECC_AGGR_MCU_R5FSS0_R5_ECC_AGGR_0_CPU0_KS_VIM_RAMECC_ID */
128 SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE, /* SEC Inject Error Type */
129 0x10, /* secFlipMask of type uint32_t */
130 SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE, /* DED Inject Error Type */
131 0x101, /* dedFlipMask of type uint32_t */
132 SDR_ECC_RAM_ID_TYPE_WRAPPER, /* ramIdType of type SDR_ECC_RamIdType */
133 0, /* Wrapper type, so no Group checker ID */
134 0x40F82004u, /* testAddressTrigLoc of type uint32_t */ // TODO - BASE OFF CSLR BASE ADDRESS VALUE, FIND RIGHT VALUE
135 NULL /* testTrigFunc filled in initialization function */
136 },
137 /* Main ESM, MSMC ECC Aggregator, Interconnect ECC Type */
138 {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0, /* eccAggrId of type SDR_ECC_MemType */
139 SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE, /* eccRamId of type SDR_ECC_MemSubType *///CSL_ECC_AGGR_COMPUTE_CLUSTER0_MSMC_ES_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ID
140 SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE, /* SEC Inject Error Type */
141 0x10, /* secFlipMask of type uint32_t */
142 SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE, /* DED Inject Error Type */
143 0x101, /* dedFlipMask of type uint32_t */
144 SDR_ECC_RAM_ID_TYPE_INTERCONNECT, /* ramIdType of type SDR_ECC_RamIdType */
145 0, /* Choose Group checker ID of 0 */
146 0x0, /* testAddressTrigLoc of type uint32_t,
147 * not used for Interconnect Type */
148 NULL /* testTrigFunc filled in initialization function */
149 },
150 /* Main ESM, MSMC ECC Aggregator, Wrapper ECC Type */
151 {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0, /* eccAggrId of type SDR_ECC_MemType */
152 SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, /* eccRamId of type SDR_ECC_MemSubType */
153 SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE, /* SEC Inject Error Type */
154 0x10, /* secFlipMask of type uint32_t */
155 SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE, /* DED Inject Error Type */
156 0x101, /* dedFlipMask of type uint32_t */
157 SDR_ECC_RAM_ID_TYPE_WRAPPER, /* ramIdType of type SDR_ECC_RamIdType */
158 0, /* Wrapper type, so no Group checker ID */
159 0x0, /* testAddressTrigLoc of type uint32_t,
160 * not used for this inaccesible Wrapper type */
161 NULL /* testTrigFunc filled in initialization function */
162 },
163 /* Multiple iterations on Main ESM, MSMC ECC Aggregator, Interconnect ECC Type */
164 {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0, /* eccAggrId of type SDR_ECC_MemType */
165 SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE, /* eccRamId of type SDR_ECC_MemSubType */
166 SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE, /* SEC Inject Error Type */
167 0x10, /* secFlipMask of type uint32_t */
168 SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE, /* DED Inject Error Type */
169 0x101, /* dedFlipMask of type uint32_t */
170 SDR_ECC_RAM_ID_TYPE_INTERCONNECT, /* ramIdType of type SDR_ECC_RamIdType */
171 0, /* Choose Group checker ID of 0 */
172 0x0, /* testAddressTrigLoc of type uint32_t,
173 * not used for Interconnect Type */
174 NULL /* testTrigFunc filled in initialization function */
175 },
176 /* Main ESM, MSMC ECC Aggregator, Wrapper ECC Type */
177 {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0, /* eccAggrId of type SDR_ECC_MemType */
178 SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, /* eccRamId of type SDR_ECC_MemSubType */
179 SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE, /* SEC Inject Error Type */
180 0x10, /* secFlipMask of type uint32_t */
181 SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE, /* DED Inject Error Type */
182 0x101, /* dedFlipMask of type uint32_t */
183 SDR_ECC_RAM_ID_TYPE_WRAPPER, /* ramIdType of type SDR_ECC_RamIdType */
184 0, /* Wrapper type, so no Group checker ID */
185 0x0, /* testAddressTrigLoc of type uint32_t,
186 * not used for this inaccessible Wrapper type */
187 NULL /* testTrigFunc filled in initialization function */
188 },
189 };
191 /* ========================================================================== */
192 /* External Variables */
193 /* ========================================================================== */
195 extern volatile uint32_t gEsmEventRcvdFlag;
197 extern volatile uint32_t eccEventInputTrig[6];
199 extern int32_t (*useCaseTriggerFuncArray[6])();
201 /* ========================================================================== */
202 /* Function Definitions */
203 /* ========================================================================== */
205 /*********************************************************************
206 * @fn runSingleSECEvent
207 *
208 * @brief Execute ECC 1 bit inject test
209 *
210 * @param eccAggrId - ID of the ECC Aggregator
211 * @param eccRamId - RAM ID into which the error will be injected
212 * @param injErrType - inject error type
213 * @param flipMask - bit mask that indicates what bit to inject the error
214 * @param ramIdType - type of RAM ID (either Wrapper or Interconnect Type)
215 * @param chkGrp - check group ID (only valid for Interconnect Type, otherwise set to 0)
216 * @param testAddressTrigLoc - memory address that needs to be read to trigger
217 * SEC event.
218 * @param testTrigFunc - function that needs to be run to trigger SEC event.
219 * It is expected that only testAddressTrigLoc or testTrigFunc
220 * is needed for each use case (and cannot be both).
221 *
222 * @return 0 : Success; < 0 for failures
223 */
224 static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
225 SDR_ECC_MemSubType eccRamId,
226 SDR_ECC_InjectErrorType injErrType,
227 uint32_t flipMask,
228 uint32_t ramIdType,
229 SDR_ECC_MemSubSubType chkGrp,
230 uint32_t testAddressTrigLoc,
231 int32_t (*testTrigFunc)(void) )
232 {
233 SDR_Result result;
234 int32_t retVal=0;
236 SDR_ECC_InjectErrorConfig_t injectErrorConfig;
237 volatile uint32_t testLocationValue;
238 #ifdef DEBUG_PRINT
239 DIAG_printf("\n Single bit error inject: test starting for eccAggr %d, eccRamId %d, " \
240 "flipMask 0x%x, ramIdType %d, testAddressTrigLoc = 0x%x\n",
241 eccAggrId, eccRamId, flipMask, ramIdType, testAddressTrigLoc);
242 #endif
243 /* Note the address is Actual error address */
244 injectErrorConfig.pErrMem = (uint32_t *)(testAddressTrigLoc);
246 /* Run one shot test for 1 bit error */
247 injectErrorConfig.flipBitMask = flipMask;
248 injectErrorConfig.chkGrp = chkGrp;
250 result = SDR_ECC_injectError(eccAggrId,
251 eccRamId,
252 injErrType,
253 &injectErrorConfig);
254 if (result != SDR_PASS ) {
255 DIAG_printf("\n Single bit error inject at pErrMem 0x%p test failed",
256 injectErrorConfig.pErrMem);
257 retVal = -1;
258 } else {
259 if (testAddressTrigLoc != 0) {
260 /* Access the memory where injection is expected */
261 testLocationValue = injectErrorConfig.pErrMem[0];
262 } else if (testTrigFunc != NULL) {
263 /* Call function to trigger error */
264 retVal = (*testTrigFunc)();
265 if (retVal != 0) {
266 DIAG_printf("\n Single bit error inject: testTrigFunc call failed");
267 }
268 }
270 #ifdef DEBUG_PRINT
271 /* Note this should result in actual error call back */
272 DIAG_printf("\n Single bit error inject at pErrMem 0x%p: test complete",
273 injectErrorConfig.pErrMem);
274 #endif
275 }
277 return retVal;
278 }
280 /*********************************************************************
281 * @fn runSingleDEDEvent
282 *
283 * @brief Execute ECC 2 bit inject test
284 *
285 * @param eccAggrId - ID of the ECC Aggregator
286 * @param eccRamId - RAM ID into which the error will be injected
287 * @param injErrType - inject error type
288 * @param flipMask - bit mask that indicates what bit to inject the error
289 * @param ramIdType - type of RAM ID (either Wrapper or Interconnect Type)
290 * @param chkGrp - check group ID (only valid for Interconnect Type, otherwise set to 0)
291 * @param testAddressTrigLoc - memory address that needs to be read to trigger
292 * SEC event.
293 * @param testTrigFunc - function that needs to be run to trigger SEC event.
294 * It is expected that only testAddressTrigLoc or testTrigFunc
295 * is needed for each use case (and cannot be both).
296 *
297 * @return 0 : Success; < 0 for failures
298 */
299 static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
300 SDR_ECC_MemSubType eccRamId,
301 SDR_ECC_InjectErrorType injErrType,
302 uint32_t flipMask,
303 uint32_t ramIdType,
304 SDR_ECC_MemSubSubType chkGrp,
305 uint32_t testAddressTrigLoc,
306 int32_t (*testTrigFunc)(void) )
307 {
308 SDR_Result result;
309 int32_t retVal=0;
311 SDR_ECC_InjectErrorConfig_t injectErrorConfig;
312 volatile uint32_t testLocationValue;
313 #ifdef DEBUG_PRINT
314 DIAG_printf("\n Double bit error inject: test starting for eccAggr %d, eccRamId %d, " \
315 "flipMask 0x%x, ramIdType %d, testAddressTrigLoc = 0x%x\n",
316 eccAggrId, eccRamId, flipMask, ramIdType, testAddressTrigLoc);
317 #endif
318 /* Note the address is Actual error address */
319 injectErrorConfig.pErrMem = (uint32_t *)(testAddressTrigLoc);
321 /* Run one shot test for 2 bit error */
322 injectErrorConfig.flipBitMask = flipMask;
323 injectErrorConfig.chkGrp = chkGrp;
325 result = SDR_ECC_injectError(eccAggrId,
326 eccRamId,
327 injErrType,
328 &injectErrorConfig);
330 if (result != SDR_PASS ) {
331 DIAG_printf("\n Double bit error inject at pErrMem 0x%p test failed",
332 injectErrorConfig.pErrMem);
333 retVal = -1;
334 } else {
335 if (testAddressTrigLoc != 0) {
336 /* Access the memory where injection is expected */
337 testLocationValue = injectErrorConfig.pErrMem[0];
338 } else if (testTrigFunc != NULL) {
339 retVal = (*testTrigFunc)();
340 if (retVal != 0) {
341 DIAG_printf("\n Double bit error inject: testTrigFunc call failed");
342 }
343 }
344 #ifdef DEBUG_PRINT
345 /* Note this should result in actual error call back */
346 DIAG_printf("\n Double bit error inject at pErrMem 0x%p: test complete",
347 injectErrorConfig.pErrMem);
348 #endif
349 }
351 return retVal;
352 }
355 /*********************************************************************
356 * @fn diag_ecc_initUseCases
357 *
358 * @brief Perform any remaining initialization of the use cases
359 * based on SoC-specific definitions
360 *
361 * @return 0 : Success; < 0 for failures
362 */
363 int32_t diag_ecc_initUseCases(void)
364 {
365 int8_t i;
366 int32_t retValue;
368 /* Populate the Use Cases with any SoC-specific testTrigFunc */
369 for (i = 0; i < 6; i++) {
370 useCaseArray[i].testTrigFunc = useCaseTriggerFuncArray[i];
371 }
373 retValue = eventTriggerSetup();
375 return (retValue);
376 }
378 /*********************************************************************
379 * @fn diag_ecc_runUseCaseTrigger
380 *
381 * @brief Initiate the input trigger event(s) for each use case
382 *
383 * @param useCaseId - use case instance for which trigger event(s)
384 * should be initiated
385 *
386 * @return 0 : Success; < 0 for failures
387 */
388 int32_t diag_ecc_runUseCaseTrigger(uint8_t useCaseId)
389 {
390 int32_t retVal1, retVal2, numMultiSecEvents, numMultiDedEvents, i;
391 int32_t status = 0;
393 DIAG_printf("\nStarting Use Case %d \n", useCaseId);
394 switch(useCaseId)
395 {
396 case 0:
397 /* UC-1: Single SEC/DED events on MCU_ESM0 with Interconnect ECC type */
398 case 1:
399 /* UC-2: Single SEC/DED events on MCU_ESM0 with Wrapper ECC type */
400 case 2:
401 /* UC-3: Single SEC/DED events on Main Domain ESM0 with Interconnect ECC type */
402 case 3:
403 /* UC-4: Single SEC/DED events on Main Domain ESM0 with Wrapper ECC type. */
404 gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
406 /* Trigger a single SEC event */
407 retVal1 = runSingleSECEvent(useCaseArray[useCaseId].eccAggrId,
408 useCaseArray[useCaseId].eccRamId,
409 useCaseArray[useCaseId].secInjErrType,
410 useCaseArray[useCaseId].secFlipMask,
411 useCaseArray[useCaseId].ramIdType,
412 useCaseArray[useCaseId].chkGrp,
413 useCaseArray[useCaseId].testAddressTrigLoc,
414 useCaseArray[useCaseId].testTrigFunc);
416 /* Wait for the ESM event to complete */
417 while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
419 /* Trigger a single DED event */
420 retVal2 = runSingleDEDEvent(useCaseArray[useCaseId].eccAggrId,
421 useCaseArray[useCaseId].eccRamId,
422 useCaseArray[useCaseId].dedInjErrType,
423 useCaseArray[useCaseId].dedFlipMask,
424 useCaseArray[useCaseId].ramIdType,
425 useCaseArray[useCaseId].chkGrp,
426 useCaseArray[useCaseId].testAddressTrigLoc,
427 useCaseArray[useCaseId].testTrigFunc);
429 if ((retVal1 == 0) && (retVal2 == 0)) {
430 eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_SUCCESS;
431 } else {
432 eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_FAILURE;
433 }
434 break;
436 case 4:
437 /* UC-5: Multiple SEC and DED events on Main Domain ESM0 with Interconnect ECC type */
438 case 5:
439 /* UC-6: Multiple SEC and DED events on Main Domain ESM0 with Wrapper ECC type */
440 numMultiSecEvents = 0;
441 numMultiDedEvents = 0;
442 for (i = 0; i < NUM_MULTIPLE_SEC_EVENTS; i++)
443 {
444 gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
445 /* Trigger a single SEC event */
446 retVal1 = runSingleSECEvent(useCaseArray[useCaseId].eccAggrId,
447 useCaseArray[useCaseId].eccRamId,
448 useCaseArray[useCaseId].secInjErrType,
449 useCaseArray[useCaseId].secFlipMask,
450 useCaseArray[useCaseId].ramIdType,
451 useCaseArray[useCaseId].chkGrp,
452 useCaseArray[useCaseId].testAddressTrigLoc,
453 useCaseArray[useCaseId].testTrigFunc);
455 /* Wait for the ESM event to complete */
456 while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
458 if (retVal1 != 0) {
459 break;
460 } else {
461 numMultiSecEvents++;
462 }
463 }
465 for (i = 0; i < NUM_MULTIPLE_DED_EVENTS; i++)
466 {
467 gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
468 /* Trigger a single DED event */
469 retVal2 = runSingleDEDEvent(useCaseArray[useCaseId].eccAggrId,
470 useCaseArray[useCaseId].eccRamId,
471 useCaseArray[useCaseId].dedInjErrType,
472 useCaseArray[useCaseId].dedFlipMask,
473 useCaseArray[useCaseId].ramIdType,
474 useCaseArray[useCaseId].chkGrp,
475 useCaseArray[useCaseId].testAddressTrigLoc,
476 useCaseArray[useCaseId].testTrigFunc);
478 /* Wait for the ESM event to complete */
479 while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
481 if (retVal2 != 0) {
482 break;
483 } else {
484 numMultiDedEvents++;
485 }
486 }
488 if ((retVal1 == 0) && (numMultiSecEvents == NUM_MULTIPLE_SEC_EVENTS) &&
489 (retVal2 == 0) && (numMultiDedEvents == NUM_MULTIPLE_DED_EVENTS)) {
490 eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_SUCCESS;
491 } else {
492 eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_FAILURE;
493 }
494 break;
496 default:
497 DIAG_printf("ERR: Invalid Use Case ID %d \n", useCaseId);
498 status = -1;
499 break;
500 }
502 return (status);
503 }