c40cbd87703d8385dfa89f1017bb374e5da5abfa
1 /*
2 * SDR ECC
3 *
4 * Software Diagnostics Reference module for ECC
5 *
6 * Copyright (c) Texas Instruments Incorporated 2020
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 */
38 #ifndef INCLUDE_SDR_ECC_SOC_H_
39 #define INCLUDE_SDR_ECC_SOC_H_
41 #include <stdint.h>
42 #include <sdr_ecc.h>
43 #include <ti/csl/csl_ecc_aggr.h>
45 #include "sdr_ecc_priv.h"
47 /* define MAX entry based on list of Subtypes */
48 #define SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID+1u)
49 #define SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES (CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID+1u)
50 #define SDR_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES (CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID+1u)
52 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with
53 * Wrapper type) */
54 #define SDR_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES (28U)
55 #define SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES (1U)
56 #define SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES (2U)
58 #define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)
60 #define SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES (CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)
62 /** ------------------------------------------------------------------------------------
63 * @brief This structure holds the list of Ram Ids for each memory subtype in MCU domain
64 * -------------------------------------------------------------------------------------
65 */
66 const SDR_RAMIdEntry_t SDR_ECC_mcuArmssRamIdTable[SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES] =
67 {
68 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
69 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
70 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE },
71 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
72 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
73 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE },
74 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
75 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
76 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE },
77 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
78 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
79 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE },
80 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
81 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
82 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE },
83 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
84 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
85 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE },
86 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
87 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
88 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE },
89 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
90 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
91 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE },
92 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
93 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
94 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE },
95 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
96 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
97 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE },
98 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
99 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
100 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE },
101 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
102 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
103 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE },
104 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
105 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
106 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE },
107 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
108 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
109 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE },
110 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
111 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
112 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE },
113 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
114 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
115 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE },
116 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
117 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
118 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE },
119 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
120 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
121 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE },
122 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
123 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
124 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE },
125 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
126 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
127 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE },
128 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
129 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
130 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE },
131 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
132 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
133 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE },
134 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
135 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
136 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE },
137 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
138 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
139 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE },
140 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
141 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
142 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE },
143 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
144 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
145 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE },
146 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
147 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
148 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE },
149 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
150 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
151 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE },
152 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID,
153 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
154 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE }, // 28 - Interconnect Type
155 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
156 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
157 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 29 - Interconnect Type
158 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
159 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
160 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 30 - Interconnect Type
161 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
162 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
163 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 31 - Interconnect Type
164 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
165 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
166 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 32 - Interconnect Type
167 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_RAM_ID,
168 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
169 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE }, // 33 - Interconnect Type
170 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
171 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
172 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE }, // 34 - Interconnect Type
173 { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
174 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
175 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE }, // 35 - Interconnect Type
176 };
178 /** ----------------------------------------------------------------------------------
179 * @brief This structure holds the memory config for each memory subtype in MCU domain
180 * -----------------------------------------------------------------------------------
181 */
183 /* NOTE: For VIM RAM Id, with a 32 bit vector, the 2 LSB bits are not used.
184 ECC is done only on 30 bits. But need to add a correction of 2 to get the address
185 calculation to be right */
186 #define SDR_ECC_VIM_RAM_ID_WIDTH_CORRECTION (2U)
188 const SDR_MemConfig_t SDR_ECC_mcuArmssMemEntries[SDR_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
189 {
190 {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID, 0u,
191 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
192 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
193 {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID, 0u,
194 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
195 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
196 {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID, 0u,
197 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
198 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
199 {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID, 0u,
200 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
201 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
202 {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID, 0u,
203 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
204 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
205 {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID, 0u,
206 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
207 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
208 {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID, 0u,
209 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
210 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
211 {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID, 0u,
212 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
213 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
214 {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID, 0u,
215 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
216 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
217 {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID, 0u,
218 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
219 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
220 {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID, 0u,
221 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
222 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
223 {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID, 0u,
224 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
225 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
226 {SDR_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID, 0u,
227 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
228 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
229 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID, 0u,
230 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
231 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
232 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID, 0u,
233 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
234 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
235 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID, 0u,
236 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
237 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
238 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID, 0u,
239 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
240 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
241 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID,0u,
242 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
243 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
244 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID, 0u,
245 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
246 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
247 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID, 0u,
248 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
249 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
250 {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID, 0u,
251 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
252 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
253 {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID, 0u,
254 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 8u,
255 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
256 {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID, 0x4u,
257 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 8u,
258 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
259 {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID, 0x41010000u,
260 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 16u,
261 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
262 {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID, 0x41010004u,
263 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 16u,
264 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
265 {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID, 0x41010008u,
266 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 16u,
267 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
268 {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID, 0x4101000cu,
269 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 16u,
270 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
271 /* NOTE: VIM width and size needs correction: see note above */
272 {SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID, 0x40f82000u,
273 ((CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE
274 *(CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH
275 +SDR_ECC_VIM_RAM_ID_WIDTH_CORRECTION))
276 /CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH),
277 4u,
278 (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH+SDR_ECC_VIM_RAM_ID_WIDTH_CORRECTION), ((bool)true) },
279 };
281 /* Max entries based on max mem type */
282 #define SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0+1u)
284 #define SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR2 - \
285 SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
287 /* Max entries based on max mem type */
288 #define SDR_ECC_AGGREGATOR_MAX_ENTRIES (SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
289 SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)
291 /** -----------------------------------------------------------------------------------
292 * @brief This structure holds the base addresses for each memory subtype in MCU domain
293 * ------------------------------------------------------------------------------------
294 */
295 CSL_ecc_aggrRegs * const SDR_ECC_aggrBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES] =
296 {
297 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
298 ((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
299 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_ADC0_ECC_REGS_BASE)),
300 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_ADC1_ECC_REGS_BASE)),
301 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_CPSW0_ECC_BASE)),
302 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_FSS0_HPB_ECC_AGGR_BASE)),
303 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_FSS0_OSPI0_ECC_AGGR_BASE)),
304 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_FSS0_OSPI1_ECC_AGGR_BASE)),
305 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_MCAN0_ECC_AGGR_BASE)),
306 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_MCAN1_ECC_AGGR_BASE)),
307 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_MSRAM_1MB0_ECC_AGGR_REGS_BASE)),
308 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_NAVSS0_ECCAGGR0_BASE)),
309 ((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
310 ((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
311 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_PSRAMECC0_ECC_AGGR_BASE)),
312 ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_CBASS_ECC_AGGR0_REGS_BASE)),
313 };
315 /* Addresses will be cast to CSL_ecc_aggrRegs after RAT translation */
316 uint64_t const SDR_ECC_aggrHighBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES] =
317 {
318 (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
319 (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
320 (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
321 };
323 CSL_ecc_aggrRegs * SDR_ECC_aggrHighBaseAddressTableTrans[SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES];
325 /** -------------------------------------------------------------------------------------
326 * @brief This structure holds the list of Ram Ids for each memory subtype in MSMC AGGR0
327 * --------------------------------------------------------------------------------------
328 */
329 /* Note: While this table lists all the possible RAM ID's for the MSMC AGGR0, only the following
330 * 2 RAM ID's have been tested:
331 * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID = 20 (Interconnect type)
332 * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID = 100 (Wrapper type) */
333 const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
334 {
335 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_RAM_ID,
336 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_INJECT_TYPE,
337 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_ECC_TYPE }, // 0
338 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_RAM_ID,
339 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_INJECT_TYPE,
340 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_ECC_TYPE }, // 1
341 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_RAM_ID,
342 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_INJECT_TYPE,
343 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_ECC_TYPE }, // 2
344 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_RAM_ID,
345 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_INJECT_TYPE,
346 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_ECC_TYPE }, // 3
347 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_RAM_ID,
348 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_INJECT_TYPE,
349 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_ECC_TYPE }, // 4
350 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_RAM_ID,
351 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
352 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE }, // 5
353 { SDR_ECC_RAMID_INVALID,
354 SDR_ECC_INJECTTYPE_INVALID,
355 SDR_ECC_ECC_TYPE_INVALD }, // 6
356 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID,
357 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
358 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE }, // 7
359 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_RAM_ID,
360 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_INJECT_TYPE,
361 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_ECC_TYPE }, // 8
362 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_RAM_ID,
363 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_INJECT_TYPE,
364 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_ECC_TYPE }, // 9
365 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_RAM_ID,
366 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_INJECT_TYPE,
367 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_ECC_TYPE }, // 10
368 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_RAM_ID,
369 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_INJECT_TYPE,
370 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_ECC_TYPE }, // 11
371 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_RAM_ID,
372 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_INJECT_TYPE,
373 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_ECC_TYPE }, // 12
374 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
375 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
376 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE }, // 13
377 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_RAM_ID,
378 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_INJECT_TYPE,
379 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_ECC_TYPE }, // 14
380 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_RAM_ID,
381 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
382 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE }, // 15
383 { SDR_ECC_RAMID_INVALID,
384 SDR_ECC_INJECTTYPE_INVALID,
385 SDR_ECC_ECC_TYPE_INVALD }, // 16
386 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_RAM_ID,
387 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
388 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE }, // 17
389 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_RAM_ID,
390 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_INJECT_TYPE,
391 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_ECC_TYPE }, // 18
392 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_RAM_ID,
393 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_INJECT_TYPE,
394 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_ECC_TYPE }, // 19
395 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID,
396 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_INJECT_TYPE,
397 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ECC_TYPE }, // 20
398 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_RAM_ID,
399 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_INJECT_TYPE,
400 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_ECC_TYPE }, // 21
401 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
402 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
403 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 22
404 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_RAM_ID,
405 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
406 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 23
407 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
408 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
409 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 24
410 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_RAM_ID,
411 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
412 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 25
413 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_RAM_ID,
414 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_INJECT_TYPE,
415 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_ECC_TYPE }, // 26
416 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_RAM_ID,
417 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_INJECT_TYPE,
418 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_ECC_TYPE }, // 27
419 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
420 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
421 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 28
422 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
423 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
424 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 29
425 { SDR_ECC_RAMID_INVALID,
426 SDR_ECC_INJECTTYPE_INVALID,
427 SDR_ECC_ECC_TYPE_INVALD }, // 30
428 { SDR_ECC_RAMID_INVALID,
429 SDR_ECC_INJECTTYPE_INVALID,
430 SDR_ECC_ECC_TYPE_INVALD }, // 31
431 { SDR_ECC_RAMID_INVALID,
432 SDR_ECC_INJECTTYPE_INVALID,
433 SDR_ECC_ECC_TYPE_INVALD }, // 32
434 { SDR_ECC_RAMID_INVALID,
435 SDR_ECC_INJECTTYPE_INVALID,
436 SDR_ECC_ECC_TYPE_INVALD }, // 33
437 { SDR_ECC_RAMID_INVALID,
438 SDR_ECC_INJECTTYPE_INVALID,
439 SDR_ECC_ECC_TYPE_INVALD }, // 34
440 { SDR_ECC_RAMID_INVALID,
441 SDR_ECC_INJECTTYPE_INVALID,
442 SDR_ECC_ECC_TYPE_INVALD }, // 35
443 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_RAM_ID,
444 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
445 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 36
446 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_RAM_ID,
447 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
448 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 37
449 { SDR_ECC_RAMID_INVALID,
450 SDR_ECC_INJECTTYPE_INVALID,
451 SDR_ECC_ECC_TYPE_INVALD }, // 38
452 { SDR_ECC_RAMID_INVALID,
453 SDR_ECC_INJECTTYPE_INVALID,
454 SDR_ECC_ECC_TYPE_INVALD }, // 39
455 { SDR_ECC_RAMID_INVALID,
456 SDR_ECC_INJECTTYPE_INVALID,
457 SDR_ECC_ECC_TYPE_INVALD }, // 40
458 { SDR_ECC_RAMID_INVALID,
459 SDR_ECC_INJECTTYPE_INVALID,
460 SDR_ECC_ECC_TYPE_INVALD }, // 41
461 { SDR_ECC_RAMID_INVALID,
462 SDR_ECC_INJECTTYPE_INVALID,
463 SDR_ECC_ECC_TYPE_INVALD }, // 42
464 { SDR_ECC_RAMID_INVALID,
465 SDR_ECC_INJECTTYPE_INVALID,
466 SDR_ECC_ECC_TYPE_INVALD }, // 43
467 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_RAM_ID,
468 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
469 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 44
470 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_RAM_ID,
471 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
472 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 45
473 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_RAM_ID,
474 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
475 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 46
476 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_RAM_ID,
477 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
478 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 47
479 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_RAM_ID,
480 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_INJECT_TYPE,
481 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_ECC_TYPE }, // 48
482 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_RAM_ID,
483 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
484 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE }, // 49
485 { SDR_ECC_RAMID_INVALID,
486 SDR_ECC_INJECTTYPE_INVALID,
487 SDR_ECC_ECC_TYPE_INVALD }, // 50
488 { SDR_ECC_RAMID_INVALID,
489 SDR_ECC_INJECTTYPE_INVALID,
490 SDR_ECC_ECC_TYPE_INVALD }, // 51
491 { SDR_ECC_RAMID_INVALID,
492 SDR_ECC_INJECTTYPE_INVALID,
493 SDR_ECC_ECC_TYPE_INVALD }, // 52
494 { SDR_ECC_RAMID_INVALID,
495 SDR_ECC_INJECTTYPE_INVALID,
496 SDR_ECC_ECC_TYPE_INVALD }, // 53
497 { SDR_ECC_RAMID_INVALID,
498 SDR_ECC_INJECTTYPE_INVALID,
499 SDR_ECC_ECC_TYPE_INVALD }, // 54
500 { SDR_ECC_RAMID_INVALID,
501 SDR_ECC_INJECTTYPE_INVALID,
502 SDR_ECC_ECC_TYPE_INVALD }, // 55
503 { SDR_ECC_RAMID_INVALID,
504 SDR_ECC_INJECTTYPE_INVALID,
505 SDR_ECC_ECC_TYPE_INVALD }, // 56
506 { SDR_ECC_RAMID_INVALID,
507 SDR_ECC_INJECTTYPE_INVALID,
508 SDR_ECC_ECC_TYPE_INVALD }, // 57
509 { SDR_ECC_RAMID_INVALID,
510 SDR_ECC_INJECTTYPE_INVALID,
511 SDR_ECC_ECC_TYPE_INVALD }, // 58
512 { SDR_ECC_RAMID_INVALID,
513 SDR_ECC_INJECTTYPE_INVALID,
514 SDR_ECC_ECC_TYPE_INVALD }, // 59
515 { SDR_ECC_RAMID_INVALID,
516 SDR_ECC_INJECTTYPE_INVALID,
517 SDR_ECC_ECC_TYPE_INVALD }, // 60
518 { SDR_ECC_RAMID_INVALID,
519 SDR_ECC_INJECTTYPE_INVALID,
520 SDR_ECC_ECC_TYPE_INVALD }, // 61
521 { SDR_ECC_RAMID_INVALID,
522 SDR_ECC_INJECTTYPE_INVALID,
523 SDR_ECC_ECC_TYPE_INVALD }, // 62
524 { SDR_ECC_RAMID_INVALID,
525 SDR_ECC_INJECTTYPE_INVALID,
526 SDR_ECC_ECC_TYPE_INVALD }, // 63
527 { SDR_ECC_RAMID_INVALID,
528 SDR_ECC_INJECTTYPE_INVALID,
529 SDR_ECC_ECC_TYPE_INVALD }, // 64
530 { SDR_ECC_RAMID_INVALID,
531 SDR_ECC_INJECTTYPE_INVALID,
532 SDR_ECC_ECC_TYPE_INVALD }, // 65
533 { SDR_ECC_RAMID_INVALID,
534 SDR_ECC_INJECTTYPE_INVALID,
535 SDR_ECC_ECC_TYPE_INVALD }, // 66
536 { SDR_ECC_RAMID_INVALID,
537 SDR_ECC_INJECTTYPE_INVALID,
538 SDR_ECC_ECC_TYPE_INVALD }, // 67
539 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_RAM_ID,
540 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
541 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE }, // 68
542 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_RAM_ID,
543 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
544 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 69
545 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_RAM_ID,
546 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_INJECT_TYPE,
547 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ECC_TYPE }, // 70
548 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_RAM_ID,
549 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_INJECT_TYPE,
550 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_ECC_TYPE }, // 71
551 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_RAM_ID,
552 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
553 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 72
554 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_RAM_ID,
555 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
556 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 73
557 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_RAM_ID,
558 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_INJECT_TYPE,
559 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_ECC_TYPE }, // 74
560 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_RAM_ID,
561 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_INJECT_TYPE,
562 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_ECC_TYPE }, // 75
563 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_RAM_ID,
564 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_INJECT_TYPE,
565 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_ECC_TYPE }, // 76
566 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_RAM_ID,
567 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
568 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 77
569 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_RAM_ID,
570 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_INJECT_TYPE,
571 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_ECC_TYPE }, // 78
572 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_RAM_ID,
573 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_INJECT_TYPE,
574 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_ECC_TYPE }, // 79
575 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_RAM_ID,
576 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
577 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 80
578 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_RAM_ID,
579 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
580 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 81
581 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_RAM_ID,
582 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_INJECT_TYPE,
583 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_ECC_TYPE }, // 82
584 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_RAM_ID,
585 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_INJECT_TYPE,
586 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_ECC_TYPE }, // 83
587 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_RAM_ID,
588 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_INJECT_TYPE,
589 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_ECC_TYPE }, // 84
590 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_RAM_ID,
591 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
592 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 85
593 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_RAM_ID,
594 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_INJECT_TYPE,
595 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_ECC_TYPE }, // 86
596 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_RAM_ID,
597 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_INJECT_TYPE,
598 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_ECC_TYPE }, // 87
599 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_RAM_ID,
600 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
601 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 88
602 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_RAM_ID,
603 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
604 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 89
605 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_RAM_ID,
606 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_INJECT_TYPE,
607 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_ECC_TYPE }, // 90
608 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_RAM_ID,
609 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_INJECT_TYPE,
610 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_ECC_TYPE }, // 91
611 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_RAM_ID,
612 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_INJECT_TYPE,
613 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_ECC_TYPE }, // 92
614 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_RAM_ID,
615 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
616 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 93
617 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_RAM_ID,
618 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_INJECT_TYPE,
619 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_ECC_TYPE }, // 94
620 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_RAM_ID,
621 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_INJECT_TYPE,
622 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_ECC_TYPE }, // 95
623 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_RAM_ID,
624 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
625 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 96
626 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_RAM_ID,
627 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
628 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 97
629 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_RAM_ID,
630 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_INJECT_TYPE,
631 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_ECC_TYPE }, // 98
632 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_RAM_ID,
633 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_INJECT_TYPE,
634 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_ECC_TYPE }, // 99
635 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID,
636 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_INJECT_TYPE,
637 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ECC_TYPE }, // 100
638 { SDR_ECC_RAMID_INVALID,
639 SDR_ECC_INJECTTYPE_INVALID,
640 SDR_ECC_ECC_TYPE_INVALD }, // 101
641 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
642 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
643 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE }, // 102
644 { SDR_ECC_RAMID_INVALID,
645 SDR_ECC_INJECTTYPE_INVALID,
646 SDR_ECC_ECC_TYPE_INVALD }, // 103
647 { SDR_ECC_RAMID_INVALID,
648 SDR_ECC_INJECTTYPE_INVALID,
649 SDR_ECC_ECC_TYPE_INVALD }, // 104
650 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_RAM_ID,
651 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
652 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE }, // 105
653 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_RAM_ID,
654 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_INJECT_TYPE,
655 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_ECC_TYPE }, // 106
656 { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID,
657 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_INJECT_TYPE,
658 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ECC_TYPE }, // 107
659 };
661 const SDR_RAMIdEntry_t SDR_ECC_mcuEccAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
662 {
663 { CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID,
664 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE,
665 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE }, // 0 - Wrapper Type
666 { CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID,
667 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE,
668 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE }, // 1 - Wrapper Type
669 { CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID,
670 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE,
671 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE }, // 2 - Interconnect Type
672 };
674 /** ----------------------------------------------------------------------------------
675 * @brief This structure holds the memory config for each memory subtype in MCU domain
676 * -----------------------------------------------------------------------------------
677 */
678 const SDR_MemConfig_t SDR_ECC_mainMsmcAggr0MemEntries[SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
679 {
680 {SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, 0u,
681 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_SIZE, 4u,
682 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
683 };
685 /** ----------------------------------------------------------------------------------
686 * @brief This structure holds the memory config for each memory subtype in MCU CBASS
687 * -----------------------------------------------------------------------------------
688 */
689 const SDR_MemConfig_t SDR_ECC_MCUCBASSMemEntries[SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
690 {
691 {SDR_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID, 0u,
692 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u, ((bool)false) },
693 {SDR_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID, 0u,
694 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u, ((bool)false) },
695 };
697 /** ----------------------------------------------------------------------------------
698 * @brief This structure holds the ECC interconnect Group Checker information for
699 * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID RAM ID
700 * -----------------------------------------------------------------------------------
701 */
702 const SDR_GrpChkConfig_t SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
703 {
704 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
705 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH},
706 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
707 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH},
708 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
709 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH},
710 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
711 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH},
712 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
713 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH},
714 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
715 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH},
716 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
717 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH},
718 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
719 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH},
720 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
721 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH},
722 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
723 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH},
724 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
725 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH},
726 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
727 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH},
728 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
729 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH},
730 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
731 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH},
732 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
733 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH},
734 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
735 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH},
736 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
737 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH},
738 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
739 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH},
740 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
741 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH},
742 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
743 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH},
744 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
745 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH},
746 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
747 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH},
748 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
749 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH},
750 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
751 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH},
752 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
753 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH},
754 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
755 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH},
756 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
757 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH},
758 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
759 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH},
760 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
761 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH},
762 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
763 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH},
764 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
765 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH},
766 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
767 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH},
768 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
769 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH},
770 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
771 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH},
772 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
773 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH},
774 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
775 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH},
776 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
777 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH},
778 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
779 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH},
780 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
781 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH},
782 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
783 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH},
784 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
785 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH},
786 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
787 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH},
788 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
789 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH},
790 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
791 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH},
792 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
793 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH},
794 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
795 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH},
796 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
797 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH},
798 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
799 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH},
800 {CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
801 CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH},
802 };
804 /** ----------------------------------------------------------------------------------
805 * @brief This structure holds the ECC interconnect Group Checker information for
806 * SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE RAM ID
807 * -----------------------------------------------------------------------------------
808 */
809 const SDR_GrpChkConfig_t SDR_ECC_ramIdMsmcMMRBuseccGrpEntries[SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES] =
810 {
811 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_CHECKER_TYPE,
812 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_WIDTH},
813 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_CHECKER_TYPE,
814 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_WIDTH},
815 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_CHECKER_TYPE,
816 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_WIDTH},
817 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_CHECKER_TYPE,
818 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_WIDTH},
819 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_CHECKER_TYPE,
820 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_WIDTH},
821 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_CHECKER_TYPE,
822 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_WIDTH},
823 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_CHECKER_TYPE,
824 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_WIDTH},
825 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_CHECKER_TYPE,
826 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_WIDTH},
827 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_CHECKER_TYPE,
828 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_WIDTH},
829 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_CHECKER_TYPE,
830 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_WIDTH},
831 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_CHECKER_TYPE,
832 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_WIDTH},
833 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_CHECKER_TYPE,
834 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_WIDTH},
835 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_CHECKER_TYPE,
836 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_WIDTH},
837 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_CHECKER_TYPE,
838 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_WIDTH},
839 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_CHECKER_TYPE,
840 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_WIDTH},
841 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_CHECKER_TYPE,
842 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_WIDTH},
843 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_CHECKER_TYPE,
844 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_WIDTH},
845 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_CHECKER_TYPE,
846 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_WIDTH},
847 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_CHECKER_TYPE,
848 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_WIDTH},
849 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_CHECKER_TYPE,
850 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_WIDTH},
851 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_CHECKER_TYPE,
852 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_WIDTH},
853 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_CHECKER_TYPE,
854 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_WIDTH},
855 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_CHECKER_TYPE,
856 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_WIDTH},
857 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_CHECKER_TYPE,
858 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_WIDTH},
859 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_CHECKER_TYPE,
860 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_WIDTH},
861 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_CHECKER_TYPE,
862 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_WIDTH},
863 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_CHECKER_TYPE,
864 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_WIDTH},
865 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_CHECKER_TYPE,
866 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_WIDTH},
867 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_CHECKER_TYPE,
868 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_WIDTH},
869 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_CHECKER_TYPE,
870 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_WIDTH},
871 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_CHECKER_TYPE,
872 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_WIDTH},
873 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_CHECKER_TYPE,
874 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_WIDTH},
875 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_CHECKER_TYPE,
876 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_WIDTH},
877 {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_CHECKER_TYPE,
878 CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_WIDTH},
879 };
881 /* NOTE: Checkers information is not available currently for MCU CBASS ECC aggregator in CSLR.
882 This is a table added to demonstrate functionality and local defines are used */
884 #define CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE CSL_ECC_AGGR_CHECKER_TYPE_REDUNDANT
885 #define CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH (6U)
887 #define CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS (1U)
889 #define CSL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES \
890 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS
892 const SDR_GrpChkConfig_t SDR_ECC_MCU_CBASS_ramId2GrpEntries[CSL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES] =
893 {
894 {CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE,
895 CSL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH },
896 };
898 #endif /* INCLUDE_SDR_ECC_SOC_H_ */