9098b9341c5fc215ca786dad0c4819bd5e59f947
[processor-sdk/pdk.git] / packages / ti / drv / adcbuf / src / adcbuf_mmwave.c
1 /*
2  *  Copyright (c) Texas Instruments Incorporated 2021
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
33 /**************************************************************************
34  *************************** Include Files ********************************
35  **************************************************************************/
36 #include <stdint.h>
37 #include <string.h>
38 #include <stdlib.h>
39 #include <ti/osal/MemoryP.h>
40 #include <ti/drv/adcbuf/adcbuf.h>
41 #include <ti/drv/adcbuf/src/adcbuf_mmwave.h>
42 #include <ti/osal/DebugP.h>
43 #include <ti/osal/HwiP.h>
44 #include <ti/csl/cslr.h>
46 /*
47  * =============================================================================
48  * Local Definitions
49  * =============================================================================
50  */
51 /* Number of register bits to configure threshold */
52 #define ADCBUF_NUMBITS_CHIRPTHRESHOLD         (5U)
54 /* Number of register bits to configure number of samples */
55 #define ADCBUF_NUMBITS_NUMBER_SAMPLES         (16)
57 /* Number of register bits to configure channel address offset */
58 #define ADCBUF_NUMBITS_CHAN_ADDR_OFFSET       (11)
60 /*
61  * =============================================================================
62  * Function prototype
63  * =============================================================================
64  */
66 /* Internal Functions */
67 static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t source);
68 static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t mode);
69 static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,  uint16_t numSamples);
70 static void ADCBUFContinuousModeStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
71 static void ADCBUFConfigureDataFormat(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t dataFormat, uint8_t interleave, uint8_t iqConfig);
72 static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel, uint16_t offset);
73 static void ADCBUFChannelDisable(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel);
74 static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const ADCBuf_TestPatternConf *testPatternConf);
75 static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
76 static void ADCBUFTestPatternStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
77 static int32_t ADCBUFCQConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, ADCBuf_CQConf *cqCfg);
78 static int32_t ADCBUFDriverParamsCheck(const ADCBuf_Params *params);
79 static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg);
82 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
83 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
84 static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel);
86 /* External Functions */
87 void ADCBUF_MMWave_init(ADCBuf_Handle handle);
88 ADCBuf_Handle ADCBUF_MMWave_open(ADCBuf_Handle handle, const ADCBuf_Params *params);
89 void ADCBUF_MMWave_close(ADCBuf_Handle handle);
90 int_fast16_t ADCBUF_MMWave_control(ADCBuf_Handle handle, uint_fast8_t cmd, void * arg);
91 uint32_t ADCBUF_MMWave_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int32_t *errCode);
93 /*
94  * =============================================================================
95  * Constants
96  * =============================================================================
97  */
99 const ADCBuf_FxnTable gADCBufFxnTable = {
100     /*! Function to close the specified peripheral */
101     &ADCBUF_MMWave_close,
102     /*! Function to driver implementation specific control function */
103     &ADCBUF_MMWave_control,
104     /*! Function to initialize the given data object */
105     &ADCBUF_MMWave_init,
106     /*! Function to open the specified peripheral */
107     &ADCBUF_MMWave_open,
108     /*! Function to get ADCBuf channel address */
109     &ADCBUF_MMWave_getChanBufAddr
110 };
112 /*
113  * =============================================================================
114  * Internal  Function Definitions
115  * =============================================================================
116  */
118 /**
119  *  @b Description
120  *  @n
121  *      Selects the source of ADCBUF (DFE or HIL)
122  *      HIL is only support in XWR16xx/XWR18xx/XWR68xx
123  *
124  *  @param[in]  ptrRssCtrlRegBase
125  *      Pointer to the RSS CTRL Register Base
126  *  @param[in]  source
127  *      Source of the ADCBuf data.
128  *
129  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
130  *
131  *  @retval
132  *      N/A
133  */
134 static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t source)
136     /* Setup the ADC buffer source */
137     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->DMMSWINT1, 
138                        CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_MASK,
139                        CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_SHIFT,
140                        source);
143 /**
144  *  @b Description
145  *  @n
146  *      Set number of Chirps  threshold for Ping buffer to trigger ping/pong buffer switch
147  *
148  *  @param[in]  ptrRssCtrlRegBase
149  *      Pointer to the RSS CTRL Register Base
150  *  @param[in]  threshold
151  *      Number of chirps
152  *
153  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
154  *
155  *  @retval
156  *      N/A
157  */
158 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
160     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
161                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_MASK,
162                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_SHIFT,
163                        threshhold);
166 /**
167  *  @b Description
168  *  @n
169  *      Set number of Chirps  threshhold for Pong buffer to trigger ping/pong buffer switch
170  *
171  *  @param[in]  ptrRssCtrlRegBase
172  *      Pointer to the RSS CTRL Register Base
173  *  @param[in]  threshold
174  *      Number of chirps
175  *
176  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
177  *
178  *  @retval
179  *      N/A
180  */
181 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
183     /* Number of chirps for Pong buffer */
184     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
185                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_MASK,
186                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_SHIFT,
187                        threshhold);
190 /**
191  *  @b Description
192  *  @n
193  *      ADC Buffer continuous mode control. Set to 1 to operate in continuous mode
194  *
195  *  @param[in]  ptrRssCtrlRegBase
196  *      Base Address to the RSS CTRL Register Base
197  *  @param[in]  mode
198  *      Continuous mode, 1 to enable, 0 to disable.
199  *
200  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
201  *
202  *  @retval
203  *      N/A
204  */
205 static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t mode)
207     /* Setup the continuous mode control */
208     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
209                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_MASK,
210                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_SHIFT,
211                        mode);
214 /**
215  *  @b Description
216  *  @n
217  *      Start ADC Buffer in continuous mode.
218  *
219  *  @param[in]  ptrRssCtrlRegBase
220  *      Base address to the RSS CTRL Register Base
221  *  @param[in]  numSamples
222  *      Number of samples to be saved in ping/pong buffer before buffer switch.
223  *
224  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
225  *
226  *  @retval
227  *      N/A
228  */
229 static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,   uint16_t numSamples)
231     /* Starts the continuous mode operation */
232     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
233                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_MASK,
234                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_SHIFT,
235                        1U);
237     /* Setup the sample count */
238     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
239                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
240                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
241                        (uint32_t) numSamples);
244 /**
245  *  @b Description
246  *  @n
247  *      Stop ADC Buffer in continuous mode.
248  *
249  *  @param[in]  ptrRssCtrlRegBase
250  *      Base address to the RSS CTRL Register Base
251  *
252  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
253  *
254  *  @retval
255  *      N/A
256  */
257 static void ADCBUFContinuousModeStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
259     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
260                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_MASK,
261                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_SHIFT,
262                        1U);
265 /**
266  *  @b Description
267  *  @n
268  *      Configure ADC Buffer data format.
269  *
270  *  @param[in]  ptrRssCtrlRegBase
271  *      Pointer to the RSS CTRL Register Base
272  *  @param[in]  dataFormat
273  *      0 for complex, 1 for real data format.
274  *  @param[in]  interleave
275  *      Enable interleave mode.
276  *  @param[in]  iqConfig
277  *      In complex mode, 0 to store as Q(MSB) + I(LSB), 1 to store as I(MSB) +Q(LSB)
278  *      In Real mode, this field is don't care
279  *
280  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
281  *
282  *  @retval
283  *      N/A
284  */
285 static void ADCBUFConfigureDataFormat(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t dataFormat, uint8_t interleave, uint8_t iqConfig)
287     if(dataFormat == 0)    /* Complex data format */
288     {
289         /* The requested data format is complex */
290         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
291                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
292                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
293                         (uint32_t)dataFormat);
295         /* Setup the IQ swap configuration */
296         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
297                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_MASK,
298                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_SHIFT,
299                         (uint32_t)iqConfig);
300     }
301     else
302     {
303         /* The requested data format is real */
304         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
305                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
306                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
307                         (uint32_t)dataFormat);
308     }
310     /* Update the interleave mode */
311     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
312                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_MASK,
313                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_SHIFT,
314                     (uint32_t)interleave);
317 /**
318  *  @b Description
319  *  @n
320  *      Enable ADC Buffer RX channels
321  *
322  *  @param[in]  ptrRssCtrlRegBase
323  *      Pointer to the RSS CTRL Register Base
324  *  @param[in]  channel
325  *      RX channel number
326  *  @param[in]  offset
327  *      Address offset in Ping/Pong buffer
328  *
329  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
330  *
331  *  @retval
332  *      N/A
333  */
334 static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel, uint16_t offset)
336     switch(channel)
337     {
338         case 0U:
339             /* Enable the channel */
340             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
341                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
342                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
343                                1U);
345             /* Setup the offset */
346             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
347                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
348                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT,
349                                ((uint32_t)offset >> 4U));
350             break;
351         case 1U:
352             /* Enable the channel */
353             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
354                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
355                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
356                                1U);
358             /* Setup the offset */
359             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
360                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
361                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT,
362                                ((uint32_t)offset >> 4U));
363             break;
364         case 2U:
365             /* Enable the channel */
366             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
367                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
368                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
369                                1U);
371             /* Setup the offset */
372             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
373                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
374                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT,
375                                ((uint32_t)offset >> 4U));
376             break;
377         case 3U:
378             /* Enable the channel */
379             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
380                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
381                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
382                                1U);
384             /* Setup the offset */
385             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
386                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
387                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT,
388                                ((uint32_t)offset >> 4U));
389             break;
391         default:
392             /* Not  supported channels, code should not end up here */
393             DebugP_assert(0);
394             break;
395     }
398 /**
399  *  @b Description
400  *  @n
401  *      Disable ADC Buffer RX channels
402  *
403  *  @param[in]  ptrRssCtrlRegBase
404  *      Pointer to the RSS CTRL Register Base
405  *  @param[in]  channel
406  *      RX channel number
407  *
408  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
409  *
410  *  @retval
411  *      N/A
412  */
413 static void ADCBUFChannelDisable(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel)
415     /* Disable the channel */
416     if(channel == 0)
417     {
418         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
419                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
420                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
421                             0U);
422     }
423     else if (channel == 1)
424     {
425         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
426                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
427                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
428                             0U);
429     }
430     else if (channel == 2)
431     {
432         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
433                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
434                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
435                             0U);
436     }
437     else if (channel == 3)
438     {
439         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
440                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
441                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
442                             0U);
443     }
447 /**
448  *  @b Description
449  *  @n
450  *      Configure Test pattern for ADC Buffer. Based
451 *   on the passed values, it sets up the offset and value for each successive
452 *   sample for the test pattern IQ data, for each of the 4 channels. It also
453 *   configures period between successive samples of test pattern, and number of
454 *   samples to store(per channel) in each Ping and Pong register in continuous
455 *   mode of ADC Buffer.
456  *
457  *  @param[in]  ptrRssCtrlRegBase
458  *      Pointer to the RSS CTRL Register Base
459  *  @param[in]  testPatternConf
460  *      Configuratio of test pattern for all channels
461  *
462  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
463  *
464  *  @retval
465  *      N/A
466  */
467 static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const ADCBuf_TestPatternConf *testPatternConf)
469     /* Setup the test pattern */
470     /* RX1 Config */
471     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
472                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_MASK,
473                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_SHIFT,
474                         testPatternConf->rxConfig[0].rxIInc);
476     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
477                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_MASK,
478                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_SHIFT,
479                         testPatternConf->rxConfig[0].rxIOffset);
481     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
482                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_MASK,
483                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_SHIFT,
484                         testPatternConf->rxConfig[0].rxQInc);
486     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
487                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_MASK,
488                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_SHIFT,
489                         testPatternConf->rxConfig[0].rxQOffset);
491     /* RX2 Config */
492     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
493                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_MASK,
494                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_SHIFT,
495                         testPatternConf->rxConfig[1].rxIInc);
497     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
498                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_MASK,
499                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_SHIFT,
500                         testPatternConf->rxConfig[1].rxIOffset);
502     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
503                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_MASK,
504                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_SHIFT,
505                         testPatternConf->rxConfig[1].rxQInc);
507     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
508                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_MASK,
509                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_SHIFT,
510                         testPatternConf->rxConfig[1].rxQOffset);
512     /* RX3 Config */
513     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
514                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_MASK,
515                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_SHIFT,
516                         testPatternConf->rxConfig[2].rxIInc);
518     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
519                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_MASK,
520                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_SHIFT,
521                         testPatternConf->rxConfig[2].rxIOffset);
523     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
524                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_MASK,
525                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_SHIFT,
526                         testPatternConf->rxConfig[2].rxQInc);
528     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
529                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_MASK,
530                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_SHIFT,
531                         testPatternConf->rxConfig[2].rxQOffset);
533     /* RX4 Config */
534     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
535                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_MASK,
536                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_SHIFT,
537                         testPatternConf->rxConfig[3].rxIInc);
539     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
540                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_MASK,
541                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_SHIFT,
542                         testPatternConf->rxConfig[3].rxIOffset);
544     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
545                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_MASK,
546                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_SHIFT,
547                         testPatternConf->rxConfig[3].rxQInc);
549     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
550                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_MASK,
551                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_SHIFT,
552                         testPatternConf->rxConfig[3].rxQOffset);
554     /* Setup the period */
555     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
556                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
557                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
558                         testPatternConf->period);
560     /* Setup the sample count */
561     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
562                         CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
563                         CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
564                         (testPatternConf->numSamples));
567 /**
568  *  @b Description
569  *  @n
570  *      Starts the test pattern generation
571  *
572  *  @param[in]  ptrRssCtrlRegBase
573  *      Pointer to the RSS CTRL Register Base
574  *
575  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
576  *
577  *  @retval
578  *      N/A
579  */
580 static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
582     /* Lower the clock */
583     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
584                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
585                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
586                         0x32U);
588     /* Test pattern start */
589     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
590                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
591                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
592                         0x7U);
595 /**
596  *  @b Description
597  *  @n
598  *      Stop the test pattern generation
599  *
600  *  @param[in]  ptrRssCtrlRegBase
601  *      Pointer to the RSS CTRL Register Base
602  *
603  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
604  *
605  *  @retval
606  *      N/A
607  */
608 static void ADCBUFTestPatternStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
610     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
611                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
612                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
613                         0x0U);
616 /**
617  *  @b Description
618  *  @n
619  *      Configure the Chirp Quality parameters
620  *
621  *  @param[in]  ptrRssCtrlRegBase
622  *      Pointer to the RSS CTRL Register Base
623  *  @param[in]  cqCfg
624  *      Pointer to the CQ configuration
625  *
626  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
627  *
628  *  @retval
629  *      N/A
630  */
631 static int32_t ADCBUFCQConfig
633     CSL_rss_ctrlRegs     *ptrRssCtrlRegBase,
634     ADCBuf_CQConf        *cqCfg
637     int32_t errCode = ADCBUF_STATUS_SUCCESS;
638     
639     /* Configure the CQ data width */
640     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
641                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_MASK,
642                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_SHIFT,
643                         cqCfg->cqDataWidth);
645     /* Configure the if 96 bit pack mode */
646     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
647                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_MASK,
648                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_SHIFT,
649                         cqCfg->cq96BitPackEn);
651     /* Configure the CQ1 base address */
652     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
653                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
654                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT,
655                         ((uint32_t)cqCfg->cq0AddrOffset >> 4U));
657     /* Configure the CQ2 base address */
658     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
659                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
660                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT,
661                         ((uint32_t)cqCfg->cq1AddrOffset >> 4U));
663     /* Configure the CQ3 base address */
664     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
665                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
666                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT,
667                         ((uint32_t)cqCfg->cq2AddrOffset >> 4U));
669     return errCode;
673 /**
674  *  @b Description
675  *  @n
676  *      Parameter check for input parameters. This function should be called when a parameter is expected.
677  *  Hence arg should be a valid pointer.
678  *
679  *  @param[in]  params
680  *      Parameter block for the ADCBUF Instance. If NULL, it will use default values.
681  *
682  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
683  *
684  *  @retval
685  *      N/A
686  */
687 static int32_t ADCBUFDriverParamsCheck(const ADCBuf_Params *params)
689     int32_t retCode = ADCBUF_STATUS_SUCCESS;
690     uint32_t    paramVal;
692     /* Check continuous mode of the ADCBUF */
693     paramVal = params->continousMode;
694     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_CONTINUOUS_MODE, (void *)&paramVal);
695     if(retCode < 0)
696     {
697         return retCode;
698     }
700     paramVal = params->chirpThresholdPing;
701     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD, (void *)&paramVal);
702     if(retCode < 0)
703     {
704         return retCode;
705     }
707     paramVal = params->chirpThresholdPong;
708     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD, (void *)&paramVal);
709     if(retCode < 0)
710     {
711         return retCode;
712     }
714     return retCode;
717 /**
718  *  @b Description
719  *  @n
720  *      Parameter check for input parameters. This function should be called when a parameter is expected.
721  *  Hence arg should be a valid pointer.
722  *
723  *  @param[in]  cmd
724  *      ADCBUF control command
725  *  @param[in]  arg
726  *      ACCBUF control arguments.
727  *
728  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
729  *
730  *  @retval
731  *      N/A
732  */
733 static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg)
735     ADCBuf_dataFormat    *dataFormat;
736     ADCBuf_RxChanConf    *rxChanConf;
737     ADCBuf_CQConf        *cqConf;
738     uint32_t             paramVal;
740     int32_t retCode = ADCBUF_STATUS_SUCCESS;
742     /* Validate the pointer to the command arguments
743      * validate argument is 4 bytes  aligned.
744      */
745     if ((arg == (void *)NULL) || (((uint32_t)arg % 4U) != 0))
746     {
747         retCode = ADCBUF_STATUS_INVALID_PARAMS;
748     }
749     else
750     {
752         switch (cmd) {
753             /* 1 bit setting Command */
754             case ADCBufMMWave_CMD_SET_SRC:
755             case ADCBufMMWave_CMD_SET_CONTINUOUS_MODE:
756                 paramVal = *(uint32_t *)arg;
757                 if (paramVal >= ((uint32_t)0x1U << 1U))
758                 {
759                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
760                 }
761                 break;
763             case ADCBufMMWave_CMD_CONF_DATA_FORMAT:
764                 dataFormat = (ADCBuf_dataFormat *)arg;
766                 if ( (dataFormat->adcOutFormat >= (uint8_t)(0x1U << 1U))  ||
767                       (dataFormat->channelInterleave >= (uint8_t)(0x1U << 1U)) ||
768                       (dataFormat->sampleInterleave >= (uint8_t)(0x1U << 1U)) )
769                 {
770                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
771                 }
772                 break;
774             case ADCBufMMWave_CMD_CONF_CQ:
775                 cqConf = (ADCBuf_CQConf *)arg;
776                 if( (cqConf->cqDataWidth > (uint8_t)(0x1U<<2U)) ||
777                      (cqConf->cq96BitPackEn > (uint8_t)(0x1U << 1U)) )
778                 {
779                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
780                 }
781                 break;
783               case ADCBufMMWave_CMD_START_CONTINUOUS_MODE:
784                 /* 16 bits for NUMBER OF SAMPLES */
785                 paramVal = *(uint32_t *)arg;
786                 if( paramVal >= ((uint32_t)0x1U << ADCBUF_NUMBITS_NUMBER_SAMPLES))
787                 {
788                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
789                 }
790                 break;
792             case ADCBufMMWave_CMD_CHANNEL_ENABLE:
793                 rxChanConf = (ADCBuf_RxChanConf *)arg;
795                 /* Hardware supports channels 0-3 */
796                 if( (rxChanConf->channel >= NUM_RX_CHANNEL) ||
797                     (((uint32_t)rxChanConf->offset >> 4) >= ((uint32_t)0x1U << ADCBUF_NUMBITS_CHAN_ADDR_OFFSET)) )
798                 {
799                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
800                 }
801                 break;
803             case ADCBufMMWave_CMD_CHANNEL_DISABLE:
804                 paramVal = *(uint32_t *)arg;
806                 /* Hardware supports channels 0-3 */
807                 if(((paramVal & 0xFFFFFFF0U) != 0U) || (paramVal == 0U))
808                 {
809                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
810                 }
811                 break;
813             /* XWR16XX specific commands */
814             case ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD:
815             case ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD:
816                 if(((*(uint8_t *)arg) == 0) || ((*(uint8_t *)arg) > (uint8_t)(0x1U <<ADCBUF_NUMBITS_CHIRPTHRESHOLD)))
817                 {
818                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
819                 }
820                 break;
822             case ADCBufMMWave_CMD_SET_CHIRP_THRESHHOLD:
823                 retCode = ADCBUF_STATUS_INVALID_CMD;
824                 break;
826             default:
827                 break;
828         }
829     }
831     return retCode;
834 static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel)
836     uint32_t retVal = 0;
838     if(channel == 0)
839     {
840         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
841                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
842                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT);
843     }
844     else if(channel == 1)
845     {
846         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
847                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
848                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT);
849     }
850     else if(channel == 2)
851     {
852         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
853                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
854                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT);
855     }
856     else if(channel == 3)
857     {
858         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
859                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
860                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT);
861     }
863     return retVal;
866 /*
867  * =============================================================================
868  * External  Function Definitions
869  * =============================================================================
870  */
872 /**
873  *  @b Description
874  *  @n
875  *      Function to initializes the ADCBUF_MMWave driver. This function
876  *   must also be called before any other ADC driver APIs.
877  *
878  *  @param[in]  handle
879  *      ADCBUF Instance Handle
880  *
881  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
882  *
883  *  @retval
884  *      N/A
885  */
886 void ADCBUF_MMWave_init(ADCBuf_Handle handle)
888     return;
891 /**
892  *  @b Description
893  *  @n
894  *      Open ADCBUF Driver
895  *
896  *  @param[in]  handle
897  *      ADCBuf Instance Handle
898  *  @param[in]  params
899  *      Parameter block for the ADCBUF Instance. If NULL, it will use default values.
900  *
901  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
902  *
903  *  @retval
904  *      Success -   ADCBUF driver handle
905  *  @retval
906  *      Error     -   NULL
907  */
908 ADCBuf_Handle ADCBUF_MMWave_open(ADCBuf_Handle handle, const ADCBuf_Params *params)
910     ADCBufMMWave_Object      *ptrADCBufObject;
911     ADCBuf_HwCfg             *ptrADCBufHwCfg;
912     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
913     ADCBuf_Handle             retHandle = NULL;
915     /* Sanity check handle */
916     DebugP_assert(handle != (ADCBuf_Handle)NULL);
918     /* Sanity check handle */
919     DebugP_assert(params != (const ADCBuf_Params *)NULL);
921     /* Get the pointer to the object and hwAttrs */
922     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
924     /* Initialize object handle */
925     ptrADCBufObject = NULL;
927     /* Sanity check the driver is not opened */
928     if (handle->object != NULL)
929     {
930         /* Error: Driver is already being used. */
931         DebugP_log1 ("ADCBUF: Driver (%p) has already been opened\n", (uintptr_t)handle->object);
932     }
933     else
934     {
935         /* Validate params */
936         if ( ADCBUFDriverParamsCheck(params)< 0)
937         {
938              /* Error: Invalid chirpThreshold, put in debug log */
939             DebugP_log1 ("ADCBUF: Invalid chirp Threshold setting(%d)\n", params->chirpThresholdPing);
940         }
941         else
942         {
943             /* Allocate memory for the driver: */
944             ptrADCBufObject = MemoryP_ctrlAlloc ((uint32_t)sizeof(ADCBufMMWave_Object), 0);
945             if (ptrADCBufObject == NULL)
946             {
947                 /* Error: memory allocation failed */
948                 DebugP_log1 ("ADCBUF: Failed allocating memory for Driver(%p) Object\n", (uintptr_t)handle);
949             }
950             else
951             {
952                 /* Initialize the memory: */
953                 memset ((void *)ptrADCBufObject, 0, sizeof(ADCBufMMWave_Object));
955                 /* Save driver object */
956                 handle->object               = (void *)ptrADCBufObject;
957             }
958         }
959     }
961     /* ADCBuf hardware initialization */
962     if (ptrADCBufObject != NULL)
963     {
964         /* Get the DSS register base address  */
965         ptrRssCtrlRegBase = ptrADCBufHwCfg->ptrRSSCtrlRegBase;
967         ptrADCBufObject->ptrRssCtrlRegBase = ptrRssCtrlRegBase;
969         /* Configuration of ADCBUF params */
970         ADCBUFSrcSelect(ptrRssCtrlRegBase, (uint32_t)params->source);
971         ADCBUFContinuousModeCtrl(ptrRssCtrlRegBase, params->continousMode);
973         /* Configurate chirp threshold */
974         ADCBUFSetPingNumChirpThreshhold(ptrRssCtrlRegBase, ((uint32_t)params->chirpThresholdPing - 1U));
975         ADCBUFSetPongNumChirpThreshhold(ptrRssCtrlRegBase, ((uint32_t)params->chirpThresholdPong - 1U));
977         /* Mark the handle as being used */
978         ptrADCBufObject->isOpen = true;
980         retHandle = handle;
981     }
983     return retHandle;
987 /**
988  *  @b Description
989  *  @n
990  *      Close ADCBUF Driver. ADCBUF_MMWave_open() has to be called first.
991  *
992  *  @param[in]  handle
993  *      ADCBUF Instance Handle
994  *
995  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
996  *
997  *  @retval
998  *      None
999  */
1000 void ADCBUF_MMWave_close(ADCBuf_Handle handle)
1002     ADCBufMMWave_Object         *ptrADCBufObject;
1004     DebugP_assert( handle != (ADCBuf_Handle)NULL );
1006     /* Get the pointer to the object */
1007     ptrADCBufObject = handle->object;
1009     /* Mark the module as available */
1010     ptrADCBufObject->isOpen = false;
1012     /* Free the memory */
1013     MemoryP_ctrlFree (ptrADCBufObject, (uint32_t)sizeof(ADCBufMMWave_Object));
1015     /* Reset the object handle : */
1016     handle->object = NULL;
1019 /**
1020  *  @b Description
1021  *  @n
1022  *      Get/Set ADCBUF_MMWave specific ADCBUF functions
1023  *
1024  *  @param[in]  handle
1025  *      ADCBUF Instance Handle
1026  *  @param[in]  cmd
1027  *      Command to the ADCBUF driver
1028  *  @param[in]  arg
1029  *      Argument for the driver command
1030  *
1031  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1032  *
1033  *  @retval
1034  *      Status of the command execution
1035  */
1036 int_fast16_t ADCBUF_MMWave_control(ADCBuf_Handle handle, uint_fast8_t cmd, void *arg)
1038     ADCBufMMWave_Object     *object;
1039     CSL_rss_ctrlRegs        *ptrRssCtrlRegBase;
1040     int_fast16_t            status = ADCBUF_STATUS_SUCCESS;
1041     ADCBuf_dataFormat       *dataFormat;
1042     ADCBuf_RxChanConf       *rxChanConf;
1043     ADCBuf_TestPatternConf  *testPatternConf;
1044     ADCBuf_CQConf           *cqConf;
1045     uint32_t                 chirpThreshold;
1047     if (handle == (ADCBuf_Handle)NULL)
1048     {
1049         status = ADCBUF_STATUS_INVALID_PARAMS;
1050         return status;
1051     }
1053     /* Get the Object from ADCBuf Handle */
1054     object = handle->object;
1056     /* Get the DSSREG base address */
1057     ptrRssCtrlRegBase = object->ptrRssCtrlRegBase;
1059     status = ADCBUFCmdParamCheck((ADCBufMMWave_CMD)cmd, arg);
1061     switch (cmd) {
1062         case ADCBufMMWave_CMD_SET_SRC:
1063             if (status == ADCBUF_STATUS_SUCCESS)
1064             {
1065                 ADCBUFSrcSelect(ptrRssCtrlRegBase, *(uint32_t *)arg);
1066             }
1067             break;
1069         case ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD:
1070             if (status == ADCBUF_STATUS_SUCCESS)
1071             {
1072                 chirpThreshold = *(uint32_t *)arg;
1073                 ADCBUFSetPingNumChirpThreshhold(ptrRssCtrlRegBase, chirpThreshold - 1U);
1074             }
1075             break;
1077         case ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD:
1078             if (status == ADCBUF_STATUS_SUCCESS)
1079             {
1080                 chirpThreshold = *(uint32_t *)arg;
1081                 ADCBUFSetPongNumChirpThreshhold(ptrRssCtrlRegBase, chirpThreshold - 1U);
1082             }
1083             break;
1085         case ADCBufMMWave_CMD_SET_CONTINUOUS_MODE:
1086             if (status == ADCBUF_STATUS_SUCCESS)
1087             {
1088                 ADCBUFContinuousModeCtrl(ptrRssCtrlRegBase, *(uint32_t *)arg);
1089             }
1090             break;
1092         case ADCBufMMWave_CMD_START_CONTINUOUS_MODE:
1093             if (status == ADCBUF_STATUS_SUCCESS)
1094             {
1095                 ADCBUFContinuousModeStart(ptrRssCtrlRegBase, *(uint16_t *)arg);
1096             }
1097             break;
1099         case ADCBufMMWave_CMD_STOP_CONTINUOUS_MODE:
1100             ADCBUFContinuousModeStop(ptrRssCtrlRegBase);
1101             status = ADCBUF_STATUS_SUCCESS;
1102             break;
1104         case ADCBufMMWave_CMD_CONF_DATA_FORMAT:
1105             if (status == ADCBUF_STATUS_SUCCESS)
1106             {
1107                 dataFormat = (ADCBuf_dataFormat *)arg;
1108                 ADCBUFConfigureDataFormat(ptrRssCtrlRegBase, dataFormat->adcOutFormat,
1109                                                              dataFormat->channelInterleave,
1110                                                              dataFormat->sampleInterleave);
1111             }
1112             break;
1114         case ADCBufMMWave_CMD_CHANNEL_ENABLE:
1115             if (status == ADCBUF_STATUS_SUCCESS)
1116             {
1117                 rxChanConf = (ADCBuf_RxChanConf *)arg;
1118                 ADCBUFChannelEnSetOffset(ptrRssCtrlRegBase, rxChanConf->channel, rxChanConf->offset);
1119             }
1120             break;
1122         case ADCBufMMWave_CMD_CHANNEL_DISABLE:
1123             if (status == ADCBUF_STATUS_SUCCESS)
1124             {
1125                 uint8_t                  channel;
1126                 uint32_t                 channelMask;
1128                 channelMask = *(uint32_t *)arg;
1129                 for(channel = 0; channel < NUM_RX_CHANNEL; channel++)
1130                 {
1131                     if(channelMask & ((uint32_t)0x1U << channel))
1132                     {
1133                         ADCBUFChannelDisable(ptrRssCtrlRegBase, channel);
1134                     }
1135                 }
1136             }
1137             break;
1139         case ADCBufMMWave_CMD_CONF_TEST_PATTERN:
1140             testPatternConf = (ADCBuf_TestPatternConf *)arg;
1141             ADCBUFTestPatternConfig(ptrRssCtrlRegBase, testPatternConf);
1142             status = ADCBUF_STATUS_SUCCESS;
1143             break;
1145         case ADCBufMMWave_CMD_START_TEST_PATTERN:
1146             ADCBUFTestPatternStart(ptrRssCtrlRegBase);
1148             /* The following is for test pattern test only, in other cases, this value should not be touched. */
1149             ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
1150                                                    31U,
1151                                                    17U,
1152                                                    0U);
1153             status = ADCBUF_STATUS_SUCCESS;
1154             break;
1156         case ADCBufMMWave_CMD_STOP_TEST_PATTERN:
1157             ADCBUFTestPatternStop(ptrRssCtrlRegBase);
1158             status = ADCBUF_STATUS_SUCCESS;
1159             break;
1161         case ADCBufMMWave_CMD_CONF_CQ:
1162             if (status == ADCBUF_STATUS_SUCCESS)
1163             {
1164                 cqConf = (ADCBuf_CQConf *)arg;
1165                 status = ADCBUFCQConfig(ptrRssCtrlRegBase, cqConf);
1166             }
1167             break;
1169         default:
1170             status = ADCBUF_STATUS_UNDEFINEDCMD;
1171             break;
1172     }
1174     return status;
1177 /**
1178  *  @b Description
1179  *  @n
1180  *      Get address of ADC buffer for a given receive channel
1181  *
1182  *  @param[in]  handle
1183  *      ADCBuf Instance Handle
1184  *  @param[in]  channel
1185  *      ADCBuf receive channel number
1186  *  @param[in]  errCode
1187  *      Error code populated by driver if error condition is detected
1188  *
1189  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1190  *
1191  *  @retval
1192  *      Success -   ADCBuf Physical adderss of the receive channel
1193  *  @retval
1194  *      Error  -    0U
1195  */
1196 uint32_t ADCBUF_MMWave_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int32_t *errCode)
1198     ADCBufMMWave_Object      *ptrADCBufObject;
1199     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
1200     ADCBuf_HwCfg             *ptrADCBufHwCfg;
1201     uint32_t                 chanAddress = (uint32_t)0U;
1203     /* Parameter check */
1204     if ((channel >= NUM_RX_CHANNEL) ||
1205        (handle == (ADCBuf_Handle)NULL))
1206     {
1207         /* Out of range channel number or invalid handle */
1208         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1209         return chanAddress;
1210     }
1212     /* Sanity check Object handle */
1213     DebugP_assert(handle->object != (ADCBufMMWave_Object *)NULL);
1215     /* Get the Object from ADCBuf Handle */
1216     ptrADCBufObject = handle->object;
1218     /* Get the pointer to the object and hwAttrs */
1219     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
1221     /* Get the DSSREG base address */
1222     ptrRssCtrlRegBase = ptrADCBufObject->ptrRssCtrlRegBase;
1224     /* Set default value for errCode */
1225     *errCode = ADCBUF_STATUS_SUCCESS;
1227     /* Check if the channel is enabled? */
1228     /*if(CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG1, ADCBUFCFG1_RX0EN_BIT_END + channel,
1229                  ADCBUFCFG1_RX0EN_BIT_START + channel) != (uint32_t)0U)*/
1230     if(isChannelEnabled(ptrRssCtrlRegBase, channel) == (uint32_t)0U)
1231     {
1232         uint32_t addrOffset;
1234         switch(channel)
1235         {
1236             case 0U:
1237                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
1238                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
1239                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT);
1240                 break;
1241             case 1U:
1242                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
1243                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
1244                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT);
1245                 break;
1247             case 2U:
1248                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
1249                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
1250                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT);
1251                 break;
1252             case 3U:
1253                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
1254                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
1255                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT);
1256                 break;
1257             default:
1258                 *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1259                 break;
1260         }
1262         if(*errCode == ADCBUF_STATUS_SUCCESS)
1263         {
1264             /* Calculate the physical address for the channel */
1265             chanAddress = ptrADCBufHwCfg->ptrADCBUFBaseAddr + ((uint32_t)addrOffset << 4U);
1266         }
1267         else
1268         {
1269             /* Code should not reach here */
1270         }
1271     }
1272     else
1273     {
1274         /* Channel is not enabled */
1275         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1276     }
1278     return chanAddress;
1282 /**
1283  *  @b Description
1284  *  @n
1285  *      Get address of CQ buffer for a given CQ
1286  *
1287  *  @param[in]  handle
1288  *      ADCBuf Instance Handle
1289  *  @param[in]  cqType
1290  *      CQ type that request the buffer address
1291  *  @param[in]  errCode
1292  *      Error code populated by driver if error condition is detected
1293  *
1294  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1295  *
1296  *  @retval
1297  *      Success -   CQ buffer Physical adderss of the requested CQ type
1298  *  @retval
1299  *      Error  -    0U
1300  */
1301 uint32_t ADCBUF_MMWave_getCQBufAddr
1303     ADCBuf_Handle handle,
1304     ADCBufMMWave_CQType cqType,
1305     int32_t *errCode
1308     ADCBufMMWave_Object      *ptrADCBufObject;
1309     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
1310     ADCBuf_HwCfg             *ptrADCBufHwCfg;
1311     uint32_t                 chanAddress = 0U;
1312     uint32_t                 addrOffset;
1314     /* Set default value for errCode */
1315     *errCode = ADCBUF_STATUS_SUCCESS;
1317     /* Parameter check */
1318     if (handle == (ADCBuf_Handle)NULL)
1319     {
1320         /* Out of range channel number or invalid handle */
1321         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1322         return chanAddress;
1323     }
1325     /* Sanity check Object handle */
1326     DebugP_assert(handle->object != (ADCBufMMWave_Object *)NULL);
1328     /* Get the Object from ADCBuf Handle */
1329     ptrADCBufObject = handle->object;
1331     /* Get the pointer to the object and hwAttrs */
1332     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
1334     /* Get the DSSREG base address */
1335     ptrRssCtrlRegBase = ptrADCBufObject->ptrRssCtrlRegBase;
1337     switch(cqType)
1338     {
1339         case ADCBufMMWave_CQType_CQ0:
1340             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1341                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
1342                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT);
1344             break;
1346         case ADCBufMMWave_CQType_CQ1:
1347             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1348                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
1349                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT);
1351             break;
1353         case ADCBufMMWave_CQType_CQ2:
1354             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1355                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
1356                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT);
1358             break;
1360         default:
1361             *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1362             break;
1363     }
1365     if(*errCode == ADCBUF_STATUS_SUCCESS)
1366     {
1367         /* Calculate the physical address for the channel */
1368         chanAddress = ptrADCBufHwCfg->ptrCQBUFBaseAddr + ((uint32_t)addrOffset << 4U);
1369     }
1370     else
1371     {
1372         /* Return 0 indicating invalid address */
1373         chanAddress = (uint32_t)0U;
1374     }
1376     return chanAddress;