Fixed Jenkins daily build error in adcbuf and cbuff driver files.
[processor-sdk/pdk.git] / packages / ti / drv / adcbuf / src / adcbuf_mmwave.c
1 /*
2  *  Copyright (c) Texas Instruments Incorporated 2021
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
33 /**************************************************************************
34  *************************** Include Files ********************************
35  **************************************************************************/
36 #include <stdint.h>
37 #include <string.h>
38 #include <stdlib.h>
39 #include <ti/osal/MemoryP.h>
40 #include <ti/drv/adcbuf/adcbuf.h>
41 #include <ti/drv/adcbuf/src/adcbuf_mmwave.h>
42 #include <ti/osal/DebugP.h>
43 #include <ti/osal/HwiP.h>
44 #include <ti/csl/cslr.h>
46 /*
47  * =============================================================================
48  * Local Definitions
49  * =============================================================================
50  */
51 /* Number of register bits to configure threshold */
52 #define ADCBUF_NUMBITS_CHIRPTHRESHOLD         (5U)
54 /* Number of register bits to configure number of samples */
55 #define ADCBUF_NUMBITS_NUMBER_SAMPLES         (16)
57 /* Number of register bits to configure channel address offset */
58 #define ADCBUF_NUMBITS_CHAN_ADDR_OFFSET       (11)
60 /*
61  * =============================================================================
62  * Function prototype
63  * =============================================================================
64  */
66 /* Internal Functions */
67 static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t source);
68 static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t mode);
69 static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,  uint16_t numSamples);
70 static void ADCBUFContinuousModeStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
71 static void ADCBUFConfigureDataFormat(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t dataFormat, uint8_t interleave, uint8_t iqConfig);
72 static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel, uint16_t offset);
73 static void ADCBUFChannelDisable(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel);
74 static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const ADCBuf_TestPatternConf *testPatternConf);
75 static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
76 static void ADCBUFTestPatternStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase);
77 static int32_t ADCBUFCQConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, ADCBuf_CQConf *cqCfg);
78 static int32_t ADCBUFDriverParamsCheck(const ADCBuf_Params *params);
79 static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg);
82 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
83 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold);
84 static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel);
86 /*
87  * =============================================================================
88  * Internal  Function Definitions
89  * =============================================================================
90  */
92 /**
93  *  @b Description
94  *  @n
95  *      Selects the source of ADCBUF (DFE or HIL)
96  *      HIL is only support in XWR16xx/XWR18xx/XWR68xx
97  *
98  *  @param[in]  ptrRssCtrlRegBase
99  *      Pointer to the RSS CTRL Register Base
100  *  @param[in]  source
101  *      Source of the ADCBuf data.
102  *
103  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
104  *
105  *  @retval
106  *      N/A
107  */
108 static void ADCBUFSrcSelect(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t source)
110     /* Setup the ADC buffer source */
111     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->DMMSWINT1, 
112                        CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_MASK,
113                        CSL_RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN_SHIFT,
114                        source);
117 /**
118  *  @b Description
119  *  @n
120  *      Set number of Chirps  threshold for Ping buffer to trigger ping/pong buffer switch
121  *
122  *  @param[in]  ptrRssCtrlRegBase
123  *      Pointer to the RSS CTRL Register Base
124  *  @param[in]  threshold
125  *      Number of chirps
126  *
127  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
128  *
129  *  @retval
130  *      N/A
131  */
132 static void ADCBUFSetPingNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
134     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
135                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_MASK,
136                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPING_SHIFT,
137                        threshhold);
140 /**
141  *  @b Description
142  *  @n
143  *      Set number of Chirps  threshhold for Pong buffer to trigger ping/pong buffer switch
144  *
145  *  @param[in]  ptrRssCtrlRegBase
146  *      Pointer to the RSS CTRL Register Base
147  *  @param[in]  threshold
148  *      Number of chirps
149  *
150  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
151  *
152  *  @retval
153  *      N/A
154  */
155 static void ADCBUFSetPongNumChirpThreshhold(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t threshhold)
157     /* Number of chirps for Pong buffer */
158     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
159                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_MASK,
160                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFNUMCHRPPONG_SHIFT,
161                        threshhold);
164 /**
165  *  @b Description
166  *  @n
167  *      ADC Buffer continuous mode control. Set to 1 to operate in continuous mode
168  *
169  *  @param[in]  ptrRssCtrlRegBase
170  *      Base Address to the RSS CTRL Register Base
171  *  @param[in]  mode
172  *      Continuous mode, 1 to enable, 0 to disable.
173  *
174  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
175  *
176  *  @retval
177  *      N/A
178  */
179 static void ADCBUFContinuousModeCtrl(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t mode)
181     /* Setup the continuous mode control */
182     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
183                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_MASK,
184                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTMODEEN_SHIFT,
185                        mode);
188 /**
189  *  @b Description
190  *  @n
191  *      Start ADC Buffer in continuous mode.
192  *
193  *  @param[in]  ptrRssCtrlRegBase
194  *      Base address to the RSS CTRL Register Base
195  *  @param[in]  numSamples
196  *      Number of samples to be saved in ping/pong buffer before buffer switch.
197  *
198  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
199  *
200  *  @retval
201  *      N/A
202  */
203 static void ADCBUFContinuousModeStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase,   uint16_t numSamples)
205     /* Starts the continuous mode operation */
206     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
207                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_MASK,
208                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTRTPL_SHIFT,
209                        1U);
211     /* Setup the sample count */
212     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
213                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
214                        CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
215                        (uint32_t) numSamples);
218 /**
219  *  @b Description
220  *  @n
221  *      Stop ADC Buffer in continuous mode.
222  *
223  *  @param[in]  ptrRssCtrlRegBase
224  *      Base address to the RSS CTRL Register Base
225  *
226  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
227  *
228  *  @retval
229  *      N/A
230  */
231 static void ADCBUFContinuousModeStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
233     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
234                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_MASK,
235                        CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFCONTSTOPPL_SHIFT,
236                        1U);
239 /**
240  *  @b Description
241  *  @n
242  *      Configure ADC Buffer data format.
243  *
244  *  @param[in]  ptrRssCtrlRegBase
245  *      Pointer to the RSS CTRL Register Base
246  *  @param[in]  dataFormat
247  *      0 for complex, 1 for real data format.
248  *  @param[in]  interleave
249  *      Enable interleave mode.
250  *  @param[in]  iqConfig
251  *      In complex mode, 0 to store as Q(MSB) + I(LSB), 1 to store as I(MSB) +Q(LSB)
252  *      In Real mode, this field is don't care
253  *
254  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
255  *
256  *  @retval
257  *      N/A
258  */
259 static void ADCBUFConfigureDataFormat(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t dataFormat, uint8_t interleave, uint8_t iqConfig)
261     if(dataFormat == 0)    /* Complex data format */
262     {
263         /* The requested data format is complex */
264         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
265                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
266                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
267                         (uint32_t)dataFormat);
269         /* Setup the IQ swap configuration */
270         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
271                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_MASK,
272                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFIQSWAP_SHIFT,
273                         (uint32_t)iqConfig);
274     }
275     else
276     {
277         /* The requested data format is real */
278         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
279                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_MASK,
280                         CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFREALONLYMODE_SHIFT,
281                         (uint32_t)dataFormat);
282     }
284     /* Update the interleave mode */
285     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
286                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_MASK,
287                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_ADCBUFWRITEMODE_SHIFT,
288                     (uint32_t)interleave);
291 /**
292  *  @b Description
293  *  @n
294  *      Enable ADC Buffer RX channels
295  *
296  *  @param[in]  ptrRssCtrlRegBase
297  *      Pointer to the RSS CTRL Register Base
298  *  @param[in]  channel
299  *      RX channel number
300  *  @param[in]  offset
301  *      Address offset in Ping/Pong buffer
302  *
303  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
304  *
305  *  @retval
306  *      N/A
307  */
308 static void ADCBUFChannelEnSetOffset(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel, uint16_t offset)
310     switch(channel)
311     {
312         case 0U:
313             /* Enable the channel */
314             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
315                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
316                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
317                                1U);
319             /* Setup the offset */
320             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
321                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
322                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT,
323                                ((uint32_t)offset >> 4U));
324             break;
325         case 1U:
326             /* Enable the channel */
327             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
328                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
329                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
330                                1U);
332             /* Setup the offset */
333             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2, 
334                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
335                                CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT,
336                                ((uint32_t)offset >> 4U));
337             break;
338         case 2U:
339             /* Enable the channel */
340             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
341                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
342                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
343                                1U);
345             /* Setup the offset */
346             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
347                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
348                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT,
349                                ((uint32_t)offset >> 4U));
350             break;
351         case 3U:
352             /* Enable the channel */
353             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
354                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
355                                CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
356                                1U);
358             /* Setup the offset */
359             CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3, 
360                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
361                                CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT,
362                                ((uint32_t)offset >> 4U));
363             break;
365         default:
366             /* Not  supported channels, code should not end up here */
367             DebugP_assert(0);
368             break;
369     }
372 /**
373  *  @b Description
374  *  @n
375  *      Disable ADC Buffer RX channels
376  *
377  *  @param[in]  ptrRssCtrlRegBase
378  *      Pointer to the RSS CTRL Register Base
379  *  @param[in]  channel
380  *      RX channel number
381  *
382  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
383  *
384  *  @retval
385  *      N/A
386  */
387 static void ADCBUFChannelDisable(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint8_t channel)
389     /* Disable the channel */
390     if(channel == 0)
391     {
392         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
393                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
394                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT,
395                             0U);
396     }
397     else if (channel == 1)
398     {
399         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
400                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
401                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT,
402                             0U);
403     }
404     else if (channel == 2)
405     {
406         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
407                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
408                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT,
409                             0U);
410     }
411     else if (channel == 3)
412     {
413         CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1, 
414                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
415                             CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT,
416                             0U);
417     }
421 /**
422  *  @b Description
423  *  @n
424  *      Configure Test pattern for ADC Buffer. Based
425 *   on the passed values, it sets up the offset and value for each successive
426 *   sample for the test pattern IQ data, for each of the 4 channels. It also
427 *   configures period between successive samples of test pattern, and number of
428 *   samples to store(per channel) in each Ping and Pong register in continuous
429 *   mode of ADC Buffer.
430  *
431  *  @param[in]  ptrRssCtrlRegBase
432  *      Pointer to the RSS CTRL Register Base
433  *  @param[in]  testPatternConf
434  *      Configuratio of test pattern for all channels
435  *
436  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
437  *
438  *  @retval
439  *      N/A
440  */
441 static void ADCBUFTestPatternConfig(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, const ADCBuf_TestPatternConf *testPatternConf)
443     /* Setup the test pattern */
444     /* RX1 Config */
445     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
446                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_MASK,
447                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IINCR_SHIFT,
448                         testPatternConf->rxConfig[0].rxIInc);
450     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1ICFG, 
451                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_MASK,
452                         CSL_RSS_CTRL_TESTPATTERNRX1ICFG_TESTPATTERNRX1ICFG_TSTPATRX1IOFFSET_SHIFT,
453                         testPatternConf->rxConfig[0].rxIOffset);
455     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
456                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_MASK,
457                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QINCR_SHIFT,
458                         testPatternConf->rxConfig[0].rxQInc);
460     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX1QCFG, 
461                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_MASK,
462                         CSL_RSS_CTRL_TESTPATTERNRX1QCFG_TESTPATTERNRX1QCFG_TSTPATRX1QOFFSET_SHIFT,
463                         testPatternConf->rxConfig[0].rxQOffset);
465     /* RX2 Config */
466     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
467                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_MASK,
468                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IINCR_SHIFT,
469                         testPatternConf->rxConfig[1].rxIInc);
471     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2ICFG, 
472                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_MASK,
473                         CSL_RSS_CTRL_TESTPATTERNRX2ICFG_TESTPATTERNRX2ICFG_TSTPATRX2IOFFSET_SHIFT,
474                         testPatternConf->rxConfig[1].rxIOffset);
476     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
477                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_MASK,
478                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QINCR_SHIFT,
479                         testPatternConf->rxConfig[1].rxQInc);
481     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX2QCFG, 
482                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_MASK,
483                         CSL_RSS_CTRL_TESTPATTERNRX2QCFG_TESTPATTERNRX2QCFG_TSTPATRX2QOFFSET_SHIFT,
484                         testPatternConf->rxConfig[1].rxQOffset);
486     /* RX3 Config */
487     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
488                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_MASK,
489                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IINCR_SHIFT,
490                         testPatternConf->rxConfig[2].rxIInc);
492     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3ICFG, 
493                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_MASK,
494                         CSL_RSS_CTRL_TESTPATTERNRX3ICFG_TESTPATTERNRX3ICFG_TSTPATRX3IOFFSET_SHIFT,
495                         testPatternConf->rxConfig[2].rxIOffset);
497     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
498                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_MASK,
499                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QINCR_SHIFT,
500                         testPatternConf->rxConfig[2].rxQInc);
502     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX3QCFG, 
503                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_MASK,
504                         CSL_RSS_CTRL_TESTPATTERNRX3QCFG_TESTPATTERNRX3QCFG_TSTPATRX3QOFFSET_SHIFT,
505                         testPatternConf->rxConfig[2].rxQOffset);
507     /* RX4 Config */
508     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
509                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_MASK,
510                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IINCR_SHIFT,
511                         testPatternConf->rxConfig[3].rxIInc);
513     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4ICFG, 
514                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_MASK,
515                         CSL_RSS_CTRL_TESTPATTERNRX4ICFG_TESTPATTERNRX4ICFG_TSTPATRX4IOFFSET_SHIFT,
516                         testPatternConf->rxConfig[3].rxIOffset);
518     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
519                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_MASK,
520                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QINCR_SHIFT,
521                         testPatternConf->rxConfig[3].rxQInc);
523     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNRX4QCFG, 
524                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_MASK,
525                         CSL_RSS_CTRL_TESTPATTERNRX4QCFG_TESTPATTERNRX4QCFG_TSTPATRX4QOFFSET_SHIFT,
526                         testPatternConf->rxConfig[3].rxQOffset);
528     /* Setup the period */
529     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
530                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
531                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
532                         testPatternConf->period);
534     /* Setup the sample count */
535     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->ADCBUFCFG4, 
536                         CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_MASK,
537                         CSL_RSS_CTRL_ADCBUFCFG4_ADCBUFCFG4_ADCBUFSAMPCNT_SHIFT,
538                         (testPatternConf->numSamples));
541 /**
542  *  @b Description
543  *  @n
544  *      Starts the test pattern generation
545  *
546  *  @param[in]  ptrRssCtrlRegBase
547  *      Pointer to the RSS CTRL Register Base
548  *
549  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
550  *
551  *  @retval
552  *      N/A
553  */
554 static void ADCBUFTestPatternStart(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
556     /* Lower the clock */
557     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
558                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_MASK,
559                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATVLDCNT_SHIFT,
560                         0x32U);
562     /* Test pattern start */
563     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
564                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
565                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
566                         0x7U);
569 /**
570  *  @b Description
571  *  @n
572  *      Stop the test pattern generation
573  *
574  *  @param[in]  ptrRssCtrlRegBase
575  *      Pointer to the RSS CTRL Register Base
576  *
577  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
578  *
579  *  @retval
580  *      N/A
581  */
582 static void ADCBUFTestPatternStop(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase)
584     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->TESTPATTERNVLDCFG, 
585                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_MASK,
586                         CSL_RSS_CTRL_TESTPATTERNVLDCFG_TESTPATTERNVLDCFG_TSTPATGENEN_SHIFT,
587                         0x0U);
590 /**
591  *  @b Description
592  *  @n
593  *      Configure the Chirp Quality parameters
594  *
595  *  @param[in]  ptrRssCtrlRegBase
596  *      Pointer to the RSS CTRL Register Base
597  *  @param[in]  cqCfg
598  *      Pointer to the CQ configuration
599  *
600  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
601  *
602  *  @retval
603  *      N/A
604  */
605 static int32_t ADCBUFCQConfig
607     CSL_rss_ctrlRegs     *ptrRssCtrlRegBase,
608     ADCBuf_CQConf        *cqCfg
611     int32_t errCode = ADCBUF_STATUS_SUCCESS;
612     
613     /* Configure the CQ data width */
614     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
615                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_MASK,
616                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQDATAWIDTH_SHIFT,
617                         cqCfg->cqDataWidth);
619     /* Configure the if 96 bit pack mode */
620     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
621                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_MASK,
622                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ96BITPACKEN_SHIFT,
623                         cqCfg->cq96BitPackEn);
625     /* Configure the CQ1 base address */
626     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
627                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
628                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT,
629                         ((uint32_t)cqCfg->cq0AddrOffset >> 4U));
631     /* Configure the CQ2 base address */
632     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
633                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
634                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT,
635                         ((uint32_t)cqCfg->cq1AddrOffset >> 4U));
637     /* Configure the CQ3 base address */
638     CSL_REG32_FINS_RAW(&ptrRssCtrlRegBase->CQCFG1, 
639                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
640                         CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT,
641                         ((uint32_t)cqCfg->cq2AddrOffset >> 4U));
643     return errCode;
647 /**
648  *  @b Description
649  *  @n
650  *      Parameter check for input parameters. This function should be called when a parameter is expected.
651  *  Hence arg should be a valid pointer.
652  *
653  *  @param[in]  params
654  *      Parameter block for the ADCBUF Instance. If NULL, it will use default values.
655  *
656  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
657  *
658  *  @retval
659  *      N/A
660  */
661 static int32_t ADCBUFDriverParamsCheck(const ADCBuf_Params *params)
663     int32_t retCode = ADCBUF_STATUS_SUCCESS;
664     uint32_t    paramVal;
666     /* Check continuous mode of the ADCBUF */
667     paramVal = params->continousMode;
668     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_CONTINUOUS_MODE, (void *)&paramVal);
669     if(retCode < 0)
670     {
671         return retCode;
672     }
674     paramVal = params->chirpThresholdPing;
675     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD, (void *)&paramVal);
676     if(retCode < 0)
677     {
678         return retCode;
679     }
681     paramVal = params->chirpThresholdPong;
682     retCode = ADCBUFCmdParamCheck( ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD, (void *)&paramVal);
683     if(retCode < 0)
684     {
685         return retCode;
686     }
688     return retCode;
691 /**
692  *  @b Description
693  *  @n
694  *      Parameter check for input parameters. This function should be called when a parameter is expected.
695  *  Hence arg should be a valid pointer.
696  *
697  *  @param[in]  cmd
698  *      ADCBUF control command
699  *  @param[in]  arg
700  *      ACCBUF control arguments.
701  *
702  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
703  *
704  *  @retval
705  *      N/A
706  */
707 static int32_t ADCBUFCmdParamCheck(ADCBufMMWave_CMD cmd, void* arg)
709     ADCBuf_dataFormat    *dataFormat;
710     ADCBuf_RxChanConf    *rxChanConf;
711     ADCBuf_CQConf        *cqConf;
712     uint32_t             paramVal;
714     int32_t retCode = ADCBUF_STATUS_SUCCESS;
716     /* Validate the pointer to the command arguments
717      * validate argument is 4 bytes  aligned.
718      */
719     if ((arg == (void *)NULL) || (((uint32_t)arg % 4U) != 0))
720     {
721         retCode = ADCBUF_STATUS_INVALID_PARAMS;
722     }
723     else
724     {
726         switch (cmd) {
727             /* 1 bit setting Command */
728             case ADCBufMMWave_CMD_SET_SRC:
729             case ADCBufMMWave_CMD_SET_CONTINUOUS_MODE:
730                 paramVal = *(uint32_t *)arg;
731                 if (paramVal >= ((uint32_t)0x1U << 1U))
732                 {
733                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
734                 }
735                 break;
737             case ADCBufMMWave_CMD_CONF_DATA_FORMAT:
738                 dataFormat = (ADCBuf_dataFormat *)arg;
740                 if ( (dataFormat->adcOutFormat >= (uint8_t)(0x1U << 1U))  ||
741                       (dataFormat->channelInterleave >= (uint8_t)(0x1U << 1U)) ||
742                       (dataFormat->sampleInterleave >= (uint8_t)(0x1U << 1U)) )
743                 {
744                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
745                 }
746                 break;
748             case ADCBufMMWave_CMD_CONF_CQ:
749                 cqConf = (ADCBuf_CQConf *)arg;
750                 if( (cqConf->cqDataWidth > (uint8_t)(0x1U<<2U)) ||
751                      (cqConf->cq96BitPackEn > (uint8_t)(0x1U << 1U)) )
752                 {
753                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
754                 }
755                 break;
757               case ADCBufMMWave_CMD_START_CONTINUOUS_MODE:
758                 /* 16 bits for NUMBER OF SAMPLES */
759                 paramVal = *(uint32_t *)arg;
760                 if( paramVal >= ((uint32_t)0x1U << ADCBUF_NUMBITS_NUMBER_SAMPLES))
761                 {
762                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
763                 }
764                 break;
766             case ADCBufMMWave_CMD_CHANNEL_ENABLE:
767                 rxChanConf = (ADCBuf_RxChanConf *)arg;
769                 /* Hardware supports channels 0-3 */
770                 if( (rxChanConf->channel >= NUM_RX_CHANNEL) ||
771                     (((uint32_t)rxChanConf->offset >> 4) >= ((uint32_t)0x1U << ADCBUF_NUMBITS_CHAN_ADDR_OFFSET)) )
772                 {
773                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
774                 }
775                 break;
777             case ADCBufMMWave_CMD_CHANNEL_DISABLE:
778                 paramVal = *(uint32_t *)arg;
780                 /* Hardware supports channels 0-3 */
781                 if(((paramVal & 0xFFFFFFF0U) != 0U) || (paramVal == 0U))
782                 {
783                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
784                 }
785                 break;
787             /* XWR16XX specific commands */
788             case ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD:
789             case ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD:
790                 if(((*(uint8_t *)arg) == 0) || ((*(uint8_t *)arg) > (uint8_t)(0x1U <<ADCBUF_NUMBITS_CHIRPTHRESHOLD)))
791                 {
792                     retCode = ADCBUF_STATUS_INVALID_PARAMS;
793                 }
794                 break;
796             case ADCBufMMWave_CMD_SET_CHIRP_THRESHHOLD:
797                 retCode = ADCBUF_STATUS_INVALID_CMD;
798                 break;
800             default:
801                 break;
802         }
803     }
805     return retCode;
808 static uint32_t isChannelEnabled(CSL_rss_ctrlRegs  *ptrRssCtrlRegBase, uint32_t channel)
810     uint32_t retVal = 0;
812     if(channel == 0)
813     {
814         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
815                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_MASK,
816                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX0EN_SHIFT);
817     }
818     else if(channel == 1)
819     {
820         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
821                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_MASK,
822                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX1EN_SHIFT);
823     }
824     else if(channel == 2)
825     {
826         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
827                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_MASK,
828                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX2EN_SHIFT);
829     }
830     else if(channel == 3)
831     {
832         retVal = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG1,
833                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_MASK,
834                                     CSL_RSS_CTRL_ADCBUFCFG1_ADCBUFCFG1_RX3EN_SHIFT);
835     }
837     return retVal;
840 /*
841  * =============================================================================
842  * External  Function Definitions
843  * =============================================================================
844  */
846 /**
847  *  @b Description
848  *  @n
849  *      Function to initializes the ADCBUF_MMWave driver. This function
850  *   must also be called before any other ADC driver APIs.
851  *
852  *  @param[in]  handle
853  *      ADCBUF Instance Handle
854  *
855  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
856  *
857  *  @retval
858  *      N/A
859  */
860 void ADCBUF_MMWave_init(ADCBuf_Handle handle)
862     return;
865 /**
866  *  @b Description
867  *  @n
868  *      Open ADCBUF Driver
869  *
870  *  @param[in]  handle
871  *      ADCBuf Instance Handle
872  *  @param[in]  params
873  *      Parameter block for the ADCBUF Instance. If NULL, it will use default values.
874  *
875  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
876  *
877  *  @retval
878  *      Success -   ADCBUF driver handle
879  *  @retval
880  *      Error     -   NULL
881  */
882 ADCBuf_Handle ADCBUF_MMWave_open(ADCBuf_Handle handle, const ADCBuf_Params *params)
884     ADCBufMMWave_Object      *ptrADCBufObject;
885     ADCBuf_HwCfg             *ptrADCBufHwCfg;
886     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
887     ADCBuf_Handle             retHandle = NULL;
889     /* Sanity check handle */
890     DebugP_assert(handle != (ADCBuf_Handle)NULL);
892     /* Sanity check handle */
893     DebugP_assert(params != (const ADCBuf_Params *)NULL);
895     /* Get the pointer to the object and hwAttrs */
896     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
898     /* Initialize object handle */
899     ptrADCBufObject = NULL;
901     /* Sanity check the driver is not opened */
902     if (handle->object != NULL)
903     {
904         /* Error: Driver is already being used. */
905         DebugP_log1 ("ADCBUF: Driver (%p) has already been opened\n", (uintptr_t)handle->object);
906     }
907     else
908     {
909         /* Validate params */
910         if ( ADCBUFDriverParamsCheck(params)< 0)
911         {
912              /* Error: Invalid chirpThreshold, put in debug log */
913             DebugP_log1 ("ADCBUF: Invalid chirp Threshold setting(%d)\n", params->chirpThresholdPing);
914         }
915         else
916         {
917             /* Allocate memory for the driver: */
918             ptrADCBufObject = (ADCBufMMWave_Object* )MemoryP_ctrlAlloc ((uint32_t)sizeof(ADCBufMMWave_Object), 0);
919             if (ptrADCBufObject == NULL)
920             {
921                 /* Error: memory allocation failed */
922                 DebugP_log1 ("ADCBUF: Failed allocating memory for Driver(%p) Object\n", (uintptr_t)handle);
923             }
924             else
925             {
926                 /* Initialize the memory: */
927                 memset ((void *)ptrADCBufObject, 0, sizeof(ADCBufMMWave_Object));
929                 /* Save driver object */
930                 handle->object               = (void *)ptrADCBufObject;
931             }
932         }
933     }
935     /* ADCBuf hardware initialization */
936     if (ptrADCBufObject != NULL)
937     {
938         /* Get the DSS register base address  */
939         ptrRssCtrlRegBase = ptrADCBufHwCfg->ptrRSSCtrlRegBase;
941         ptrADCBufObject->ptrRssCtrlRegBase = ptrRssCtrlRegBase;
943         /* Configuration of ADCBUF params */
944         ADCBUFSrcSelect(ptrRssCtrlRegBase, (uint32_t)params->source);
945         ADCBUFContinuousModeCtrl(ptrRssCtrlRegBase, params->continousMode);
947         /* Configurate chirp threshold */
948         ADCBUFSetPingNumChirpThreshhold(ptrRssCtrlRegBase, ((uint32_t)params->chirpThresholdPing - 1U));
949         ADCBUFSetPongNumChirpThreshhold(ptrRssCtrlRegBase, ((uint32_t)params->chirpThresholdPong - 1U));
951         /* Mark the handle as being used */
952         ptrADCBufObject->isOpen = true;
954         retHandle = handle;
955     }
957     return retHandle;
961 /**
962  *  @b Description
963  *  @n
964  *      Close ADCBUF Driver. ADCBUF_MMWave_open() has to be called first.
965  *
966  *  @param[in]  handle
967  *      ADCBUF Instance Handle
968  *
969  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
970  *
971  *  @retval
972  *      None
973  */
974 void ADCBUF_MMWave_close(ADCBuf_Handle handle)
976     ADCBufMMWave_Object         *ptrADCBufObject;
978     DebugP_assert( handle != (ADCBuf_Handle)NULL );
980     /* Get the pointer to the object */
981     ptrADCBufObject = (ADCBufMMWave_Object* )handle->object;
983     /* Mark the module as available */
984     ptrADCBufObject->isOpen = false;
986     /* Free the memory */
987     MemoryP_ctrlFree (ptrADCBufObject, (uint32_t)sizeof(ADCBufMMWave_Object));
989     /* Reset the object handle : */
990     handle->object = NULL;
993 /**
994  *  @b Description
995  *  @n
996  *      Get/Set ADCBUF_MMWave specific ADCBUF functions
997  *
998  *  @param[in]  handle
999  *      ADCBUF Instance Handle
1000  *  @param[in]  cmd
1001  *      Command to the ADCBUF driver
1002  *  @param[in]  arg
1003  *      Argument for the driver command
1004  *
1005  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1006  *
1007  *  @retval
1008  *      Status of the command execution
1009  */
1010 int_fast16_t ADCBUF_MMWave_control(ADCBuf_Handle handle, uint_fast8_t cmd, void *arg)
1012     ADCBufMMWave_Object     *object;
1013     CSL_rss_ctrlRegs        *ptrRssCtrlRegBase;
1014     int_fast16_t            status = ADCBUF_STATUS_SUCCESS;
1015     ADCBuf_dataFormat       *dataFormat;
1016     ADCBuf_RxChanConf       *rxChanConf;
1017     ADCBuf_TestPatternConf  *testPatternConf;
1018     ADCBuf_CQConf           *cqConf;
1019     uint32_t                 chirpThreshold;
1021     if (handle == (ADCBuf_Handle)NULL)
1022     {
1023         status = ADCBUF_STATUS_INVALID_PARAMS;
1024         return status;
1025     }
1027     /* Get the Object from ADCBuf Handle */
1028     object = (ADCBufMMWave_Object* )handle->object;
1030     /* Get the DSSREG base address */
1031     ptrRssCtrlRegBase = object->ptrRssCtrlRegBase;
1033     status = ADCBUFCmdParamCheck((ADCBufMMWave_CMD)cmd, arg);
1035     switch (cmd) {
1036         case ADCBufMMWave_CMD_SET_SRC:
1037             if (status == ADCBUF_STATUS_SUCCESS)
1038             {
1039                 ADCBUFSrcSelect(ptrRssCtrlRegBase, *(uint32_t *)arg);
1040             }
1041             break;
1043         case ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD:
1044             if (status == ADCBUF_STATUS_SUCCESS)
1045             {
1046                 chirpThreshold = *(uint32_t *)arg;
1047                 ADCBUFSetPingNumChirpThreshhold(ptrRssCtrlRegBase, chirpThreshold - 1U);
1048             }
1049             break;
1051         case ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD:
1052             if (status == ADCBUF_STATUS_SUCCESS)
1053             {
1054                 chirpThreshold = *(uint32_t *)arg;
1055                 ADCBUFSetPongNumChirpThreshhold(ptrRssCtrlRegBase, chirpThreshold - 1U);
1056             }
1057             break;
1059         case ADCBufMMWave_CMD_SET_CONTINUOUS_MODE:
1060             if (status == ADCBUF_STATUS_SUCCESS)
1061             {
1062                 ADCBUFContinuousModeCtrl(ptrRssCtrlRegBase, *(uint32_t *)arg);
1063             }
1064             break;
1066         case ADCBufMMWave_CMD_START_CONTINUOUS_MODE:
1067             if (status == ADCBUF_STATUS_SUCCESS)
1068             {
1069                 ADCBUFContinuousModeStart(ptrRssCtrlRegBase, *(uint16_t *)arg);
1070             }
1071             break;
1073         case ADCBufMMWave_CMD_STOP_CONTINUOUS_MODE:
1074             ADCBUFContinuousModeStop(ptrRssCtrlRegBase);
1075             status = ADCBUF_STATUS_SUCCESS;
1076             break;
1078         case ADCBufMMWave_CMD_CONF_DATA_FORMAT:
1079             if (status == ADCBUF_STATUS_SUCCESS)
1080             {
1081                 dataFormat = (ADCBuf_dataFormat *)arg;
1082                 ADCBUFConfigureDataFormat(ptrRssCtrlRegBase, dataFormat->adcOutFormat,
1083                                                              dataFormat->channelInterleave,
1084                                                              dataFormat->sampleInterleave);
1085             }
1086             break;
1088         case ADCBufMMWave_CMD_CHANNEL_ENABLE:
1089             if (status == ADCBUF_STATUS_SUCCESS)
1090             {
1091                 rxChanConf = (ADCBuf_RxChanConf *)arg;
1092                 ADCBUFChannelEnSetOffset(ptrRssCtrlRegBase, rxChanConf->channel, rxChanConf->offset);
1093             }
1094             break;
1096         case ADCBufMMWave_CMD_CHANNEL_DISABLE:
1097             if (status == ADCBUF_STATUS_SUCCESS)
1098             {
1099                 uint8_t                  channel;
1100                 uint32_t                 channelMask;
1102                 channelMask = *(uint32_t *)arg;
1103                 for(channel = 0; channel < NUM_RX_CHANNEL; channel++)
1104                 {
1105                     if(channelMask & ((uint32_t)0x1U << channel))
1106                     {
1107                         ADCBUFChannelDisable(ptrRssCtrlRegBase, channel);
1108                     }
1109                 }
1110             }
1111             break;
1113         case ADCBufMMWave_CMD_CONF_TEST_PATTERN:
1114             testPatternConf = (ADCBuf_TestPatternConf *)arg;
1115             ADCBUFTestPatternConfig(ptrRssCtrlRegBase, testPatternConf);
1116             status = ADCBUF_STATUS_SUCCESS;
1117             break;
1119         case ADCBufMMWave_CMD_START_TEST_PATTERN:
1120             ADCBUFTestPatternStart(ptrRssCtrlRegBase);
1122             /* The following is for test pattern test only, in other cases, this value should not be touched. */
1123             ptrRssCtrlRegBase->ADCBUFCFG1 = CSL_FINSR(ptrRssCtrlRegBase->ADCBUFCFG1,
1124                                                    31U,
1125                                                    17U,
1126                                                    0U);
1127             status = ADCBUF_STATUS_SUCCESS;
1128             break;
1130         case ADCBufMMWave_CMD_STOP_TEST_PATTERN:
1131             ADCBUFTestPatternStop(ptrRssCtrlRegBase);
1132             status = ADCBUF_STATUS_SUCCESS;
1133             break;
1135         case ADCBufMMWave_CMD_CONF_CQ:
1136             if (status == ADCBUF_STATUS_SUCCESS)
1137             {
1138                 cqConf = (ADCBuf_CQConf *)arg;
1139                 status = ADCBUFCQConfig(ptrRssCtrlRegBase, cqConf);
1140             }
1141             break;
1143         default:
1144             status = ADCBUF_STATUS_UNDEFINEDCMD;
1145             break;
1146     }
1148     return status;
1151 /**
1152  *  @b Description
1153  *  @n
1154  *      Get address of ADC buffer for a given receive channel
1155  *
1156  *  @param[in]  handle
1157  *      ADCBuf Instance Handle
1158  *  @param[in]  channel
1159  *      ADCBuf receive channel number
1160  *  @param[in]  errCode
1161  *      Error code populated by driver if error condition is detected
1162  *
1163  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1164  *
1165  *  @retval
1166  *      Success -   ADCBuf Physical adderss of the receive channel
1167  *  @retval
1168  *      Error  -    0U
1169  */
1170 uint32_t ADCBUF_MMWave_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int32_t *errCode)
1172     ADCBufMMWave_Object      *ptrADCBufObject;
1173     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
1174     ADCBuf_HwCfg             *ptrADCBufHwCfg;
1175     uint32_t                 chanAddress = (uint32_t)0U;
1177     /* Parameter check */
1178     if ((channel >= NUM_RX_CHANNEL) ||
1179        (handle == (ADCBuf_Handle)NULL))
1180     {
1181         /* Out of range channel number or invalid handle */
1182         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1183         return chanAddress;
1184     }
1186     /* Sanity check Object handle */
1187     DebugP_assert(handle->object != (ADCBufMMWave_Object *)NULL);
1189     /* Get the Object from ADCBuf Handle */
1190     ptrADCBufObject = (ADCBufMMWave_Object* )handle->object;
1192     /* Get the pointer to the object and hwAttrs */
1193     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
1195     /* Get the DSSREG base address */
1196     ptrRssCtrlRegBase = ptrADCBufObject->ptrRssCtrlRegBase;
1198     /* Set default value for errCode */
1199     *errCode = ADCBUF_STATUS_SUCCESS;
1201     /* Check if the channel is enabled? */
1202     /*if(CSL_FEXTR(ptrRssCtrlRegBase->ADCBUFCFG1, ADCBUFCFG1_RX0EN_BIT_END + channel,
1203                  ADCBUFCFG1_RX0EN_BIT_START + channel) != (uint32_t)0U)*/
1204     if(isChannelEnabled(ptrRssCtrlRegBase, channel) == (uint32_t)0U)
1205     {
1206         uint32_t addrOffset;
1208         switch(channel)
1209         {
1210             case 0U:
1211                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
1212                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_MASK,
1213                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX0_SHIFT);
1214                 break;
1215             case 1U:
1216                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG2,
1217                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_MASK,
1218                                                 CSL_RSS_CTRL_ADCBUFCFG2_ADCBUFCFG2_ADCBUFADDRX1_SHIFT);
1219                 break;
1221             case 2U:
1222                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
1223                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_MASK,
1224                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX2_SHIFT);
1225                 break;
1226             case 3U:
1227                 addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->ADCBUFCFG3,
1228                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_MASK,
1229                                                 CSL_RSS_CTRL_ADCBUFCFG3_ADCBUFCFG3_ADCBUFADDRX3_SHIFT);
1230                 break;
1231             default:
1232                 *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1233                 break;
1234         }
1236         if(*errCode == ADCBUF_STATUS_SUCCESS)
1237         {
1238             /* Calculate the physical address for the channel */
1239             chanAddress = ptrADCBufHwCfg->ptrADCBUFBaseAddr + ((uint32_t)addrOffset << 4U);
1240         }
1241         else
1242         {
1243             /* Code should not reach here */
1244         }
1245     }
1246     else
1247     {
1248         /* Channel is not enabled */
1249         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1250     }
1252     return chanAddress;
1256 /**
1257  *  @b Description
1258  *  @n
1259  *      Get address of CQ buffer for a given CQ
1260  *
1261  *  @param[in]  handle
1262  *      ADCBuf Instance Handle
1263  *  @param[in]  cqType
1264  *      CQ type that request the buffer address
1265  *  @param[in]  errCode
1266  *      Error code populated by driver if error condition is detected
1267  *
1268  *  \ingroup ADCBUF_DRIVER_INTERNAL_FUNCTION
1269  *
1270  *  @retval
1271  *      Success -   CQ buffer Physical adderss of the requested CQ type
1272  *  @retval
1273  *      Error  -    0U
1274  */
1275 uint32_t ADCBUF_MMWave_getCQBufAddr
1277     ADCBuf_Handle handle,
1278     ADCBufMMWave_CQType cqType,
1279     int32_t *errCode
1282     ADCBufMMWave_Object      *ptrADCBufObject;
1283     CSL_rss_ctrlRegs         *ptrRssCtrlRegBase;
1284     ADCBuf_HwCfg             *ptrADCBufHwCfg;
1285     uint32_t                 chanAddress = 0U;
1286     uint32_t                 addrOffset;
1288     /* Set default value for errCode */
1289     *errCode = ADCBUF_STATUS_SUCCESS;
1291     /* Parameter check */
1292     if (handle == (ADCBuf_Handle)NULL)
1293     {
1294         /* Out of range channel number or invalid handle */
1295         *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1296         return chanAddress;
1297     }
1299     /* Sanity check Object handle */
1300     DebugP_assert(handle->object != (ADCBufMMWave_Object *)NULL);
1302     /* Get the Object from ADCBuf Handle */
1303     ptrADCBufObject = (ADCBufMMWave_Object* )handle->object;
1305     /* Get the pointer to the object and hwAttrs */
1306     ptrADCBufHwCfg = (ADCBuf_HwCfg *)handle->hwAttrs;
1308     /* Get the DSSREG base address */
1309     ptrRssCtrlRegBase = ptrADCBufObject->ptrRssCtrlRegBase;
1311     switch(cqType)
1312     {
1313         case ADCBufMMWave_CQType_CQ0:
1314             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1315                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_MASK,
1316                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ0BASEADDR_SHIFT);
1318             break;
1320         case ADCBufMMWave_CQType_CQ1:
1321             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1322                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_MASK,
1323                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ1BASEADDR_SHIFT);
1325             break;
1327         case ADCBufMMWave_CQType_CQ2:
1328             addrOffset = CSL_REG32_FEXT_RAW(&ptrRssCtrlRegBase->CQCFG1,
1329                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_MASK,
1330                                             CSL_RSS_CTRL_CQCFG1_CQCFG1_CQ2BASEADDR_SHIFT);
1332             break;
1334         default:
1335             *errCode = ADCBUF_STATUS_INVALID_PARAMS;
1336             break;
1337     }
1339     if(*errCode == ADCBUF_STATUS_SUCCESS)
1340     {
1341         /* Calculate the physical address for the channel */
1342         chanAddress = ptrADCBufHwCfg->ptrCQBUFBaseAddr + ((uint32_t)addrOffset << 4U);
1343     }
1344     else
1345     {
1346         /* Return 0 indicating invalid address */
1347         chanAddress = (uint32_t)0U;
1348     }
1350     return chanAddress;