1 /****************************************************************************\\r
2 * (C) Copyright 2009, Texas Instruments, Inc. *\r
3 * *\r
4 * Redistribution and use in source and binary forms, with or without *\r
5 * modification, are permitted provided that the following conditions *\r
6 * are met: *\r
7 * *\r
8 * Redistributions of source code must retain the above copyright *\r
9 * notice, this list of conditions and the following disclaimer. *\r
10 * *\r
11 * Redistributions in binary form must reproduce the above copyright *\r
12 * notice, this list of conditions and the following disclaimer in the *\r
13 * documentation and/or other materials provided with the *\r
14 * distribution. *\r
15 * *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of *\r
17 * its contributors may be used to endorse or promote products derived *\r
18 * from this software without specific prior written permission. *\r
19 * *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *\r
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *\r
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *\r
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *\r
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *\r
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *\r
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *\r
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *\r
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *\r
31 ****************************************************************************\r
32 * *\r
33 * Target processors : TMS320C66xx *\r
34 * *\r
35 \****************************************************************************/\r
36 \r
37 #include <string.h>\r
38 #include <stdio.h>\r
39 #include <stdint.h>\r
40 \r
41 #include <ti/csl/csl.h>\r
42 #include <ti/drv/aif2/aif2fl.h>\r
43 #include <ti/drv/aif2/aif2fl_hwControlAux.h>\r
44 #ifndef K2\r
45 #include <ti/csl/csl_psc.h>\r
46 #include <ti/csl/csl_pscAux.h>\r
47 #else\r
48 #include <ti/csl/csl_serdes_restore_default.h>\r
49 #include <ti/csl/csl_serdes_aif2.h>\r
50 #endif\r
51 #include <ti/csl/soc.h>\r
52 #include <ti/csl/csl_cgem.h>\r
53 \r
54 #include <ti/drv/aif2/AIF_defs.h>\r
55 #include <ti/drv/aif2/AIF_init_dat.h>\r
56 #include <ti/drv/aif2/AIF_fsync.h>\r
57 #include <ti/drv/aif2/AIF_calcParam.h>\r
58 #include <ti/drv/aif2/aif2_osal.h>\r
59 #include <ti/drv/aif2/aif2ver.h>\r
60 #include <ti/drv/aif2/AIF_cfg.h>\r
61 \r
62 #include <ti/drv/cppi/cppi_drv.h>\r
63 #include <ti/drv/cppi/cppi_desc.h>\r
64 #include <ti/drv/qmss/qmss_drv.h>\r
65 \r
66 #define __AIF_INIT_C\r
67 #include <ti/drv/aif2/AIF_init.h>\r
68 \r
69 // Bit count over 32 bits\r
70 #ifdef _TMS320C6X\r
71 #define _bitc32(a) _dotpu4(_bitc4(a),0x01010101)\r
72 #else\r
73 static uint32_t _bitc32(uint32_t i)\r
74 {\r
75 i = i - ((i >> 1) & 0x55555555);\r
76 i = (i & 0x33333333) + ((i >> 2) & 0x33333333);\r
77 return (((i + (i >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24;\r
78 }\r
79 #endif\r
80 \r
81 #ifdef _TMS320C6X\r
82 #pragma CODE_SECTION(AIF_initHw, ".text:aifDriver");\r
83 #pragma CODE_SECTION(AIF_startHw, ".text:aifDriver");\r
84 #pragma CODE_SECTION(AIF_initDio, ".text:aifDriver");\r
85 #pragma CODE_SECTION(AIF_initPktDma, ".text:aifDriver");\r
86 #pragma CODE_SECTION(AIF_getEgressGroupId, ".text:aifDriver");\r
87 #ifdef K2\r
88 #pragma CODE_SECTION(AIF_serdesConfig, ".text:aifDriver");\r
89 #pragma CODE_SECTION(AIF_serdesRestoreDefault, ".text:aifDriver");\r
90 #endif\r
91 #pragma CODE_SECTION(AIF_configureAtEvent, ".text:aifDriver");\r
92 #pragma CODE_SECTION(AIF_enableAtEvent, ".text:aifDriver");\r
93 #pragma CODE_SECTION(AIF_disableAtEvent, ".text:aifDriver");\r
94 #pragma CODE_SECTION(AIF_configureEgrDioEvent, ".text:aifDriver");\r
95 #pragma CODE_SECTION(AIF_enableEgrDioEvent, ".text:aifDriver");\r
96 #pragma CODE_SECTION(AIF_disableEgrDioEvent, ".text:aifDriver");\r
97 #pragma CODE_SECTION(AIF_configureIngrDioEvent, ".text:aifDriver");\r
98 #pragma CODE_SECTION(AIF_enableIngrDioEvent, ".text:aifDriver");\r
99 #pragma CODE_SECTION(AIF_disableIngrDioEvent, ".text:aifDriver");\r
100 #pragma CODE_SECTION(AIF_configureEgrDioEngine, ".text:aifDriver");\r
101 #pragma CODE_SECTION(AIF_configureIngrDioEngine, ".text:aifDriver");\r
102 #pragma CODE_SECTION(AIF_setRadTimerTc, ".text:aifDriver");\r
103 #pragma CODE_SECTION(AIF_setPhyTimerInit, ".text:aifDriver");\r
104 #pragma CODE_SECTION(AIF_setUlRadTimerInit, ".text:aifDriver");\r
105 #pragma CODE_SECTION(AIF_setDlRadTimerInit, ".text:aifDriver");\r
106 #pragma CODE_SECTION(AIF_setRmLinkSetupParams, ".text:aifDriver");\r
107 #pragma CODE_SECTION(AIF_setLinkPiMax, ".text:aifDriver");\r
108 #pragma CODE_SECTION(AIF_setPeFrameTC, ".text:aifDriver");\r
109 #pragma CODE_SECTION(AIF_setPeFrameMsgTc, ".text:aifDriver");\r
110 #pragma CODE_SECTION(AIF_setPdChDioOffset, ".text:aifDriver");\r
111 #pragma CODE_SECTION(AIF2_getVersion, ".text:aifDriver");\r
112 #pragma CODE_SECTION(AIF2_getVersionStr, ".text:aifDriver");\r
113 \r
114 #pragma CODE_SECTION(initEgrGroupInfo, ".text:aifDriver");\r
115 #pragma CODE_SECTION(initIngrGroupInfo, ".text:aifDriver");\r
116 #pragma CODE_SECTION(addAxCtoEgrGroupTable, ".text:aifDriver");\r
117 #pragma CODE_SECTION(addAxCtoIngrGroupTable, ".text:aifDriver");\r
118 #pragma CODE_SECTION(getEgrGroupId, ".text:aifDriver");\r
119 \r
120 #pragma DATA_SECTION(aif2Setup,".far:aifDriver");\r
121 #pragma DATA_SECTION(aif2Param,".far:aifDriver");\r
122 #pragma DATA_SECTION(linkSetup,".far:aifDriver");\r
123 #pragma DATA_SECTION(globalSetup,".far:aifDriver");\r
124 #pragma DATA_SECTION(commonSetup,".far:aifDriver");\r
125 #pragma DATA_SECTION(SdCommonSetup,".far:aifDriver");\r
126 #pragma DATA_SECTION(PdCommonSetup,".far:aifDriver");\r
127 #pragma DATA_SECTION(PeCommonSetup,".far:aifDriver");\r
128 #pragma DATA_SECTION(IngrDbSetup,".far:aifDriver");\r
129 #pragma DATA_SECTION(EgrDbSetup,".far:aifDriver");\r
130 #pragma DATA_SECTION(AdCommonSetup,".far:aifDriver");\r
131 #pragma DATA_SECTION(AdDioSetup,".far:aifDriver");\r
132 #pragma DATA_SECTION(AtCommonSetup,".far:aifDriver");\r
133 #pragma DATA_SECTION(AtEventSetup,".far:aifDriver");\r
134 #pragma DATA_SECTION(PhyTimerTc,".far:aifDriver");\r
135 #pragma DATA_SECTION(RadTimerTc,".far:aifDriver");\r
136 #pragma DATA_SECTION(PhyTimerInit,".far:aifDriver");\r
137 #pragma DATA_SECTION(RadTimerInit,".far:aifDriver");\r
138 #pragma DATA_SECTION(UlRadTimerInit,".far:aifDriver");\r
139 #pragma DATA_SECTION(DlRadTimerInit,".far:aifDriver");\r
140 #pragma DATA_SECTION(ComLinkSetup,".far:aifDriver");\r
141 #pragma DATA_SECTION(SdLinkSetup,".far:aifDriver");\r
142 #pragma DATA_SECTION(RmLinkSetup,".far:aifDriver");\r
143 #pragma DATA_SECTION(TmLinkSetup,".far:aifDriver");\r
144 #pragma DATA_SECTION(PdLinkSetup,".far:aifDriver");\r
145 #pragma DATA_SECTION(PeLinkSetup,".far:aifDriver");\r
146 #pragma DATA_SECTION(RtLinkSetup,".far:aifDriver");\r
147 #pragma DATA_SECTION(AtLinkSetup,".far:aifDriver");\r
148 #pragma DATA_SECTION(Aif2Obj,".far:aifDriver");\r
149 #pragma DATA_SECTION(Aif2Context,".far:aifDriver");\r
150 #pragma DATA_SECTION(superPacket,".far:aifDriver");\r
151 #pragma DATA_SECTION(egrGroupInfo,".far:aifDriver");\r
152 #pragma DATA_SECTION(aif2LldVersionStr,".far:aifDriver");\r
153 #endif\r
154 \r
155 #ifdef _TMS320C6X\r
156 #ifdef _LITTLE_ENDIAN\r
157 #define DEVICE_LE\r
158 #endif\r
159 #else\r
160 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\r
161 #define DEVICE_LE\r
162 #endif\r
163 #endif\r
164 \r
165 \r
166 static Aif2Fl_Setup aif2Setup;//Aif2 HW setup\r
167 static Aif2Fl_Param aif2Param;//AIF2 module specific parameters\r
168 static Aif2Fl_LinkSetup linkSetup[AIF_MAX_NUM_LINKS];// Setup for links\r
169 static Aif2Fl_GlobalSetup globalSetup;// global config for AIF2\r
170 static Aif2Fl_CommonSetup commonSetup; // Setup for common params\r
171 \r
172 static Aif2Fl_SdCommonSetup SdCommonSetup;//SERDES common setup\r
173 static Aif2Fl_PdCommonSetup PdCommonSetup;//PD common setup\r
174 static Aif2Fl_PeCommonSetup PeCommonSetup;//PE common setup\r
175 static Aif2Fl_IngrDbSetup IngrDbSetup;// Ingress data buffer setup\r
176 static Aif2Fl_EgrDbSetup EgrDbSetup;// Egress data buffer setup\r
177 static Aif2Fl_AdCommonSetup AdCommonSetup;// Aif2 DMA common setup\r
178 static Aif2Fl_AdDioSetup AdDioSetup;// Aif2 DIO common setup\r
179 static Aif2Fl_AtCommonSetup AtCommonSetup; // Aif2 Timer common setup\r
180 static Aif2Fl_AtEventSetup AtEventSetup; // Aif2 Timer external and internal event setup\r
181 static Aif2Fl_AtCountObj PhyTimerTc;// AT Phy Terminal Count setup\r
182 static Aif2Fl_AtCountObj RadTimerTc;// AT Rad Terminal Count setup\r
183 static Aif2Fl_AtCountObj PhyTimerInit;// AT Phy Init value setup\r
184 static Aif2Fl_AtCountObj RadTimerInit;// AT Rad Init value setup\r
185 static Aif2Fl_AtCountObj UlRadTimerInit;// AT Rad Init value setup\r
186 static Aif2Fl_AtCountObj DlRadTimerInit;// AT Rad Init value setup\r
187 \r
188 static Aif2Fl_CommonLinkSetup ComLinkSetup[AIF_MAX_NUM_LINKS]; // Aif2 link common setup\r
189 static Aif2Fl_SdLinkSetup SdLinkSetup[AIF_MAX_NUM_LINKS]; //SERDES link setup\r
190 static Aif2Fl_RmLinkSetup RmLinkSetup[AIF_MAX_NUM_LINKS]; //RM link setup\r
191 static Aif2Fl_TmLinkSetup TmLinkSetup[AIF_MAX_NUM_LINKS]; //TM link setup\r
192 static Aif2Fl_PdLinkSetup PdLinkSetup[AIF_MAX_NUM_LINKS]; //PD link setup\r
193 static Aif2Fl_PeLinkSetup PeLinkSetup[AIF_MAX_NUM_LINKS]; //PE link setup\r
194 static Aif2Fl_RtLinkSetup RtLinkSetup[AIF_MAX_NUM_LINKS]; //RT link setup\r
195 static Aif2Fl_AtLinkSetup AtLinkSetup[AIF_MAX_NUM_LINKS]; // Aif2 timer link setup (Pi, Delta, PE signal)\r
196 \r
197 static Aif2Fl_Obj Aif2Obj;\r
198 static Aif2Fl_Context Aif2Context;\r
199 \r
200 static uint16_t superPacket;\r
201 \r
202 #ifndef _TMS320C6X\r
203 extern AIF_InitCfg *pGlobalAif2Cfg;\r
204 #endif\r
205 \r
206 #ifdef K2\r
207 #define QMSS_AIF_QUEUE_BASE 512\r
208 #endif\r
209 \r
210 //Initialize AIF2 DIO buffers\r
211 void \r
212 AIF_initDio(\r
213 AIF_ConfigHandle hAif\r
214 )\r
215 {\r
216 uint32_t i,j, start_channel_pe, start_channel_pd, num_channel_pe, num_channel_pd;\r
217 int DIO_nb_link[3]={0,0,0};\r
218 int DIO_first_link[3]={-1,-1,-1};\r
219 \r
220 // Compute first link and num link per DIO engine\r
221 for(i=0; i< AIF_MAX_NUM_LINKS; i++)\r
222 {\r
223 if(1==hAif->linkConfig[i].linkEnable)\r
224 {\r
225 DIO_nb_link[hAif->linkConfig[i].dioEngine]+=1;\r
226 if (DIO_first_link[hAif->linkConfig[i].dioEngine] == (-1))\r
227 {\r
228 DIO_first_link[hAif->linkConfig[i].dioEngine] = i;\r
229 hAif->dioConfig[hAif->linkConfig[i].dioEngine].mode = hAif->linkConfig[i].mode;\r
230 }\r
231 }\r
232 }\r
233 \r
234 for(i=0; i<AIF2_MAX_NUM_DIO_ENGINE; i++)\r
235 {\r
236 hAif->dioConfig[i].numLink = DIO_nb_link[i];\r
237 hAif->dioConfig[i].firstLink = DIO_first_link[i];\r
238 }\r
239 \r
240 // Compute first DB channel offset and last DB channel offset for each DIO engine\r
241 start_channel_pe = 0;\r
242 start_channel_pd = 0;\r
243 for(i=0; i<AIF2_MAX_NUM_DIO_ENGINE; i++)\r
244 {\r
245 num_channel_pe = 0;\r
246 num_channel_pd = 0;\r
247 for(j=hAif->dioConfig[i].firstLink;j<(hAif->dioConfig[i].firstLink + hAif->dioConfig[i].numLink);j++)\r
248 {\r
249 if(1==hAif->linkConfig[j].linkEnable)\r
250 {\r
251 num_channel_pe+=hAif->linkConfig[j].numPeAxC;\r
252 num_channel_pd+=hAif->linkConfig[j].numPdAxC;\r
253 }\r
254 \r
255 }\r
256 hAif->dioConfig[i].offsetPeDBCH = start_channel_pe;\r
257 start_channel_pe += num_channel_pe;\r
258 hAif->dioConfig[i].numPeDBCH = num_channel_pe;\r
259 \r
260 hAif->dioConfig[i].offsetPdDBCH = start_channel_pd;\r
261 start_channel_pd += num_channel_pd;\r
262 hAif->dioConfig[i].numPdDBCH = num_channel_pd;\r
263 }\r
264 \r
265 /* Initialize DIO engine counters for each of the links */\r
266 memset((char*)aif2DioIntCount,(char)0x00, sizeof(aif2DioIntCount));\r
267 \r
268 }\r
269 \r
270 int32_t\r
271 AIF_initPktDma(\r
272 AIF_ConfigHandle hAif\r
273 )\r
274 {\r
275 #ifdef _TMS320C6X\r
276 Cppi_CpDmaInitCfg aif2CPDMACfg;\r
277 Cppi_DescCfg descCfg;\r
278 Cppi_MonolithicDesc *ptrMonoDesc;\r
279 Cppi_HostDesc *ptrHostDesc;\r
280 Cppi_DescTag descTag;\r
281 Cppi_RxChInitCfg rxCfg;\r
282 Cppi_TxChInitCfg txCfg;\r
283 Qmss_Queue queueInfo;\r
284 uint32_t axcConfigTx, axcConfigRx;\r
285 \r
286 uint32_t psMsgEnable = 0;\r
287 uint8_t isAllocated;\r
288 uint32_t i,j,k, numAxC, numAllocated;\r
289 uint32_t *dataPtr;\r
290 \r
291 memset(&descTag, 0x00, sizeof(Cppi_DescTag));\r
292 memset(&descCfg, 0x00, sizeof(Cppi_DescCfg));\r
293 \r
294 /* Initialize Pkt dma if necessary */\r
295 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
296 if (hAif->linkConfig[i].psMsgEnable){\r
297 psMsgEnable = 1;\r
298 }\r
299 }\r
300 \r
301 for(i=0; i< AIF_MAX_NUM_LINKS; i++)\r
302 {\r
303 if (hAif->linkConfig[i].linkEnable == 1)\r
304 {\r
305 if (hAif->superPacket == true)\r
306 {\r
307 superPacket = true;\r
308 hAif->linkConfig[i].numPdAxC=1;\r
309 } else {\r
310 superPacket = false;\r
311 }\r
312 }\r
313 }\r
314 \r
315 \r
316 \r
317 /* Initialize the AIF2 CPDMA config structure. */\r
318 memset ((void *)&aif2CPDMACfg, 0, sizeof(Cppi_CpDmaInitCfg));\r
319 \r
320 /* Setup the AIF2 CPDMA Configuration. */\r
321 aif2CPDMACfg.dmaNum = Cppi_CpDma_AIF_CPDMA;\r
322 \r
323 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
324 {\r
325 aif2CPDMACfg.writeFifoDepth = 8;\r
326 }\r
327 \r
328 /* Open the AIF2 CPDMA. Needed even if DIO used, as we need to disable PKTDMA loopback mode */\r
329 hAif->pktDmaConfig.hCppi = Cppi_open (&aif2CPDMACfg);\r
330 \r
331 /* Disable the AIF2-CPDMA Loopback mode in the CPPI */\r
332 Cppi_setCpdmaLoopback (hAif->pktDmaConfig.hCppi, 0);\r
333 \r
334 /* If PktDma mode and/or ctrl messages enabled, open and populate free queues, open tx/rx queues, configure flows */\r
335 if (psMsgEnable == 1)\r
336 {\r
337 /***********************************************************************\r
338 ********************** Transmit Configuration *************************\r
339 ***********************************************************************/\r
340 for(i=0; i< AIF2_CPRI_MAX_CW_SUBSTREAM; i++)\r
341 {\r
342 if (hAif->pktDmaConfig.hRxFlowCtrl[i] != NULL)\r
343 {\r
344 \r
345 /***********************************************************************\r
346 ********************** Transmit Queues Configuration ******************\r
347 ***********************************************************************/\r
348 \r
349 /* Initialize the Transmit descriptors. We want all the transmit descriptors to go\r
350 * back to the Transmit Free Queue after transmission. */\r
351 descCfg.memRegion = hAif->pktDmaConfig.txRegionCtrl[i];\r
352 descCfg.descNum = hAif->pktDmaConfig.txNumDescCtrl[i];\r
353 descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;\r
354 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
355 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
356 descCfg.descType = Cppi_DescType_MONOLITHIC;\r
357 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
358 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
359 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
360 descCfg.returnPushPolicy = Qmss_Location_TAIL;\r
361 descCfg.cfg.mono.dataOffset = 12; // size of header for control words\r
362 \r
363 /* Initialize the descriptors and place all of them into the general purpose queue */\r
364 hAif->pktDmaConfig.txFqCtrl[i] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
365 if (hAif->pktDmaConfig.txFqCtrl[i] < 0)\r
366 {\r
367 Aif2_osalLog("Error: AIF2 Transmit Completion Queue failed to open\n");\r
368 return -1;\r
369 }\r
370 /* Get the Queue Information for the Transmit Free Queue */\r
371 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.txFqCtrl[i]);\r
372 \r
373 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
374 for (j = 0; j < hAif->pktDmaConfig.txNumDescCtrl[i]; j++)\r
375 {\r
376 /* Get a mono descriptor from the free GP queue. */\r
377 ptrMonoDesc = (Cppi_MonolithicDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.txFqCtrl[i]));\r
378 \r
379 Cppi_setPacketLen(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,hAif->pktDmaConfig.txDescSizeCtrl[i]);\r
380 descTag.srcTagLo = 124+i;\r
381 Cppi_setTag(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,&descTag);\r
382 Cppi_setPSFlags(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,0);\r
383 Cppi_setPSLen(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,0);\r
384 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,queueInfo);\r
385 \r
386 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
387 Qmss_queuePushDesc(hAif->pktDmaConfig.txFqCtrl[i], (uint32_t*)ptrMonoDesc);\r
388 }\r
389 \r
390 /* Open the AIF2 transmit queue for this control stream */\r
391 hAif->pktDmaConfig.txQCtrl[i] = Qmss_queueOpen (Qmss_QueueType_AIF_QUEUE , QMSS_AIF_QUEUE_BASE+124+i, &isAllocated);\r
392 if (hAif->pktDmaConfig.txQCtrl[i] < 0)\r
393 {\r
394 Aif2_osalLog("Error: AIF2 Transmit Queue failed to open\n");\r
395 return -1;\r
396 }\r
397 \r
398 /***********************************************************************\r
399 ********************** Receive Queues Configuration *******************\r
400 ***********************************************************************/\r
401 \r
402 /* Initialize the Receive descriptors */\r
403 descCfg.memRegion = hAif->pktDmaConfig.rxRegionCtrl[i];\r
404 descCfg.descNum = hAif->pktDmaConfig.rxNumDescCtrl[i];\r
405 descCfg.destQueueNum = hAif->pktDmaConfig.hRxFlowCtrl[i]->rx_fdq0_sz0_qnum;\r
406 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
407 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
408 descCfg.descType = (Cppi_DescType)hAif->pktDmaConfig.hRxFlowCtrl[i]->rx_desc_type;\r
409 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
410 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
411 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
412 descCfg.returnPushPolicy = Qmss_Location_TAIL;\r
413 descCfg.cfg.mono.dataOffset = hAif->pktDmaConfig.hRxFlowCtrl[i]->rx_sop_offset; // size of header for control words\r
414 \r
415 /* Initialize the descriptors and place all of them into the general purpose queue */\r
416 hAif->pktDmaConfig.rxFqCtrl[i] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
417 if (hAif->pktDmaConfig.rxFqCtrl[i] < 0)\r
418 {\r
419 Aif2_osalLog("Error: AIF2 Receive Completion Queue failed to open\n");\r
420 return -1;\r
421 }\r
422 \r
423 /* Get the Queue Information for the Transmit Free Queue */\r
424 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.rxFqCtrl[i]);\r
425 \r
426 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
427 for (j = 0; j < hAif->pktDmaConfig.rxNumDescCtrl[i]; j++)\r
428 {\r
429 /* Get a mono descriptor from the free GP queue. */\r
430 ptrMonoDesc = (Cppi_MonolithicDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.rxFqCtrl[i]));\r
431 \r
432 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,queueInfo);\r
433 \r
434 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
435 Qmss_queuePushDesc(hAif->pktDmaConfig.rxFqCtrl[i], (uint32_t*)ptrMonoDesc);\r
436 }\r
437 \r
438 /* Open the AIF2 transmit queue for this control stream, queueType does not matter since we specify a valid queue number */\r
439 hAif->pktDmaConfig.rxQCtrl[i] = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE , hAif->pktDmaConfig.hRxFlowCtrl[i]->rx_dest_qnum, &isAllocated);\r
440 if (hAif->pktDmaConfig.rxQCtrl[i] < 0)\r
441 {\r
442 Aif2_osalLog("Error: AIF2 Receive Queue failed to open\n");\r
443 return -1;\r
444 }\r
445 \r
446 /***********************************************************************\r
447 ********************** PktDma channel Configuration *******************\r
448 ***********************************************************************/\r
449 \r
450 /* Open the AIF2 Receive Channel and keep it disabled */\r
451 rxCfg.channelNum = 124+i;\r
452 rxCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE;\r
453 hAif->pktDmaConfig.rxChCtrl[i] = Cppi_rxChannelOpen(hAif->pktDmaConfig.hCppi, &rxCfg, &isAllocated);\r
454 if (hAif->pktDmaConfig.rxChCtrl[i] == NULL)\r
455 {\r
456 Aif2_osalLog("Error: Opening AIF2 Rx channel %d failed\n", rxCfg.channelNum);\r
457 return -1;\r
458 }\r
459 /* Open the AIF2 Transmit Channel and keep it disabled. */\r
460 txCfg.channelNum = 124+i;\r
461 txCfg.priority = 0;\r
462 txCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE;\r
463 txCfg.filterEPIB = 0;\r
464 txCfg.filterPS = 0;\r
465 txCfg.aifMonoMode = 0;\r
466 hAif->pktDmaConfig.txChCtrl[i] = Cppi_txChannelOpen(hAif->pktDmaConfig.hCppi, &txCfg, &isAllocated);\r
467 if (hAif->pktDmaConfig.txChCtrl[i] == NULL)\r
468 {\r
469 Aif2_osalLog("Error: Opening AIF2 Tx channel %d failed\n", txCfg.channelNum);\r
470 return -1;\r
471 }\r
472 \r
473 /***********************************************************************\r
474 ********************** Receive Flow Configuration *********************\r
475 ***********************************************************************/\r
476 hAif->pktDmaConfig.hRxFlowCtrl[i]->flowIdNum = 124+i;\r
477 Cppi_configureRxFlow (hAif->pktDmaConfig.hCppi, hAif->pktDmaConfig.hRxFlowCtrl[i], &isAllocated);\r
478 \r
479 }\r
480 }\r
481 }\r
482 \r
483 if (hAif->pktdmaOrDioEngine == AIF2FL_CPPI)\r
484 {\r
485 if ((hAif->mode == AIF_GENERICPACKET_MODE)){\r
486 \r
487 axcConfigTx =0;\r
488 axcConfigRx =0;\r
489 for(i=0; i< AIF_MAX_NUM_LINKS; i++){\r
490 /***********************************************************************\r
491 ********************** Transmit Configuration *************************\r
492 ***********************************************************************/\r
493 if (hAif->linkConfig[i].linkEnable) // check for first RxFlow existing\r
494 {\r
495 numAxC = hAif->linkConfig[i].numPeAxC;\r
496 for (k=0; k <numAxC ; k++)\r
497 {\r
498 /***********************************************************************\r
499 ********************** Transmit Queues Configuration ******************\r
500 ***********************************************************************/\r
501 \r
502 /* Initialize the Transmit descriptors. We want all the transmit descriptors to go\r
503 * back to the Transmit Free Queue after transmission. */\r
504 descCfg.memRegion = hAif->pktDmaConfig.txRegionAxC[axcConfigTx];\r
505 descCfg.descNum = hAif->pktDmaConfig.txNumDescAxC[axcConfigTx];\r
506 descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;\r
507 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
508 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
509 descCfg.descType = Cppi_DescType_HOST;\r
510 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
511 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
512 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
513 //descCfg.returnPushPolicy = Qmss_Location_TAIL; //FIXME\r
514 \r
515 \r
516 /* Initialize the descriptors and place all of them into the general purpose queue */\r
517 hAif->pktDmaConfig.txFqAxC[axcConfigTx] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
518 if (hAif->pktDmaConfig.txFqAxC[axcConfigTx] < 0)\r
519 {\r
520 Aif2_osalLog("Error: AIF2 Transmit Completion Queue failed to open\n");\r
521 return -1;\r
522 }\r
523 /* Get the Queue Information for the Transmit Free Queue */\r
524 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.txFqAxC[axcConfigTx]);\r
525 \r
526 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
527 for (j = 0; j < hAif->pktDmaConfig.txNumDescAxC[axcConfigTx]; j++)\r
528 {\r
529 dataPtr = hAif->pktDmaConfig.txDataBuff[axcConfigTx] + (j * hAif->pktDmaConfig.txDescSizeAxC[axcConfigTx] / 4);\r
530 /* Get a mono descriptor from the free GP queue. */\r
531 ptrHostDesc = (Cppi_HostDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.txFqAxC[axcConfigTx]));\r
532 Cppi_setData(descCfg.descType, (Cppi_Desc*)ptrHostDesc,(uint8_t*) dataPtr, hAif->pktDmaConfig.txDescSizeAxC[axcConfigTx]);\r
533 Cppi_setDataLen(descCfg.descType,(Cppi_Desc*)ptrHostDesc,0);\r
534 Cppi_setOriginalBufInfo(descCfg.descType, (Cppi_Desc*)ptrHostDesc,(uint8_t*) dataPtr, hAif->pktDmaConfig.txDescSizeAxC[axcConfigTx]);\r
535 Cppi_getNextBD(descCfg.descType,NULL);\r
536 Cppi_setReturnPolicy(descCfg.descType, (Cppi_Desc*)ptrHostDesc,(Cppi_ReturnPolicy)1);\r
537 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrHostDesc,queueInfo);\r
538 \r
539 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
540 Qmss_queuePushDesc(hAif->pktDmaConfig.txFqAxC[axcConfigTx], (uint32_t*)ptrHostDesc);\r
541 }\r
542 \r
543 /* Open the AIF2 transmit queue for this control stream */\r
544 hAif->pktDmaConfig.txQAxC[axcConfigTx] = Qmss_queueOpen (Qmss_QueueType_AIF_QUEUE , QMSS_AIF_QUEUE_BASE+axcConfigTx, &isAllocated);\r
545 if (hAif->pktDmaConfig.txQAxC[axcConfigTx] < 0)\r
546 {\r
547 Aif2_osalLog("Error: AIF2 Transmit Queue failed to open\n");\r
548 return -1;\r
549 }\r
550 \r
551 /* Open the AIF2 Transmit Channel and keep it disabled. */\r
552 memset(&txCfg, 0, sizeof(txCfg));\r
553 txCfg.channelNum = axcConfigTx;\r
554 txCfg.priority = 0;\r
555 txCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE;\r
556 txCfg.filterEPIB = 0;\r
557 txCfg.filterPS = 0;\r
558 txCfg.aifMonoMode = 0;\r
559 hAif->pktDmaConfig.txChAxC[axcConfigTx] = Cppi_txChannelOpen(hAif->pktDmaConfig.hCppi, &txCfg, &isAllocated);\r
560 if (hAif->pktDmaConfig.txChAxC[axcConfigTx] == NULL)\r
561 {\r
562 Aif2_osalLog("Error: Opening AIF2 Tx channel %d failed\n", txCfg.channelNum);\r
563 return -1;\r
564 }\r
565 \r
566 axcConfigTx++;\r
567 }\r
568 \r
569 /***********************************************************************\r
570 ********************** Receive Queues Configuration *******************\r
571 ***********************************************************************/\r
572 numAxC = hAif->linkConfig[i].numPdAxC;\r
573 for (k=0; k <numAxC ; k++)\r
574 {\r
575 /* Initialize the Receive descriptors */\r
576 descCfg.memRegion = hAif->pktDmaConfig.rxRegionAxC[axcConfigRx];\r
577 descCfg.descNum = hAif->pktDmaConfig.rxNumDescAxC[axcConfigRx];\r
578 descCfg.destQueueNum = hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_fdq0_sz0_qnum;\r
579 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
580 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
581 descCfg.descType = (Cppi_DescType)hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_desc_type;\r
582 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
583 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
584 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
585 descCfg.returnPushPolicy = Qmss_Location_TAIL;\r
586 \r
587 /* Initialize the descriptors and place all of them into the general purpose queue */\r
588 hAif->pktDmaConfig.rxFqAxC[axcConfigRx] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
589 if (hAif->pktDmaConfig.rxFqAxC[axcConfigRx] < 0)\r
590 {\r
591 Aif2_osalLog("Error: AIF2 Receive Completion Queue failed to open\n");\r
592 return -1;\r
593 }\r
594 \r
595 /* Get the Queue Information for the Transmit Free Queue */\r
596 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.rxFqAxC[axcConfigRx]);\r
597 \r
598 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
599 for (j = 0; j < hAif->pktDmaConfig.rxNumDescAxC[axcConfigRx]; j++)\r
600 {\r
601 dataPtr = hAif->pktDmaConfig.rxDataBuff[axcConfigRx] + (j * hAif->pktDmaConfig.txDescSizeAxC[axcConfigRx] / 4);\r
602 /* Get a mono descriptor from the free GP queue. */\r
603 ptrHostDesc = (Cppi_HostDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.rxFqAxC[axcConfigRx]));\r
604 Cppi_setDataLen(descCfg.descType,(Cppi_Desc*)ptrHostDesc,0);\r
605 Cppi_setOriginalBufInfo(descCfg.descType, (Cppi_Desc*)ptrHostDesc, (uint8_t*) dataPtr, hAif->pktDmaConfig.txDescSizeAxC[axcConfigRx]);\r
606 Cppi_getNextBD(descCfg.descType,NULL);\r
607 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrHostDesc,queueInfo);\r
608 \r
609 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
610 Qmss_queuePushDesc(hAif->pktDmaConfig.rxFqAxC[axcConfigRx], (uint32_t*)ptrHostDesc);\r
611 }\r
612 \r
613 /* Open the AIF2 transmit queue for this control stream, queueType does not matter since we specify a valid queue number */\r
614 hAif->pktDmaConfig.rxQAxC[axcConfigRx] = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE , hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_dest_qnum, &isAllocated);\r
615 if (hAif->pktDmaConfig.rxQAxC[axcConfigRx] < 0)\r
616 {\r
617 Aif2_osalLog("Error: AIF2 Receive Queue failed to open\n");\r
618 return -1;\r
619 }\r
620 \r
621 /* Open the AIF2 Receive Channel and keep it disabled */\r
622 memset(&rxCfg, 0, sizeof(rxCfg));\r
623 rxCfg.channelNum = axcConfigRx;\r
624 rxCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE;\r
625 hAif->pktDmaConfig.rxChAxC[axcConfigRx] = Cppi_rxChannelOpen(hAif->pktDmaConfig.hCppi, &rxCfg, &isAllocated);\r
626 if (hAif->pktDmaConfig.rxChAxC[axcConfigRx] == NULL)\r
627 {\r
628 Aif2_osalLog("Error: Opening AIF2 Rx channel %d failed\n", rxCfg.channelNum);\r
629 return -1;\r
630 }\r
631 \r
632 /***********************************************************************\r
633 ********************** Receive Flow Configuration *********************\r
634 ***********************************************************************/\r
635 hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->flowIdNum = axcConfigRx;\r
636 Cppi_configureRxFlow (hAif->pktDmaConfig.hCppi, hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx], &isAllocated);\r
637 \r
638 axcConfigRx++;\r
639 }\r
640 \r
641 }\r
642 }\r
643 }\r
644 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)){\r
645 axcConfigTx =0;\r
646 axcConfigRx =0;\r
647 for(i=0; i< AIF_MAX_NUM_LINKS; i++){\r
648 if ((hAif->linkConfig[i].linkEnable)&&(hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx] != NULL)) // check for first RxFlow existing\r
649 {\r
650 numAxC = hAif->linkConfig[i].numPeAxC;\r
651 for (k=0; k <numAxC ; k++)\r
652 {\r
653 /***********************************************************************\r
654 ********************** Transmit Configuration *************************\r
655 ***********************************************************************/\r
656 \r
657 /* Initialize the Transmit descriptors. We want all the transmit descriptors to go\r
658 * back to the Transmit Free Queue after transmission. */\r
659 descCfg.memRegion = hAif->pktDmaConfig.txRegionAxC[axcConfigTx];\r
660 descCfg.descNum = hAif->pktDmaConfig.txNumDescAxC[axcConfigTx];\r
661 descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;\r
662 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
663 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
664 descCfg.descType = Cppi_DescType_MONOLITHIC;\r
665 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
666 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
667 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
668 descCfg.returnPushPolicy = Qmss_Location_TAIL;\r
669 descCfg.cfg.mono.dataOffset = 12; // size of header for control words\r
670 if (descCfg.descNum != 0)\r
671 {\r
672 /* Initialize the descriptors and place all of them into the general purpose queue */\r
673 hAif->pktDmaConfig.txFqAxC[axcConfigTx] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
674 if (hAif->pktDmaConfig.txFqAxC[axcConfigTx] < 0)\r
675 {\r
676 Aif2_osalLog("Error: AIF2 Transmit Completion Queue failed to open\n");\r
677 return -1;\r
678 }\r
679 /* Get the Queue Information for the Transmit Free Queue */\r
680 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.txFqAxC[axcConfigTx]);\r
681 \r
682 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
683 for (j = 0; j < hAif->pktDmaConfig.txNumDescAxC[axcConfigTx]; j++)\r
684 {\r
685 /* Get a mono descriptor from the free GP queue. */\r
686 ptrMonoDesc = (Cppi_MonolithicDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.txFqAxC[axcConfigTx]));\r
687 Cppi_setPacketLen(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,hAif->pktDmaConfig.txDescSizeAxC[axcConfigTx]);\r
688 descTag.srcTagLo = 0;\r
689 Cppi_setTag(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,&descTag);\r
690 Cppi_setPSFlags(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,0);\r
691 Cppi_setPSLen(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,0);\r
692 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,queueInfo);\r
693 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
694 Qmss_queuePushDesc(hAif->pktDmaConfig.txFqAxC[axcConfigTx], (uint32_t*)ptrMonoDesc);\r
695 }\r
696 \r
697 /* Open the AIF2 transmit queue for this AxC stream */\r
698 hAif->pktDmaConfig.txQAxC[axcConfigTx] = Qmss_queueOpen (Qmss_QueueType_AIF_QUEUE , QMSS_AIF_QUEUE_BASE+axcConfigTx, &isAllocated);\r
699 if (hAif->pktDmaConfig.txQAxC[axcConfigTx] < 0)\r
700 {\r
701 Aif2_osalLog("Error: AIF2 Transmit Queue failed to open\n");\r
702 return -1;\r
703 }\r
704 \r
705 /***********************************************************************\r
706 ********************** PktDma channel Configuration *******************\r
707 ***********************************************************************/\r
708 \r
709 /* Open the AIF2 Transmit Channel and keep it disabled. */\r
710 memset(&txCfg, 0, sizeof(txCfg));\r
711 txCfg.channelNum = axcConfigTx;\r
712 txCfg.priority = 0;\r
713 txCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE;\r
714 txCfg.filterEPIB = 0;\r
715 txCfg.filterPS = 0;\r
716 /* It is possible for the FFTC to send output packets directly to the AIF2 without any DSP intervention. In that case, the AIF_MONO_MODE should\r
717 * be turned off and FFTC uses a descriptor size field of 16 bytes as normal mode, because FFTC can not set 64 bytes to DESC_SIZE field before\r
718 * pushing the descriptor into the AIF2 TX queue.\r
719 */\r
720 txCfg.aifMonoMode = 0;\r
721 \r
722 hAif->pktDmaConfig.txChAxC[axcConfigTx] = Cppi_txChannelOpen(hAif->pktDmaConfig.hCppi, &txCfg, &isAllocated);\r
723 if (hAif->pktDmaConfig.txChAxC[axcConfigTx] == NULL)\r
724 {\r
725 Aif2_osalLog("Error: Opening AIF2 Tx channel %d failed\n", txCfg.channelNum);\r
726 return -1;\r
727 }\r
728 }\r
729 axcConfigTx++;\r
730 } ///eof Transmit config\r
731 \r
732 \r
733 /***********************************************************************\r
734 ********************** Receive Queues Configuration *******************\r
735 ***********************************************************************/\r
736 numAxC = hAif->linkConfig[i].numPdAxC;\r
737 for (k=0; k <numAxC ; k++){\r
738 /* Initialize the Receive descriptors */\r
739 /* Initialize the Receive descriptors */\r
740 descCfg.memRegion = hAif->pktDmaConfig.rxRegionAxC[axcConfigRx];\r
741 descCfg.descNum = hAif->pktDmaConfig.rxNumDescAxC[axcConfigRx];\r
742 descCfg.destQueueNum = hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_fdq0_sz0_qnum;\r
743 descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
744 descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
745 descCfg.descType = (Cppi_DescType)hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_desc_type;\r
746 descCfg.returnQueue.qMgr = QMSS_PARAM_NOT_SPECIFIED;\r
747 descCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;\r
748 descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
749 descCfg.returnPushPolicy = Qmss_Location_TAIL;\r
750 descCfg.cfg.mono.dataOffset = hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_sop_offset; // size of header\r
751 \r
752 if (descCfg.descNum != 0)\r
753 {\r
754 /* Initialize the descriptors and place all of them into the general purpose queue */\r
755 hAif->pktDmaConfig.rxFqAxC[axcConfigRx] = Cppi_initDescriptor (&descCfg, &numAllocated);\r
756 if (hAif->pktDmaConfig.rxFqAxC[axcConfigRx] < 0)\r
757 {\r
758 Aif2_osalLog("Error: AIF2 Receive Completion Queue failed to open\n");\r
759 return -1;\r
760 }\r
761 \r
762 /* Get the Queue Information for the Transmit Free Queue */\r
763 queueInfo = Qmss_getQueueNumber(hAif->pktDmaConfig.rxFqAxC[axcConfigRx]);\r
764 \r
765 /* Pop off all descriptors from the Queue and add the missing init parameters. */\r
766 for (j = 0; j < hAif->pktDmaConfig.rxNumDescAxC[axcConfigRx]; j++)\r
767 {\r
768 /* Get a mono descriptor from the free GP queue. */\r
769 ptrMonoDesc = (Cppi_MonolithicDesc *)QMSS_DESC_PTR(Qmss_queuePop(hAif->pktDmaConfig.rxFqAxC[axcConfigRx]));\r
770 Cppi_setReturnQueue(descCfg.descType,(Cppi_Desc*)ptrMonoDesc,queueInfo);\r
771 \r
772 /* Add the packet descriptor to the AIF2 Transmit Free Queue. */\r
773 Qmss_queuePushDesc(hAif->pktDmaConfig.rxFqAxC[axcConfigRx], (uint32_t*)ptrMonoDesc);\r
774 }\r
775 \r
776 //Qmss_QueueType_GENERAL_PURPOSE_QUEUE to be verified\r
777 \r
778 /* Open the AIF2 receive queue for this control stream, queueType does not matter since we specify a valid queue number */\r
779 hAif->pktDmaConfig.rxQAxC[axcConfigRx] = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE , hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->rx_dest_qnum, &isAllocated);\r
780 if (hAif->pktDmaConfig.rxQAxC[axcConfigRx] < 0)\r
781 {\r
782 Aif2_osalLog("Error: AIF2 Receive Queue failed to open\n");\r
783 return -1;\r
784 }\r
785 \r
786 /***********************************************************************\r
787 ********************** PktDma channel Configuration *******************\r
788 ***********************************************************************/\r
789 \r
790 /* Open the AIF2 Receive Channel and keep it disabled */\r
791 memset(&rxCfg, 0, sizeof(rxCfg));\r
792 rxCfg.channelNum = axcConfigRx;\r
793 rxCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE;\r
794 hAif->pktDmaConfig.rxChAxC[axcConfigRx] = Cppi_rxChannelOpen(hAif->pktDmaConfig.hCppi, &rxCfg, &isAllocated);\r
795 if (hAif->pktDmaConfig.rxChAxC[axcConfigRx] == NULL)\r
796 {\r
797 Aif2_osalLog("Error: Opening AIF2 Rx channel %d failed\n", rxCfg.channelNum);\r
798 return -1;\r
799 }\r
800 /***********************************************************************\r
801 ********************** Receive Flow Configuration *********************\r
802 ***********************************************************************/\r
803 hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx]->flowIdNum = axcConfigRx;\r
804 Cppi_configureRxFlow (hAif->pktDmaConfig.hCppi, hAif->pktDmaConfig.hRxFlowAxC[axcConfigRx], &isAllocated);\r
805 }\r
806 \r
807 axcConfigRx++;\r
808 }\r
809 }\r
810 }\r
811 }\r
812 }\r
813 #else\r
814 Aif2_osalLog("Error: AIF2 LLD API supported only on C6X %d \n", (uint32_t)hAif);\r
815 #endif\r
816 return 0;\r
817 }\r
818 \r
819 typedef struct {\r
820 AIF_SampleRate samplingRate;\r
821 AIF_LteCpType cpType;\r
822 uint32_t startAxC;\r
823 uint32_t endAxC;\r
824 uint32_t isPopulated; //0 if not, 1 if yes\r
825 } baseGroupInfo_t;\r
826 \r
827 typedef struct {\r
828 baseGroupInfo_t g;\r
829 uint32_t cellId;\r
830 } egrGroupInfo_t;\r
831 \r
832 #define ingrGroupInfo_t baseGroupInfo_t\r
833 \r
834 #define AIF_NUM_PD_PE_FRAME_TC_GROUPS 6\r
835 egrGroupInfo_t egrGroupInfo[AIF_NUM_PD_PE_FRAME_TC_GROUPS];\r
836 \r
837 static void initEgrGroupInfo(void)\r
838 {\r
839 memset(egrGroupInfo, 0, AIF_NUM_PD_PE_FRAME_TC_GROUPS * sizeof(egrGroupInfo_t));\r
840 }\r
841 \r
842 static void initIngrGroupInfo(ingrGroupInfo_t *ingrGroupInfoTable, uint32_t tableSize)\r
843 {\r
844 memset(ingrGroupInfoTable, 0, tableSize * sizeof(ingrGroupInfo_t));\r
845 }\r
846 \r
847 //returns groupId\r
848 static uint32_t addAxCtoEgrGroupTable(uint32_t AxC, AIF_SampleRate samplingRate, AIF_LteCpType cpType, \r
849 uint32_t cellId, uint32_t *newEntry)\r
850 {\r
851 uint32_t i, found = 0, id;\r
852 egrGroupInfo_t *g;\r
853 \r
854 for(i = 0; i < AIF_NUM_PD_PE_FRAME_TC_GROUPS; i++) {\r
855 g = &egrGroupInfo[i];\r
856 if (g->g.isPopulated) {\r
857 //check if entries match\r
858 if ((samplingRate == g->g.samplingRate) && (cpType == g->g.cpType) && (cellId == g->cellId)) {\r
859 //matched, add AxC\r
860 if (AxC < g->g.startAxC) {\r
861 g->g.startAxC = AxC;\r
862 }\r
863 if (AxC > g->g.endAxC) {\r
864 g->g.endAxC = AxC;\r
865 }\r
866 *newEntry = 0;\r
867 return(i);\r
868 }\r
869 }\r
870 }\r
871 \r
872 //find the first unpopulated group and populate it\r
873 for(i = 0; i < AIF_NUM_PD_PE_FRAME_TC_GROUPS; i++) {\r
874 g = &egrGroupInfo[i];\r
875 if (! g->g.isPopulated) {\r
876 found = 1;\r
877 id = i;\r
878 break;\r
879 }\r
880 }\r
881 if (! found) { //error\r
882 return(AIF_NUM_PD_PE_FRAME_TC_GROUPS); //return invalid groupId\r
883 }\r
884 \r
885 //populate\r
886 g->g.samplingRate = samplingRate;\r
887 g->cellId = cellId;\r
888 g->g.cpType = cpType;\r
889 g->g.startAxC = AxC;\r
890 g->g.isPopulated = 1;\r
891 *newEntry = 1;\r
892 return(id);\r
893 }\r
894 \r
895 //returns groupId\r
896 static uint32_t addAxCtoIngrGroupTable(ingrGroupInfo_t *ingrGroupInfoTable, uint32_t tableSize, uint32_t AxC, \r
897 AIF_SampleRate samplingRate, AIF_LteCpType cpType, uint32_t *newEntry)\r
898 {\r
899 uint32_t i, found = 0, id;\r
900 ingrGroupInfo_t *g;\r
901 \r
902 for(i = 0; i < tableSize; i++) {\r
903 g = &ingrGroupInfoTable[i];\r
904 if (g->isPopulated) {\r
905 //check if entries match\r
906 if ((samplingRate == g->samplingRate) && (cpType == g->cpType)) {\r
907 //matched, add AxC\r
908 if (AxC < g->startAxC) {\r
909 g->startAxC = AxC;\r
910 }\r
911 if (AxC > g->endAxC) {\r
912 g->endAxC = AxC;\r
913 }\r
914 *newEntry = 0;\r
915 return(i);\r
916 }\r
917 }\r
918 }\r
919 \r
920 //find the first unpopulated group and populate it\r
921 for(i = 0; i < tableSize; i++) {\r
922 g = &ingrGroupInfoTable[i];\r
923 if (! g->isPopulated) {\r
924 found = 1;\r
925 id = i;\r
926 break;\r
927 }\r
928 }\r
929 if (! found) { //error\r
930 return(tableSize); //invalid group Id\r
931 }\r
932 //populate\r
933 g->samplingRate = samplingRate;\r
934 g->cpType = cpType;\r
935 g->startAxC = AxC;\r
936 g->isPopulated = 1;\r
937 *newEntry = 1;\r
938 return(id);\r
939 }\r
940 \r
941 static uint32_t getEgrGroupId(uint32_t AxC)\r
942 {\r
943 uint32_t i;\r
944 \r
945 for(i = 0; i < AIF_NUM_PD_PE_FRAME_TC_GROUPS; i++) {\r
946 if ((AxC >= egrGroupInfo[i].g.startAxC) && (AxC <= egrGroupInfo[i].g.endAxC)) {\r
947 return(i);\r
948 }\r
949 }\r
950 return(AIF_NUM_PD_PE_FRAME_TC_GROUPS); //invalid group\r
951 }\r
952 \r
953 uint32_t AIF_getEgressGroupId(uint32_t AxC)\r
954 {\r
955 return(getEgrGroupId(AxC));\r
956 }\r
957 \r
958 /* Setup AIF given user configuration*/\r
959 \r
960 void AIF_initHw(\r
961 AIF_ConfigHandle hAif\r
962 )\r
963 {\r
964 Aif2Fl_Status status;\r
965 \r
966 uint32_t i,j,k,z;\r
967 #ifndef K2\r
968 uint8_t serdes_blockb8_used =0;\r
969 uint8_t serdes_blockb4_used =0;\r
970 #endif\r
971 \r
972 uint32_t offset_channel_pe, offset_channel_pd, max_channel_pe, max_channel_pd, obsai_type=0, first_link, baseAddress, baseIngr=0, baseEgr=0;\r
973 uint32_t EventModulo,DioFrameEventOffset;\r
974 uint32_t dbmxPe[6];\r
975 uint32_t dbmxPd;\r
976 uint32_t numAxCPd;\r
977 uint32_t maxAxC = 0, totalAxC = 0;\r
978 uint32_t FrameMsg1=0, FrameMsg=0, FrameMsg2=0;\r
979 uint32_t tddSubFrameBitMap, offsetTdd, tddSpecSubFrameBitMap;\r
980 uint8_t tddTable[140];\r
981 uint32_t lte1_4 = 0;\r
982 \r
983 uint32_t samplePerFrame = 0;\r
984 uint8_t frameIndexSc = 0;\r
985 uint32_t linkRate;\r
987 AIF_SampleRate sampleRate;\r
988 uint32_t groupId=0, cellId, isNewGroup=0;\r
989 AIF_LteCpType lteCpType;\r
990 ingrGroupInfo_t ingrGroupInfo[AIF_NUM_PD_PE_FRAME_TC_GROUPS];\r
991 \r
992 uint32_t clockCountTc[7];\r
993 \r
994 //////////////////Initialize Aif2 structures to avoid unwanted configuration ////////////////////////////////////////\r
995 memset(&globalSetup, 0, sizeof(globalSetup));\r
996 for(i=0; i< AIF_MAX_NUM_LINKS; i++)\r
997 memset(&linkSetup[i], 0, sizeof(Aif2Fl_LinkSetup));\r
998 memset(&commonSetup, 0, sizeof(commonSetup));\r
999 \r
1000 memset(&SdCommonSetup, 0, sizeof(SdCommonSetup));\r
1001 memset(&PdCommonSetup, 0, sizeof(PdCommonSetup));\r
1002 memset(&PeCommonSetup, 0, sizeof(PeCommonSetup));\r
1003 memset(&IngrDbSetup, 0, sizeof(IngrDbSetup));\r
1004 memset(&EgrDbSetup, 0, sizeof(EgrDbSetup));\r
1005 memset(&AdCommonSetup, 0, sizeof(AdCommonSetup));\r
1006 memset(&AdDioSetup, 0, sizeof(AdDioSetup));\r
1007 memset(&AtCommonSetup, 0, sizeof(AtCommonSetup));\r
1008 memset(&AtEventSetup, 0, sizeof(AtEventSetup));\r
1009 memset(&PhyTimerInit, 0, sizeof(PhyTimerInit));\r
1010 memset(&RadTimerInit, 0, sizeof(RadTimerInit));\r
1011 memset(&UlRadTimerInit, 0, sizeof(UlRadTimerInit));\r
1012 memset(&DlRadTimerInit, 0, sizeof(DlRadTimerInit));\r
1013 memset(&PhyTimerTc, 0, sizeof(PhyTimerTc));\r
1014 memset(&RadTimerTc, 0, sizeof(RadTimerTc));\r
1015 \r
1016 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1017 memset(&ComLinkSetup[i], 0, sizeof(Aif2Fl_CommonLinkSetup));\r
1018 memset(&SdLinkSetup[i], 0, sizeof(Aif2Fl_SdLinkSetup));\r
1019 memset(&RmLinkSetup[i], 0, sizeof(Aif2Fl_RmLinkSetup));\r
1020 memset(&TmLinkSetup[i], 0, sizeof(Aif2Fl_TmLinkSetup));\r
1021 memset(&PdLinkSetup[i], 0, sizeof(Aif2Fl_PdLinkSetup));\r
1022 memset(&PeLinkSetup[i], 0, sizeof(Aif2Fl_PeLinkSetup));\r
1023 memset(&RtLinkSetup[i], 0, sizeof(Aif2Fl_RtLinkSetup));\r
1024 memset(&AtLinkSetup[i], 0, sizeof(Aif2Fl_AtLinkSetup));\r
1025 }\r
1026 \r
1027 //FIXME definition of superpacket variable already in pktdmaInit\r
1028 for(i=0; i< AIF_MAX_NUM_LINKS; i++)\r
1029 {\r
1030 if (hAif->linkConfig[i].linkEnable == 1)\r
1031 {\r
1032 if (hAif->superPacket == true)\r
1033 {\r
1034 superPacket = true;\r
1035 hAif->linkConfig[i].numPdAxC=1;\r
1036 } else {\r
1037 superPacket = false;\r
1038 }\r
1039 }\r
1040 }\r
1041 \r
1042 /* Initialize CSL library, this step is required - Does not do anything at the moment! */\r
1043 status = Aif2Fl_init(&Aif2Context);\r
1044 if (status != AIF2FL_SOK)\r
1045 Aif2_osalLog("bad context initialization \n");\r
1046 \r
1047 #ifndef _TMS320C6X\r
1048 pGlobalAif2Cfg = hAif->hAif2SerDesBaseAddr;\r
1049 #endif\r
1050 \r
1051 hAif->hFl = Aif2Fl_open(&Aif2Obj, 0, &aif2Param, &status);\r
1052 \r
1053 hAif->hAif2Setup = &aif2Setup;\r
1054 \r
1055 /////////////////populating AIF2 major setup structures //////////////////////////////////////////////////////////\r
1056 aif2Setup.globalSetup = &globalSetup;\r
1057 aif2Setup.commonSetup = &commonSetup;\r
1058 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1059 aif2Setup.linkSetup[i] = &linkSetup[i];\r
1060 }\r
1061 \r
1062 // populate global config fields\r
1063 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1064 if(1==hAif->linkConfig[i].linkEnable) {\r
1065 globalSetup.ActiveLink[i] = true;\r
1066 totalAxC = totalAxC+ hAif->linkConfig[i].numPeAxC;\r
1067 }\r
1068 }\r
1069 globalSetup.frameMode = AIF2FL_FRAME_MODE_NORMAL;\r
1070 \r
1071 //populate common config fields\r
1072 #ifdef K2\r
1073 commonSetup.pSdCommonSetup = NULL;\r
1074 #else \r
1075 commonSetup.pSdCommonSetup = &SdCommonSetup;\r
1076 #endif \r
1077 commonSetup.pPdCommonSetup = &PdCommonSetup;\r
1078 commonSetup.pPeCommonSetup = &PeCommonSetup;\r
1079 commonSetup.pIngrDbSetup = &IngrDbSetup;\r
1080 commonSetup.pEgrDbSetup = &EgrDbSetup;\r
1081 commonSetup.pAdCommonSetup = &AdCommonSetup;\r
1082 commonSetup.pAdDioSetup = &AdDioSetup;\r
1083 commonSetup.pAtCommonSetup = &AtCommonSetup;\r
1084 commonSetup.pAtEventSetup = &AtEventSetup;\r
1085 \r
1086 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1087 ////////////Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links)////////////\r
1088 //populate link config fields for link 1\r
1089 linkSetup[i].linkIndex = (Aif2Fl_LinkIndex)i;\r
1090 linkSetup[i].pComLinkSetup = &ComLinkSetup[i];\r
1091 #ifdef K2 \r
1092 linkSetup[i].pSdLinkSetup = NULL;\r
1093 #else\r
1094 linkSetup[i].pSdLinkSetup = &SdLinkSetup[i];\r
1095 #endif \r
1096 linkSetup[i].pRmLinkSetup = &RmLinkSetup[i];\r
1097 linkSetup[i].pTmLinkSetup = &TmLinkSetup[i];\r
1098 linkSetup[i].pPdLinkSetup = &PdLinkSetup[i];\r
1099 linkSetup[i].pPeLinkSetup = &PeLinkSetup[i];\r
1100 linkSetup[i].pRtLinkSetup = &RtLinkSetup[i];\r
1101 linkSetup[i].pAtLinkSetup = &AtLinkSetup[i];\r
1102 }\r
1103 \r
1104 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1105 //Link Common setup\r
1106 ComLinkSetup[i].linkProtocol = hAif->protocol;\r
1107 ComLinkSetup[i].IngrDataWidth = hAif->linkConfig[i].inboundDataWidth;\r
1108 ComLinkSetup[i].EgrDataWidth = hAif->linkConfig[i].outboundDataWidth;\r
1109 if(8==hAif->linkConfig[i].linkRate){\r
1110 ComLinkSetup[i].linkRate = AIF2FL_LINK_RATE_8x;\r
1111 }\r
1112 else if (2==hAif->linkConfig[i].linkRate) {\r
1113 ComLinkSetup[i].linkRate = AIF2FL_LINK_RATE_2x;\r
1114 }\r
1115 else if (5==hAif->linkConfig[i].linkRate) {\r
1116 ComLinkSetup[i].linkRate = AIF2FL_LINK_RATE_5x; //only for CPRI\r
1117 }\r
1118 else {\r
1119 ComLinkSetup[i].linkRate = AIF2FL_LINK_RATE_4x;\r
1120 }\r
1121 }\r
1122 \r
1123 #ifndef K2\r
1124 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1125 // populate SD link fields default for AIF2 2 AIF2 or Loopback modes\r
1126 SdLinkSetup[i].rxAlign = AIF2FL_SD_RX_COMMA_ALIGNMENT_ENABLE;\r
1127 SdLinkSetup[i].rxLos = AIF2FL_SD_RX_LOS_ENABLE;\r
1128 SdLinkSetup[i].rxCdrAlgorithm = (Aif2Fl_SdRxCdrAlg)1; // Newer CSL AIF2FL_SD_RX_CDR_SECOND_ORDER_THRESH_7 (not in PDK yet); Older CSL AIF2FL_SD_RX_CDR_FIRST_ORDER_THRESH_17;\r
1129 SdLinkSetup[i].rxInvertPolarity = AIF2FL_SD_RX_NORMAL_POLARITY;\r
1130 SdLinkSetup[i].rxTermination = AIF2FL_SD_RX_TERM_COMMON_POINT_0_7;\r
1131 SdLinkSetup[i].rxEqualizerConfig = AIF2FL_SD_RX_EQ_ADAPTIVE;\r
1132 SdLinkSetup[i].bRxEqHold = false; //inline with rxEqualizerConfig\r
1133 SdLinkSetup[i].bRxOffsetComp = true; //for equalization not used\r
1134 SdLinkSetup[i].bEnableTxSyncMater = true; //enable link as master lane for Synchro\r
1135 SdLinkSetup[i].txInvertPolarity = AIF2FL_SD_TX_PAIR_NORMAL_POLARITY;\r
1136 SdLinkSetup[i].txOutputSwing = AIF2FL_SD_TX_OUTPUT_SWING_14;\r
1137 SdLinkSetup[i].txPrecursorTapWeight = AIF2FL_SD_TX_PRE_TAP_WEIGHT_2; //- 5%\r
1138 SdLinkSetup[i].txPostcursorTapWeight = AIF2FL_SD_TX_POST_TAP_WEIGHT_24; // +20%\r
1139 SdLinkSetup[i].bTxFirFilterUpdate = true;\r
1140 if (hAif->linkConfig[i].comType == AIF1_2_AIF2) {\r
1141 SdLinkSetup[i].rxLos = AIF2FL_SD_RX_LOS_DISABLE;\r
1142 SdLinkSetup[i].rxCdrAlgorithm = AIF2FL_SD_RX_CDR_FIRST_ORDER_THRESH_1;\r
1143 SdLinkSetup[i].txOutputSwing = AIF2FL_SD_TX_OUTPUT_SWING_15;\r
1144 SdLinkSetup[i].bRxOffsetComp = false;\r
1145 SdLinkSetup[i].txPrecursorTapWeight = AIF2FL_SD_TX_PRE_TAP_WEIGHT_0;\r
1146 SdLinkSetup[i].txPostcursorTapWeight = AIF2FL_SD_TX_POST_TAP_WEIGHT_0;\r
1147 SdLinkSetup[i].bTxFirFilterUpdate = false;//FIR filter update on\r
1148 }\r
1149 }\r
1150 \r
1151 #else\r
1152 /*SdLinkSetup[0].rxAlign = AIF2FL_SD_RX_COMMA_ALIGNMENT_ENABLE;\r
1153 SdLinkSetup[0].rxLos = AIF2FL_SD_RX_LOS_ENABLE;*/\r
1154 #endif\r
1155 \r
1156 for(i=0; i< AIF_MAX_NUM_LINKS; i++) {\r
1157 //TM link setup\r
1158 TmLinkSetup[i].bEnableTmLink = true;\r
1159 TmLinkSetup[i].bEnableRmLos = false;\r
1160 if (8==hAif->linkConfig[i].linkRate && hAif->protocol == AIF2FL_LINK_PROTOCOL_OBSAI)\r
1161 TmLinkSetup[i].SeedValue = 0x2;//this should be non-zero value for scrambler\r
1162 else\r
1163 TmLinkSetup[i].SeedValue = 0x1;//this should be non-zero value for scrambler\r
1164 if (8==hAif->linkConfig[i].linkRate && hAif->protocol == AIF2FL_LINK_PROTOCOL_OBSAI)\r
1165 TmLinkSetup[i].bEnableScrambler = true;//8x rates requires scrambler\r
1166 else\r
1167 TmLinkSetup[i].bEnableScrambler = false;//other rates requires no scrambler\r
1168 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol){\r
1169 TmLinkSetup[i].pCpriTmSetup.L1InbandEn = 0;//disable 9 bits mask\r
1170 TmLinkSetup[i].pCpriTmSetup.RmLinkLosError = (Aif2Fl_LinkIndex)i;//select link as source RM link\r
1171 TmLinkSetup[i].pCpriTmSetup.RmLinkLofError = (Aif2Fl_LinkIndex)i;//select link as source RM link\r
1172 TmLinkSetup[i].pCpriTmSetup.RmLinkLosRx = (Aif2Fl_LinkIndex)i;//select link as source RM link\r
1173 TmLinkSetup[i].pCpriTmSetup.RmLinkLofRx = (Aif2Fl_LinkIndex)i;//select link as source RM link\r
1174 TmLinkSetup[i].pCpriTmSetup.RmLinkRaiRx = (Aif2Fl_LinkIndex)i;//select link as source RM link\r
1175 TmLinkSetup[i].pCpriTmSetup.TxStartup = 0;\r
1176 TmLinkSetup[i].pCpriTmSetup.TxPointerP = 20;\r
1177 TmLinkSetup[i].pCpriTmSetup.TxProtocolVer = 1;\r
1178 }\r
1179 }\r
1180 \r
1181 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1182 // populate Rx MAC link fields\r
1183 RmLinkSetup[i].bEnableRmLink = true; //EnableRxMac\r
1184 RmLinkSetup[i].RmFifoThold = AIF2FL_RM_FIFO_THOLD_4DUAL; // 4 dual words or 8 dual words to add more delay for adjusting jitter\r
1185 RmLinkSetup[i].bEnableLcvControl = true; //line code violation counter\r
1186 RmLinkSetup[i].RmErrorSuppress = AIF2FL_RM_ERROR_ALLOW; // to be verified in aif1\r
1187 RmLinkSetup[i].bEnableSdAutoAlign = false;
1188 if (8==hAif->linkConfig[i].linkRate && hAif->protocol == AIF2FL_LINK_PROTOCOL_OBSAI)\r
1189 RmLinkSetup[i].bEnableScrambler = true;//4x link rate requires no scrambler\r
1190 else\r
1191 RmLinkSetup[i].bEnableScrambler = false;//4x link rate requires no scrambler
1192 RmLinkSetup[i].bEnableLcvUnsync = false;\r
1193 //RmLinkSetup[i].bEnableLcvControl = false;\r
1194 RmLinkSetup[i].bEnableWatchDog = false;\r
1195 RmLinkSetup[i].WatchDogWrap = 0xFF;//set watch dog wrap value\r
1196 RmLinkSetup[i].bEnableClockQuality = false;\r
1197 RmLinkSetup[i].ClockMonitorWrap = 0;\r
1198 if (hAif->linkConfig[i].comType == AIF2_2_AIF2 || hAif->linkConfig[i].comType == AIF2_LOOPBACK) {\r
1199 RmLinkSetup[i].losDetThreshold = AIF2_RM_LOS_DET_THOLD;\r
1200 RmLinkSetup[i].SyncThreshold = AIF2_RM_SYNC_THOLD;\r
1201 RmLinkSetup[i].FrameSyncThreshold = AIF2_RM_SYNC_THOLD;\r
1202 RmLinkSetup[i].UnsyncThreshold = AIF2_RM_UNSYNC_THOLD;\r
1203 RmLinkSetup[i].FrameUnsyncThreshold = AIF2_RM_UNSYNC_THOLD;\r
1204 } else {\r
1205 RmLinkSetup[i].losDetThreshold = AIF1_RM_LOS_DET_THOLD;\r
1206 RmLinkSetup[i].SyncThreshold = AIF1_RM_SYNC_THOLD;\r
1207 RmLinkSetup[i].FrameSyncThreshold = AIF1_RM_SYNC_THOLD;\r
1208 RmLinkSetup[i].UnsyncThreshold = AIF1_RM_UNSYNC_THOLD;\r
1209 RmLinkSetup[i].FrameUnsyncThreshold = AIF1_RM_UNSYNC_THOLD;\r
1210 }\r
1211 }\r
1212 \r
1213 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1214 //RT link setup\r
1215 if (hAif->linkConfig[i].RtEnabled)\r
1216 {\r
1217 RtLinkSetup[i].CiSelect = hAif->linkConfig[i].RtLinkRout;\r
1218 RtLinkSetup[i].bEnableEmptyMsg = true;\r
1219 RtLinkSetup[i].RtConfig = AIF2FL_RT_MODE_RETRANSMIT;// takes PE input only\r
1220 } else {\r
1221 RtLinkSetup[i].CiSelect = (Aif2Fl_LinkIndex)i;\r
1222 RtLinkSetup[i].bEnableEmptyMsg = true;\r
1223 RtLinkSetup[i].RtConfig = AIF2FL_RT_MODE_TRANSMIT;// takes PE input only\r
1224 }\r
1225 }\r
1226 \r
1227 // Compute first DB channel for each link\r
1228 offset_channel_pe = 0; offset_channel_pd = 0; first_link = AIF_MAX_NUM_LINKS + 1;\r
1229 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1230 if (1 == hAif->linkConfig[i].linkEnable) {\r
1231 hAif->linkConfig[i].firstPeDBCH = offset_channel_pe;\r
1232 hAif->linkConfig[i].firstPdDBCH = offset_channel_pd;\r
1233 offset_channel_pe += hAif->linkConfig[i].numPeAxC;\r
1234 offset_channel_pd += hAif->linkConfig[i].numPdAxC;\r
1235 if (first_link == AIF_MAX_NUM_LINKS + 1) first_link = i;\r
1236 }\r
1237 }\r
1238 max_channel_pe = offset_channel_pe;\r
1239 max_channel_pd = offset_channel_pd;\r
1240 \r
1241 \r
1242 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1243 // populate PD link fields\r
1244 if((hAif->linkConfig[i].numPdAxC != 0) || (hAif->linkConfig[i].psMsgEnable == 1))\r
1245 PdLinkSetup[i].bEnablePdLink = true; //EnablePd\r
1246 PdLinkSetup[i].Crc8Poly = AIF2_CRC8_POLY;\r
1247 PdLinkSetup[i].Crc8Seed = AIF2_CRC8_SEED;\r
1248 maxAxC = hAif->linkConfig[i].numPdAxC;\r
1249 if (AIF2FL_LINK_PROTOCOL_CPRI == hAif->protocol) {\r
1250 if ((AIF2FL_DATA_WIDTH_16_BIT==hAif->linkConfig[i].inboundDataWidth)||\r
1251 (AIF2FL_DATA_WIDTH_8_BIT==hAif->linkConfig[i].inboundDataWidth))\r
1252 {\r
1253 if (hAif->linkConfig[i].linkRate == 8)\r
1254 dbmxPd = hAif->linkConfig[i].linkRate*4 - 2;\r
1255 else\r
1256 dbmxPd = hAif->linkConfig[i].linkRate*4 - 1;\r
1257 //numAxCPe = maxAxC;\r
1258 } else {\r
1259 dbmxPd = hAif->linkConfig[i].linkRate*4;\r
1260 }\r
1261 numAxCPd = maxAxC; // default for WCDMA\r
1262 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)){\r
1263 if (superPacket == 0)\r
1264 {\r
1265 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_1P92MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/1920);\r
1266 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_7P68MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/7680);\r
1267 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_15P36MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/15360);\r
1268 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720); // same as LTE15\r
1269 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_30P72MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720);\r
1270 } else {\r
1271 dbmxPd = hAif->linkConfig[i].numPdAxC;\r
1272 }\r
1273 }\r
1274 if (hAif->mode == AIF_LTE_WCDMA_MODE){\r
1275 if (hAif->linkConfig[i].mode == LTE)\r
1276 {\r
1277 if (superPacket == 0)\r
1278 {\r
1279 // dbmxPd = hAif->linkConfig[i].linkRate >> 1;\r
1280 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_1P92MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/1920);\r
1281 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_7P68MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/7680);\r
1282 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_15P36MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/15360);\r
1283 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720); // same as LTE15\r
1284 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_30P72MHZ) dbmxPd = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720);\r
1285 }\r
1286 else\r
1287 dbmxPd = hAif->linkConfig[i].numPdAxC;\r
1288 } else {\r
1289 if ((AIF2FL_DATA_WIDTH_16_BIT==hAif->linkConfig[i].inboundDataWidth)||\r
1290 (AIF2FL_DATA_WIDTH_8_BIT==hAif->linkConfig[i].inboundDataWidth))\r
1291 {\r
1292 if (hAif->linkConfig[i].linkRate == 8)\r
1293 dbmxPd = hAif->linkConfig[i].linkRate*4 - 2;\r
1294 else\r
1295 dbmxPd = hAif->linkConfig[i].linkRate*4 - 1;\r
1296 } else {\r
1297 dbmxPd = hAif->linkConfig[i].linkRate*4;\r
1298 }\r
1299 }\r
1300 }\r
1301 if (hAif->mode == AIF_GENERICPACKET_MODE) numAxCPd = 1;\r
1302 PdLinkSetup[i].CpriEnetStrip = 0;\r
1303 PdLinkSetup[i].CpriCwNullDelimitor = 0xFB;//K 27.7 charactor\r
1304 if (hAif->linkConfig[i].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
1305 {\r
1306 PdLinkSetup[i].PdCpriCrcType[0] = AIF2FL_CRC_8BIT;\r
1307 if (hAif->linkConfig[i].inboundDataWidth == AIF2FL_DATA_WIDTH_7_BIT) PdLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_7BIT_SAMPLE;\r
1308 else PdLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_8BIT_SAMPLE;\r
1309 } else {\r
1310 PdLinkSetup[i].PdCpriCrcType[0] = AIF2FL_CRC_16BIT;\r
1311 if (hAif->mode != AIF_GENERICPACKET_MODE){\r
1312 if (hAif->linkConfig[i].inboundDataWidth == AIF2FL_DATA_WIDTH_15_BIT) PdLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_15BIT_SAMPLE;\r
1313 else PdLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_16BIT_SAMPLE;\r
1314 }\r
1315 }\r
1316 PdLinkSetup[i].bEnableCpriCrc[0] = false;//disable CPRI CRC for control channel 0,\r
1317 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
1318 PdLinkSetup[i].PdPackDmaCh[hAif->linkConfig[i].firstPdDBCH] = hAif->linkConfig[i].firstPdDBCH;\r
1319 PdLinkSetup[i].bEnablePack[hAif->linkConfig[i].firstPdDBCH] = true;// true to enable CPRI control channel 0 packing\r
1320 PdLinkSetup[i].CpriCwPktDelimitor[hAif->linkConfig[i].firstPdDBCH] = AIF2FL_CW_DELIM_4B5B;\r
1321 } else {\r
1322 for (j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
1323 {\r
1324 if (hAif->linkConfig[i].psMsgEnable)\r
1325 {\r
1326 PdLinkSetup[i].bEnableCpriCrc[j] = false;//disable CPRI CRC for control channel 0,\r
1327 PdLinkSetup[i].PdCpriCrcType[j] = AIF2FL_CRC_32BIT;\r
1328 }\r
1329 PdLinkSetup[i].PdPackDmaCh[j] = 124+j;//Set DB channel 124 as a dma ch for control channel 0\r
1330 if (hAif->linkConfig[i].psMsgEnable) PdLinkSetup[i].bEnablePack[j] = true;\r
1331 else PdLinkSetup[i].bEnablePack[j] = false;\r
1332 if (j==0) PdLinkSetup[i].CpriCwPktDelimitor[j] = AIF2FL_CW_DELIM_4B5B;\r
1333 else PdLinkSetup[i].CpriCwPktDelimitor[j] = AIF2FL_CW_DELIM_NULLDELM;\r
1334 }\r
1335 }\r
1336 \r
1337 PdLinkSetup[i].PdCpriDualBitMap.DbmX = dbmxPd - 1;// set X-1 where X calculated in calcParam\r
1338 if (hAif->mode == AIF_GENERICPACKET_MODE) PdLinkSetup[i].PdCpriDualBitMap.DbmXBubble = 0;\r
1339 else PdLinkSetup[i].PdCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample\r
1340 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1341 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Size = 0;//set n-1\r
1342 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Map[0] = 0x0;\r
1343 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Size = 0;\r
1344 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1345 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ)\r
1346 {\r
1347 if (hAif->linkConfig[i].linkRate == 4)\r
1348 {\r
1349 PdLinkSetup[i].PdCpriDualBitMap.DbmX = 1; // forcing format to A0, A1,A0,A1,A0,A1,B,B\r
1350 PdLinkSetup[i].PdCpriDualBitMap.DbmXBubble = 1;// bubbles of 2 AxC samples\r
1351 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1352 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Size = 2;//set n-1\r
1353 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Map[0] = 0x4;\r
1354 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Size = 0;\r
1355 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1356 } else if (hAif->linkConfig[i].linkRate == 8)\r
1357 {\r
1358 PdLinkSetup[i].PdCpriDualBitMap.DbmX = 4; // forcing format to A0, A1,A2,A3,A4,A0, A1,A2,A3,A4,B A0, A1,A2,A3,A4\r
1359 PdLinkSetup[i].PdCpriDualBitMap.DbmXBubble = 0;// bubbles of 1 AxC sample\r
1360 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1361 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Size = 2;//set n-1\r
1362 PdLinkSetup[i].PdCpriDualBitMap.Dbm1Map[0] = 0x2;\r
1363 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Size = 0;\r
1364 PdLinkSetup[i].PdCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1365 }\r
1366 }\r
1367 \r
1368 if (((superPacket == 0) && (hAif->mode == AIF_LTE_FDD_MODE)) || (hAif->mode == AIF_LTE_WCDMA_MODE) || (hAif->mode == AIF_LTE_TDD_MODE))\r
1369 {\r
1370 k=0;
1371 if (hAif->linkConfig[i].multiRate == 0){\r
1372 for (z=0;z<=numAxCPd;z++)\r
1373 {\r
1374 for (j=0; j<dbmxPd; j++)\r
1375 {\r
1376 if ((hAif->linkConfig[i].maskPattern[k]>>j)&1)\r
1377 {\r
1378 PdLinkSetup[i].CpriDmaCh[j+(hAif->linkConfig[i].firstPdAxC)] = ((hAif->linkConfig[i].firstPdDBCH) + z);\r
1379 PdLinkSetup[i].bEnableCpriX[j+(hAif->linkConfig[i].firstPdAxC)] = TRUE; //enable CPRI X channel\r
1380 }
1381 }\r
1382 k++;\r
1383 }\r
1384 } else {\r
1385 for (z=0;z<numAxCPd;z++)\r
1386 {\r
1387 for (j=0; j<dbmxPd; j++)\r
1388 {
1389 if ((hAif->AxCconfig[hAif->linkConfig[i].firstPdDBCH+k].maskPattern>>j)&1)\r
1390 {\r
1391 PdLinkSetup[i].CpriDmaCh[j] = ((hAif->linkConfig[i].firstPdDBCH) + z);\r
1392 PdLinkSetup[i].bEnableCpriX[j] = TRUE; //enable CPRI X channel\r
1393 }
1394 }\r
1395 k++;\r
1396 }\r
1397 }\r
1398 }\r
1399 \r
1400 /*\r
1401 * If the DSP 0 will send data on 8x link to DSP 1 and from DSP 1 retransmitted to DSP 0\r
1402 * On DSP 1 side I want to enable PD channels 0-14 --- > pdCommonSetup_.PdChConfig[i].bChannelEn and map the AxC 0 - 14 to those channels.\r
1403 * On DSP 0 side I want to enable PD channels 0-14 ---> pdCommonSetup_.PdChConfig[i].bChannelEn and map the AxC 15 - 29 to those channels.\r
1404 * For the PD, you need to enable 15 channels (i = [0-14]) with pdCommonSetup_.PdChConfig[i].bChannelEn.\r
1405 * Then map those channels to the correct AxCs:\r
1406 * PdLinkSetup[i].CpriDmaCh[j] = i; with i = [0-14] and (j = [0-14] on DSP_1, j = [15-30] on DSP_0).\r
1407 *\r
1408 */\r
1409 \r
1410 for (j = 0; j < numAxCPd; j++)//cpri id lut setup for X position 0,1,2... numAxC //FIXME\r
1411 {\r
1412 if ((superPacket == 1) || (((hAif->mode != AIF_LTE_FDD_MODE) && (hAif->mode != AIF_LTE_TDD_MODE) && (hAif->mode != AIF_LTE_WCDMA_MODE))))\r
1413 {\r
1414 PdLinkSetup[i].CpriDmaCh[j+(hAif->linkConfig[i].firstPdAxC)] = (hAif->linkConfig[i].firstPdDBCH + j);\r
1415 PdLinkSetup[i].bEnableCpriX[j+(hAif->linkConfig[i].firstPdAxC)] = true; //enable CPRI X channel\r
1416 }\r
1417 if (hAif->mode == AIF_GENERICPACKET_MODE)\r
1418 PdLinkSetup[i].bEnableCpriPkt[j+(hAif->linkConfig[i].firstPdAxC)] = true;//use AxC data mode\r
1419 else\r
1420 PdLinkSetup[i].bEnableCpriPkt[j+(hAif->linkConfig[i].firstPdAxC)] = false;//use AxC data mode\r
1421 if ((hAif->linkConfig[i].linkRate==8) && (hAif->linkConfig[i].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA) && (hAif->linkConfig[i].firstPdDBCH+21<(j+(hAif->linkConfig[i].firstPdAxC)) && (j+(hAif->linkConfig[i].firstPdAxC))<hAif->linkConfig[i].firstPdDBCH+30))\r
1422 PdLinkSetup[i].Cpri8WordOffset[j+(hAif->linkConfig[i].firstPdAxC)] = 1;\r
1423 else\r
1424 PdLinkSetup[i].Cpri8WordOffset[j+(hAif->linkConfig[i].firstPdAxC)] = hAif->linkConfig[i].cpri8WordOffset[j];//more detailed CPRI AxC offset\r
1425 }\r
1426 if ((hAif->mode != AIF_GENERICPACKET_MODE) && ( 8!= hAif->linkConfig[i].linkRate)){\r
1427 for (j = 0; j < 256; j++)//cpri cw lut setup\r
1428 {\r
1429 if (((j >= 20) && (j < 64)) || ((j >= 84) && (j < 128)) || ((j>= 148) &&\\r
1430 (j < 192)) || ((j >= 212) && (j < 256))) {\r
1431 PdLinkSetup[i].CpriCwChannel[j] = 0; //set CW sub channel num to pack 0\r
1432 PdLinkSetup[i].bEnableCpriCw[j] = true; //enable CW sub channel for FastC&M\r
1433 }\r
1434 }\r
1435 }\r
1436 } else { // OBSAI\r
1437 obsai_type = 0;\r
1438 if (hAif->mode == AIF_WCDMA_MODE) {\r
1439 obsai_type = AIF2_OBSAI_TYPE_WCDMA_FDD;\r
1440 }\r
1441 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)) {\r
1442 obsai_type = AIF2_OBSAI_TYPE_LTE;\r
1443 }\r
1444 if (hAif->mode == AIF_GENERICPACKET_MODE)\r
1445 obsai_type = AIF2_OBSAI_TYPE_GENERIC;\r
1446 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
1447 {\r
1448 if (hAif->linkConfig[i].mode == LTE)\r
1449 {\r
1450 obsai_type = AIF2_OBSAI_TYPE_LTE;\r
1451 } else {\r
1452 obsai_type = AIF2_OBSAI_TYPE_WCDMA_FDD;\r
1453 }\r
1454 }\r
1455 \r
1456 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
1457 PdLinkSetup[i].PdTypeLut[obsai_type].ObsaiTsFormat = AIF2FL_TSTAMP_FORMAT_GEN_PKT;\r
1458 PdLinkSetup[i].PdTypeLut[obsai_type].PdCrcType = AIF2FL_CRC_16BIT;\r
1459 PdLinkSetup[i].PdTypeLut[obsai_type].bEnableCrc = false;\r
1460 PdLinkSetup[i].PdTypeLut[obsai_type].PdObsaiMode = AIF2FL_PD_DATA_PKT;\r
1461 \r
1462 } else {\r
1463 PdLinkSetup[i].PdTypeLut[obsai_type].ObsaiTsFormat = AIF2FL_TSTAMP_FORMAT_NORM_TS;\r
1464 if (hAif->linkConfig[i].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
1465 PdLinkSetup[i].PdTypeLut[obsai_type].PdCrcType = AIF2FL_CRC_8BIT;\r
1466 else\r
1467 PdLinkSetup[i].PdTypeLut[obsai_type].PdCrcType = AIF2FL_CRC_16BIT;\r
1468 PdLinkSetup[i].PdTypeLut[obsai_type].bEnableCrc = false;\r
1469 PdLinkSetup[i].PdTypeLut[obsai_type].PdObsaiMode = AIF2FL_PD_DATA_AXC;\r
1470 }\r
1471 PdLinkSetup[i].PdTypeLut[obsai_type].bEnableEnetStrip = false;\r
1472 PdLinkSetup[i].PdTypeLut[obsai_type].bEnableCrcHeader = false;//OBSAI crc calculation for header\r
1473 }\r
1474 }\r
1475 \r
1476 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1477 if (hAif->linkConfig[i].RtEnabled==0)\r
1478 {\r
1479 // populate PE link fields\r
1480 if((hAif->linkConfig[i].numPeAxC != 0) || (hAif->linkConfig[i].psMsgEnable == 1))\r
1481 PeLinkSetup[i].bEnablePeLink = true; //bEnablePe = true;\r
1482 PeLinkSetup[i].PeCppiDioSel = hAif->pktdmaOrDioEngine;\r
1483 if (hAif->mode == AIF_LTE_TDD_MODE)\r
1484 PeLinkSetup[i].TddAxc = true;\r
1485 else\r
1486 PeLinkSetup[i].TddAxc = false;\r
1487 PeLinkSetup[i].Crc8Poly = AIF2_CRC8_POLY;\r
1488 PeLinkSetup[i].Crc8Seed = AIF2_CRC8_SEED;\r
1489 if (AIF2FL_LINK_PROTOCOL_CPRI == hAif->protocol) {\r
1490 maxAxC = hAif->linkConfig[i].numPeAxC;\r
1491 if ((AIF2FL_DATA_WIDTH_16_BIT==hAif->linkConfig[i].outboundDataWidth)||\r
1492 (AIF2FL_DATA_WIDTH_8_BIT==hAif->linkConfig[i].outboundDataWidth))\r
1493 {\r
1494 if (hAif->linkConfig[i].linkRate == 8)\r
1495 dbmxPe[i] = hAif->linkConfig[i].linkRate*4 - 2;\r
1496 else\r
1497 dbmxPe[i] = hAif->linkConfig[i].linkRate*4 - 1;\r
1498 } else {\r
1499 dbmxPe[i] = hAif->linkConfig[i].linkRate*4;\r
1500 }\r
1501 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)){ \r
1502 //dbmxPe = 2;\r
1503 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_1P92MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/1920);\r
1504 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_7P68MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/7680);\r
1505 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_15P36MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/15360);\r
1506 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720); // same as LTE20\r
1507 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_30P72MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720);\r
1508 }\r
1509 \r
1510 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
1511 {\r
1512 if (hAif->linkConfig[i].mode == LTE)\r
1513 {\r
1514 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_1P92MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/1920);\r
1515 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_7P68MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/7680);\r
1516 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_15P36MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/15360);\r
1517 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720); // same as LTE20\r
1518 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_30P72MHZ) dbmxPe[i] = _bitc32(hAif->linkConfig[i].maskPattern[0]) * (hAif->linkConfig[i].linkRate*4*256*15/30720);\r
1519 } else {\r
1520 if ((AIF2FL_DATA_WIDTH_16_BIT==hAif->linkConfig[i].outboundDataWidth)||\r
1521 (AIF2FL_DATA_WIDTH_8_BIT==hAif->linkConfig[i].outboundDataWidth))\r
1522 {\r
1523 if (hAif->linkConfig[i].linkRate == 8)\r
1524 dbmxPe[i] = hAif->linkConfig[i].linkRate*4 - 2;\r
1525 else\r
1526 dbmxPe[i] = hAif->linkConfig[i].linkRate*4 - 1;\r
1527 } else {\r
1528 dbmxPe[i] = hAif->linkConfig[i].linkRate*4;\r
1529 }\r
1530 }\r
1531 }\r
1532 PeLinkSetup[i].PeDelay = AIF2_DB_PE_DELAY_CPRI;\r
1533 PeLinkSetup[i].PeCpriDualBitMap.DbmX = dbmxPe[i] - 1;//15 for 4x link speed with 8bit data. set X-1\r
1534 if (hAif->mode == AIF_GENERICPACKET_MODE) PeLinkSetup[i].PeCpriDualBitMap.DbmXBubble = 0;\r
1535 else PeLinkSetup[i].PeCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample\r
1536 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1537 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Size = 0;//set n-1\r
1538 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Map[0] = 0x0;\r
1539 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Size = 0;\r
1540 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1541 \r
1542 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) {\r
1543 if (hAif->linkConfig[i].linkRate == 4)\r
1544 {\r
1545 PeLinkSetup[i].PeCpriDualBitMap.DbmX = 1; // forcing format\r
1546 PeLinkSetup[i].PeCpriDualBitMap.DbmXBubble = 1;//bubbles of 2 AxC samples\r
1547 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1548 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Size = 2;//set n-1\r
1549 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Map[0] = 0x4;\r
1550 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Size = 0;\r
1551 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1552 } else if (hAif->linkConfig[i].linkRate == 8)\r
1553 {\r
1554 PeLinkSetup[i].PeCpriDualBitMap.DbmX = 4; // forcing format\r
1555 PeLinkSetup[i].PeCpriDualBitMap.DbmXBubble = 0;//bubbles of 1 AxC sample\r
1556 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Mult = 0;//set n-1\r
1557 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Size = 2;//set n-1\r
1558 PeLinkSetup[i].PeCpriDualBitMap.Dbm1Map[0] = 0x2;\r
1559 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Size = 0;\r
1560 PeLinkSetup[i].PeCpriDualBitMap.Dbm2Map[0] = 0x0;\r
1561 }\r
1562 }\r
1563 if (hAif->linkConfig[i].outboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
1564 {\r
1565 if (hAif->linkConfig[i].outboundDataWidth == AIF2FL_DATA_WIDTH_7_BIT) PeLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_7BIT_SAMPLE;\r
1566 else PeLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_8BIT_SAMPLE;\r
1567 } else {\r
1568 if (hAif->linkConfig[i].outboundDataWidth == AIF2FL_DATA_WIDTH_15_BIT) PeLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_15BIT_SAMPLE;\r
1569 else PeLinkSetup[i].CpriAxCPack = AIF2FL_CPRI_16BIT_SAMPLE;\r
1570 }\r
1571 PeLinkSetup[i].CpriCwNullDelimitor = 0xFB;//K 27.7 charactor\r
1572 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
1573 PeLinkSetup[i].bEnablePack[hAif->linkConfig[i].firstPeDBCH] = true;//trial at false\r
1574 PeLinkSetup[i].PePackDmaCh[hAif->linkConfig[i].firstPeDBCH] = hAif->linkConfig[i].firstPeDBCH;\r
1575 PeLinkSetup[i].CpriCwPktDelimitor[hAif->linkConfig[i].firstPeDBCH] = AIF2FL_CW_DELIM_4B5B;\r
1576 } else {\r
1577 for (j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
1578 {\r
1579 if (hAif->linkConfig[i].psMsgEnable) PeLinkSetup[i].bEnablePack[j] = true;\r
1580 else PeLinkSetup[i].bEnablePack[j] = false;\r
1581 if (j == 0) PeLinkSetup[i].CpriCwPktDelimitor[j] = AIF2FL_CW_DELIM_4B5B;\r
1582 else PeLinkSetup[i].CpriCwPktDelimitor[j] = AIF2FL_CW_DELIM_NULLDELM;\r
1583 PeLinkSetup[i].PePackDmaCh[j] = 124+j;\r
1584 }\r
1585 if ((hAif->mode != AIF_GENERICPACKET_MODE) && ( 8!= hAif->linkConfig[i].linkRate)){\r
1586 for (j = 0; j < 256; j++)//cpri cw lut setup\r
1587 {\r
1588 if (((j >= 20) && (j < 64)) || ((j >= 84) && (j < 128)) || ((j>= 148) &&\\r
1589 (j < 192)) || ((j >= 212) && (j < 256))) {\r
1590 PeLinkSetup[i].CpriCwChannel[j] = 0; //set CW sub channel num to pack 0\r
1591 PeLinkSetup[i].bEnableCpriCw[j] = true; //enable CW sub channel for FastC&M\r
1592 }\r
1593 }\r
1594 }\r
1595 }\r
1596 } else {\r
1597 PeLinkSetup[i].bEnObsaiBubbleBW = false;\r
1598 PeLinkSetup[i].PeDelay = AIF2_DB_PE_DELAY_OBSAI;//28 sys_clks delay between DB and PE\r
1599 }\r
1600 }\r
1601 }\r
1602 \r
1603 \r
1604 // Based on computations from AIF_calcParam\r
1605 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1606 AtLinkSetup[i].PE1Offset = hAif->linkConfig[i].pe2Offset - 10;\r
1607 AtLinkSetup[i].PE2Offset = hAif->linkConfig[i].pe2Offset;\r
1608 AtLinkSetup[i].DeltaOffset = hAif->linkConfig[i].deltaOffset;\r
1609 AtLinkSetup[i].PiMin = hAif->linkConfig[i].piMin;\r
1610 AtLinkSetup[i].PiMax = hAif->linkConfig[i].piMin + 100;\r
1611 AtLinkSetup[i].IsNegativeDelta = false;//positive delta\r
1612 }\r
1613 #ifndef K2\r
1614 // Identify which SerDes block to use\r
1615 for(i=AIF2FL_LINK_0; i<AIF2FL_LINK_4; i++)\r
1616 {\r
1617 // moved to link setup\r
1618 if(1==hAif->linkConfig[i].linkEnable) serdes_blockb8_used=1;\r
1619 }\r
1620 \r
1621 for(i=AIF2FL_LINK_4; i<(AIF2FL_LINK_5 + 1); i++)\r
1622 {\r
1623 // moved to link setup\r
1624 if(1==hAif->linkConfig[i].linkEnable) serdes_blockb4_used=1;\r
1625 }\r
1626 \r
1627 //SD common setup\r
1628 if ( serdes_blockb8_used ==1){\r
1629 SdCommonSetup.bEnablePllB8 = true;\r
1630 SdCommonSetup.CLKBYP_B8 = AIF2FL_PLL_CLOCK_NO_BYPASS;\r
1631 SdCommonSetup.LB_B8 = AIF2FL_PLL_LOOP_BAND_MID;//High BW is also fine\r
1632 SdCommonSetup.VoltRangeB8 = AIF2FL_PLL_VOLTAGE_LOW;//fixed factor\r
1633 SdCommonSetup.SleepPllB8 = AIF2FL_PLL_AWAKE;\r
1634 if(AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
1635 //20x for obsai with 153.6Mhz sys_clock, 25Xfor OBSAI when reference clock is 122.88 Mhz\r
1636 if (153600==hAif->aif2ClkSpeedKhz)\r
1637 SdCommonSetup.pllMpyFactorB8 = AIF2FL_PLL_MUL_FACTOR_20X;\r
1638 else // 128.88Mhz\r
1639 SdCommonSetup.pllMpyFactorB8 = AIF2FL_PLL_MUL_FACTOR_25X;\r
1640 } else {\r
1641 //16x for cpri with 153.6Mhz sys_clock, 20X for CPRI when reference clock is 122.88 Mhz\r
1642 if (153600==hAif->aif2ClkSpeedKhz)\r
1643 SdCommonSetup.pllMpyFactorB8 = AIF2FL_PLL_MUL_FACTOR_16X;\r
1644 else // 128.88Mhz\r
1645 SdCommonSetup.pllMpyFactorB8 = AIF2FL_PLL_MUL_FACTOR_20X;\r
1646 }\r
1647 SdCommonSetup.SysClockSelect = AIF2FL_SD_BYTECLOCK_FROM_B8;\r
1648 }\r
1649 if ( serdes_blockb4_used ==1){\r
1650 SdCommonSetup.bEnablePllB4 = true;\r
1651 SdCommonSetup.CLKBYP_B4 = AIF2FL_PLL_CLOCK_NO_BYPASS;\r
1652 SdCommonSetup.LB_B4 = AIF2FL_PLL_LOOP_BAND_MID;//High BW is also fine\r
1653 SdCommonSetup.VoltRangeB4 = AIF2FL_PLL_VOLTAGE_LOW;//fixed factor\r
1654 SdCommonSetup.SleepPllB4 = AIF2FL_PLL_AWAKE;\r
1655 if(AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
1656 //20x for obsai with 153.6Mhz sys_clock, 25Xfor OBSAI when reference clock is 122.88 Mhz\r
1657 if (153600==hAif->aif2ClkSpeedKhz)\r
1658 SdCommonSetup.pllMpyFactorB4 = AIF2FL_PLL_MUL_FACTOR_20X;\r
1659 else // 128.88Mhz\r
1660 SdCommonSetup.pllMpyFactorB4 = AIF2FL_PLL_MUL_FACTOR_25X;\r
1661 } else {\r
1662 //16x for cpri with 153.6Mhz sys_clock, 20X for CPRI when reference clock is 122.88 Mhz\r
1663 if (153600==hAif->aif2ClkSpeedKhz)\r
1664 SdCommonSetup.pllMpyFactorB4 = AIF2FL_PLL_MUL_FACTOR_16X;\r
1665 else // 128.88Mhz\r
1666 SdCommonSetup.pllMpyFactorB4 = AIF2FL_PLL_MUL_FACTOR_20X;\r
1667 }\r
1668 if ( serdes_blockb8_used ==0)\r
1669 SdCommonSetup.SysClockSelect = AIF2FL_SD_BYTECLOCK_FROM_B4;\r
1670 }\r
1671 \r
1672 for(i=0, j=0; i< AIF_MAX_NUM_LINKS; i++)\r
1673 {\r
1674 if(1==hAif->linkConfig[i].linkEnable)\r
1675 SdCommonSetup.DisableLinkClock[i] = false;//enable link clock\r
1676 else\r
1677 SdCommonSetup.DisableLinkClock[i] = true; //disable link clock\r
1678 }\r
1679 #else\r
1680 /*SERDES CSL now out of AIF2 - dedicated functions in AIF2 LLD were created to handle K-II SerDes settings*/\r
1681 #endif\r
1682 \r
1683 //PD common setup\r
1684 PdCommonSetup.PdCppiDioSel = hAif->pktdmaOrDioEngine;\r
1685 if(AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol) {\r
1686 PdCommonSetup.AxCOffsetWin = AIF2_CPRI_AXC_OFFSET_WIN;\r
1687 // Radio frame size for CPRI\r
1688 PdCommonSetup.PdRadtTC = AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;\r
1689 } else {\r
1690 PdCommonSetup.AxCOffsetWin = AIF2_OBSAI_AXC_OFFSET_WIN;\r
1691 // Radio frame size for OBSAI\r
1692 PdCommonSetup.PdRadtTC = AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;\r
1693 }\r
1694 if (hAif->mode == AIF_WCDMA_MODE) {\r
1695 PdCommonSetup.PdFrameTC[0].FrameIndexSc = 0;//start index\r
1696 PdCommonSetup.PdFrameTC[0].FrameIndexTc = 0;//terminal index\r
1697 PdCommonSetup.PdFrameTC[0].FrameSymbolTc = 15-1;//15 slots for WCDMA\r
1698 PdCommonSetup.PdFrameMsgTc[0] = 639;\r
1699 PdCommonSetup.PdFrameTC[1].FrameIndexSc = 1;//start index\r
1700 PdCommonSetup.PdFrameTC[1].FrameIndexTc = 1;//terminal index\r
1701 PdCommonSetup.PdFrameTC[1].FrameSymbolTc = 15-1;//15 slots for WCDMA\r
1702 PdCommonSetup.PdFrameMsgTc[1] = 639;\r
1703 }\r
1704 \r
1705 if (hAif->mode == AIF_GENERICPACKET_MODE) {\r
1706 // TO BE FIXED\r
1707 }\r
1708 \r
1709 z = first_link; //track to which link this channel corresponds\r
1710 frameIndexSc = 0;\r
1711 initIngrGroupInfo(&ingrGroupInfo[0], AIF_NUM_PD_PE_FRAME_TC_GROUPS);\r
1712 for(i=0;i<max_channel_pd;i++)//for channel 0,...to max channels used by all links\r
1713 {\r
1714 if (i >= (hAif->linkConfig[z].firstPdDBCH + hAif->linkConfig[z].numPdAxC))\r
1715 {\r
1716 do{\r
1717 z++;\r
1718 }while((0 == hAif->linkConfig[z].linkEnable));\r
1719 }\r
1720 \r
1721 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
1722 if (hAif->linkConfig[z].multiRate == 0)\r
1723 sampleRate = hAif->linkConfig[z].sampleRate;\r
1724 else\r
1725 sampleRate = hAif->AxCconfig[i].sampleRate;\r
1726 linkRate = hAif->linkConfig[z].linkRate;\r
1727 lteCpType = hAif->AxCconfig[i].lteCpType;\r
1728 if ((groupId = addAxCtoIngrGroupTable(&ingrGroupInfo[0], AIF_NUM_PD_PE_FRAME_TC_GROUPS, i, sampleRate, lteCpType, &isNewGroup))\r
1729 == AIF_NUM_PD_PE_FRAME_TC_GROUPS) {\r
1730 Aif2_osalLog("Fatal Error: addAxCtoIngrGroupTable returned bad ID\n");\r
1731 }\r
1732 \r
1733 if (isNewGroup) {\r
1734 if (hAif->mode == AIF_LTE_WCDMA_MODE) {\r
1735 PdCommonSetup.PdFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
1736 PdCommonSetup.PdFrameTC[groupId].FrameIndexTc = frameIndexSc;//terminal index\r
1737 if (sampleRate == AIF_SRATE_3P84MHZ)\r
1738 PdCommonSetup.PdFrameTC[groupId].FrameSymbolTc = 15-1;//140 symbols for LTE\r
1739 else\r
1740 PdCommonSetup.PdFrameTC[groupId].FrameSymbolTc = 120-1;//140 symbols for LTE\r
1741 frameIndexSc += 1;\r
1742 } else if (sampleRate != AIF_SRATE_1P92MHZ) {\r
1743 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
1744 PdCommonSetup.PdFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
1745 PdCommonSetup.PdFrameTC[groupId].FrameIndexTc = frameIndexSc + (AIF2_LTE_SYMBOL_NUM-1);//terminal index\r
1746 PdCommonSetup.PdFrameTC[groupId].FrameSymbolTc = AIF2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE\r
1747 frameIndexSc += AIF2_LTE_SYMBOL_NUM;\r
1748 }\r
1749 else { // Extended CP\r
1750 PdCommonSetup.PdFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
1751 PdCommonSetup.PdFrameTC[groupId].FrameIndexTc = frameIndexSc + (AIF2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index\r
1752 PdCommonSetup.PdFrameTC[groupId].FrameSymbolTc = AIF2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE\r
1753 frameIndexSc += AIF2_LTE_SYMBOL_NUM_EXT_CP;\r
1754 }\r
1755 } else { //AIF_SRATE_1P92MHZ\r
1756 PdCommonSetup.PdFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
1757 PdCommonSetup.PdFrameTC[groupId].FrameIndexTc = frameIndexSc;//terminal index\r
1758 PdCommonSetup.PdFrameTC[groupId].FrameSymbolTc = 20-1;//20 slots for LTE\r
1759 frameIndexSc += 1;\r
1760 }\r
1761 if (sampleRate == AIF_SRATE_1P92MHZ) {\r
1762 FrameMsg1 = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPRENORMAL1_SIZE;\r
1763 FrameMsg = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPRENORMAL_SIZE;\r
1764 FrameMsg2 = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPREEXTENDED_SIZE;\r
1765 totalAxC = linkRate*4*256*15/7680;\r
1766 lte1_4 = 1;\r
1767 }\r
1768 if (sampleRate == AIF_SRATE_3P84MHZ) {\r
1769 FrameMsg1 = 0;\r
1770 FrameMsg = 0;\r
1771 FrameMsg2 = 2560;\r
1772 totalAxC = 0;\r
1773 }\r
1774 if (sampleRate == AIF_SRATE_7P68MHZ) {\r
1775 FrameMsg1 = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPRENORMAL1_SIZE;\r
1776 FrameMsg = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPRENORMAL_SIZE;\r
1777 FrameMsg2 = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPREEXTENDED_SIZE;\r
1778 totalAxC = linkRate*4*256*15/7680;\r
1779 }\r
1780 if (sampleRate == AIF_SRATE_15P36MHZ) {\r
1781 FrameMsg1 = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPRENORMAL1_SIZE;\r
1782 FrameMsg = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPRENORMAL_SIZE;\r
1783 FrameMsg2 = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPREEXTENDED_SIZE;\r
1784 totalAxC = linkRate*4*256*15/15360;\r
1785 }\r
1786 if (sampleRate == AIF_SRATE_23P04MHZ) {\r
1787 FrameMsg1 = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPRENORMAL1_SIZE;\r
1788 FrameMsg = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPRENORMAL_SIZE;\r
1789 FrameMsg2 = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPREEXTENDED_SIZE;\r
1790 totalAxC = linkRate*4*256*15/30720; // same as LTE20\r
1791 }\r
1792 if (sampleRate == AIF_SRATE_30P72MHZ) {\r
1793 FrameMsg1 = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPRENORMAL1_SIZE;\r
1794 FrameMsg = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPRENORMAL_SIZE;\r
1795 FrameMsg2 = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPREEXTENDED_SIZE;\r
1796 totalAxC = linkRate*4*256*15/30720;\r
1797 }\r
1798 \r
1799 if (superPacket == 0){\r
1800 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
1801 {\r
1802 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc] = (FrameMsg2/ AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1803 } else if (lte1_4 == 1) {\r
1804 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
1805 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc] = ((FrameMsg1+6*FrameMsg)/ AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1806 }\r
1807 else {\r
1808 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc] = ((6*FrameMsg2)/ AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1809 }\r
1810 } else {\r
1811 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
1812 //frame message terminal count for first normal cyclic prefix symbol\r
1813 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc] = (FrameMsg1/ AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1814 //frame message terminal count for other 6 normal cyclic prefix LTE symbols\r
1815 for(j=1;j<(AIF2_LTE_SYMBOL_NUM);j++){\r
1816 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc + j] = (FrameMsg /AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1817 }\r
1818 }\r
1819 else { //extended\r
1820 //frame message terminal count for all 6 extended cyclic prefix LTE symbols\r
1821 for(j=0 ;j<(AIF2_LTE_SYMBOL_NUM_EXT_CP);j++){\r
1822 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc+ j] = (FrameMsg2 /AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1823 }\r
1824 }\r
1825 }\r
1826 }else{\r
1827 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
1828 //frame message terminal count for first normal cyclic prefix symbol\r
1829 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc] = (totalAxC)*(FrameMsg1 / AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1830 //frame message terminal count for other 6 normal cyclic prefix LTE symbols\r
1831 for(j=1;j<(AIF2_LTE_SYMBOL_NUM);j++){\r
1832 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc + j] = (totalAxC)*(FrameMsg /AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1833 }\r
1834 }\r
1835 else {\r
1836 //frame message terminal count for all 6 extended cyclic prefix LTE symbols\r
1837 for(j=0;j<(AIF2_LTE_SYMBOL_NUM_EXT_CP);j++){\r
1838 PdCommonSetup.PdFrameMsgTc[PdCommonSetup.PdFrameTC[groupId].FrameIndexSc + j] = (totalAxC)*(FrameMsg2 /AIF2_NUM_WORDS_PER_QWORD) - 1;\r
1839 }\r
1840 }\r
1841 }\r
1842 }\r
1843 }\r
1844 \r
1845 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
1846 \r
1847 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
1848 {\r
1849 if (hAif->linkConfig[z].mode == LTE)\r
1850 {\r
1851 obsai_type = AIF2_OBSAI_TYPE_LTE;\r
1852 } else {\r
1853 obsai_type = AIF2_OBSAI_TYPE_WCDMA_FDD;\r
1854 }\r
1855 }\r
1856 \r
1857 PdCommonSetup.PdRoute[i].RouteTs = 0;//Route OBSAI time stamp\r
1858 PdCommonSetup.PdRoute[i].RouteType = obsai_type;//Route OBSAI type\r
1859 PdCommonSetup.PdRoute[i].RouteAddr = i;//Route OBSAI address\r
1860 \r
1861 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
1862 PdCommonSetup.PdRoute[i].RouteLink = (Aif2Fl_LinkIndex) (AIF2FL_LINK_0 + z);//Route link\r
1863 PdCommonSetup.PdRoute[i].RouteMask = AIF2FL_ROUTE_MASK_4LSB;\r
1864 //PdCommonSetup.PdRoute[i].RouteTs = 0x10;\r
1865 } else {\r
1866 PdCommonSetup.PdRoute[i].RouteMask = AIF2FL_ROUTE_MASK_NONE;//Route TS mask\r
1867 PdCommonSetup.AxCOffset[i] = hAif->AxCconfig[i].pdAxCOffset;\r
1868 PdCommonSetup.AxCOffsetWin = AIF2_OBSAI_AXC_OFFSET_WIN; //AxC offset window\r
1869 if (hAif->mode == AIF_LTE_WCDMA_MODE) // dual mode\r
1870 {\r
1871 if (hAif->linkConfig[z].mode == LTE)\r
1872 PdCommonSetup.PdChConfig1[i].FrameCounter = 0;//framing counter group number\r
1873 else\r
1874 PdCommonSetup.PdChConfig1[i].FrameCounter = 1;//framing counter group number\r
1875 } else {\r
1876 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)){\r
1877 PdCommonSetup.PdChConfig1[i].FrameCounter = groupId;\r
1878 } else {\r
1879 PdCommonSetup.PdChConfig1[i].FrameCounter = 0;//framing counter group number\r
1880 }\r
1881 }\r
1882 PdCommonSetup.PdRoute[i].RouteLink = z;//Route link\r
1883 }\r
1884 } else { // CPRI\r
1885 PdCommonSetup.AxCOffset[i] = hAif->AxCconfig[i].pdAxCOffset;\r
1886 if ((8==hAif->linkConfig[z].linkRate) && (hAif->mode == AIF_WCDMA_MODE)) {\r
1887 PdCommonSetup.PdChConfig1[i].FrameCounter = 1;//framing counter group number\r
1888 } else if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
1889 PdCommonSetup.PdChConfig1[i].FrameCounter = groupId;\r
1890 } else {\r
1891 PdCommonSetup.PdChConfig1[i].FrameCounter = 0;//framing counter group number\r
1892 }\r
1893 }\r
1894 PdCommonSetup.PdChConfig[i].bChannelEn = true;//Channel enable\r
1895 PdCommonSetup.PdChConfig[i].DataFormat = hAif->linkConfig[z].inboundDataType; //Data format\r
1896 PdCommonSetup.PdChConfig1[i].bTsWatchDogEn = false;//disable watchdog\r
1897 PdCommonSetup.PdChConfig1[i].DataFormat = AIF2FL_GSM_DATA_OTHER;//Non GSM data\r
1898 PdCommonSetup.PdChConfig1[i].DioOffset = 0;//Use zero offset for simple test\r
1899 if (hAif->mode == AIF_LTE_TDD_MODE)\r
1900 {\r
1901 tddSubFrameBitMap = hAif->linkConfig[z].lteTddUlDlCfg[i];\r
1902 for (k=0;k<10;k++)\r
1903 {\r
1904 // DL SF\r
1905 if ((tddSubFrameBitMap & 0x00000003) == 0x00000000) {\r
1906 for (j=0;j<(AIF2_LTE_SYMBOL_NUM*2);j++)\r
1907 {\r
1908 tddTable[j+AIF2_LTE_SYMBOL_NUM*2*k] = 0;\r
1909 }\r
1910 }\r
1911 // UL SF\r
1912 if ((tddSubFrameBitMap & 0x00000003) == 0x00000003) {\r
1913 for (j=0;j<(AIF2_LTE_SYMBOL_NUM*2);j++)\r
1914 {\r
1915 tddTable[j+AIF2_LTE_SYMBOL_NUM*2*k] = 1;\r
1916 }\r
1917 }\r
1918 // Special SF\r
1919 if ((tddSubFrameBitMap & 0x00000003) == 0x00000001) {\r
1920 tddSpecSubFrameBitMap = hAif->linkConfig[z].lteTddSsfNcpCfg[i];\r
1921 for (j=0;j<(AIF2_LTE_SYMBOL_NUM*2);j++)\r
1922 {\r
1923 if ((tddSpecSubFrameBitMap & 0x00000003) == 0x00000003) {\r
1924 tddTable[j+AIF2_LTE_SYMBOL_NUM*2*k] = 1;\r
1925 } else {\r
1926 tddTable[j+AIF2_LTE_SYMBOL_NUM*2*k] = 0;\r
1927 }\r
1928 tddSpecSubFrameBitMap>>=2;\r
1929 }\r
1930 }\r
1931 tddSubFrameBitMap>>=2;\r
1932 }\r
1933 \r
1934 offsetTdd = 0;\r
1935 PdCommonSetup.PdChConfig1[i].TddEnable = 0;\r
1936 PdCommonSetup.TddEnable1[i] = 0;\r
1937 PdCommonSetup.TddEnable2[i] = 0;\r
1938 PdCommonSetup.TddEnable3[i] = 0;\r
1939 PdCommonSetup.TddEnable4[i] = 0;\r
1940 for (j=0;j<16;j++)\r
1941 {\r
1942 PdCommonSetup.PdChConfig1[i].TddEnable += tddTable[j+offsetTdd]<<j;\r
1943 }\r
1944 offsetTdd += j;\r
1945 for (j=0;j<32;j++)\r
1946 {\r
1947 PdCommonSetup.TddEnable1[i] += tddTable[j+offsetTdd]<<j; //enables all symbols(FDD)\r
1948 }\r
1949 offsetTdd += j;\r
1950 for (j=0;j<32;j++)\r
1951 {\r
1952 PdCommonSetup.TddEnable2[i] += tddTable[j+offsetTdd]<<j; //enables all symbols(FDD)\r
1953 }\r
1954 offsetTdd += j;\r
1955 for (j=0;j<32;j++)\r
1956 {\r
1957 PdCommonSetup.TddEnable3[i] += tddTable[j+offsetTdd]<<j; //enables all symbols(FDD)\r
1958 }\r
1959 offsetTdd += j;\r
1960 for (j=0;j<32;j++)\r
1961 {\r
1962 PdCommonSetup.TddEnable4[i] += tddTable[j+offsetTdd]<<j; //enables all symbols(FDD)\r
1963 }\r
1964 \r
1965 } else {\r
1966 PdCommonSetup.PdChConfig1[i].TddEnable = 0xFFFF;//enables all symbols(FDD)\r
1967 PdCommonSetup.TddEnable1[i] = 0xFFFFFFFF;//enables all symbols(FDD)\r
1968 PdCommonSetup.TddEnable2[i] = 0xFFFFFFFF;//enables all symbols(FDD)\r
1969 PdCommonSetup.TddEnable3[i] = 0xFFFFFFFF;//enables all symbols(FDD)\r
1970 PdCommonSetup.TddEnable4[i] = 0xFFFFFFFF;//enables all symbols(FDD)\r
1971 }\r
1972 }\r
1973 \r
1974 // channel for ps\r
1975 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
1976 if ((hAif->linkConfig[i].psMsgEnable) && (hAif->linkConfig[i].linkEnable)) {\r
1977 for (j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
1978 {\r
1979 // map control stream 0 of each link to channel 124\r
1980 PdCommonSetup.PdChConfig[124+j].bChannelEn = true;\r
1981 PdCommonSetup.PdChConfig[124+j].DataFormat = AIF2FL_LINK_DATA_TYPE_NORMAL;\r
1982 }\r
1983 }\r
1984 }\r
1985 \r
1986 //PE common setup\r
1987 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
1988 if(AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
1989 PeCommonSetup.PeTokenPhase = 1;//Phase alignment for scheduling DMA OBSAI: only lsb is used\r
1990 else\r
1991 PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA OBSAI: only lsb is used\r
1992 PeCommonSetup.EnetHeaderSelect = 0;//bit order for Ethernet preamble and SOF\r
1993 } else {\r
1994 if(AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
1995 PeCommonSetup.PeTokenPhase = 1;//Phase alignment for scheduling DMA OBSAI: only lsb is used\r
1996 else\r
1997 PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA OBSAI: only lsb is used\r
1998 \r
1999 PeCommonSetup.EnetHeaderSelect = 0;//bit order for Ethernet preamble and SOF\r
2000 }\r
2001 if (hAif->mode == AIF_WCDMA_MODE) {\r
2002 PeCommonSetup.GlobalDioLen = AIF2FL_DB_DIO_LEN_128;\r
2003 }\r
2004 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)){\r
2005 PeCommonSetup.EnetHeaderSelect = 1;//bit order for Ethernet preamble and SOF\r
2006 }\r
2007 if (hAif->mode == AIF_LTE_WCDMA_MODE){\r
2008 PeCommonSetup.EnetHeaderSelect = 1;//bit order for Ethernet preamble and SOF\r
2009 PeCommonSetup.GlobalDioLen = AIF2FL_DB_DIO_LEN_256;\r
2010 }\r
2011 \r
2012 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
2013 //Doubling of entries for normal CP to go to sub-frame for supporting MBFSN.\r
2014 #define MBSFN_FACTOR 2\r
2015 frameIndexSc = 0;\r
2016 initEgrGroupInfo();\r
2017 } else { \r
2018 for (i = 0; i < 6; i++) {\r
2019 PeCommonSetup.PeFrameTC[i].FrameIndexSc = PdCommonSetup.PdFrameTC[i].FrameIndexSc;\r
2020 PeCommonSetup.PeFrameTC[i].FrameIndexTc = PdCommonSetup.PdFrameTC[i].FrameIndexTc;\r
2021 PeCommonSetup.PeFrameTC[i].FrameSymbolTc = PdCommonSetup.PdFrameTC[i].FrameSymbolTc;\r
2022 }\r
2023 } \r
2024 \r
2025 z = first_link; //track to which link this channel corresponds\r
2026 k = 0;\r
2027 for (i = 0; i < max_channel_pe; i++)//for channel 0,...to max channels used by all links\r
2028 {\r
2029 if (i >= (hAif->linkConfig[z].firstPeDBCH\r
2030 + hAif->linkConfig[z].numPeAxC)) {\r
2031 do {\r
2032 z++;\r
2033 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2034 k = 0;\r
2035 }\r
2036 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
2037 if (hAif->linkConfig[z].multiRate == 0)\r
2038 sampleRate = hAif->linkConfig[z].sampleRate;\r
2039 else\r
2040 sampleRate = hAif->AxCconfig[i].sampleRate;\r
2041 linkRate = hAif->linkConfig[z].linkRate;\r
2042 lteCpType = hAif->AxCconfig[i].lteCpType;\r
2043 cellId = hAif->AxCconfig[i].egressLTEcellId;\r
2044 \r
2045 if ((groupId = addAxCtoEgrGroupTable(i, sampleRate, lteCpType, cellId, &isNewGroup))\r
2046 == AIF_NUM_PD_PE_FRAME_TC_GROUPS) {\r
2047 Aif2_osalLog("Fatal Error: addAxCtoEgrGroupTable returned bad ID\n");\r
2048 }\r
2049 \r
2050 if (isNewGroup) {\r
2051 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
2052 {\r
2053 PeCommonSetup.PeFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
2054 PeCommonSetup.PeFrameTC[groupId].FrameIndexTc = frameIndexSc;//terminal index\r
2055 if (sampleRate == AIF_SRATE_3P84MHZ)\r
2056 PeCommonSetup.PeFrameTC[groupId].FrameSymbolTc = 15-1;//20 slots for LTE\r
2057 else\r
2058 PeCommonSetup.PeFrameTC[groupId].FrameSymbolTc = 120-1;//20 slots for LTE\r
2059 frameIndexSc += 1;\r
2060 } else if (sampleRate != AIF_SRATE_1P92MHZ) {\r
2061 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2062 PeCommonSetup.PeFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
2063 PeCommonSetup.PeFrameTC[groupId].FrameIndexTc = frameIndexSc + ((MBSFN_FACTOR * AIF2_LTE_SYMBOL_NUM) - 1);//terminal index\r
2064 PeCommonSetup.PeFrameTC[groupId].FrameSymbolTc = AIF2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE\r
2065 frameIndexSc += (MBSFN_FACTOR * AIF2_LTE_SYMBOL_NUM);\r
2066 }\r
2067 else { // Extended CP\r
2068 PeCommonSetup.PeFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
2069 PeCommonSetup.PeFrameTC[groupId].FrameIndexTc = frameIndexSc + (AIF2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index\r
2070 PeCommonSetup.PeFrameTC[groupId].FrameSymbolTc = AIF2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE\r
2071 frameIndexSc += AIF2_LTE_SYMBOL_NUM_EXT_CP;\r
2072 }\r
2073 } else { //AIF_SRATE_1P92MHZ\r
2074 PeCommonSetup.PeFrameTC[groupId].FrameIndexSc = frameIndexSc;//start index\r
2075 PeCommonSetup.PeFrameTC[groupId].FrameIndexTc = frameIndexSc;//terminal index\r
2076 PeCommonSetup.PeFrameTC[groupId].FrameSymbolTc = 20-1;//20 slots for LTE\r
2077 frameIndexSc += 1;\r
2078 }\r
2079 \r
2080 if (sampleRate == AIF_SRATE_1P92MHZ) {\r
2081 FrameMsg1 = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPRENORMAL1_SIZE;\r
2082 FrameMsg = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPRENORMAL_SIZE;\r
2083 FrameMsg2 = AIF2_LTE1P4_FFT_SIZE + AIF2_LTE1P4_CYPREEXTENDED_SIZE;\r
2084 }\r
2085 if (sampleRate == AIF_SRATE_3P84MHZ) {\r
2086 FrameMsg1 = 0;\r
2087 FrameMsg = 0;\r
2088 FrameMsg2 = 2560;\r
2089 totalAxC = 0;\r
2090 }\r
2091 if (sampleRate == AIF_SRATE_7P68MHZ) {\r
2092 FrameMsg1 = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPRENORMAL1_SIZE;\r
2093 FrameMsg = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPRENORMAL_SIZE;\r
2094 FrameMsg2 = AIF2_LTE5_FFT_SIZE + AIF2_LTE5_CYPREEXTENDED_SIZE;\r
2095 }\r
2096 if (sampleRate == AIF_SRATE_15P36MHZ) {\r
2097 FrameMsg1 = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPRENORMAL1_SIZE;\r
2098 FrameMsg = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPRENORMAL_SIZE;\r
2099 FrameMsg2 = AIF2_LTE10_FFT_SIZE + AIF2_LTE10_CYPREEXTENDED_SIZE;\r
2100 }\r
2101 if (sampleRate == AIF_SRATE_23P04MHZ) {\r
2102 FrameMsg1 = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPRENORMAL1_SIZE;\r
2103 FrameMsg = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPRENORMAL_SIZE;\r
2104 FrameMsg2 = AIF2_LTE15_FFT_SIZE + AIF2_LTE15_CYPREEXTENDED_SIZE;\r
2105 }\r
2106 if (sampleRate == AIF_SRATE_30P72MHZ) {\r
2107 FrameMsg1 = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPRENORMAL1_SIZE;\r
2108 FrameMsg = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPRENORMAL_SIZE;\r
2109 FrameMsg2 = AIF2_LTE20_FFT_SIZE + AIF2_LTE20_CYPREEXTENDED_SIZE;\r
2110 }\r
2112 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol){\r
2113 if (hAif->mode == AIF_LTE_WCDMA_MODE)
2114 {\r
2115 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = FrameMsg2 - 1;\r
2116 } else if (sampleRate == AIF_SRATE_1P92MHZ) {\r
2117 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2118 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = (FrameMsg1+6*FrameMsg) - 1;\r
2119 }\r
2120 else {\r
2121 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = (6*FrameMsg2) - 1;\r
2122 }\r
2123 } else {\r
2124 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2125 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = FrameMsg1 - 1;\r
2126 //frame message terminal count for other 6 normal cyclic prefix LTE symbols\r
2127 for(j=1;j<(AIF2_LTE_SYMBOL_NUM);j++){\r
2128 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] = FrameMsg - 1;\r
2129 }\r
2130 //Copy 1st slot into 2nd slot for MBSFN\r
2131 for(j = AIF2_LTE_SYMBOL_NUM; j < (MBSFN_FACTOR * AIF2_LTE_SYMBOL_NUM); j++) {\r
2132 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] =\r
2133 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + (j - AIF2_LTE_SYMBOL_NUM)];\r
2134 }\r
2135 }\r
2136 else {\r
2137 //frame message terminal count for all 6 extended cyclic prefix LTE symbols\r
2138 for(j=0;j<(AIF2_LTE_SYMBOL_NUM_EXT_CP);j++){\r
2139 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] = FrameMsg2 - 1;\r
2140 }\r
2141 }\r
2142 }\r
2143 } else {\r
2144 if (sampleRate == AIF_SRATE_1P92MHZ)\r
2145 {\r
2146 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2147 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = ((FrameMsg1+6*FrameMsg)/AIF2_NUM_WORDS_PER_QWORD) - 1;\r
2148 }\r
2149 else {\r
2150 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = (6*FrameMsg2) - 1;\r
2151 }\r
2152 } else {\r
2153 if (lteCpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2154 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc] = (FrameMsg1/AIF2_NUM_WORDS_PER_QWORD) - 1;\r
2155 //frame message terminal count for other 6 normal cyclic prefix LTE symbols\r
2156 for(j=1;j<(AIF2_LTE_SYMBOL_NUM);j++){\r
2157 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] = (FrameMsg/AIF2_NUM_WORDS_PER_QWORD) - 1;\r
2158 }\r
2159 //Copy 1st slot into 2nd slot for MBSFN\r
2160 for(j = AIF2_LTE_SYMBOL_NUM; j < (MBSFN_FACTOR * AIF2_LTE_SYMBOL_NUM); j++) {\r
2161 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] =\r
2162 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + (j - AIF2_LTE_SYMBOL_NUM)];\r
2163 }\r
2164 }\r
2165 else {\r
2166 //frame message terminal count for all 6 extended cyclic prefix LTE symbols\r
2167 for(j=0;j<(AIF2_LTE_SYMBOL_NUM_EXT_CP);j++){\r
2168 PeCommonSetup.PeFrameMsgTc[PeCommonSetup.PeFrameTC[groupId].FrameIndexSc + j] = (FrameMsg2/AIF2_NUM_WORDS_PER_QWORD) - 1;\r
2169 }\r
2170 }\r
2171 }\r
2172 }\r
2173 }\r
2174 }\r
2175 \r
2176 PeCommonSetup.bEnableCh[i] = true;//Enable PE channel\r
2177 PeCommonSetup.PeDmaCh0[i].bCrcEn = false;//disable CRC\r
2178 if (hAif->linkConfig[z].RtEnabled==1)\r
2179 PeCommonSetup.PeDmaCh0[i].RtControl = AIF2FL_PE_RT_RETRANS;//use PE insert option\r
2180 else\r
2181 PeCommonSetup.PeDmaCh0[i].RtControl = AIF2FL_PE_RT_INSERT;//use PE insert option\r
2182 if (hAif->linkConfig[i].outboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
2183 {\r
2184 PeCommonSetup.PeDmaCh0[i].CrcType = AIF2FL_CRC_8BIT;//CRC type\r
2185 } else {\r
2186 PeCommonSetup.PeDmaCh0[i].CrcType = AIF2FL_CRC_16BIT;//CRC type\r
2187 }\r
2188 PeCommonSetup.PeDmaCh0[i].isEthernet = false;//AxC data\r
2189 PeCommonSetup.PeDmaCh0[i].CrcObsaiHeader = false;\r
2190 PeCommonSetup.PeInFifo[i].SyncSymbol = 0;//Sync symbol offset\r
2191 if ((hAif->mode == AIF_WCDMA_MODE) || (hAif->mode == AIF_GENERICPACKET_MODE) || (hAif->linkConfig[z].mode == WCDMA)) {\r
2192 PeCommonSetup.PeInFifo[i].MFifoWmark = 2;//Message FIFO water mark\r
2193 PeCommonSetup.PeInFifo[i].MFifoFullLevel = 3;//Message FIFO full level\r
2194 }\r
2195 else {\r
2196 PeCommonSetup.PeInFifo[i].MFifoWmark = 3;//Message FIFO water mark\r
2197 PeCommonSetup.PeInFifo[i].MFifoFullLevel = 5;//Message FIFO full level\r
2198 }\r
2199 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
2200 \r
2201 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
2202 {\r
2203 if (hAif->linkConfig[z].mode == LTE)\r
2204 {\r
2205 PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//use framing terminal count 0\r
2206 obsai_type = AIF2_OBSAI_TYPE_LTE;\r
2207 } else {\r
2208 PeCommonSetup.PeDmaCh0[i].FrameTC = 1;//use framing terminal count 0\r
2209 obsai_type = AIF2_OBSAI_TYPE_WCDMA_FDD;\r
2210 }\r
2211 } else {\r
2212 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)) {\r
2213 PeCommonSetup.PeDmaCh0[i].FrameTC = groupId;\r
2214 \r
2215 } else {\r
2216 PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//framing counter group number\r
2217 }\r
2218 }\r
2219 PeCommonSetup.PeAxcOffset[i] = hAif->AxCconfig[i].peAxCOffset;\r
2220 PeCommonSetup.PeChObsaiType[i] = obsai_type;//OBSAI header type\r
2221 PeCommonSetup.PeChObsaiAddr[i] = i;//OBSAI header address (use simple rising sequence)\r
2222 if (hAif->mode == AIF_GENERICPACKET_MODE){\r
2223 PeCommonSetup.PeChObsaiTS[i] = 0x0;//OBSAI header Time Stamp\r
2224 PeCommonSetup.PeChObsaiTsMask[i] = AIF2FL_ROUTE_MASK_4LSB;\r
2225 PeCommonSetup.PeChObsaiTsfomat[i] = AIF2FL_TSTAMP_FORMAT_GEN_PKT;//OBSAI header noraml TS format\r
2226 PeCommonSetup.PeObsaiPkt[i] = true;//Select OBSAI AxC or packet mode\r
2227 PeCommonSetup.ChIndex0[k+(64*z)] = i;\r
2228 PeCommonSetup.bEnableChIndex0[k+(64*z)]= true;\r
2229 } else {\r
2230 PeCommonSetup.PeChObsaiTsMask[i] = AIF2FL_ROUTE_MASK_NONE;//not use Ts field\r
2231 PeCommonSetup.PeChObsaiTsfomat[i] = AIF2FL_TSTAMP_FORMAT_NORM_TS;//OBSAI header noraml TS format\r
2232 PeCommonSetup.PeObsaiPkt[i] = false;//Select OBSAI AxC or packet mode\r
2233 PeCommonSetup.PeChObsaiTS[i] = 0;//OBSAI header Time Stamp\r
2234 PeCommonSetup.ChIndex0[k+(64*z)] = i;\r
2235 PeCommonSetup.bEnableChIndex0[k+(64*z)]= true;\r
2236 }\r
2237 PeCommonSetup.PeBbHop[i] = false;//Take OBSAI address from CPPI PS bits\r
2238 } else { // CPRI\r
2239 if ((8==hAif->linkConfig[z].linkRate) && (hAif->mode == AIF_WCDMA_MODE)) {\r
2240 PeCommonSetup.PeDmaCh0[i].FrameTC = 1;//use framing terminal count 0\r
2241 } else if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
2242 PeCommonSetup.PeDmaCh0[i].FrameTC = groupId;\r
2243 } else {\r
2244 PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//framing counter group number\r
2245 }\r
2246 if ((8==hAif->linkConfig[z].linkRate) && (hAif->linkConfig[z].outboundDataType == AIF2FL_LINK_DATA_TYPE_RSA) && (hAif->linkConfig[z].firstPeDBCH+21<i && i<hAif->linkConfig[z].firstPeDBCH+30))\r
2247 PeCommonSetup.PeAxcOffset[i] = hAif->AxCconfig[i].peAxCOffset + 64;\r
2248 else\r
2249 PeCommonSetup.PeAxcOffset[i] = hAif->AxCconfig[i].peAxCOffset;\r
2250 if (hAif->mode == AIF_LTE_FDD_MODE || hAif->mode == AIF_LTE_TDD_MODE || (hAif->mode == AIF_LTE_WCDMA_MODE))\r
2251 {\r
2252 for(j=0;j<dbmxPe[z];j++)\r
2253 {\r
2254 // ChIndex0 for link0, ChIndex1 for link1 i for AxC (maxAxC) k for AxC of the specific link\r
2255 if (z == (Aif2Fl_LinkIndex)0){\r
2256 if (hAif->linkConfig[z].multiRate == 0){\r
2257 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2258 {\r
2259 PeCommonSetup.ChIndex0[j] = i;\r
2260 PeCommonSetup.bEnableChIndex0[j] = true;\r
2261 }\r
2262 } else {\r
2263 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2264 {\r
2265 PeCommonSetup.ChIndex0[j] = i;\r
2266 PeCommonSetup.bEnableChIndex0[j] = true;\r
2267 }\r
2268 }\r
2269 PeCommonSetup.CpriPktEn0[j] = false;\r
2270 }\r
2271 if (z == (Aif2Fl_LinkIndex)1){\r
2272 if (hAif->linkConfig[z].multiRate == 0){\r
2273 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2274 {\r
2275 PeCommonSetup.ChIndex1[j] = i;\r
2276 PeCommonSetup.bEnableChIndex1[j] = true;\r
2277 }\r
2278 } else {\r
2279 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2280 {\r
2281 PeCommonSetup.ChIndex1[j] = i;\r
2282 PeCommonSetup.bEnableChIndex1[j] = true;\r
2283 }\r
2284 }\r
2285 PeCommonSetup.CpriPktEn1[j] = false;\r
2286 }\r
2287 if (z == (Aif2Fl_LinkIndex) 2) {\r
2288 if (hAif->linkConfig[z].multiRate == 0){\r
2289 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2290 {\r
2291 PeCommonSetup.ChIndex2[j] = i;\r
2292 PeCommonSetup.bEnableChIndex2[j] = true;\r
2293 }\r
2294 } else {\r
2295 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2296 {\r
2297 PeCommonSetup.ChIndex2[j] = i;\r
2298 PeCommonSetup.bEnableChIndex2[j] = true;\r
2299 }\r
2300 }\r
2301 PeCommonSetup.CpriPktEn2[j] = false;\r
2302 }\r
2303 if (z == (Aif2Fl_LinkIndex) 3) {\r
2304 if (hAif->linkConfig[z].multiRate == 0){\r
2305 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2306 {\r
2307 PeCommonSetup.ChIndex3[j] = i;\r
2308 PeCommonSetup.bEnableChIndex3[j] = true;\r
2309 }\r
2310 } else {\r
2311 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2312 {\r
2313 PeCommonSetup.ChIndex3[j] = i;\r
2314 PeCommonSetup.bEnableChIndex3[j] = true;\r
2315 }\r
2316 }\r
2317 PeCommonSetup.CpriPktEn3[j] = false;\r
2318 }\r
2319 if (z == (Aif2Fl_LinkIndex) 4) {\r
2320 if (hAif->linkConfig[z].multiRate == 0){\r
2321 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2322 {\r
2323 PeCommonSetup.ChIndex4[j] = i;\r
2324 PeCommonSetup.bEnableChIndex4[j] = true;\r
2325 } \r
2326 } else {\r
2327 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2328 {\r
2329 PeCommonSetup.ChIndex4[j] = i;\r
2330 PeCommonSetup.bEnableChIndex4[j] = true;\r
2331 }\r
2332 }\r
2333 PeCommonSetup.CpriPktEn4[j] = false;\r
2334 }\r
2335 if (z == (Aif2Fl_LinkIndex) 5) {\r
2336 if (hAif->linkConfig[z].multiRate == 0){\r
2337 if ((hAif->linkConfig[z].maskPattern[k]>>j)&1)\r
2338 {\r
2339 PeCommonSetup.ChIndex5[j] = i;\r
2340 PeCommonSetup.bEnableChIndex5[j] = true;\r
2341 }\r
2342 } else {\r
2343 if ((hAif->AxCconfig[i].maskPattern>>j)&1)\r
2344 {\r
2345 PeCommonSetup.ChIndex5[j] = i;\r
2346 PeCommonSetup.bEnableChIndex5[j] = true;\r
2347 }\r
2348 }\r
2349 PeCommonSetup.CpriPktEn5[j] = false;\r
2350 }\r
2351 }\r
2352 } else {\r
2353 // ChIndex0 for link0, ChIndex1 for link1\r
2354 if (z == (Aif2Fl_LinkIndex)0){\r
2355 PeCommonSetup.ChIndex0[k] = i;\r
2356 PeCommonSetup.bEnableChIndex0[k] = true;\r
2357 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn0[k] = true;\r
2358 else PeCommonSetup.CpriPktEn0[k] = false;\r
2359 }\r
2360 if (z == (Aif2Fl_LinkIndex)1){\r
2361 PeCommonSetup.ChIndex1[k] = i;\r
2362 PeCommonSetup.bEnableChIndex1[k] = true;\r
2363 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn1[k] = true;\r
2364 else PeCommonSetup.CpriPktEn1[k] = false;\r
2365 }\r
2366 if (z == (Aif2Fl_LinkIndex) 2) {\r
2367 PeCommonSetup.ChIndex2[k] = i;\r
2368 PeCommonSetup.bEnableChIndex2[k] = true;\r
2369 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn2[k] = true;\r
2370 else PeCommonSetup.CpriPktEn2[k] = false;\r
2371 }\r
2372 if (z == (Aif2Fl_LinkIndex) 3) {\r
2373 PeCommonSetup.ChIndex3[k] = i;\r
2374 PeCommonSetup.bEnableChIndex3[k] = true;\r
2375 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn3[k] = true;\r
2376 else PeCommonSetup.CpriPktEn3[k] = false;\r
2377 }\r
2378 if (z == (Aif2Fl_LinkIndex) 4) {\r
2379 PeCommonSetup.ChIndex4[k] = i;\r
2380 PeCommonSetup.bEnableChIndex4[k] = true;\r
2381 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn4[k] = true;\r
2382 else PeCommonSetup.CpriPktEn4[k] = false;\r
2383 }\r
2384 if (z == (Aif2Fl_LinkIndex) 5) {\r
2385 PeCommonSetup.ChIndex5[k] = i;\r
2386 PeCommonSetup.bEnableChIndex5[k] = true;\r
2387 if (hAif->mode == AIF_GENERICPACKET_MODE) PeCommonSetup.CpriPktEn5[k] = true;\r
2388 else PeCommonSetup.CpriPktEn5[k] = false;\r
2389 }\r
2390 }\r
2391 }\r
2392 k++;\r
2393 }\r
2394 \r
2395 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol){\r
2396 //2560 CPRI samples (4 byte) are in WCDMA slot time\r
2397 if (hAif->mode == AIF_WCDMA_MODE) {\r
2398 PeCommonSetup.PeFrameMsgTc[0] = ((PdCommonSetup.PdFrameMsgTc[0]+1)*4)-1;\r
2399 PeCommonSetup.PeFrameMsgTc[1] = ((PdCommonSetup.PdFrameMsgTc[1]+1)*4)-1;\r
2400 }\r
2401 \r
2402 // channel for ps\r
2403 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
2404 if ((hAif->linkConfig[i].psMsgEnable) && (hAif->linkConfig[i].linkEnable)) {\r
2405 for(j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
2406 {\r
2407 PeCommonSetup.bEnableCh[124+j] = true;//Enable Control channel\r
2408 PeCommonSetup.PeDmaCh0[124+j].bCrcEn = false;//disable CRC\r
2409 PeCommonSetup.PeDmaCh0[124+j].RtControl = AIF2FL_PE_RT_INSERT;//use PE insert option\r
2410 if (j == 0) PeCommonSetup.PeDmaCh0[124+j].isEthernet = false;\r
2411 else PeCommonSetup.PeDmaCh0[124+j].isEthernet = false;\r
2412 PeCommonSetup.PeInFifo[124+j].MFifoWmark = 2;//Message FIFO water mark\r
2413 PeCommonSetup.PeInFifo[124+j].MFifoFullLevel = 3;//Message FIFO full level\r
2414 }\r
2415 }\r
2416 }\r
2417 } else {\r
2418 if ((hAif->mode == AIF_WCDMA_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
2419 PeCommonSetup.PeFrameMsgTc[0] = PdCommonSetup.PdFrameMsgTc[0];//OBSAI frame message terminal count for slot 0 ~ 14\r
2420 PeCommonSetup.PeFrameMsgTc[1] = PdCommonSetup.PdFrameMsgTc[1];\r
2421 }\r
2422 \r
2423 for (i = 0; i < AIF_MAX_NUM_LINKS; i++) {\r
2424 if (hAif->linkConfig[i].linkEnable) {\r
2425 // channel for ps (TO BE DEBUGGED)\r
2426 if (hAif->linkConfig[i].psMsgEnable) {\r
2427 PeCommonSetup.PeChObsaiType[122 + i] = AIF2_OBSAI_TYPE_WCDMA_FDD;//OBSAI header type\r
2428 PeCommonSetup.PeChObsaiTS[122 + i] = 0;//OBSAI header Time Stamp\r
2429 PeCommonSetup.PeChObsaiAddr[122 + i] = i;//OBSAI header address (use simple rising sequence)\r
2430 PeCommonSetup.PeChObsaiTsMask[122 + i] = AIF2FL_ROUTE_MASK_NONE;//not use Ts field\r
2431 PeCommonSetup.PeChObsaiTsfomat[122 + i] = AIF2FL_TSTAMP_FORMAT_NORM_TS;//OBSAI header noraml TS format\r
2432 PeCommonSetup.PeObsaiPkt[122 + i] = true;//Select OBSAI packet mode\r
2433 PeCommonSetup.PeBbHop[122 + i] = true;//Take OBSAI address from CPPI PS bits\r
2434 PeCommonSetup.PeModuloTc[i + 6].bEnableRule = true; //enable rule\r
2435 PeCommonSetup.PeModuloTc[i + 6].RuleModulo = 0;//modulo termical count(Modulo -1)\r
2436 PeCommonSetup.PeModuloTc[i + 6].bRuleObsaiCtlMsg = true;\r
2437 PeCommonSetup.PeModuloTc[i + 6].RuleIndex = 0;//Setup modulo rule index (0 ~ Modulo-1)\r
2438 PeCommonSetup.PeModuloTc[i + 6].RuleLink = i;//Route egress modulo rule 0 to link 0\r
2439 PeCommonSetup.PeObsaiDualBitMap[i + 6].DbmX = 0;//DbmX number(1 PS channel for 4x link). set X-1 value\r
2440 PeCommonSetup.PeObsaiDualBitMap[i + 6].DbmXBubble= 0;//OBSAI 4 AxC sample length bubble\r
2441 PeCommonSetup.PeObsaiDualBitMap[i + 6].Dbm1Mult = 0;//Dbm1 repetition number set n-1 value\r
2442 PeCommonSetup.PeObsaiDualBitMap[i + 6].Dbm1Size = 0;//Dbm1 size (1 ~ 100) set n-1 value\r
2443 PeCommonSetup.PeObsaiDualBitMap[i + 6].Dbm1Map[0]= 0x0;// no bubble\r
2444 PeCommonSetup.PeObsaiDualBitMap[i + 6].Dbm2Size = 0; //Dbm2 size (0 ~ 70)set n value\r
2445 PeCommonSetup.PeObsaiDualBitMap[i + 6].Dbm2Map[0] = 0x0;\r
2446 }\r
2447 \r
2448 //modulo rule 0 setup\r
2449 PeCommonSetup.PeModuloTc[i].bEnableRule = true; //enable rule\r
2450 PeCommonSetup.PeModuloTc[i].RuleModulo = 0;//modulo termical count(Modulo -1)\r
2451 PeCommonSetup.PeModuloTc[i].bRuleObsaiCtlMsg = false;\r
2452 PeCommonSetup.PeModuloTc[i].RuleIndex = 0;//Setup modulo rule index (0 ~ Modulo-1)\r
2453 PeCommonSetup.PeModuloTc[i].RuleLink = i;//Route egress modulo rule 0 to link 0\r
2454 \r
2455 //DBM rule 0 setup\r
2456 if (hAif->linkConfig[i].sampleRate == AIF_SRATE_23P04MHZ) {\r
2457 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Mult = 0;//Dbm1 repetition number set n-1 value\r
2458 PeCommonSetup.PeObsaiDualBitMap[i].Dbm2Size = 0; //Dbm2 size (0 ~ 70)set n value\r
2459 PeCommonSetup.PeObsaiDualBitMap[i].Dbm2Map[0] = 0x0;\r
2460 if (hAif->linkConfig[i].linkRate == 8) {\r
2461 PeCommonSetup.PeObsaiDualBitMap[i].DbmX = (hAif->linkConfig[i].linkRate*4*256*15/23040) - 1;\r
2462 PeCommonSetup.PeObsaiDualBitMap[i].DbmXBubble = 0;//OBSAI 4 AxC sample length bubble\r
2463 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Map[0] = 0x2;\r
2464 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Size = 2;//Dbm1 size (1 ~ 100) set n-1 value\r
2465 } else if (hAif->linkConfig[i].linkRate == 4) {\r
2466 PeCommonSetup.PeObsaiDualBitMap[i].DbmX = 7; // Eight message slot for only 2 AxCs\r
2467 PeCommonSetup.PeObsaiDualBitMap[i].DbmXBubble = 0;//OBSAI two msg length bubble\r
2468 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Map[0] = 0x0;\r
2469 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Size = 0;//Dbm1 size (1 ~ 100) set n-1 value\r
2470 for(j=2;j<8;j+=2)\r
2471 {\r
2472 PeCommonSetup.ChIndex0[j+(64*i)] = PeCommonSetup.ChIndex0[0+(64*i)];\r
2473 PeCommonSetup.ChIndex0[j+1+(64*i)] = PeCommonSetup.ChIndex0[1+(64*i)];\r
2474 if (j<6) {\r
2475 PeCommonSetup.bEnableChIndex0[j+(64*i)] = true;\r
2476 PeCommonSetup.bEnableChIndex0[j+1+(64*i)]= true;\r
2477 } else {\r
2478 PeCommonSetup.bEnableChIndex0[j+(64*i)] = false;\r
2479 PeCommonSetup.bEnableChIndex0[j+1+(64*i)]= false;\r
2480 }\r
2481 }\r
2482 }\r
2483 } else {\r
2484 if (hAif->mode == AIF_WCDMA_MODE)\r
2485 PeCommonSetup.PeObsaiDualBitMap[i].DbmX = (hAif->linkConfig[i].linkRate*4) - 1; //hAif->linkConfig[i].numPeAxC - 1;//DbmX number(16 for 4x link). set X-1 value\r
2486 else\r
2487 PeCommonSetup.PeObsaiDualBitMap[i].DbmX = hAif->linkConfig[i].numPeAxC - 1;//DbmX number(16 for 4x link). set X-1 value\r
2488 PeCommonSetup.PeObsaiDualBitMap[i].DbmXBubble = 0;//OBSAI 4 AxC sample length bubble\r
2489 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Mult = 0;//Dbm1 repetition number set n-1 value\r
2490 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Size = 0;//Dbm1 size (1 ~ 100) set n-1 value\r
2491 PeCommonSetup.PeObsaiDualBitMap[i].Dbm1Map[0] = 0x0;// no bubble\r
2492 PeCommonSetup.PeObsaiDualBitMap[i].Dbm2Size = 0; //Dbm2 size (0 ~ 70)set n value\r
2493 PeCommonSetup.PeObsaiDualBitMap[i].Dbm2Map[0] = 0x0;\r
2494 }\r
2495 }\r
2496 \r
2497 }\r
2498 }\r
2499 \r
2500 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
2501 {\r
2502 //Ingress DB setup\r
2503 IngrDbSetup.bEnableIngrDb = true; //Enable Ingress DB\r
2504 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
2505 IngrDbSetup.DioBufferLen = AIF2FL_DB_DIO_LEN_256; //Ingress DB DIO buffer length\r
2506 else\r
2507 IngrDbSetup.DioBufferLen = AIF2FL_DB_DIO_LEN_128; //Ingress DB DIO buffer length\r
2508 \r
2509 z = first_link; //track to which link this channel corresponds\r
2510 baseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0;\r
2511 for (i = 0; i < max_channel_pd; i++)//for channel 0,...to max channels used by all links\r
2512 {\r
2513 if (i >= (hAif->linkConfig[z].firstPdDBCH\r
2514 + hAif->linkConfig[z].numPdAxC)) {\r
2515 do {\r
2516 z++;\r
2517 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2518 }\r
2519 IngrDbSetup.bEnableChannel[i] = true; //Enable 4 Ingress DB channel\r
2520 IngrDbSetup.IngrDbChannel[i].BaseAddress = baseAddress;\r
2521 if (((hAif->linkConfig[z].multiRate == 0) && (hAif->mode == AIF_LTE_WCDMA_MODE && hAif->linkConfig[z].mode == LTE)) || ((hAif->linkConfig[z].multiRate == 1) && (hAif->mode == AIF_LTE_WCDMA_MODE && (hAif->AxCconfig[i].sampleRate != AIF_SRATE_3P84MHZ))))\r
2522 {\r
2523 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //No swap for DL\r
2524 baseAddress += 2;\r
2525 IngrDbSetup.IngrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2526 } else {\r
2527 if (hAif->linkConfig[z].inboundDataType==AIF2FL_LINK_DATA_TYPE_NORMAL) {\r
2528 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //No swap for DL\r
2529 baseAddress += 1;\r
2530 } else {\r
2531 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_BYTE_SWAP; //swap for UL\r
2532 baseAddress += 2;\r
2533 }\r
2534 IngrDbSetup.IngrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2535 }\r
2536 }\r
2537 baseIngr = baseAddress;\r
2538 \r
2539 //Egress DB setup\r
2540 EgrDbSetup.bEnableEgrDb = true; //Enable Egress DB\r
2541 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
2542 {\r
2543 EgrDbSetup.DioBufferLen = AIF2FL_DB_DIO_LEN_256; //Egress DB DIO buffer length\r
2544 EgrDbSetup.PmControl = AIF2FL_DB_PM_TOKEN_FIFO;//to enhance CPRI performance\r
2545 } else {\r
2546 EgrDbSetup.DioBufferLen = AIF2FL_DB_DIO_LEN_128; //Egress DB DIO buffer length\r
2547 EgrDbSetup.PmControl = AIF2FL_DB_AXC_TOKEN_FIFO;//to enhance CPRI performance\r
2548 }\r
2549 z = first_link; //track to which link this channel corresponds\r
2550 baseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0;\r
2551 for (i = 0; i < max_channel_pe; i++)//for channel 0,...to max channels used by all links\r
2552 {\r
2553 if (i >= (hAif->linkConfig[z].firstPeDBCH\r
2554 + hAif->linkConfig[z].numPeAxC)) {\r
2555 do {\r
2556 z++;\r
2557 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2558 }\r
2559 EgrDbSetup.bEnableChannel[i] = true; //Enable 4 Egress DB channel\r
2560 EgrDbSetup.EgrDbChannel[i].BaseAddress = baseAddress;\r
2561 if (((hAif->linkConfig[z].multiRate == 0) && (hAif->mode == AIF_LTE_WCDMA_MODE && hAif->linkConfig[z].mode == LTE)) || ((hAif->linkConfig[z].multiRate == 1) && (hAif->mode == AIF_LTE_WCDMA_MODE && (hAif->AxCconfig[i].sampleRate != AIF_SRATE_3P84MHZ))))\r
2562 {\r
2563 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //No swap for DL\r
2564 baseAddress += 2;\r
2565 EgrDbSetup.EgrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2566 } else {\r
2567 if (hAif->linkConfig[z].outboundDataType==AIF2FL_LINK_DATA_TYPE_NORMAL)\r
2568 {\r
2569 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //No swap for DL\r
2570 baseAddress += 1;\r
2571 } else {\r
2572 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_BYTE_SWAP; //swap for UL\r
2573 baseAddress += 2;\r
2574 }\r
2575 EgrDbSetup.EgrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2576 }\r
2577 }\r
2578 baseEgr = baseAddress;\r
2579 \r
2580 } else {\r
2581 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)) {\r
2582 \r
2583 IngrDbSetup.bEnableIngrDb = true; //Enable Ingress DB\r
2584 z = first_link; //track to which link this channel corresponds\r
2585 baseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0;\r
2586 for (i = 0; i < max_channel_pd; i++)//for channel 0,...to max channels used by all links\r
2587 {\r
2588 if (i >= (hAif->linkConfig[z].firstPdDBCH\r
2589 + hAif->linkConfig[z].numPdAxC)) {\r
2590 do {\r
2591 z++;\r
2592 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2593 }\r
2594 IngrDbSetup.bEnableChannel[i] = true; //Enable 4 Ingress DB channel\r
2595 #ifdef DEVICE_LE\r
2596 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //Word swap for DL (LE), No SWAP for (BE)\r
2597 #else\r
2598 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_NO_SWAP; //Word swap for DL (LE), No SWAP for (BE)\r
2599 #endif\r
2600 IngrDbSetup.IngrDbChannel[i].BaseAddress = baseAddress;\r
2601 \r
2602 if (hAif->linkConfig[z].multiRate == 0){\r
2603 if (hAif->linkConfig[z].sampleRate == AIF_SRATE_1P92MHZ)\r
2604 {\r
2605 baseAddress += i;\r
2606 } else {\r
2607 baseAddress += (1 << hAif->AxCconfig[i].ingressBufDepth);\r
2608 } \r
2609 } else {\r
2610 if (hAif->AxCconfig[i].sampleRate == AIF_SRATE_1P92MHZ)\r
2611 {\r
2612 baseAddress += i;\r
2613 } else {\r
2614 baseAddress += (1 << hAif->AxCconfig[i].ingressBufDepth);\r
2615 }\r
2616 }\r
2617 \r
2618 IngrDbSetup.IngrDbChannel[i].BufDepth = hAif->AxCconfig[i].ingressBufDepth; //Set DB FIFO depth for channel 0 to 64 QW(Quad word)\r
2619 \r
2620 IngrDbSetup.IngrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2621 IngrDbSetup.IngrDbChannel[i].bEnablePsData = true; //Enable 4 bytes PS data\r
2622 IngrDbSetup.IngrDbChannel[i].PacketType = 0; //User data\r
2623 \r
2624 }\r
2625 \r
2626 baseIngr = baseAddress;\r
2627 \r
2628 //Egress DB setup\r
2629 \r
2630 EgrDbSetup.bEnableEgrDb = true; //Enable Ingress DB\r
2631 EgrDbSetup.PmControl = AIF2FL_DB_AXC_TOKEN_FIFO;//to enhance CPRI performance\r
2632 z = first_link; //track to which link this channel corresponds\r
2633 baseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0;\r
2634 for (i = 0; i < max_channel_pe; i++)//for channel 0,...to max channels used by all links\r
2635 {\r
2636 if (i >= (hAif->linkConfig[z].firstPeDBCH\r
2637 + hAif->linkConfig[z].numPeAxC)) {\r
2638 do {\r
2639 z++;\r
2640 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2641 }\r
2642 EgrDbSetup.bEnableChannel[i] = true; //Enable 4 Egress DB channel\r
2643 \r
2644 #ifdef DEVICE_LE\r
2645 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //Word swap for DL (LE), No SWAP for (BE)\r
2646 #else\r
2647 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_NO_SWAP; //Word swap for DL (LE), No SWAP for (BE)\r
2648 #endif\r
2649 EgrDbSetup.EgrDbChannel[i].BaseAddress = baseAddress;\r
2650 if (hAif->linkConfig[z].multiRate == 0){\r
2651 if (hAif->linkConfig[z].sampleRate == AIF_SRATE_1P92MHZ)\r
2652 {\r
2653 baseAddress += i;\r
2654 } else {\r
2655 baseAddress += (1 << hAif->AxCconfig[i].egressBufDepth);\r
2656 }\r
2657 } else {\r
2658 if (hAif->AxCconfig[i].sampleRate == AIF_SRATE_1P92MHZ)\r
2659 {\r
2660 baseAddress += i;\r
2661 } else {\r
2662 baseAddress += (1 << hAif->AxCconfig[i].egressBufDepth);\r
2663 }\r
2664 }\r
2665 EgrDbSetup.EgrDbChannel[i].BufDepth = hAif->AxCconfig[i].egressBufDepth; //Set DB FIFO depth for channel 0 to 64 QW(Quad word)\r
2666 EgrDbSetup.EgrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2667 }\r
2668 \r
2669 baseEgr = baseAddress; \r
2670 }\r
2671 if ((hAif->mode == AIF_GENERICPACKET_MODE) ) {\r
2672 \r
2673 IngrDbSetup.bEnableIngrDb = true; //Enable Ingress DB\r
2674 z = first_link; //track to which link this channel corresponds\r
2675 baseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0;\r
2676 for (i = 0; i < max_channel_pd; i++)//for channel 0,...to max channels used by all links\r
2677 {\r
2678 if (i >= (hAif->linkConfig[z].firstPdDBCH\r
2679 + hAif->linkConfig[z].numPdAxC)) {\r
2680 do {\r
2681 z++;\r
2682 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2683 }\r
2684 IngrDbSetup.bEnableChannel[i] = true; //Enable 4 Ingress DB channel\r
2685 IngrDbSetup.IngrDbChannel[i].BaseAddress = baseAddress;\r
2686 baseAddress += 8;\r
2687 IngrDbSetup.IngrDbChannel[i].BufDepth = hAif->AxCconfig[i].ingressBufDepth; //Set DB FIFO depth for channel 0 to 64 QW(Quad word)\r
2688 IngrDbSetup.IngrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //DL\r
2689 IngrDbSetup.IngrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2690 IngrDbSetup.IngrDbChannel[i].bEnablePsData = false; //Enable 4 bytes PS data\r
2691 IngrDbSetup.IngrDbChannel[i].PacketType = 0; //User data\r
2692 }\r
2693 baseIngr = baseAddress;\r
2694 \r
2695 //Egress DB setup\r
2696 EgrDbSetup.bEnableEgrDb = true; //Enable Ingress DB\r
2697 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol) EgrDbSetup.PmControl = AIF2FL_DB_AXC_TOKEN_FIFO;//for normal packet performance\r
2698 else EgrDbSetup.PmControl = AIF2FL_DB_PM_TOKEN_FIFO;//for normal packet performance\r
2699 z = first_link; //track to which link this channel corresponds\r
2700 baseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0;\r
2701 for (i = 0; i < max_channel_pe; i++)//for channel 0,...to max channels used by all links\r
2702 {\r
2703 if (i >= (hAif->linkConfig[z].firstPeDBCH\r
2704 + hAif->linkConfig[z].numPeAxC)) {\r
2705 do {\r
2706 z++;\r
2707 } while ((0 == hAif->linkConfig[z].linkEnable));\r
2708 }\r
2709 EgrDbSetup.bEnableChannel[i] = true; //Enable 4 Egress DB channel\r
2710 EgrDbSetup.EgrDbChannel[i].BaseAddress = baseAddress;\r
2711 baseAddress += 8;\r
2712 EgrDbSetup.EgrDbChannel[i].BufDepth = hAif->AxCconfig[i].egressBufDepth; //Set DB FIFO depth for channel 0\r
2713 EgrDbSetup.EgrDbChannel[i].DataSwap = AIF2FL_DB_WORD_SWAP; //DL\r
2714 EgrDbSetup.EgrDbChannel[i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2715 }\r
2716 baseEgr = baseAddress;\r
2717 }\r
2718 }\r
2719 //configure for PS\r
2720 for (i=0; i<AIF_MAX_NUM_LINKS; i++)\r
2721 {\r
2722 if ((hAif->linkConfig[i].psMsgEnable) && (hAif->linkConfig[i].linkEnable)) {\r
2723 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol) {\r
2724 for(j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
2725 {\r
2726 IngrDbSetup.bEnableChannel[124+j] = true; //Enable 4 Ingress DB channel\r
2727 IngrDbSetup.IngrDbChannel[124+j].BaseAddress = baseIngr+(j*8);\r
2728 #ifdef DEVICE_LE\r
2729 IngrDbSetup.IngrDbChannel[124+j].DataSwap = AIF2FL_DB_BYTE_SWAP;//AIF2FL_DB_WORD_SWAP; //No swap\r
2730 #else \r
2731 IngrDbSetup.IngrDbChannel[124+j].DataSwap = AIF2FL_DB_NO_SWAP;//AIF2FL_DB_WORD_SWAP; //No swap\r
2732 #endif \r
2733 IngrDbSetup.IngrDbChannel[124+j].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2734 }\r
2735 } else { // OBSAI\r
2736 IngrDbSetup.bEnableChannel[122+i] = true; //Enable 4 Ingress DB channel\r
2737 IngrDbSetup.IngrDbChannel[122+i].BaseAddress = baseIngr;\r
2738 IngrDbSetup.IngrDbChannel[122+i].DataSwap = AIF2FL_DB_BYTE_SWAP; //AIF2FL_DB_WORD_SWAP; //No swap\r
2739 IngrDbSetup.IngrDbChannel[122+i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2740 }\r
2741 }\r
2742 }\r
2743 \r
2744 //configure for PS\r
2745 for (i=0; i<AIF_MAX_NUM_LINKS; i++)\r
2746 {\r
2747 if ((hAif->linkConfig[i].psMsgEnable) && (hAif->linkConfig[i].linkEnable)) {\r
2748 if (AIF2FL_LINK_PROTOCOL_CPRI==hAif->protocol) {\r
2749 for(j=0;j<AIF2_CPRI_MAX_CW_SUBSTREAM;j++)\r
2750 {\r
2751 EgrDbSetup.bEnableChannel[124+j] = true; //Enable 4 Egress DB channel\r
2752 EgrDbSetup.EgrDbChannel[124+j].BaseAddress = baseEgr+(j*8);\r
2753 #ifdef DEVICE_LE\r
2754 EgrDbSetup.EgrDbChannel[124+j].DataSwap = AIF2FL_DB_BYTE_SWAP;//AIF2FL_DB_WORD_SWAP; //No swap\r
2755 #else\r
2756 EgrDbSetup.EgrDbChannel[124+j].DataSwap = AIF2FL_DB_NO_SWAP;//AIF2FL_DB_WORD_SWAP; //No swap\r
2757 #endif \r
2758 EgrDbSetup.EgrDbChannel[124+j].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2759 }\r
2760 } else { // OBSAI\r
2761 EgrDbSetup.bEnableChannel[122+i] = true; //Enable 4 Egress DB channel\r
2762 EgrDbSetup.EgrDbChannel[122+i].BaseAddress = baseEgr;\r
2763 EgrDbSetup.EgrDbChannel[122+i].DataSwap = AIF2FL_DB_BYTE_SWAP;//AIF2FL_DB_WORD_SWAP; //No swap\r
2764 EgrDbSetup.EgrDbChannel[122+i].IQOrder = AIF2FL_DB_IQ_NO_SWAP; //No Order change\r
2765 }\r
2766 }\r
2767 }\r
2768 \r
2769 // AD Common\r
2770 AdCommonSetup.IngrGlobalEnable = true;\r
2771 AdCommonSetup.EgrGlobalEnable = true;\r
2772 AdCommonSetup.FailMode = AIF2FL_AD_DROP;//drop fail packet\r
2773 AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512\r
2774 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
2775 {\r
2776 //DIO setup\r
2777 AdCommonSetup.IngrGlobalDioEnable = true;\r
2778 AdCommonSetup.EgrGlobalDioEnable = true;\r
2779 AdCommonSetup.IngrPriority = AIF2FL_AD_DIO_PRI;\r
2780 AdCommonSetup.EgrPriority = AIF2FL_AD_AXC_PRI;\r
2781 } else {\r
2782 // PKTDMA setup\r
2783 AdCommonSetup.IngrGlobalDioEnable = false;\r
2784 AdCommonSetup.EgrGlobalDioEnable = false;\r
2785 AdCommonSetup.IngrPriority = AIF2FL_AD_PKT_PRI;\r
2786 if ((hAif->mode == AIF_GENERICPACKET_MODE) )\r
2787 AdCommonSetup.EgrPriority = AIF2FL_AD_NON_AXC_PRI;\r
2788 else AdCommonSetup.EgrPriority = AIF2FL_AD_AXC_PRI;\r
2789 }\r
2790 \r
2791 // AD DIO engine setup\r
2792 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
2793 {\r
2794 for (i=0; i<AIF2_MAX_NUM_DIO_ENGINE; i++)\r
2795 {\r
2796 if (hAif->dioConfig[i].numLink != 0)\r
2797 {\r
2798 if (hAif->dioConfig[i].mode == LTE)\r
2799 {\r
2800 if (hAif->dioConfig[i].numPdDBCH) AdDioSetup.IngrDioEngineEnable[i] = true;\r
2801 AdDioSetup.IngrDioEngine[i].BcnTableSelect = AIF2FL_AD_DIO_BCN_TABLE_0;\r
2802 AdDioSetup.IngrDioEngine[i].NumAxC = hAif->dioConfig[i].numPdDBCH - 1;\r
2803 AdDioSetup.IngrDioEngine[i].DmaNumBlock = hAif->dioConfig[i].inNumBlock - 1; //block wrap2 value (n-1)\r
2804 AdDioSetup.IngrDioEngine[i].NumQuadWord = AIF2FL_AD_4QUAD;//Use 1 QW per channel in DL for ABT\r
2805 AdDioSetup.IngrDioEngine[i].bEnEgressRsaFormat = false;\r
2806 AdDioSetup.IngrDioEngine[i].DmaBlockAddrStride = 4;\r
2807 AdDioSetup.IngrDioEngine[i].bEnDmaChannel = true; //Enable Dma channel\r
2808 AdDioSetup.IngrDioEngine[i].DmaBurstLen = AIF2FL_AD_4QUAD;//1 max QW burst per one transfer\r
2809 AdDioSetup.IngrDioEngine[i].DmaBaseAddr = (uint32_t)hAif->dioConfig[i].in;\r
2810 AdDioSetup.IngrDioEngine[i].DmaBurstAddrStride = 4 * hAif->dioConfig[i].inNumBlock;//DMA burst stride to 1 (wrap1)if 1QW and 4 for 4QW for DMABurstLen\r
2811 for (k = 0, j = hAif->dioConfig[i].offsetPdDBCH; j < (hAif->dioConfig[i].numPdDBCH + hAif->dioConfig[i].offsetPdDBCH); j++, k++)\r
2812 {\r
2813 AdDioSetup.IngrDioEngine[i].DBCN[k] = j; //set ingress table DBCN for channel 0\r
2814 }\r
2815 \r
2816 if (hAif->linkConfig[i].RtEnabled==0)\r
2817 {\r
2818 if (hAif->dioConfig[i].numPeDBCH) AdDioSetup.EgrDioEngineEnable[i] = true;\r
2819 AdDioSetup.EgrDioEngine[i].BcnTableSelect = AIF2FL_AD_DIO_BCN_TABLE_0;\r
2820 AdDioSetup.EgrDioEngine[i].NumAxC = hAif->dioConfig[i].numPeDBCH - 1;\r
2821 AdDioSetup.EgrDioEngine[i].DmaNumBlock = hAif->dioConfig[i].outNumBlock - 1; //block wrap2 value (n-1)\r
2822 AdDioSetup.EgrDioEngine[i].NumQuadWord = AIF2FL_AD_4QUAD;//Use 1 QW per channel in DL for ABT\r
2823 AdDioSetup.EgrDioEngine[i].bEnEgressRsaFormat = false;\r
2824 AdDioSetup.EgrDioEngine[i].DmaBlockAddrStride = 4;\r
2825 AdDioSetup.EgrDioEngine[i].bEnDmaChannel = true; //Enable Dma channel\r
2826 AdDioSetup.EgrDioEngine[i].DmaBurstLen = AIF2FL_AD_4QUAD;//1 max QW burst per one transfer\r
2827 AdDioSetup.EgrDioEngine[i].DmaBaseAddr = (uint32_t)hAif->dioConfig[i].out;\r
2828 AdDioSetup.EgrDioEngine[i].DmaBurstAddrStride = 4 *hAif->dioConfig[i].outNumBlock;//DMA burst stride to 1 (wrap1)if 1QW and 4 for 4QW for DMABurstLen\r
2829 for (k = 0, j = hAif->dioConfig[i].offsetPeDBCH; j < (hAif->dioConfig[i].numPeDBCH + hAif->dioConfig[i].offsetPeDBCH); j++, k++)\r
2830 {\r
2831 AdDioSetup.EgrDioEngine[i].DBCN[k] = j; //set ingress table DBCN for channel 0\r
2832 }\r
2833 }\r
2834 } else {\r
2835 //DIO Ingress-Egress for L2/RSA are engine0\r
2836 if (hAif->dioConfig[i].numPdDBCH) AdDioSetup.IngrDioEngineEnable[i] = true;\r
2837 AdDioSetup.IngrDioEngine[i].BcnTableSelect = AIF2FL_AD_DIO_BCN_TABLE_0;\r
2838 AdDioSetup.IngrDioEngine[i].NumAxC = hAif->dioConfig[i].numPdDBCH - 1;\r
2839 AdDioSetup.IngrDioEngine[i].DmaNumBlock = hAif->dioConfig[i].inNumBlock - 1; //block wrap2 value (n-1)\r
2840 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
2841 {\r
2842 AdDioSetup.IngrDioEngine[i].NumQuadWord = AIF2FL_AD_2QUAD;//Use 2 QW per channel in UL\r
2843 AdDioSetup.IngrDioEngine[i].bEnEgressRsaFormat = true;\r
2844 if (hAif->dioConfig[i].usedWithRAC == 0) {\r
2845 AdDioSetup.IngrDioEngine[i].DmaBlockAddrStride = 2 * (hAif->dioConfig[i].numPdDBCH);\r
2846 } else {\r
2847 // The fact that the RAC FE is mapped with a jump of 0x800 every 8 chips with 4 blocks every 32-chip period\r
2848 // -> Block Stride is 0x80\r
2849 // -> Burst Stried is 4\r
2850 AdDioSetup.IngrDioEngine[i].DmaBlockAddrStride = 0x80;\r
2851 }\r
2852 } else {\r
2853 AdDioSetup.IngrDioEngine[i].NumQuadWord = AIF2FL_AD_1QUAD;//Use 1 QW per channel in DL for ABT\r
2854 AdDioSetup.IngrDioEngine[i].bEnEgressRsaFormat = false;\r
2855 AdDioSetup.IngrDioEngine[i].DmaBlockAddrStride = hAif->dioConfig[i].numPdDBCH;\r
2856 }\r
2857 AdDioSetup.IngrDioEngine[i].bEnDmaChannel = true; //Enable Dma channel\r
2858 AdDioSetup.IngrDioEngine[i].DmaBurstLen = AIF2FL_AD_4QUAD;//1 max QW burst per one transfer\r
2859 AdDioSetup.IngrDioEngine[i].DmaBaseAddr = (uint32_t)hAif->dioConfig[i].in;\r
2860 AdDioSetup.IngrDioEngine[i].DmaBurstAddrStride = 4;//DMA burst stride to 1 (wrap1)if 1QW and 4 for 4QW for DMABurstLen\r
2861 for (k = 0, j = hAif->dioConfig[i].offsetPdDBCH; j < (hAif->dioConfig[i].numPdDBCH + hAif->dioConfig[i].offsetPdDBCH); j++, k++)\r
2862 {\r
2863 AdDioSetup.IngrDioEngine[i].DBCN[k] = j; //set ingress table DBCN for channel 0\r
2864 }\r
2865 \r
2866 if (hAif->linkConfig[i].RtEnabled==0)\r
2867 {\r
2868 if (hAif->dioConfig[i].numPeDBCH) AdDioSetup.EgrDioEngineEnable[i] = true;\r
2869 AdDioSetup.EgrDioEngine[i].BcnTableSelect = AIF2FL_AD_DIO_BCN_TABLE_0;\r
2870 AdDioSetup.EgrDioEngine[i].NumAxC = hAif->dioConfig[i].numPeDBCH - 1;\r
2871 AdDioSetup.EgrDioEngine[i].DmaNumBlock = hAif->dioConfig[i].outNumBlock - 1; //block wrap2 value (n-1)\r
2872 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].outboundDataType==AIF2FL_LINK_DATA_TYPE_RSA)\r
2873 {\r
2874 AdDioSetup.EgrDioEngine[i].NumQuadWord = AIF2FL_AD_2QUAD;//Use 2 QW per channel in UL\r
2875 AdDioSetup.EgrDioEngine[i].bEnEgressRsaFormat = true;\r
2876 AdDioSetup.EgrDioEngine[i].DmaBlockAddrStride = 2 * (hAif->dioConfig[i].numPeDBCH);\r
2877 } else {\r
2878 AdDioSetup.EgrDioEngine[i].NumQuadWord = AIF2FL_AD_1QUAD;//Use 1 QW per channel in DL for ABT\r
2879 AdDioSetup.EgrDioEngine[i].bEnEgressRsaFormat = false;\r
2880 AdDioSetup.EgrDioEngine[i].DmaBlockAddrStride = hAif->dioConfig[i].numPeDBCH;\r
2881 }\r
2882 AdDioSetup.EgrDioEngine[i].bEnDmaChannel = true; //Enable Dma channel\r
2883 AdDioSetup.EgrDioEngine[i].DmaBurstLen = AIF2FL_AD_4QUAD;//1 max QW burst per one transfer\r
2884 AdDioSetup.EgrDioEngine[i].DmaBaseAddr = (uint32_t)hAif->dioConfig[i].out;\r
2885 AdDioSetup.EgrDioEngine[i].DmaBurstAddrStride = 4;//DMA burst stride to 1 (wrap1)if 1QW and 4 for 4QW for DMABurstLen\r
2886 for (k = 0, j = hAif->dioConfig[i].offsetPeDBCH; j < (hAif->dioConfig[i].numPeDBCH + hAif->dioConfig[i].offsetPeDBCH); j++, k++)\r
2887 {\r
2888 AdDioSetup.EgrDioEngine[i].DBCN[k] = j; //set ingress table DBCN for channel 0\r
2889 }\r
2890 }\r
2891 }\r
2892 }\r
2893 if (hAif->dioConfig[i].duplicateOnDioEng2)\r
2894 {\r
2895 AdDioSetup.IngrDioEngineEnable[2]=AdDioSetup.IngrDioEngineEnable[i];\r
2896 AdDioSetup.IngrDioEngine[2]=AdDioSetup.IngrDioEngine[i];\r
2897 AdDioSetup.EgrDioEngineEnable[2]=AdDioSetup.EgrDioEngineEnable[i];\r
2898 AdDioSetup.EgrDioEngine[2]=AdDioSetup.EgrDioEngine[i];\r
2899 AdDioSetup.IngrDioEngine[2].DmaBaseAddr = (uint32_t)hAif->dioConfig[2].in;\r
2900 }\r
2901 }\r
2902 }\r
2903 \r
2904 //AT Common setup\r
2905 if (hAif->aif2TimerSyncSource != AIF2FL_PHYT_CMP_SYNC) {\r
2906 AtCommonSetup.PhySyncSel = hAif->aif2TimerSyncSource;\r
2907 } else {\r
2908 AtCommonSetup.PhySyncSel = AIF2FL_CHIP_INPUT_SYNC;\r
2909 }\r
2910 if (hAif->phytCompValue)\r
2911 {\r
2912 AtCommonSetup.RadSyncSel = AIF2FL_PHYT_CMP_SYNC;\r
2913 AtCommonSetup.PhytCompValue = hAif->phytCompValue;\r
2914 \r
2915 } else {\r
2916 AtCommonSetup.RadSyncSel = hAif->aif2TimerSyncSource;\r
2917 AtCommonSetup.PhytCompValue = 0;\r
2918 }\r
2919 \r
2920 AtCommonSetup.AutoResyncMode = hAif->autoResyncMode;\r
2921 AtCommonSetup.SyncMode = AIF2FL_NON_RP1_MODE; // same with AIF and Fsync\r
2922 AtCommonSetup.CrcMode = AIF2FL_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test same with AIF and Fsync\r
2923 \r
2924 if ((hAif->mode == AIF_WCDMA_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
2925 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
2926 AtCommonSetup.WcdmaDivTC = 79; //80 is default divide value for WCDMA 307.2/3.84Mhz\r
2927 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = AIF2_CLOCK_COUNT_TC_WCDMA_FDD;//set WCDMA Clock count TC to 204799\r
2928 }\r
2929 else {\r
2930 AtCommonSetup.WcdmaDivTC = 63; //64 is default divide value for WCDMA CPRI\r
2931 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = AIF2_CLOCK_COUNT_TC_WCDMA_FDD_CPRI;\r
2932 }\r
2933 }\r
2934 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)) {\r
2935 if (hAif->radTimerConfig[0].userSpecified == false) {\r
2936 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
2937 if (lte1_4 == 1)\r
2938 {\r
2939 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = (AIF2_CLOCK_COUNT_TC_OBSAI+1)/2-1;\r
2940 } else {\r
2941 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = (AIF2_CLOCK_COUNT_TC_FIRST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2942 AtCommonSetup.AtTerminalCount.RadClockCountTc[1] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2943 AtCommonSetup.AtTerminalCount.RadClockCountTc[2] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2944 AtCommonSetup.AtTerminalCount.RadClockCountTc[3] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2945 AtCommonSetup.AtTerminalCount.RadClockCountTc[4] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2946 AtCommonSetup.AtTerminalCount.RadClockCountTc[5] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2947 AtCommonSetup.AtTerminalCount.RadClockCountTc[6] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI-1);//set Clock count TC for OBSAI\r
2948 }\r
2949 } else {\r
2950 if (lte1_4 == 1)\r
2951 {\r
2952 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = (AIF2_CLOCK_COUNT_TC_CPRI+1)/2-1;\r
2953 } else {\r
2954 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = (AIF2_CLOCK_COUNT_TC_FIRST_OFDM_SYM_CPRI-1);//set Clock count TC for CPRI\r
2955 AtCommonSetup.AtTerminalCount.RadClockCountTc[1] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2956 AtCommonSetup.AtTerminalCount.RadClockCountTc[2] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2957 AtCommonSetup.AtTerminalCount.RadClockCountTc[3] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2958 AtCommonSetup.AtTerminalCount.RadClockCountTc[4] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2959 AtCommonSetup.AtTerminalCount.RadClockCountTc[5] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2960 AtCommonSetup.AtTerminalCount.RadClockCountTc[6] = (AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI-1);//set Clock count TC forCPRI\r
2961 }\r
2962 }\r
2963 } else {\r
2964 if (hAif->radTimerConfig[0].lte.cpType == AIF2_LTE_CPTYPE_NORMAL) {\r
2965 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
2966 clockCountTc[0] = AIF2_CLOCK_COUNT_TC_FIRST_OFDM_SYM_OBSAI;//set Clock count TC for OBSAI\r
2967 for (i=1;i<AIF2_LTE_SYMBOL_NUM;i++) {\r
2968 clockCountTc[i] = AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_OBSAI;//set Clock count TC for OBSAI\r
2969 }\r
2970 } else {\r
2971 clockCountTc[0] = AIF2_CLOCK_COUNT_TC_FIRST_OFDM_SYM_CPRI;//set Clock count TC for OBSAI\r
2972 for (i=1;i<AIF2_LTE_SYMBOL_NUM;i++) {\r
2973 clockCountTc[i] = AIF2_CLOCK_COUNT_TC_REST_OFDM_SYM_CPRI;//set Clock count TC for OBSAI\r
2974 }\r
2975 }\r
2976 k = 0;\r
2977 for (i=0;i<AIF2_LTE_SYMBOL_NUM;i++) {\r
2978 for (j=0;j<hAif->radTimerConfig[0].lte.numSymbolsForSymbolStrobe;j++) {\r
2979 AtCommonSetup.AtTerminalCount.RadClockCountTc[i] += clockCountTc[k++];\r
2980 if (k==AIF2_LTE_SYMBOL_NUM) k=0;\r
2981 }\r
2982 AtCommonSetup.AtTerminalCount.RadClockCountTc[i] -= 1;\r
2983 }\r
2984 } else { // Extended CP\r
2985 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
2986 for (i=0;i<AIF2_LTE_SYMBOL_NUM_EXT_CP;i++) {\r
2987 AtCommonSetup.AtTerminalCount.RadClockCountTc[i] = (hAif->radTimerConfig[0].lte.numSymbolsForSymbolStrobe*AIF2_CLOCK_COUNT_TC_EXTCP_OFDM_SYM_OBSAI)-1;//set Clock count TC for OBSAI\r
2988 }\r
2989 } else {\r
2990 for (i=0;i<AIF2_LTE_SYMBOL_NUM_EXT_CP;i++) {\r
2991 AtCommonSetup.AtTerminalCount.RadClockCountTc[i] = (hAif->radTimerConfig[0].lte.numSymbolsForSymbolStrobe*AIF2_CLOCK_COUNT_TC_EXTCP_OFDM_SYM_CPRI)-1;//set Clock count TC for OBSAI\r
2992 }\r
2993 }\r
2994 }\r
2995 }\r
2996 }\r
2997 \r
2998 if ((hAif->mode == AIF_GENERICPACKET_MODE)){\r
2999 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
3000 AtCommonSetup.PhytCompValue = 0;\r
3001 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = AIF2_CLOCK_COUNT_TC_OBSAI;//CLOCK_COUNT_TC_LTE_FDD;//set Clock count TC to 307199\r
3002 } else {\r
3003 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = AIF2_CLOCK_COUNT_TC_CPRI;//set Clock count TC for CPRI\r
3004 }\r
3005 }\r
3006 AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit;\r
3007 PhyTimerInit.ClockNum = 0;\r
3008 PhyTimerInit.FrameLsbNum = 0;\r
3009 PhyTimerInit.FrameMsbNum = 0;\r
3010 \r
3011 AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit;\r
3012 if (hAif->radTimerConfig[0].userSpecified == false) {\r
3013 if (hAif->aif2TimerSyncSource != AIF2FL_PHYT_CMP_SYNC) {\r
3014 RadTimerInit.ClockNum = 0;\r
3015 } else {\r
3016 RadTimerInit.ClockNum = 2;\r
3017 }\r
3018 RadTimerInit.SymbolNum = 0;\r
3019 RadTimerInit.FrameLsbNum = 0;\r
3020 RadTimerInit.FrameMsbNum = 0;\r
3021 } else {\r
3022 RadTimerInit.ClockNum = hAif->radTimerConfig[0].initClockNum;\r
3023 RadTimerInit.SymbolNum = hAif->radTimerConfig[0].initSymbolNum;\r
3024 RadTimerInit.FrameLsbNum = hAif->radTimerConfig[0].initFrameLsbNum;\r
3025 RadTimerInit.FrameMsbNum = hAif->radTimerConfig[0].initFrameMsbNum;\r
3026 }\r
3027 \r
3028 AtCommonSetup.AtInit.pUlRadTimerInit = &UlRadTimerInit;\r
3029 UlRadTimerInit.SymbolNum = 14; // WCDMA same with AIF and Fsync\r
3030 UlRadTimerInit.FrameLsbNum = 4095;\r
3031 UlRadTimerInit.FrameMsbNum = 0;\r
3032 UlRadTimerInit.FcbMinusOne = 1; // Applies to RP1 interface only\r
3033 //full symbol clock value - first ingress DIO event time (as for RAC processing)\r
3034 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
3035 UlRadTimerInit.ClockNum = 204800 - ((8*80) + hAif->linkConfig[hAif->dioConfig[0].firstLink].piMin + 20 + 180);\r
3036 } else {\r
3037 UlRadTimerInit.ClockNum = 163840 - ((8*64) + hAif->linkConfig[hAif->dioConfig[0].firstLink].piMin + 20 + 160);\r
3038 }\r
3039 \r
3040 AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc;\r
3041 PhyTimerTc.FrameLsbNum = AIF2_FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095\r
3042 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
3043 PhyTimerTc.ClockNum = AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER; //set phy clock TC to 3071999=10ms\r
3044 } else {\r
3045 PhyTimerTc.ClockNum = AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER; //set phy clock TC to 2457600 - 1\r
3046 }\r
3047 \r
3048 AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc;\r
3049 if ((hAif->mode == AIF_WCDMA_MODE) || (hAif->mode == AIF_LTE_WCDMA_MODE)) {\r
3050 RadTimerTc.FrameLsbNum = AIF2_FRAME_COUNT_TC_WCDMA_FDD;//set WCDMA Frame TC to 4095\r
3051 RadTimerTc.SymbolNum = AIF2_SLOT_COUNT_TC_WCDMA_FDD; //set WCDMA Slot TC to 14\r
3052 }\r
3053 if ((hAif->mode == AIF_LTE_FDD_MODE) || (hAif->mode == AIF_LTE_TDD_MODE)) {\r
3054 if (hAif->radTimerConfig[0].userSpecified == false) {\r
3055 RadTimerTc.FrameLsbNum = AIF2_FRAME_COUNT_TC_WCDMA_FDD;//set LTE Frame TC to 4095
3056 if (lte1_4 == 1){\r
3057 //RadTimerTc.ClockNum = AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;\r
3058 RadTimerTc.SymbolNum = 20 -1; //set LTE 20 slot in 10ms\r
3059 RadTimerTc.LutIndexNum = 0; //set LTE LutIndex TC\r
3060 } else {\r
3061 /*if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3062 RadTimerTc.ClockNum = AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;\r
3063 else\r
3064 RadTimerTc.ClockNum = AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;*/
3065 RadTimerTc.SymbolNum = 140 -1; //set LTE 10 subframes in 10ms\r
3066 RadTimerTc.LutIndexNum = AIF2_LTE_SYMBOL_NUM - 1; //set LTE LutIndex TC\r
3067 }\r
3068 } else {\r
3069 // user defined init values\r
3070 RadTimerTc.FrameLsbNum = hAif->radTimerConfig[0].frameTerminalCount - 1;\r
3071 if (hAif->radTimerConfig[0].lte.cpType == AIF2_LTE_CPTYPE_NORMAL) {\r
3072 RadTimerTc.LutIndexNum = AIF2_LTE_SYMBOL_NUM - 1;\r
3073 } else {\r
3074 RadTimerTc.LutIndexNum = AIF2_LTE_SYMBOL_NUM_EXT_CP - 1;\r
3075 }\r
3076 RadTimerTc.SymbolNum = hAif->radTimerConfig[0].lte.numSymbolStrobesForFrameStrobe - 1;\r
3077 }\r
3078 }\r
3079 if ((hAif->mode == AIF_GENERICPACKET_MODE)) {\r
3080 RadTimerTc.FrameLsbNum = AIF2_FRAME_COUNT_TC_WCDMA_FDD;//set Frame TC to 4095\r
3081 RadTimerTc.SymbolNum = 9; //set Symbol TC to 9 -- need to set a definition in AIF_defs.h\r
3082 RadTimerTc.LutIndexNum = 0; //set LutIndex TC to 0\r
3083 }\r
3084 \r
3085 // Event 7 - 10 ms tick from PHYT\r
3086 AtEventSetup.AtRadEvent[7].EventSelect = AIF2FL_EVENT_7;\r
3087 AtEventSetup.AtRadEvent[7].EventOffset = 0;\r
3088 if ((hAif->mode == AIF_GENERICPACKET_MODE)) AtEventSetup.AtRadEvent[7].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3089 else AtEventSetup.AtRadEvent[7].EvtStrobeSel = AIF2FL_PHYT_FRAME;\r
3090 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3091 AtEventSetup.AtRadEvent[7].EventModulo = AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;\r
3092 else\r
3093 AtEventSetup.AtRadEvent[7].EventModulo = AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER + 1;\r
3094 AtEventSetup.AtRadEvent[7].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3095 AtEventSetup.AtRadEvent[7].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3096 AtEventSetup.bEnableRadEvent[7] = true;//Enable Event\r
3097 \r
3098 if (hAif->mode == AIF_WCDMA_MODE)\r
3099 {\r
3100 //AT Event setup for generating 4 chip trigger for TAC (Event 8 is specified for this purpose) WCDMA OBSAI DL\r
3101 AtEventSetup.AtRadEvent[8].EventSelect = AIF2FL_EVENT_8;\r
3102 AtEventSetup.AtRadEvent[8].EventOffset = 0;\r
3103 AtEventSetup.AtRadEvent[8].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3104 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3105 AtEventSetup.AtRadEvent[8].EventModulo = 319; //set Modulus count (WCDMA 4 chip time)\r
3106 else\r
3107 AtEventSetup.AtRadEvent[8].EventModulo = 255; //set Modulus count (WCDMA 4 chip time)\r
3108 AtEventSetup.AtRadEvent[8].EventMaskLsb = 0xFFFFFFFF;\r
3109 AtEventSetup.AtRadEvent[8].EventMaskMsb = 0xFFFFFFFF;\r
3110 AtEventSetup.bEnableRadEvent[8] = true;//Enable Event\r
3111 \r
3112 //AT Event setup to generate 32 chip trigger for RAC_A (Event 9) WCDMA UL\r
3113 AtEventSetup.AtRadEvent[9].EventSelect = AIF2FL_EVENT_9;\r
3114 AtEventSetup.AtRadEvent[9].EvtStrobeSel = AIF2FL_ULRADT_FRAME; //First Ul frame event will occurr after 4480 clocks\r
3115 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
3116 AtEventSetup.AtRadEvent[9].EventModulo = 2559; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3117 AtEventSetup.AtRadEvent[9].EventOffset = 31 * 80;\r
3118 } else {\r
3119 AtEventSetup.AtRadEvent[9].EventModulo = 2047; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3120 AtEventSetup.AtRadEvent[9].EventOffset = 31 * 64;\r
3121 }\r
3122 AtEventSetup.AtRadEvent[9].EventMaskLsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3123 AtEventSetup.AtRadEvent[9].EventMaskMsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3124 AtEventSetup.bEnableRadEvent[9] = true;//Enable Event*/\r
3125 \r
3126 //AT Event setup to generate 32 chip trigger for RAC_B (Event 10) WCDMA UL\r
3127 AtEventSetup.AtRadEvent[10].EventSelect = AIF2FL_EVENT_10;\r
3128 AtEventSetup.AtRadEvent[10].EventOffset = 0;\r
3129 AtEventSetup.AtRadEvent[10].EvtStrobeSel = AIF2FL_ULRADT_FRAME;\r
3130 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
3131 AtEventSetup.AtRadEvent[10].EventModulo = 2559; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3132 AtEventSetup.AtRadEvent[10].EventOffset = 31 * 80;\r
3133 } else {\r
3134 AtEventSetup.AtRadEvent[10].EventModulo = 2047; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3135 AtEventSetup.AtRadEvent[10].EventOffset = 31 * 64;\r
3136 }\r
3137 AtEventSetup.AtRadEvent[10].EventMaskLsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3138 AtEventSetup.AtRadEvent[10].EventMaskMsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3139 AtEventSetup.bEnableRadEvent[10] = true;//Enable Event*/\r
3140 #ifdef K2 // support K-II devices with up to 4 RAC\r
3141 //AT Event setup to generate 32 chip trigger for RAC_C (Event 11) WCDMA UL\r
3142 AtEventSetup.AtRadEvent[11].EventSelect = AIF2FL_EVENT_11;\r
3143 AtEventSetup.AtRadEvent[11].EvtStrobeSel = AIF2FL_ULRADT_FRAME; //First Ul frame event will occurr after 4480 clocks\r
3144 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
3145 AtEventSetup.AtRadEvent[11].EventModulo = 2559; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3146 AtEventSetup.AtRadEvent[11].EventOffset = 31 * 80;\r
3147 } else {\r
3148 AtEventSetup.AtRadEvent[11].EventModulo = 2047; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3149 AtEventSetup.AtRadEvent[11].EventOffset = 31 * 64;\r
3150 }\r
3151 AtEventSetup.AtRadEvent[11].EventMaskLsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3152 AtEventSetup.AtRadEvent[11].EventMaskMsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3153 AtEventSetup.bEnableRadEvent[11] = true;//Enable Event*/\r
3154 \r
3155 //AT Event setup to generate 32 chip trigger for RAC_D (Event 12) WCDMA UL\r
3156 AtEventSetup.AtRadEvent[12].EventSelect = AIF2FL_EVENT_12;\r
3157 AtEventSetup.AtRadEvent[12].EventOffset = 0;\r
3158 AtEventSetup.AtRadEvent[12].EvtStrobeSel = AIF2FL_ULRADT_FRAME;\r
3159 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) {\r
3160 AtEventSetup.AtRadEvent[12].EventModulo = 2559; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3161 AtEventSetup.AtRadEvent[12].EventOffset = 31 * 80;\r
3162 } else {\r
3163 AtEventSetup.AtRadEvent[12].EventModulo = 2047; //set Modulus count for event 1 (WCDMA 32 chip time)\r
3164 AtEventSetup.AtRadEvent[12].EventOffset = 31 * 64;\r
3165 }\r
3166 AtEventSetup.AtRadEvent[12].EventMaskLsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3167 AtEventSetup.AtRadEvent[12].EventMaskMsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD\r
3168 AtEventSetup.bEnableRadEvent[12] = true;//Enable Event*/\r
3169 #endif\r
3170 }\r
3171 \r
3172 if (hAif->mode == AIF_LTE_FDD_MODE) {\r
3173 if(lte1_4 == 1)\r
3174 {\r
3175 AtEventSetup.AtRadEvent[5].EventSelect = AIF2FL_EVENT_5;\r
3176 AtEventSetup.AtRadEvent[5].EventOffset = 800;\r
3177 AtEventSetup.AtRadEvent[5].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3178 AtEventSetup.AtRadEvent[5].EventModulo = 122879; //LTE 0.5ms slot time\r
3179 AtEventSetup.AtRadEvent[5].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3180 AtEventSetup.AtRadEvent[5].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3181 AtEventSetup.bEnableRadEvent[5] = true;//Enable Event\r
3182 } else {\r
3183 // event for superpacket post processing with EDMA\r
3184 AtEventSetup.AtRadEvent[0].EventSelect = AIF2FL_EVENT_0;\r
3185 AtEventSetup.AtRadEvent[0].EventOffset = 0;\r
3186 AtEventSetup.AtRadEvent[0].EvtStrobeSel = AIF2FL_ULRADT_FRAME;\r
3187 AtEventSetup.AtRadEvent[0].EventModulo = 0xFFFFFFFF;\r
3188 AtEventSetup.AtRadEvent[0].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3189 AtEventSetup.AtRadEvent[0].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3190 AtEventSetup.bEnableRadEvent[0] = true;//Enable Event\r
3191 \r
3192 // Event for timeSlot event generation\r
3193 AtEventSetup.AtRadEvent[5].EventSelect = AIF2FL_EVENT_5;\r
3194 AtEventSetup.AtRadEvent[5].EventOffset = 800; //98304; //800\r
3195 AtEventSetup.AtRadEvent[5].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3196 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3197 AtEventSetup.AtRadEvent[5].EventModulo = 153599; //LTE 0.5ms slot time\r
3198 else\r
3199 AtEventSetup.AtRadEvent[5].EventModulo = 122879; //LTE 0.5ms slot time\r
3200 AtEventSetup.AtRadEvent[5].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3201 AtEventSetup.AtRadEvent[5].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3202 AtEventSetup.bEnableRadEvent[5] = true;//Enable Event\r
3203 \r
3204 \r
3205 // Event for SubFrame event generation\r
3206 AtEventSetup.AtRadEvent[6].EventSelect = AIF2FL_EVENT_6;\r
3207 AtEventSetup.AtRadEvent[6].EventOffset = 800;\r
3208 //AtEventSetup.AtRadEvent[6].EventOffset = AIF2_CLOCK_COUNT_TC_CPRI - (AIF2_CLOCK_COUNT_TC_CPRI / 10); // TEST\r
3209 AtEventSetup.AtRadEvent[6].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3210 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3211 AtEventSetup.AtRadEvent[6].EventModulo = 307199;//LTE 1ms sub-frame time\r
3212 else\r
3213 AtEventSetup.AtRadEvent[6].EventModulo = AIF2_CLOCK_COUNT_TC_CPRI;//LTE 1ms sub-frame time\r
3214 AtEventSetup.AtRadEvent[6].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3215 AtEventSetup.AtRadEvent[6].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3216 AtEventSetup.bEnableRadEvent[6] = true;//Enable Event\r
3217 }\r
3218 \r
3219 }\r
3220 \r
3221 if (hAif->mode == AIF_LTE_TDD_MODE)\r
3222 {\r
3223 // Event for timeSlot event generation\r
3224 AtEventSetup.AtRadEvent[5].EventSelect = AIF2FL_EVENT_5;\r
3225 AtEventSetup.AtRadEvent[5].EventOffset = 800; //98304; //800\r
3226 AtEventSetup.AtRadEvent[5].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3227 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol)\r
3228 AtEventSetup.AtRadEvent[5].EventModulo = 153599; //LTE 0.5ms slot time\r
3229 else\r
3230 AtEventSetup.AtRadEvent[5].EventModulo = 122879; //LTE 0.5ms slot time\r
3231 AtEventSetup.AtRadEvent[5].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3232 AtEventSetup.AtRadEvent[5].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3233 AtEventSetup.bEnableRadEvent[5] = true;//Enable Event\r
3234 \r
3235 \r
3236 // Event for Symbol event generation\r
3237 AtEventSetup.AtRadEvent[6].EventSelect = AIF2FL_EVENT_6;\r
3238 AtEventSetup.AtRadEvent[6].EventOffset = 800; //3128;\r
3239 AtEventSetup.AtRadEvent[6].EvtStrobeSel = AIF2FL_RADT_SYMBOL;\r
3240 AtEventSetup.AtRadEvent[6].EventModulo = 0x3FFFFF; //17535;//LTE symbol time\r
3241 AtEventSetup.AtRadEvent[6].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3242 AtEventSetup.AtRadEvent[6].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3243 AtEventSetup.bEnableRadEvent[6] = true;//Enable Event\r
3244 }\r
3245 \r
3246 if (hAif->mode == AIF_LTE_WCDMA_MODE)\r
3247 {\r
3248 \r
3249 // Event for timeSlot event generation\r
3250 AtEventSetup.AtRadEvent[5].EventSelect = AIF2FL_EVENT_5;\r
3251 AtEventSetup.AtRadEvent[5].EventOffset = 800; //98304; //800\r
3252 AtEventSetup.AtRadEvent[5].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3253 AtEventSetup.AtRadEvent[5].EventModulo = 122879; //LTE 0.5ms slot time\r
3254 AtEventSetup.AtRadEvent[5].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3255 AtEventSetup.AtRadEvent[5].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3256 AtEventSetup.bEnableRadEvent[5] = true;//Enable Event\r
3257 \r
3258 //Configure and enable AIF2 Event 6 for Edma process for dual mode\r
3259 AtEventSetup.AtRadEvent[6].EventSelect = AIF2FL_EVENT_6;\r
3260 AtEventSetup.AtRadEvent[6].EventOffset = 11000; //98304; //800\r
3261 AtEventSetup.AtRadEvent[6].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3262 AtEventSetup.AtRadEvent[6].EventModulo = 17535; //the longest symbol\r
3263 AtEventSetup.AtRadEvent[6].EventMaskLsb = 0xFFFFFFFF; // only for GSM so NA\r
3264 AtEventSetup.AtRadEvent[6].EventMaskMsb = 0xFFFFFFFF; // only for GSM so NA\r
3265 AtEventSetup.bEnableRadEvent[6] = true;//Enable Event\r
3266 }\r
3267 \r
3268 //AT Event setup for DIO engines\r
3269 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
3270 {\r
3271 for (i=0; i<AIF2_MAX_NUM_DIO_ENGINE; i++)\r
3272 {
3273 if(hAif->dioConfig[i].sampleRate == AIF_SRATE_30P72MHZ)\r
3274 samplePerFrame = 307200;\r
3275 else if(hAif->dioConfig[i].sampleRate == AIF_SRATE_15P36MHZ)\r
3276 samplePerFrame = 153600;\r
3277 else if(hAif->dioConfig[i].sampleRate == AIF_SRATE_7P68MHZ)\r
3278 samplePerFrame = 76800;\r
3279 else\r
3280 samplePerFrame = 38400;\r
3281 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){
3282 if (hAif->dioConfig[i].mode == LTE)\r
3283 {\r
3284 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*16; //2 chip event for LTE\r
3285 // DioFrameEventOffset = 840;//Pi Max(350) + 2 WCDMA chip time(130) + PD delay and fuzzy factors(180)\r
3286 DioFrameEventOffset = EventModulo + hAif->linkConfig[hAif->dioConfig[i].firstLink].piMin + 20 + 180 ;\r
3287 } else {
3288 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA){\r
3289 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*8; //Modulus count for In DIO event (WCDMA 8 chip time) OBSAI
3290 } else {\r
3291 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*4; //Modulus count for In DIO event (WCDMA 4 chip time) OBSAI\r
3292 }\r
3293 //DioFrameEventOffset = EventModulo + hAif->linkConfig[hAif->dioConfig[i].firstLink].pe2Offset + 60 + 20 + 180 ;//1190;//Pi Max + 4 WCDMA chip time + PD delay and fuzzy factors for ingress DMA timing\r
3294 DioFrameEventOffset = EventModulo + hAif->linkConfig[hAif->dioConfig[i].firstLink].piMin + 20 + 180 ;\r
3295 }\r
3296 } else {\r
3297 if (hAif->dioConfig[i].mode == LTE)\r
3298 {\r
3299 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*16; //2 chip event for LTE\r
3300 // DioFrameEventOffset = 660;//Pi Max(350) + 2 WCDMA chip time(130) + PD delay and fuzzy factors(180)\r
3301 DioFrameEventOffset = EventModulo + hAif->linkConfig[hAif->dioConfig[i].firstLink].piMin + 20 + 160 ;\r
3302 } else {
3303 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].inboundDataType==AIF2FL_LINK_DATA_TYPE_RSA){\r
3304 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*8; //(8 chip * 64 CPRI clock -1) set Modulus count for In DIO event 0 (WCDMA 8 chip time)
3305 } else {\r
3306 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*4; //(4 chip * 64 CPRI clock -1) set Modulus count for In DIO event 0 (WCDMA 4 chip time)\r
3307 }\r
3308 DioFrameEventOffset = EventModulo + hAif->linkConfig[hAif->dioConfig[i].firstLink].piMin + 20 + 160 ;\r
3309 }\r
3310 }\r
3311 if (hAif->dioConfig[i].numLink != 0)\r
3312 {\r
3313 AtEventSetup.AtIngrDioEvent[i].EventSelect = (Aif2Fl_AtEventIndex) (AIF2FL_IN_DIO_EVENT_0+i);//(Aif2Fl_AtEventIndex) (AIF2FL_IN_DIO_EVENT_0+i);//Select In DIO Event 1\r
3314 AtEventSetup.AtIngrDioEvent[i].EventOffset = 0;//fine offset value\r
3315 AtEventSetup.AtIngrDioEvent[i].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3316 AtEventSetup.AtIngrDioEvent[i].EventModulo = EventModulo - 1;// set Modulus count for In DIO event (WCDMA 4 chip time)\r
3317 AtEventSetup.AtIngrDioEvent[i].DioFrameEventOffset = DioFrameEventOffset;\r
3318 AtEventSetup.AtIngrDioEvent[i].DioFrameStrobeSel = AIF2FL_RADT_FRAME; //frame event strobe selection\r
3319 if (hAif->dioConfig[i].numPdDBCH) AtEventSetup.bEnableIngrDioEvent[i] = true;//Enable In DIO Event 1 L2/RSA\r
3320 }\r
3321 \r
3322 if (AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol){\r
3323 if (hAif->dioConfig[i].mode == LTE)\r
3324 {\r
3325 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*16; //2 chip event for LTE\r
3326 DioFrameEventOffset = 0;\r
3327 } else {
3328 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].outboundDataType==AIF2FL_LINK_DATA_TYPE_RSA){\r
3329 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*8; //Modulus count for In DIO event (WCDMA 8 chip time) OBSAI
3330 } else {\r
3331 EventModulo = (AIF2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*4; //Modulus count for In DIO event (WCDMA 4 chip time) OBSAI\r
3332 }\r
3333 DioFrameEventOffset = 0;\r
3334 }\r
3335 } else {\r
3336 if (hAif->dioConfig[i].mode == LTE)\r
3337 {\r
3338 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*16; //2 chip event for LTE\r
3339 DioFrameEventOffset = 0;\r
3340 } else {
3341 if (hAif->linkConfig[hAif->dioConfig[i].firstLink].outboundDataType==AIF2FL_LINK_DATA_TYPE_RSA){\r
3342 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*8; //(8 chip * 64 CPRI clock -1) set Modulus count for In DIO event 0 (WCDMA 8 chip time)
3343 } else {\r
3344 EventModulo = (AIF2_CPRI_CLOCK_COUNT_TC_PHY_TIMER+1)/samplePerFrame*4; //(4 chip * 64 CPRI clock -1) set Modulus count for In DIO event 0 (WCDMA 4 chip time)\r
3345 }\r
3346 DioFrameEventOffset = 0;\r
3347 }\r
3348 }\r
3349 \r
3350 if ((hAif->dioConfig[i].numLink != 0) && (hAif->linkConfig[i].RtEnabled==0))\r
3351 {\r
3352 AtEventSetup.AtEgrDioEvent[i].EventSelect = (Aif2Fl_AtEventIndex) (AIF2FL_E_DIO_EVENT_0+i); //Select E DIO Event 1\r
3353 AtEventSetup.AtEgrDioEvent[i].EventOffset = 0;//300;//delay for TAC operation time\r
3354 AtEventSetup.AtEgrDioEvent[i].EvtStrobeSel = AIF2FL_RADT_FRAME;\r
3355 AtEventSetup.AtEgrDioEvent[i].EventModulo = EventModulo - 1;//set Modulus count for E DIO event (WCDMA 4 chip time)\r
3356 AtEventSetup.AtEgrDioEvent[i].DioFrameEventOffset = DioFrameEventOffset;\r
3357 AtEventSetup.AtEgrDioEvent[i].DioFrameStrobeSel = AIF2FL_RADT_FRAME; //frame event strobe selection\r
3358 if (hAif->dioConfig[i].numPeDBCH) AtEventSetup.bEnableEgrDioEvent[i] = true;//Enable E DIO Event 1 L2/RSA\r
3359 //#ifdef K2\r
3360 // AtEventSetup.AtEgrDioEvent[i].EvtStrobeSel = AIF2FL_RADT_SYMBOL;\r
3361 // AtEventSetup.AtEgrDioEvent[i].EventOffset = 230;//fine offset value\r
3362 //#endif\r
3363 }\r
3364 if (hAif->dioConfig[i].duplicateOnDioEng2)\r
3365 {\r
3366 AtEventSetup.AtIngrDioEvent[2]=AtEventSetup.AtIngrDioEvent[i];\r
3367 AtEventSetup.AtEgrDioEvent[2]=AtEventSetup.AtEgrDioEvent[i];\r
3368 AtEventSetup.AtIngrDioEvent[2].EventSelect = (Aif2Fl_AtEventIndex) (AIF2FL_IN_DIO_EVENT_2);\r
3369 AtEventSetup.AtEgrDioEvent[2].EventSelect = (Aif2Fl_AtEventIndex) (AIF2FL_E_DIO_EVENT_2);\r
3370 AtEventSetup.bEnableIngrDioEvent[2] = true;//Enable E DIO Event 1 L2/RSA\r
3371 AtEventSetup.bEnableEgrDioEvent[2] = true;//Enable E DIO Event 1 L2/RSA\r
3372 }\r
3373 }\r
3374 }\r
3375 \r
3376 } //eof AIF_initHw\r
3377 \r
3378 /* Start AIF given this user configuration*/\r
3379 #ifdef K2\r
3380 static void AIF_serdesConfig(AIF_ConfigHandle hAif, uint8_t enableB8, uint8_t enableB4);\r
3381 #endif\r
3382 void AIF_startHw(\r
3383 AIF_ConfigHandle hAif\r
3384 )\r
3385 {\r
3386 uint16_t ctrlArg;\r
3387 int32_t i;\r
3388 #ifndef K2\r
3389 uint16_t response =0;\r
3390 #endif\r
3391 uint8_t serdes_blockb8_used =0;\r
3392 uint8_t serdes_blockb4_used =0;\r
3393 #ifdef _TMS320C6X\r
3394 Cppi_RxChInitCfg dioRxCfg;\r
3395 Cppi_TxChInitCfg dioTxCfg;\r
3396 uint8_t isAllocated;\r
3397 #else\r
3398 // used for DIO mode only\r
3399 CSL_Cppidma_global_configRegs* pktDMAGlobalCfg = (CSL_Cppidma_global_configRegs*)((uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].cfgBase) + 0x14000);\r
3400 CSL_Cppidma_rx_channel_configRegs* pktDMARxCfg = (CSL_Cppidma_rx_channel_configRegs*)((uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].cfgBase) + 0x18000);\r
3401 CSL_Cppidma_tx_channel_configRegs* pktDMATxCfg = (CSL_Cppidma_tx_channel_configRegs*)((uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].cfgBase) + 0x16000);\r
3402 #endif\r
3403 Aif2Fl_Status status;\r
3404 \r
3405 // Identify which SerDes block to use\r
3406 for(i=AIF2FL_LINK_0; i<AIF2FL_LINK_4; i++)\r
3407 {\r
3408 // moved to link setup\r
3409 if(1==hAif->linkConfig[i].linkEnable) serdes_blockb8_used=1;\r
3410 }\r
3411 \r
3412 for(i=AIF2FL_LINK_4; i<(AIF2FL_LINK_5 + 1); i++)\r
3413 {\r
3414 // moved to link setup\r
3415 if(1==hAif->linkConfig[i].linkEnable) serdes_blockb4_used=1;\r
3416 }\r
3417 #ifdef K2\r
3418 AIF_serdesConfig(hAif, serdes_blockb8_used, serdes_blockb4_used);\r
3419 #endif \r
3420 \r
3421 /****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/\r
3422 status = Aif2Fl_hwSetup(hAif->hFl, hAif->hAif2Setup);\r
3423 \r
3424 if(status != AIF2FL_SOK)\r
3425 Aif2_osalLog( "hwSetup structure is not initialized \n");\r
3426 \r
3427 ctrlArg = true;\r
3428 for(i= 0; i< AIF_MAX_NUM_LINKS; i++)\r
3429 {\r
3430 if(1==hAif->linkConfig[i].linkEnable)\r
3431 {\r
3432 \r
3433 hAif->hFl->arg_link = (Aif2Fl_LinkIndex)i;\r
3434 #ifndef K2\r
3435 if (( serdes_blockb8_used ==1)&& (i<4)) while(response == 0)\r
3436 { // wait until SD PLL is locked\r
3437 if(AIF2FL_SOK != Aif2Fl_getHwStatus(hAif->hFl, AIF2FL_QUERY_SD_B8_PLL_LOCK, (void *)&response))\r
3438 Aif2_osalLog ("unable to get Hw status \n");\r
3439 }\r
3440 response = 0;\r
3441 if (( serdes_blockb4_used ==1)&& (i>=4)) while(response == 0) \r
3442 {\r
3443 if( AIF2FL_SOK != Aif2Fl_getHwStatus(hAif->hFl, AIF2FL_QUERY_SD_B4_PLL_LOCK, (void *)&response))\r
3444 Aif2_osalLog ("unable to get Hw status \n");\r
3445 }\r
3446 \r
3447 if (hAif->linkConfig[i].comType == AIF2_LOOPBACK) { //setup links for internal loopback mode\r
3448 ctrlArg = true;\r
3449 if (AIF2FL_SOK != Aif2Fl_hwControl(hAif->hFl, AIF2FL_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg))\r
3450 Aif2_osalLog ("aif2 enable link loopback fail \n");\r
3451 }\r
3452 else {\r
3453 ctrlArg = false;\r
3454 if (AIF2FL_SOK != Aif2Fl_hwControl(hAif->hFl, AIF2FL_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg))\r
3455 Aif2_osalLog ("aif2 disable link loopback fail \n");\r
3456 }\r
3457 #endif\r
3458 ctrlArg = true;\r
3459 if (AIF2FL_SOK != Aif2Fl_hwControl(hAif->hFl, AIF2FL_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg))\r
3460 Aif2_osalLog ("aif2 enable Tx link fail \n");\r
3461 if (AIF2FL_SOK != Aif2Fl_hwControl(hAif->hFl, AIF2FL_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg))\r
3462 Aif2_osalLog ("aif2 enable Rx link fail \n");\r
3463 }\r
3464 } \r
3465 \r
3466 // Disable loopback in PKT DMA (used also for DIO mode) - done in AIF_initPktDma()\r
3467 if (hAif->pktdmaOrDioEngine == AIF2FL_DIO)\r
3468 {\r
3469 #ifdef _TMS320C6X\r
3470 // Enable channel 128 for DIO mode\r
3471 // enable Rx and Tx for DIO\r
3472 memset(&dioRxCfg, 0, sizeof(dioRxCfg));\r
3473 dioRxCfg.channelNum = 128;\r
3474 dioRxCfg.rxEnable = Cppi_ChState_CHANNEL_DISABLE;\r
3475 hAif->pktDmaConfig.dioRxChAxC = Cppi_rxChannelOpen(hAif->pktDmaConfig.hCppi, &dioRxCfg, &isAllocated);\r
3476 if (hAif->pktDmaConfig.dioRxChAxC == NULL)\r
3477 {\r
3478 Aif2_osalLog("Error: Opening AIF2 Rx channel %d failed\n", dioRxCfg.channelNum);\r
3479 }\r
3480 memset(&dioTxCfg, 0, sizeof(dioTxCfg));\r
3481 dioTxCfg.channelNum = 128;\r
3482 dioTxCfg.txEnable = Cppi_ChState_CHANNEL_DISABLE;\r
3483 hAif->pktDmaConfig.dioTxChAxC = Cppi_txChannelOpen(hAif->pktDmaConfig.hCppi, &dioTxCfg, &isAllocated);\r
3484 if (hAif->pktDmaConfig.dioTxChAxC == NULL)\r
3485 {\r
3486 Aif2_osalLog("Error: Opening AIF2 Tx channel %d failed\n", dioTxCfg.channelNum);\r
3487 }\r
3488 Cppi_channelEnable (hAif->pktDmaConfig.dioTxChAxC);\r
3489 Cppi_channelEnable (hAif->pktDmaConfig.dioRxChAxC);\r
3490 #else\r
3491 // Enable channel 128 for DIO mode\r
3492 // disable loopback\r
3493 CSL_FINS (pktDMAGlobalCfg->EMULATION_CONTROL_REG,CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN, 0);\r
3494 //set write arbitration FIFO depth to 8\r
3495 CSL_FINS(pktDMAGlobalCfg->PERF_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_WARB_FIFO_DEPTH, 8);\r
3496 // enable Tx for DIO\r
3497 CSL_FINS(pktDMATxCfg->TX_CHANNEL_GLOBAL_CONFIG[128].TX_CHANNEL_GLOBAL_CONFIG_REG_A, CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE, (uint32_t)1);\r
3498 // enable Rx for DIO\r
3499 CSL_FINS(pktDMARxCfg->RX_CHANNEL_GLOBAL_CONFIG[128].RX_CHANNEL_GLOBAL_CONFIG_REG, CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE, (uint32_t)1);\r
3500 #endif\r
3501 \r
3502 }\r
3503 \r
3504 \r
3505 /* Initialize synchronization counters for event tracking */\r
3506 AIF_initFsync(hAif);\r
3507 \r
3508 ctrlArg = true;\r
3509 //AT Arm timer\r
3510 if (AIF2FL_SOK != Aif2Fl_hwControl(hAif->hFl, AIF2FL_CMD_AT_ARM_TIMER, (void *)&ctrlArg))\r
3511 Aif2_osalLog("aif2 AT arm timer fail \n");\r
3512 \r
3513 Aif2_osalMulticoreSyncBarrier();\r
3514 \r
3515 } //eof AIF_startHw\r
3516 \r
3517 void\r
3518 AIF_configureAtEvent(\r
3519 Aif2Fl_AtEvent* hAtEvent\r
3520 )\r
3521 {\r
3522 uint32_t evtNum = (uint32_t)hAtEvent->EventSelect;\r
3523 \r
3524 AtEventSetup.AtRadEvent[evtNum].EventSelect = hAtEvent->EventSelect;\r
3525 AtEventSetup.AtRadEvent[evtNum].EventOffset = hAtEvent->EventOffset;\r
3526 AtEventSetup.AtRadEvent[evtNum].EvtStrobeSel = hAtEvent->EvtStrobeSel;\r
3527 AtEventSetup.AtRadEvent[evtNum].EventModulo = hAtEvent->EventModulo;\r
3528 AtEventSetup.AtRadEvent[evtNum].EventMaskLsb = hAtEvent->EventMaskLsb;\r
3529 AtEventSetup.AtRadEvent[evtNum].EventMaskMsb = hAtEvent->EventMaskMsb;\r
3530 }\r
3531 \r
3532 void AIF_enableAtEvent(\r
3533 Aif2Fl_AtEventIndex event\r
3534 )\r
3535 { \r
3536 AtEventSetup.bEnableRadEvent[(uint32_t)event] = true;\r
3537 }\r
3538 \r
3539 void AIF_disableAtEvent(\r
3540 Aif2Fl_AtEventIndex event\r
3541 )\r
3542 {\r
3543 AtEventSetup.bEnableRadEvent[(uint32_t)event] = false;\r
3544 }\r
3545 \r
3546 void\r
3547 AIF_configureEgrDioEvent(\r
3548 Aif2Fl_AtEvent* hAtEvent,\r
3549 uint32_t dioNum\r
3550 \r
3551 )\r
3552 {\r
3553 AtEventSetup.AtEgrDioEvent[dioNum].EventSelect = hAtEvent->EventSelect; //Select E DIO Event (for instance AIF2FL_E_DIO_EVENT_0)\r
3554 AtEventSetup.AtEgrDioEvent[dioNum].EventOffset = hAtEvent->EventOffset;\r
3555 AtEventSetup.AtEgrDioEvent[dioNum].EvtStrobeSel = hAtEvent->EvtStrobeSel;\r
3556 AtEventSetup.AtEgrDioEvent[dioNum].EventModulo = hAtEvent->EventModulo;\r
3557 AtEventSetup.AtEgrDioEvent[dioNum].DioFrameEventOffset = hAtEvent->DioFrameEventOffset;\r
3558 AtEventSetup.AtEgrDioEvent[dioNum].DioFrameStrobeSel = hAtEvent->DioFrameStrobeSel;\r
3559 }\r
3560 \r
3561 void AIF_enableEgrDioEvent(\r
3562 uint32_t dioNum\r
3563 )\r
3564 {\r
3565 AtEventSetup.bEnableEgrDioEvent[dioNum] = true;\r
3566 }\r
3567 \r
3568 void AIF_disableEgrDioEvent(\r
3569 uint32_t dioNum\r
3570 )\r
3571 {\r
3572 AtEventSetup.bEnableEgrDioEvent[dioNum] = false;\r
3573 }\r
3574 \r
3575 void\r
3576 AIF_configureIngrDioEvent(\r
3577 Aif2Fl_AtEvent* hAtEvent,\r
3578 uint32_t dioNum\r
3579 \r
3580 )\r
3581 {\r
3582 AtEventSetup.AtIngrDioEvent[dioNum].EventSelect = hAtEvent->EventSelect; //Select E DIO Event (for instance AIF2FL_E_DIO_EVENT_0)\r
3583 AtEventSetup.AtIngrDioEvent[dioNum].EventOffset = hAtEvent->EventOffset;\r
3584 AtEventSetup.AtIngrDioEvent[dioNum].EvtStrobeSel = hAtEvent->EvtStrobeSel;\r
3585 AtEventSetup.AtIngrDioEvent[dioNum].EventModulo = hAtEvent->EventModulo;\r
3586 AtEventSetup.AtIngrDioEvent[dioNum].DioFrameEventOffset = hAtEvent->DioFrameEventOffset;\r
3587 AtEventSetup.AtIngrDioEvent[dioNum].DioFrameStrobeSel = hAtEvent->DioFrameStrobeSel;\r
3588 }\r
3589 \r
3590 void AIF_enableIngrDioEvent(\r
3591 uint32_t dioNum\r
3592 )\r
3593 {\r
3594 AtEventSetup.bEnableIngrDioEvent[dioNum] = true;\r
3595 }\r
3596 \r
3597 void AIF_disableIngrDioEvent(\r
3598 uint32_t dioNum\r
3599 )\r
3600 {\r
3601 AtEventSetup.bEnableIngrDioEvent[dioNum] = false;\r
3602 }\r
3603 \r
3604 void\r
3605 AIF_configureEgrDioEngine(\r
3606 Aif2Fl_AdDioEngine* hEgrDioEngine,\r
3607 uint32_t dioNum\r
3608 )\r
3609 {\r
3610 uint32_t k;\r
3611 AdDioSetup.EgrDioEngineEnable[dioNum] = true;\r
3612 AdDioSetup.EgrDioEngine[dioNum].BcnTableSelect = hEgrDioEngine->BcnTableSelect;\r
3613 AdDioSetup.EgrDioEngine[dioNum].NumAxC = hEgrDioEngine->NumAxC;\r
3614 AdDioSetup.EgrDioEngine[dioNum].DmaNumBlock = hEgrDioEngine->DmaNumBlock;\r
3615 AdDioSetup.EgrDioEngine[dioNum].NumQuadWord = hEgrDioEngine->NumQuadWord;\r
3616 AdDioSetup.EgrDioEngine[dioNum].bEnEgressRsaFormat = hEgrDioEngine->bEnEgressRsaFormat;\r
3617 AdDioSetup.EgrDioEngine[dioNum].DmaBlockAddrStride = hEgrDioEngine->DmaBlockAddrStride;\r
3618 AdDioSetup.EgrDioEngine[dioNum].bEnDmaChannel = true; //Enable Dma channel\r
3619 AdDioSetup.EgrDioEngine[dioNum].DmaBurstLen = hEgrDioEngine->DmaBurstLen;\r
3620 AdDioSetup.EgrDioEngine[dioNum].DmaBaseAddr = hEgrDioEngine->DmaBaseAddr;\r
3621 AdDioSetup.EgrDioEngine[dioNum].DmaBurstAddrStride = hEgrDioEngine->DmaBurstAddrStride;\r
3622 for (k = 0; k < 64; k++)\r
3623 {\r
3624 AdDioSetup.EgrDioEngine[dioNum].DBCN[k] = hEgrDioEngine->DBCN[k]; //set egress table DBCN for channel 0\r
3625 }\r
3626 }\r
3627 \r
3628 void\r
3629 AIF_configureIngrDioEngine(\r
3630 Aif2Fl_AdDioEngine* hIngrDioEngine,\r
3631 uint32_t dioNum\r
3632 )\r
3633 {\r
3634 uint32_t k;\r
3635 AdDioSetup.IngrDioEngineEnable[dioNum] = true;\r
3636 AdDioSetup.IngrDioEngine[dioNum].BcnTableSelect = hIngrDioEngine->BcnTableSelect;\r
3637 AdDioSetup.IngrDioEngine[dioNum].NumAxC = hIngrDioEngine->NumAxC;\r
3638 AdDioSetup.IngrDioEngine[dioNum].DmaNumBlock = hIngrDioEngine->DmaNumBlock;\r
3639 AdDioSetup.IngrDioEngine[dioNum].NumQuadWord = hIngrDioEngine->NumQuadWord;\r
3640 #ifdef K2\r
3641 AdDioSetup.IngrDioEngine[dioNum].bEnIngressRsaFormat = hIngrDioEngine->bEnIngressRsaFormat;\r
3642 #endif\r
3643 AdDioSetup.IngrDioEngine[dioNum].DmaBlockAddrStride = hIngrDioEngine->DmaBlockAddrStride;\r
3644 AdDioSetup.IngrDioEngine[dioNum].bEnDmaChannel = true; //Enable Dma channel\r
3645 AdDioSetup.IngrDioEngine[dioNum].DmaBurstLen = hIngrDioEngine->DmaBurstLen;\r
3646 AdDioSetup.IngrDioEngine[dioNum].DmaBaseAddr = hIngrDioEngine->DmaBaseAddr;\r
3647 AdDioSetup.IngrDioEngine[dioNum].DmaBurstAddrStride = hIngrDioEngine->DmaBurstAddrStride;\r
3648 for (k = 0; k < 64; k++)\r
3649 {\r
3650 AdDioSetup.IngrDioEngine[dioNum].DBCN[k] = hIngrDioEngine->DBCN[k]; //set ingress table DBCN for channel 0\r
3651 }\r
3652 }\r
3653 \r
3654 void\r
3655 AIF_setRadTimerTc(\r
3656 uint32_t clockNum,\r
3657 uint8_t symbolNum,\r
3658 uint32_t frameLsbNum,\r
3659 uint8_t lutIndexNum,\r
3660 uint32_t *radClockCountTc\r
3661 )\r
3662 {\r
3663 uint32_t i;\r
3664 \r
3665 RadTimerTc.ClockNum = clockNum;\r
3666 RadTimerTc.SymbolNum = symbolNum;\r
3667 RadTimerTc.FrameLsbNum = frameLsbNum;\r
3668 RadTimerTc.LutIndexNum = lutIndexNum;\r
3669 for (i=0;i<=lutIndexNum;i++)\r
3670 {\r
3671 AtCommonSetup.AtTerminalCount.RadClockCountTc[i] = radClockCountTc[i];\r
3672 }\r
3673 }\r
3674 \r
3675 void\r
3676 AIF_setPhyTimerInit(\r
3677 uint32_t ClockNum,\r
3678 uint32_t FrameLsbNum,\r
3679 uint32_t FrameMsbNum\r
3680 )\r
3681 {\r
3682 PhyTimerInit.ClockNum = ClockNum;\r
3683 PhyTimerInit.FrameLsbNum = FrameLsbNum;\r
3684 PhyTimerInit.FrameMsbNum = FrameMsbNum;\r
3685 }\r
3686 \r
3687 void\r
3688 AIF_setUlRadTimerInit(\r
3689 uint32_t SymbolNum,\r
3690 uint32_t ClockNum,\r
3691 uint32_t FrameLsbNum,\r
3692 uint32_t FrameMsbNum,\r
3693 uint16_t FcbMinusOne\r
3694 )\r
3695 {\r
3696 UlRadTimerInit.ClockNum = ClockNum;\r
3697 UlRadTimerInit.SymbolNum = SymbolNum;\r
3698 UlRadTimerInit.FrameLsbNum = FrameLsbNum;\r
3699 UlRadTimerInit.FrameMsbNum = FrameMsbNum;\r
3700 UlRadTimerInit.FcbMinusOne = FcbMinusOne;\r
3701 }\r
3702 \r
3703 void\r
3704 AIF_setDlRadTimerInit(\r
3705 uint32_t SymbolNum,\r
3706 uint32_t ClockNum,\r
3707 uint32_t FrameLsbNum,\r
3708 uint32_t FrameMsbNum,\r
3709 uint16_t FcbMinusOne\r
3710 )\r
3711 {\r
3712 DlRadTimerInit.ClockNum = ClockNum;\r
3713 DlRadTimerInit.SymbolNum = SymbolNum;\r
3714 DlRadTimerInit.FrameLsbNum = FrameLsbNum;\r
3715 DlRadTimerInit.FrameMsbNum = FrameMsbNum;\r
3716 DlRadTimerInit.FcbMinusOne = FcbMinusOne;\r
3717 }\r
3718 \r
3719 void\r
3720 AIF_setRmLinkSetupParams (\r
3721 int32_t link,\r
3722 Aif2Fl_RmFifoThold RmFifoThold,\r
3723 uint16_t bEnableLcvControl,\r
3724 uint16_t losDetThreshold,\r
3725 uint16_t SyncThreshold,\r
3726 uint16_t FrameSyncThreshold,\r
3727 uint16_t UnsyncThreshold,\r
3728 uint16_t FrameUnsyncThreshold\r
3729 )\r
3730 {\r
3731 RmLinkSetup[link].RmFifoThold = RmFifoThold; \r
3732 RmLinkSetup[link].bEnableLcvControl = bEnableLcvControl;\r
3733 RmLinkSetup[link].losDetThreshold = losDetThreshold;\r
3734 RmLinkSetup[link].SyncThreshold = SyncThreshold;\r
3735 RmLinkSetup[link].FrameSyncThreshold = FrameSyncThreshold;\r
3736 RmLinkSetup[link].UnsyncThreshold = UnsyncThreshold;\r
3737 RmLinkSetup[link].FrameUnsyncThreshold = FrameUnsyncThreshold;\r
3738 }\r
3739 \r
3740 void\r
3741 AIF_setLinkPiMax (\r
3742 int32_t link,\r
3743 uint32_t piMax\r
3744 )\r
3745 {\r
3746 AtLinkSetup[link].PiMax = piMax;\r
3747 }\r
3748 \r
3749 void AIF_setPeFrameTC (\r
3750 int32_t index,\r
3751 Aif2Fl_FrameCounter *cfg\r
3752 )\r
3753 {\r
3754 PeCommonSetup.PeFrameTC[index].FrameIndexSc = cfg->FrameIndexSc;\r
3755 PeCommonSetup.PeFrameTC[index].FrameIndexTc = cfg->FrameIndexTc; \r
3756 PeCommonSetup.PeFrameTC[index].FrameSymbolTc = cfg->FrameSymbolTc;\r
3757 } \r
3758 \r
3759 void AIF_setPeFrameMsgTc (\r
3760 int32_t indx,\r
3761 uint16_t val\r
3762 )\r
3763 {\r
3764 PeCommonSetup.PeFrameMsgTc[indx] = val;\r
3765 }\r
3766 \r
3767 void AIF_setPdChDioOffset (\r
3768 int32_t indx,\r
3769 uint8_t val\r
3770 )\r
3771 {\r
3772 PdCommonSetup.PdChConfig1[indx].DioOffset = val;\r
3773 }\r
3774 \r
3775 uint32_t AIF2_getVersion (void)\r
3776 {\r
3777 return AIF2_DRV_VERSION_ID;\r
3778 }\r
3779 \r
3780 const char aif2LldVersionStr[] = AIF2_DRV_VERSION_STR ":" __DATE__ ":" __TIME__;\r
3781 \r
3782 const char* AIF2_getVersionStr (void)\r
3783 {\r
3784 return aif2LldVersionStr;\r
3785 }\r
3786 \r
3787 #ifdef K2\r
3788 \r
3789 static uint32_t AIF2FL_SERDES_B4_CFG_REGS;\r
3790 static uint32_t AIF2FL_SERDES_B8_CFG_REGS;\r
3791 static uint32_t AIF2FL_CONTROL_REGS;\r
3792 \r
3793 static void AIF_serdesRestoreDefault(\r
3794 uint32_t base_addr\r
3795 )\r
3796 {\r
3797 uint32_t i;\r
3798 \r
3799 CSL_SerDes_COMLANE_Restore_Default(base_addr);\r
3800 for(i=0; i < 4; i++)\r
3801 {\r
3802 CSL_SerDes_Lane_Restore_Default(base_addr, i);\r
3803 }\r
3804 CSL_SerDes_CMU_Restore_Default(base_addr);\r
3805 }\r
3806 \r
3807 static void AIF_serdesConfig(\r
3808 AIF_ConfigHandle hAif,\r
3809 uint8_t enableB8,\r
3810 uint8_t enableB4\r
3811 )\r
3812 {\r
3813 uint32_t retval, i;\r
3814 CSL_SERDES_REF_CLOCK refClock=CSL_SERDES_REF_CLOCK_122p88M;\r
3815 CSL_SERDES_LINK_RATE serdesRate;\r
3816 CSL_SERDES_LOOPBACK loopback;\r
3817 \r
3818 #ifndef _TMS320C6X\r
3819 AIF2FL_SERDES_B4_CFG_REGS = (uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].serDesB4CfgBase);\r
3820 AIF2FL_SERDES_B8_CFG_REGS = (uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].serDesB8CfgBase);\r
3821 AIF2FL_CONTROL_REGS = (uint32_t)(hAif->hAif2SerDesBaseAddr->dev.bases[0].cfgBase);\r
3822 #else\r
3823 AIF2FL_SERDES_B4_CFG_REGS = (0x02324000);\r
3824 AIF2FL_SERDES_B8_CFG_REGS = (0x02326000);\r
3825 AIF2FL_CONTROL_REGS = (0x01F00000);\r
3826 #endif\r
3827 \r
3828 if (122880==hAif->aif2ClkSpeedKhz) {\r
3829 refClock = CSL_SERDES_REF_CLOCK_122p88M;\r
3830 } else if (153600==hAif->aif2ClkSpeedKhz) {\r
3831 refClock = CSL_SERDES_REF_CLOCK_153p6M;\r
3832 } else {\r
3833 Aif2_osalLog("Error: Invalid reference clock\n");\r
3834 }\r
3835 \r
3836 if(AIF2FL_LINK_PROTOCOL_OBSAI==hAif->protocol) //used for OBSAI 2x,4x,8x and CPRI 5x\r
3837 {\r
3838 serdesRate = CSL_SERDES_LINK_RATE_6p144G;\r
3839 } else { //used for CPRI 2x,4x,8x\r
3840 serdesRate = CSL_SERDES_LINK_RATE_4p9152G;\r
3841 }\r
3842 \r
3843 // Call the shutdown for each SerDes and restore default values if SerDes were already in use\r
3844 CSL_AIF2SerdesShutdown(AIF2FL_SERDES_B8_CFG_REGS);\r
3845 CSL_AIF2SerdesShutdown(AIF2FL_SERDES_B4_CFG_REGS);\r
3846 if (!CSL_AIF2SerdesIsReset(AIF2FL_SERDES_B8_CFG_REGS)) {\r
3847 AIF_serdesRestoreDefault(AIF2FL_SERDES_B8_CFG_REGS);\r
3848 }\r
3849 if (!CSL_AIF2SerdesIsReset(AIF2FL_SERDES_B4_CFG_REGS)) {\r
3850 AIF_serdesRestoreDefault(AIF2FL_SERDES_B4_CFG_REGS);\r
3851 }\r
3852 \r
3853 if (enableB8)\r
3854 {\r
3855 CSL_AIF2SerdesInitB8(AIF2FL_SERDES_B8_CFG_REGS, refClock, serdesRate);\r
3856 for(i=0; i < 4; i++)\r
3857 {\r
3858 if(1==hAif->linkConfig[i].linkEnable) {\r
3859 CSL_AIF2SerdesLaneConfig(AIF2FL_SERDES_B8_CFG_REGS, refClock, serdesRate, i);\r
3860 }\r
3861 }\r
3862 CSL_AIF2SerdesComEnable(AIF2FL_SERDES_B8_CFG_REGS);\r
3863 }\r
3864 \r
3865 if (enableB4)\r
3866 {\r
3867 CSL_AIF2SerdesInitB4(AIF2FL_SERDES_B4_CFG_REGS, refClock, serdesRate);\r
3868 for(i=0; i < 2; i++)\r
3869 {\r
3870 if(1==hAif->linkConfig[AIF2FL_LINK_4 + i].linkEnable) {\r
3871 CSL_AIF2SerdesLaneConfig(AIF2FL_SERDES_B4_CFG_REGS, refClock, serdesRate, i);\r
3872 }\r
3873 }\r
3874 CSL_AIF2SerdesComEnable(AIF2FL_SERDES_B4_CFG_REGS);\r
3875 }\r
3876 \r
3877 //AIF2 Lane Enable\r
3878 for(i=0; i < 6; i++)\r
3879 {\r
3880 if(1==hAif->linkConfig[i].linkEnable) {\r
3881 if (hAif->linkConfig[i].comType == AIF2_LOOPBACK) { //setup links for internal loopback mode\r
3882 loopback = CSL_SERDES_LOOPBACK_ENABLED;\r
3883 } else {\r
3884 loopback = CSL_SERDES_LOOPBACK_DISABLED;\r
3885 }\r
3886 if(hAif->linkConfig[i].linkRate == 8) {\r
3887 if (i < (uint32_t)AIF2FL_LINK_4) {\r
3888 CSL_AIF2SerdesLaneEnable(AIF2FL_CONTROL_REGS, AIF2FL_SERDES_B8_CFG_REGS, i, AIF2FL_LINK_RATE_8x);\r
3889 CSL_AIF2SerdesLoopbackEnable(AIF2FL_SERDES_B8_CFG_REGS, i, loopback);\r
3890 } else {\r
3891 CSL_AIF2SerdesLaneEnable(AIF2FL_CONTROL_REGS, AIF2FL_SERDES_B4_CFG_REGS, i, AIF2FL_LINK_RATE_8x);\r
3892 CSL_AIF2SerdesLoopbackEnable(AIF2FL_SERDES_B4_CFG_REGS, i - AIF2FL_LINK_4, loopback);\r
3893 }\r
3894 } else { \r
3895 if (i < (uint32_t)AIF2FL_LINK_4) {\r
3896 CSL_AIF2SerdesLaneEnable(AIF2FL_CONTROL_REGS, AIF2FL_SERDES_B8_CFG_REGS, i, AIF2FL_LINK_RATE_4x);\r
3897 CSL_AIF2SerdesLoopbackEnable(AIF2FL_SERDES_B8_CFG_REGS, i, loopback);\r
3898 } else {\r
3899 CSL_AIF2SerdesLaneEnable(AIF2FL_CONTROL_REGS, AIF2FL_SERDES_B4_CFG_REGS, i, AIF2FL_LINK_RATE_4x);\r
3900 CSL_AIF2SerdesLoopbackEnable(AIF2FL_SERDES_B4_CFG_REGS, i - AIF2FL_LINK_4, loopback);\r
3901 }\r
3902 }\r
3903 \r
3904 }\r
3905 }\r
3906 if (enableB8)\r
3907 {\r
3908 //AIF2 B8 PLL Enable\r
3909 CSL_AIF2SerdesPllEnableB8(AIF2FL_CONTROL_REGS,AIF2FL_SERDES_B8_CFG_REGS); \r
3910 \r
3911 //AIF2 PLL Status Poll\r
3912 retval = CSL_SERDES_STATUS_PLL_NOT_LOCKED;\r
3913 while(retval == CSL_SERDES_STATUS_PLL_NOT_LOCKED)\r
3914 {\r
3915 retval = CSL_AIF2SerdesGetStatusB8(AIF2FL_CONTROL_REGS);\r
3916 }\r
3917 }\r
3918 if (enableB4)\r
3919 {\r
3920 //AIF2 B4 PLL Enable\r
3921 CSL_AIF2SerdesPllEnableB4(AIF2FL_CONTROL_REGS,AIF2FL_SERDES_B4_CFG_REGS);\r
3922 \r
3923 //AIF2 PLL Status Poll\r
3924 retval = CSL_SERDES_STATUS_PLL_NOT_LOCKED;\r
3925 while(retval == CSL_SERDES_STATUS_PLL_NOT_LOCKED)\r
3926 {\r
3927 retval = CSL_AIF2SerdesGetStatusB4(AIF2FL_CONTROL_REGS);\r
3928 }\r
3929 }\r
3930 \r
3931 /* The TX byte clock from either B8 or B4 SERDES link will be selected as sys_clk once the PLL has acquired lock.*/\r
3932 if ((enableB8 == 0) && (enableB4))\r
3933 CSL_AIF2SerdesClkSelB4(AIF2FL_CONTROL_REGS);\r
3934 \r
3935 //AIF2 Links Clock Enable\r
3936 for(i=0; i < 6; i++)\r
3937 {\r
3938 if(1==hAif->linkConfig[i].linkEnable) {\r
3939 CSL_AIF2LinkClkEnable(AIF2FL_CONTROL_REGS, i);\r
3940 } else {\r
3941 CSL_AIF2LinkClkDisable(AIF2FL_CONTROL_REGS, i);\r
3942 }\r
3943 }\r
3944 }\r
3945 \r
3946 #endif // K2\r
3947 \r
3948 ////////////////////\r
3949 \r