1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file cal_hal.c
35 *
36 * \brief This file defines all abstractions for CAL module.
37 * This abstraction will support multiple instances of PPI, CSI. Operates 2
38 * modes primarily. memory to memory mode and capture mode.
39 *
40 */
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 #include <stdint.h>
47 #include <stddef.h>
48 #include <string.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/hw_types.h>
52 #include <ti/csl/cslr_cal.h>
54 #include <ti/drv/cal/cal.h>
55 #include <ti/drv/cal/src/hal/cal_hal.h>
57 /* ========================================================================== */
58 /* Macros & Typedefs */
59 /* ========================================================================== */
61 #define SMA_SW_CSI2_X0_UP_MASK (0x00000001U)
62 #define SMA_SW_CSI2_Y0_UP_MASK (0x00000002U)
64 #define SMA_SW_CSI2_X1_UP_MASK (0x00000004U)
65 #define SMA_SW_CSI2_Y1_UP_MASK (0x00000008U)
67 #define SMA_SW_CSI2_X2_UP_MASK (0x00000010U)
68 #define SMA_SW_CSI2_Y2_UP_MASK (0x00000020U)
70 #define SMA_SW_CSI2_X3_UP_MASK (0x00000040U)
71 #define SMA_SW_CSI2_Y3_UP_MASK (0x00000080U)
73 #define SMA_SW_CSI2_X4_UP_MASK (0x00000100U)
74 #define SMA_SW_CSI2_Y4_UP_MASK (0x00000200U)
76 #define SMA_SW_CSI2_X0_DW_MASK (0x00000400U)
77 #define SMA_SW_CSI2_Y0_DW_MASK (0x00000800U)
79 #define SMA_SW_CSI2_X1_DW_MASK (0x00001000U)
80 #define SMA_SW_CSI2_Y1_DW_MASK (0x00002000U)
82 #define SMA_SW_CSI2_X2_DW_MASK (0x00004000U)
83 #define SMA_SW_CSI2_Y2_DW_MASK (0x00008000U)
85 #define SMA_SW_CSI2_X3_DW_MASK (0x00010000U)
86 #define SMA_SW_CSI2_Y3_DW_MASK (0x00020000U)
88 #define SMA_SW_CSI2_X4_DW_MASK (0x00040000U)
89 #define SMA_SW_CSI2_Y4_DW_MASK (0x00080000U)
91 /**< Bit 2 set, used to compute register values for lanes enabled. */
92 #define CAL_BIT_2_SET ((uint32_t)0x4U)
94 #if (CAL_CAPT_MAX_CMPLXIO_INST != CSL_CAL_CMPLXIO_CNT)
95 #error "Number of complex IO's dont match"
96 #endif
98 /**< If PPI is enabled before DMA writes are, there is possibility that 1st
99 frame received will be written to address 0x0.
100 As Write DMA address is latched with a frame start event.
101 If PPI is enabled, before any buffer are primed, the write address is
102 not yet updated. 0x0 being reset value of write DMA address, 1st
103 frame would be written there. */
104 #define ENABLE_PPI_WHEN_STARTING
106 /**< Functional PHY clock is expected to be 96 MHz
107 Period of PHY clock in nS is 10.41666
108 ((1/<PHY Clock) / 1e-9) */
109 #define DPHY_FUNCTIONAL_CLK_PERIOD (10.41666)
112 /* ========================================================================== */
113 /* Structure Declarations */
114 /* ========================================================================== */
116 /**
117 * struct Cal_HalInstObj
118 * \brief Describes a instance of Cal configuration.
119 */
120 typedef struct Cal_HalInstObj
121 {
122 uint32_t instId;
123 /**< Instance ID */
124 uint32_t baseAddr;
125 /**< Base address of the CAL module */
126 uint32_t phy0BaseAddress;
127 /**< If this CAL instance has an associated PHY, this will hold a non-null
128 * value */
129 uint32_t phy1BaseAddress;
130 /**< If this CAL instance has an associated PHY, this will hold a non-null
131 * value */
132 uint32_t isInited;
133 /**< Flag to indicate successful initialization */
134 uint32_t openCnt;
135 /**< Number of times the hal is opened. */
136 Cal_HalInstCfg_t instCfg;
137 /**< Instance configuration */
138 } Cal_HalInstObj_t;
140 /**
141 * struct Cal_HalObj
142 * \brief Describes a cal object.
143 */
144 typedef struct Cal_HalObj
145 {
146 Cal_HalMode_t mode;
147 /**< Mode */
148 Cal_HalInstObj_t *pInstObj;
149 /**< Pointer to instance specific config */
150 } Cal_HalObj_t;
152 /* ========================================================================== */
153 /* Constants */
154 /* ========================================================================== */
156 /* ========================================================================== */
157 /* Macros & Typedefs */
158 /* ========================================================================== */
160 /* None */
162 /* ========================================================================== */
163 /* Function Declarations */
164 /* ========================================================================== */
166 /**
167 * \brief Resets the CAL instance
168 *
169 * \param baseAddr Base address of the CAL instance to be reset.
170 *
171 * \return FVID2_SOK on success else error code.
172 *
173 **/
174 static int32_t CalReset(uint32_t baseAddr);
176 /**
177 * \brief Configure instance LANE config and frame mode of operation. Note
178 * that the low level port is enabled for reception.
179 *
180 * \param baseAddr Base address of the CAL.
181 * \param pCfg Valid lane and frame mode configurations
182 *
183 * \return FVID2_SOK on success else error code.
184 *
185 **/
186 static int32_t CalCfgInstLanePpiCfg(uint32_t baseAddr,
187 Cal_HalInstCfg_t *pCfg);
189 /**
190 * \brief Resets CAL / PHY and applies instance specific config for capture
191 * Updated DMA read specifics for other modes.
192 *
193 * \param hndl Handle returned when opened.
194 * \param cfg Valid configuration for mode specified in open.
195 * \param mode Mode as specified during open.
196 *
197 * \return FVID2_SOK on success else error code.
198 *
199 **/
200 static int32_t CalResetApplyInstConfig(const Cal_HalObj_t *pHndl,
201 Cal_HalInstCfg_t *pCfg,
202 Cal_HalMode_t mode,
203 uint32_t enPhy);
204 /**
205 * \brief Applies supplied configurations, for all mode & all blocks.
206 *
207 * \param hndl Handle returned when opened.
208 * \param cfg Valid configuration for mode specified in open.
209 *
210 * \return FVID2_SOK on success else error code.
211 *
212 **/
213 static int32_t CalSetCfg(const Cal_HalObj_t *hndl, const Cal_HalCfg_t *cfg);
215 /**
216 * \brief Applies configurations required for m2m mode.
217 *
218 * \param pInst Pointer to instance object.
219 * \param cfg Valid configuration for m2m.
220 * \param mode Indicates if in capture / m2m mode.
221 *
222 * \return FVID2_SOK on success else error code.
223 *
224 **/
225 static int32_t CalSetCfgForMode(const Cal_HalInstObj_t *pInst,
226 const Cal_HalCfg_t *cfg,
227 Cal_HalMode_t mode);
229 /**
230 * \brief Applies CSI2 Virtual processing configurations.
231 *
232 * \param pInst Pointer to instance object.
233 * \param cfg Valid configuration for Virtual Channels of CSI2.
234 *
235 * \return FVID2_SOK on success else error code.
236 *
237 **/
238 static int32_t CalCsi2VcCfg(const Cal_HalInstObj_t *pInst,
239 const Cal_HalCsi2VcCfg_t *cfg,
240 uint32_t cportId);
242 /**
243 * \brief Applies pixel processing configurations.
244 *
245 * \param pInst Pointer to instance object.
246 * \param cfg Valid configuration for pixel processing.
247 *
248 * \return FVID2_SOK on success else error code.
249 *
250 **/
251 static int32_t CalSetPixProcCfg(const Cal_HalInstObj_t *pInst,
252 const Cal_PixProc_t *cfg,
253 uint32_t cportId);
255 /**
256 * \brief Applies BYS Out port configurations.
257 *
258 * \param pInst Pointer to instance object.
259 * \param cfg Valid configuration for BYS Out port.
260 *
261 * \return FVID2_SOK on success else error code.
262 *
263 **/
264 static int32_t CalSetBysOutCfg(const Cal_HalInstObj_t *pInst,
265 const Cal_BysOut_t *cfg,
266 uint32_t cportId);
268 /**
269 * \brief Applies VPORT out configurations.
270 *
271 * \param pInst Pointer to instance object.
272 * \param cfg Valid configuration for VPORT Out.
273 *
274 * \return FVID2_SOK on success else error code.
275 *
276 **/
277 static int32_t CalSetVportCfg(const Cal_HalInstObj_t *pInst,
278 const Cal_VPort_t *cfg,
279 uint32_t cportId);
281 /**
282 * \brief Applies DMA Read configurations.
283 *
284 * \param pInst Pointer to instance object.
285 * \param cfg Valid configuration for DMA Read.
286 *
287 * \return FVID2_SOK on success else error code.
288 *
289 **/
290 static int32_t CalSetRdDmaCfg(const Cal_HalInstObj_t *pInst,
291 const Cal_HalRdDmaCfg_t *cfg,
292 uint32_t cportId);
294 /**
295 * \brief Applies DMA Read frame size
296 *
297 * \param pInst Pointer to instance object.
298 * \param cfg Valid configuration for frame config.
299 *
300 * \return FVID2_SOK on success else error code.
301 *
302 **/
303 static int32_t CalSetRdDmaFrameCfg(const Cal_HalInstObj_t *pInst,
304 const Fvid2_Format *cfg);
306 /**
307 * \brief Applies DMA Write configurations.
308 *
309 * \param pInst Pointer to instance object.
310 * \param cfg Valid configuration for DMA Write.
311 *
312 * \return FVID2_SOK on success else error code.
313 *
314 **/
315 static int32_t CalSetWrDmaCfg(const Cal_HalInstObj_t *pInst,
316 const Cal_HalWrDmaCfg_t *cfg,
317 uint32_t cportId);
319 /**
320 * \brief Sets the DMA mode, expected to be used to enable/disable DMA writes
321 * For all the DMA write contexts that have been configured, the
322 * supplied mode is applied
323 *
324 * \param pInstObj Pointer to instance object.
325 * \param pDmaCfg Pointer to DMA config
326 *
327 * \return FVID2_SOK on success else error code.
328 *
329 **/
330 static int32_t calSetWrDmaMode(const Cal_HalInstObj_t *pInstObj,
331 const Cal_HalDmaVcCfg_t *pDmaCfg);
333 /**
334 * \brief Sets the DMA configurations such as burst size, mode, etc...
335 *
336 * \param pInstObj Pointer to instance object.
337 * \param pDmaCfg Pointer to DMA config
338 *
339 * \return FVID2_SOK
340 *
341 **/
342 static int32_t CalCfgInstWrDma(
343 uint32_t baseAddr, const Cal_HalInstCfg_t *pCfg);
345 /**
346 * \brief Configure the interrupt generation on reception of specified line
347 * of video data.
348 *
349 * \param pInstObj Pointer to instance object.
350 * \param plnEvtCfg Pointer to line event configuration
351 *
352 * \return FVID2_SOK
353 *
354 **/
355 static int32_t CalSetLineEventCfg(const Cal_HalInstObj_t *pInstObj,
356 const Cal_HalLineEventCfg_t *plnEvtCfg);
358 /* ========================================================================== */
359 /* Global Variables */
360 /* ========================================================================== */
361 #define CAL_HAL_INST_OBJ_DEFAULTS ( 0x0, /* instId */ \
362 0x0, /* baseAddr */ \
363 0x0, /* phy0BaseAddress */ \
364 0x0, /* phy1BaseAddress */ \
365 (uint32_t) FALSE, /* isInited */ \
366 0x0, /* openCnt */ \
367 )
368 static Cal_HalInstObj_t gCalInstObj[CSL_CAL_PER_CNT] =
369 {
370 {
371 0x0, /* instId */
372 0x0, /* baseAddr */
373 0x0, /* phy0BaseAddress */
374 0x0, /* phy1BaseAddress */
375 (uint32_t) FALSE, /* isInited */
376 0x0 /* openCnt */
377 }
378 #if (CSL_CAL_PER_CNT > 1U)
379 ,
380 {
381 0x0,
382 0x0,
383 (uint32_t)FALSE,
384 0x0,
385 0x0
386 }
387 #endif
388 /* Currently we do not have SoC with more than 2 CAL instances */
389 };
390 /**< Instance specific config */
392 static Cal_HalObj_t gCalObj \
393 [CSL_CAL_PER_CNT][CAL_HAL_OPEN_NUM];
394 /**< Handle / open specific config */
396 static Cal_HalInstCfg_t gCalInstDefaults;
397 /**< Default instance config */
399 #if defined (SOC_TDA2EX)
400 static Cal_HalInstParams_t gCalHalInstParams [CSL_CAL_PER_CNT] = {{0,
401 ISS_CALA_BASE_REGISTER,
402 ISS_CALA_CAMERARX_CORE_0_BASE_REGISTER,
403 ISS_CALA_CAMERARX_CORE_1_BASE_REGISTER, NULL}};
404 #endif
405 #if defined (SOC_AM65XX)
406 static Cal_HalInstParams_t gCalHalInstParams [CSL_CAL_PER_CNT] = {{0,
407 CSL_CAL0_BASE,
408 (CSL_CAL0_BASE + CSL_CAL_SCP_SCP_PHY_A(0)),
409 0U, 0U}};
410 #endif
411 /**< Cal Platform data */
413 /* ========================================================================== */
414 /* Function Definitions */
415 /* ========================================================================== */
417 int32_t Cal_halInit(uint32_t numInst,
418 const Cal_HalInstParams_t *initPrms, void *arg)
419 {
420 uint32_t i, j;
421 uint32_t isInited = (uint32_t)FALSE;
423 GT_assert(CalTrace, (CSL_CAL_PER_CNT >= numInst));
424 GT_assert(CalTrace, (NULL != initPrms));
425 GT_assert(CalTrace, (0x0 != initPrms->baseAddress));
427 for(i = 0; i < CSL_CAL_PER_CNT; i++)
428 {
429 if((uint32_t)FALSE != gCalInstObj[i].isInited)
430 {
431 /* Has been initialized earlier. Exit now */
432 isInited = (uint32_t)TRUE;
433 /* This is MISRA C violation, for having multiple returns.
434 * This should not cause any issues. Please ignore */
435 }
436 }
438 if((uint32_t)FALSE == isInited)
439 {
440 /* Do not require to initialize gCalObj, we rely primarily
441 * on gCalInstObj
442 * The association between gCalInstObj & gCalObj is done
443 * further down */
444 /* . Set defaults */
445 /* Indicates the urgency of real time traffic using the
446 * number of contexts
447 * currently in use by the write DMA.
448 * 00: SAFE (n<MFLAGL)
449 * 01: VULNERABLE (MFLAGL<=n<MFLAGH)
450 * 11: ENDANGERED (MFLAGH<=n)
451 * Assuming 4 write DMA contexts, n = 4 */
453 gCalInstDefaults.mFlagH = 10U;
454 gCalInstDefaults.mFlagL = 6U;
455 /* Assuming CAL receives via a sensor */
456 gCalInstDefaults.rdDmaStall = (uint32_t)TRUE;
457 gCalInstDefaults.pwrScpClk = (uint32_t)FALSE;
458 gCalInstDefaults.dmaBurstSize = CSL_CAL_C2VID_CTRL_BURSTSIZE_BURST128;
459 gCalInstDefaults.tagCnt = 15U;
460 gCalInstDefaults.postedWrites = (uint32_t)FALSE;
462 for(i = 0; i < CSL_CAL_CMPLXIO_CNT; i++)
463 {
464 gCalInstDefaults.csi2PhyClock[i] = 400U;
466 gCalInstDefaults.numCmplxIoInst = CSL_CAL_CMPLXIO_CNT;
467 gCalInstDefaults.cmplxIoCfg[i].enable = (uint32_t)TRUE;
468 gCalInstDefaults.cmplxIoCfg[i].clockLane.pol = (uint32_t)FALSE;
469 gCalInstDefaults.cmplxIoCfg[i].clockLane.position = 5U;
470 gCalInstDefaults.cmplxIoCfg[i].data1Lane.pol = (uint32_t)FALSE;
471 gCalInstDefaults.cmplxIoCfg[i].data1Lane.position = 1U;
472 gCalInstDefaults.cmplxIoCfg[i].data2Lane.pol = (uint32_t)FALSE;
473 gCalInstDefaults.cmplxIoCfg[i].data2Lane.position = 2U;
474 gCalInstDefaults.cmplxIoCfg[i].data3Lane.pol = (uint32_t)FALSE;
475 gCalInstDefaults.cmplxIoCfg[i].data3Lane.position = 3U;
476 gCalInstDefaults.cmplxIoCfg[i].data4Lane.pol = (uint32_t)FALSE;
477 gCalInstDefaults.cmplxIoCfg[i].data4Lane.position = 4U;
478 gCalInstDefaults.cmplxIoCfg[i].pwrAuto = (uint32_t)FALSE;
479 /* Always
480 * powered
481 * up
482 */
483 }
484 for(i = 0; i < CSL_CAL_PPI_CNT; i++)
485 {
486 gCalInstDefaults.numPpiInst = CSL_CAL_PPI_CNT;
487 gCalInstDefaults.ppiCfg[i].enable = (uint32_t)FALSE;
488 gCalInstDefaults.ppiCfg[i].instance = 0x0U;
489 gCalInstDefaults.ppiCfg[i].frame = (uint32_t)TRUE;
490 gCalInstDefaults.ppiCfg[i].ecc = (uint32_t)FALSE;
492 /* Careful while updating these, are used to determine
493 the stop state
494 detection.
495 Please ignore force_rx_mode_0I01 - will be removed */
496 gCalInstDefaults.ppiCfg[i].csi2Cfg.force_rx_mode_0I01 = 1U;
497 gCalInstDefaults.ppiCfg[i].csi2Cfg.stop_state_x16_I01 = 1U;
498 gCalInstDefaults.ppiCfg[i].csi2Cfg.stop_state_x4_I01 = 0U;
499 gCalInstDefaults.ppiCfg[i].csi2Cfg.stop_state_counter_I01 = 0x197U;
500 }
502 for(i = 0; ((i < numInst) && (i < CSL_CAL_PER_CNT)); i++)
503 {
504 gCalInstObj[i].instId = i;
505 GT_assert(CalTrace, (0x0 != initPrms->baseAddress));
506 gCalInstObj[i].baseAddr = initPrms->baseAddress;
507 gCalInstObj[i].phy0BaseAddress = initPrms->phy0BaseAddress;
508 gCalInstObj[i].phy1BaseAddress = initPrms->phy1BaseAddress;
509 gCalInstObj[i].openCnt = 0U;
510 gCalInstObj[i].isInited = (uint32_t)TRUE;
511 memcpy((void *) & gCalInstObj[i].instCfg,
512 (const void *) &gCalInstDefaults,
513 sizeof(Cal_HalInstCfg_t));
514 for(j = 0; j < CAL_HAL_OPEN_NUM; j++)
515 {
516 gCalObj[i][j].pInstObj = &gCalInstObj[i];
517 }
519 initPrms++;
520 }
521 }
523 return FVID2_SOK;
524 }
526 /**************************Function Separator**********************************/
528 int32_t Cal_halDeInit(void *arg)
529 {
530 uint32_t i;
532 for(i = 0; i < CSL_CAL_PER_CNT; i++)
533 {
534 GT_assert(CalTrace, (0x0 == gCalInstObj[i].openCnt));
535 memset(&gCalInstObj[i], 0U, sizeof(Cal_HalInstObj_t));
536 }
537 /* Do not require any updates to gCalObj, the close will take care */
538 return FVID2_SOK;
539 }
541 /**************************Function Separator**********************************/
543 Cal_HalHandle Cal_halOpen(const Cal_HalOpenParams_t *openPrms,
544 void *arg)
545 {
546 Cal_HalObj_t *hndl = NULL;
547 int32_t rtnVal;
548 uint32_t openCnt;
550 rtnVal = FVID2_SOK;
551 if(NULL == openPrms)
552 {
553 rtnVal = FVID2_EBADARGS;
554 }
556 if((FVID2_SOK == rtnVal) && (CSL_CAL_PER_CNT <= openPrms->instId))
557 {
558 rtnVal = FVID2_EBADARGS;
559 }
560 if((FVID2_SOK == rtnVal) &&
561 ((CAL_HAL_MODE_MIN >= openPrms->mode) ||
562 (CAL_HAL_MODE_MAX <= openPrms->mode)))
563 {
564 rtnVal = FVID2_EBADARGS;
565 }
566 if(FVID2_SOK == rtnVal)
567 {
568 openCnt = gCalObj[openPrms->instId][0].pInstObj->openCnt;
569 if(CAL_HAL_OPEN_NUM <= openCnt)
570 {
571 rtnVal = FVID2_EALLOC;
572 }
573 }
575 if(FVID2_SOK == rtnVal)
576 {
577 hndl = &gCalObj[openPrms->instId][openCnt];
578 if(NULL == hndl->pInstObj)
579 {
580 /* Not initialized/ */
581 rtnVal = FVID2_EBADARGS;
582 }
583 }
584 if(FVID2_SOK == rtnVal)
585 {
586 hndl->pInstObj->openCnt++;
588 rtnVal = CalResetApplyInstConfig(hndl, &hndl->pInstObj->instCfg,
589 openPrms->mode, (uint32_t)FALSE);
590 if(FVID2_SOK == rtnVal)
591 {
592 hndl->mode = openPrms->mode;
593 }
594 }
596 return ((Cal_HalHandle) hndl);
597 }
599 /**************************Function Separator**********************************/
601 int32_t Cal_halClose(Cal_HalHandle handle, void *arg)
602 {
603 uint32_t instance, i;
604 int32_t rtnVal = FVID2_SOK;
605 volatile uint32_t reg, timeOut;
606 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
608 if(NULL == hndl)
609 {
610 rtnVal = FVID2_EBADARGS;
611 }
612 else
613 {
614 GT_assert(CalTrace, (NULL != hndl->pInstObj));
615 }
617 if(FVID2_SOK == rtnVal)
618 {
619 if(0x0 == hndl->pInstObj->openCnt)
620 {
621 rtnVal = FVID2_EBADARGS;
622 }
623 }
625 if(FVID2_SOK == rtnVal)
626 {
627 if(CAL_HAL_MODE_CAPTURE == hndl->mode)
628 {
629 rtnVal = FVID2_SOK;
630 for(i = 0; ((FVID2_SOK == rtnVal) &&
631 (i < hndl->pInstObj->instCfg.numPpiInst)); i++)
632 {
633 if((uint32_t)FALSE != hndl->pInstObj->instCfg.ppiCfg[i].enable)
634 {
635 instance = hndl->pInstObj->instCfg.ppiCfg[i].instance;
636 if(CSL_CAL_PPI_CNT < instance)
637 {
638 rtnVal = FVID2_EBADARGS;
639 break;
640 }
641 #ifndef ENABLE_PPI_WHEN_STARTING
642 if(1U == hndl->pInstObj->openCnt)
643 {
644 /* Last instance of open, disable PPI */
645 reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
646 CSL_CAL_C2PPI_CSI2_PPI_CTRL(instance));
647 reg &= ~CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
648 HW_WR_REG32(hndl->pInstObj->baseAddr +
649 CSL_CAL_C2PPI_CSI2_PPI_CTRL(instance), reg);
650 rtnVal = FVID2_SOK;
651 }
652 #endif /* ENABLE_PPI_WHEN_STARTING */
653 }
654 }
655 for(i = 0; i < CSL_CAL_CMPLXIO_CNT; i++)
656 {
657 if(1U == hndl->pInstObj->openCnt)
658 {
659 reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
660 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i));
661 reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
662 HW_WR_REG32(hndl->pInstObj->baseAddr +
663 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i), reg);
665 /* Wait for power down completion */
666 timeOut = 0xFFFFU;
667 while(timeOut)
668 {
669 reg = HW_RD_REG32(hndl->pInstObj->baseAddr +
670 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(i));
671 if(0U == (reg & CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK))
672 {
673 break;
674 }
675 timeOut--;
676 }
677 if(0U == timeOut)
678 {
679 /* Could not power down the PHY... */
680 rtnVal = FVID2_ETIMEOUT;
681 GT_assert(CalTrace, ((uint32_t)FALSE));
682 break;
683 }
684 }
685 }
686 }
687 else if(CAL_HAL_MODE_M2M == hndl->mode)
688 {
689 rtnVal = FVID2_SOK;
690 if(1U == hndl->pInstObj->openCnt)
691 {
692 /* For the very last clos ensure that there are no pending
693 DMA reads */
694 reg = HW_RD_REG32(hndl->pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
695 if(CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK == (reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK))
696 {
697 rtnVal = FVID2_EDEVICE_INUSE;
698 }
699 }
700 }
701 else
702 {
703 GT_assert(CalTrace,
704 (CAL_HAL_MODE_CMPLXIO_CTRL != hndl->mode));
705 rtnVal = FVID2_SOK;
706 }
707 hndl->pInstObj->openCnt--;
709 hndl->mode = CAL_HAL_MODE_MIN;
710 }
712 return rtnVal;
713 }
715 /**************************Function Separator**********************************/
716 int32_t Cal_halCaptureStart(Cal_HalHandle handle,
717 void *arg)
718 {
719 Cal_HalInstObj_t *pInstObj;
720 volatile uint32_t reg;
721 uint32_t idx, baseAddr, offset;
722 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
723 int32_t rtnVal = FVID2_EBADARGS;
725 if (NULL != hndl)
726 {
727 if (NULL != hndl->pInstObj)
728 {
729 if ((CAL_HAL_MODE_CAPTURE == hndl->mode) && (NULL != arg))
730 {
731 pInstObj = hndl->pInstObj;
733 rtnVal = calSetWrDmaMode(pInstObj, (Cal_HalDmaVcCfg_t *)arg);
734 #ifdef ENABLE_PPI_WHEN_STARTING
735 for (idx = 0; idx < pInstObj->instCfg.numPpiInst; idx++)
736 {
737 if ((uint32_t)FALSE != pInstObj->instCfg.ppiCfg[idx].enable)
738 {
739 baseAddr = pInstObj->baseAddr;
740 offset = pInstObj->instCfg.ppiCfg[idx].instance;
741 reg =
742 HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
743 reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
744 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset),
745 reg);
746 }
747 }
748 #endif /* ENABLE_PPI_WHEN_STARTING */
749 } /* CAL_HAL_MODE_CAPTURE == hndl->mode */
750 } /* NULL != hndl->pInstObj */
751 }
753 return (rtnVal);
754 }
756 /**************************Function Separator**********************************/
757 int32_t Cal_halCaptureStop(Cal_HalHandle handle, void *arg)
758 {
759 Cal_HalInstObj_t *pInstObj;
760 volatile uint32_t reg;
761 uint32_t idx, baseAddr, offset;
762 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
763 int32_t rtnVal = FVID2_EBADARGS;
765 if (NULL != hndl)
766 {
767 if (NULL != hndl->pInstObj)
768 {
769 if ((CAL_HAL_MODE_CAPTURE == hndl->mode) && (NULL != arg))
770 {
771 pInstObj = hndl->pInstObj;
773 rtnVal = calSetWrDmaMode(pInstObj, (Cal_HalDmaVcCfg_t *)arg);
774 #ifdef ENABLE_PPI_WHEN_STARTING
775 /* TODO - Check if all write DMAs have been stopped.
776 Otherwise multiple handle will not work.
777 Right way would be
778 . Do it in the core
779 . If NOT the last wr context
780 . Setup to receive into 10 X 10 buffer
781 . Updated size, offset
782 . On disable of last context
783 . Setup to receive into 10 x 10 buffer,
784 . Disable PPI
785 . */
787 for(idx = 0; idx < pInstObj->instCfg.numPpiInst; idx++)
788 {
789 if((uint32_t)FALSE !=
790 pInstObj->instCfg.ppiCfg[idx].enable)
791 {
792 baseAddr = pInstObj->baseAddr;
793 offset = pInstObj->instCfg.ppiCfg[idx].instance;
794 reg =
795 HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
796 reg &= ~((uint32_t) CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK);
797 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset),
798 reg);
799 }
800 }
801 #endif /* ENABLE_PPI_WHEN_STARTING */
802 }
803 }
804 }
806 return (rtnVal);
807 }
809 /**************************Function Separator**********************************/
810 int32_t Cal_halUpdateBufAddr(Cal_HalHandle handle,
811 const Cal_HalBufferAddr_t *bufPtrs)
812 {
813 volatile uint32_t reg;
814 uint32_t idx, baseAddr;
815 int32_t rtnVal = FVID2_EBADARGS;
816 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
818 if (NULL != hndl)
819 {
820 if(NULL != hndl->pInstObj)
821 {
822 if (NULL != bufPtrs)
823 {
824 rtnVal = FVID2_SOK;
825 for(idx = 0U; idx < bufPtrs->numBuff; idx++)
826 {
827 if((uint32_t)0U == (uint32_t)bufPtrs->buffAddr[idx])
828 {
829 rtnVal = FVID2_EBADARGS;
830 }
831 if((CAL_HAL_MODE_M2M == hndl->mode) ||
832 (CAL_HAL_MODE_CAPTURE == hndl->mode))
833 {
834 if(CAL_CAPT_MAX_STREAMS <= bufPtrs->wrDmaCtx[idx])
835 {
836 rtnVal = FVID2_EBADARGS;
837 }
838 }
840 if(FVID2_SOK != rtnVal)
841 {
842 break;
843 }
845 baseAddr = hndl->pInstObj->baseAddr;
846 if(((uint32_t)0x0 == (uint32_t)bufPtrs->cPortId[idx]) &&
847 (CAL_HAL_MODE_M2M == hndl->mode))
848 {
849 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_ADDR);
850 reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_ADDR_ADDR_MASK;
851 reg |= CSL_CAL_C2VID_RD_DMA_PIX_ADDR_ADDR_MASK &
852 bufPtrs->buffAddr[idx];
853 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_ADDR, reg);
855 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST);
856 reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK;
857 reg |= CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK &
858 bufPtrs->pitch[idx];
859 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST, reg);
860 }
862 if((CAL_HAL_MODE_M2M == hndl->mode) ||
863 (CAL_HAL_MODE_CAPTURE == hndl->mode))
864 {
865 reg = HW_RD_REG32(baseAddr +
866 CSL_CAL_WR_DMA_WR_DMA_ADDR(bufPtrs->wrDmaCtx
867 [idx]));
868 reg &= ~CSL_CAL_WR_DMA_WR_DMA_ADDR_ADDR_MASK;
869 reg |= CSL_CAL_WR_DMA_WR_DMA_ADDR_ADDR_MASK &
870 bufPtrs->buffAddr[idx];
871 HW_WR_REG32(baseAddr +
872 CSL_CAL_WR_DMA_WR_DMA_ADDR(
873 bufPtrs->wrDmaCtx[idx]), reg);
874 }
875 }
876 }
877 }
878 }
880 return (rtnVal);
881 }
883 /**************************Function Separator**********************************/
885 int32_t Cal_halRdDmaStart(Cal_HalHandle handle,
886 Cal_HalCtrlProcMode_t procMode,
887 void *arg)
888 {
889 int32_t rtnVal = FVID2_SOK;
890 volatile uint32_t reg;
891 Cal_HalInstObj_t *pInstObj;
892 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
894 if(NULL == hndl)
895 {
896 rtnVal = FVID2_EBADARGS;
897 }
899 if((FVID2_SOK == rtnVal) && (NULL == hndl->pInstObj))
900 {
901 rtnVal = FVID2_EBADARGS;
902 }
904 if(FVID2_SOK == rtnVal)
905 {
906 pInstObj = hndl->pInstObj;
908 rtnVal = FVID2_EAGAIN;
910 reg = HW_RD_REG32(pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
911 if(CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK != (reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK))
912 {
913 reg |= CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK;
914 rtnVal = FVID2_SOK;
915 HW_WR_REG32(pInstObj->baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
916 }
917 }
919 return rtnVal;
920 }
922 /**************************Function Separator**********************************/
924 int32_t Cal_halControl(Cal_HalHandle handle,
925 uint32_t cmd,
926 void *cmdArgs,
927 void *arg)
928 {
929 Cal_HalInstObj_t *pInstObj;
930 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
932 int32_t rtnVal = FVID2_SOK;
934 if(NULL == hndl)
935 {
936 rtnVal = FVID2_EBADARGS;
937 }
939 if((FVID2_SOK == rtnVal) && (NULL != hndl->pInstObj))
940 {
941 pInstObj = hndl->pInstObj;
942 }
943 else
944 {
945 rtnVal = FVID2_EBADARGS;
946 }
948 if((FVID2_SOK == rtnVal) && (0U == pInstObj->baseAddr))
949 {
950 rtnVal = FVID2_EBADARGS;
951 }
953 if((FVID2_SOK == rtnVal) && (0x0 == pInstObj->openCnt))
954 {
955 rtnVal = FVID2_EFAIL;
956 }
958 if(FVID2_SOK == rtnVal)
959 {
960 switch(cmd)
961 {
962 case IOCTL_CAL_HAL_UPDATE_BUFFERS:
963 rtnVal = FVID2_EBADARGS;
964 break;
966 case IOCTL_CAL_HAL_RD_FMT_UPDATE:
967 rtnVal = CalSetRdDmaFrameCfg(pInstObj, (Fvid2_Format *)cmdArgs);
968 break;
970 case IOCTL_CAL_HAL_START:
971 rtnVal = Cal_halCaptureStart (handle, cmdArgs);
972 break;
974 case IOCTL_CAL_HAL_STOP:
975 rtnVal = Cal_halCaptureStop (handle, cmdArgs);
976 break;
978 case IOCTL_CAL_HAL_SETCFG:
979 if(NULL != cmdArgs)
980 {
981 rtnVal = CalSetCfg(hndl, (Cal_HalCfg_t *) cmdArgs);
982 }
983 else
984 {
985 rtnVal = FVID2_EBADARGS;
986 }
987 break;
989 case IOCTL_CAL_HAL_GET_INSTANCECFG:
990 if(NULL != cmdArgs)
991 {
992 memcpy((void *) cmdArgs,
993 (const void *) &hndl->pInstObj->instCfg,
994 sizeof(Cal_HalInstCfg_t));
995 }
996 else
997 {
998 rtnVal = FVID2_EBADARGS;
999 }
1000 break;
1002 case IOCTL_CAL_HAL_SET_INSTANCECFG:
1003 if(NULL != cmdArgs)
1004 {
1005 rtnVal = CalResetApplyInstConfig(
1006 hndl,
1007 (Cal_HalInstCfg_t *)
1008 cmdArgs,
1009 hndl->mode,
1010 (uint32_t)TRUE);
1012 if(FVID2_SOK == rtnVal)
1013 {
1014 memcpy((void *) & hndl->pInstObj->instCfg,
1015 (const void *) cmdArgs,
1016 sizeof(Cal_HalInstCfg_t));
1017 }
1018 }
1019 else
1020 {
1021 rtnVal = FVID2_EBADARGS;
1022 }
1023 break;
1024 case IOCTL_CAL_HAL_SET_VPORT_CFG:
1025 if(NULL != cmdArgs)
1026 {
1027 rtnVal = CalSetVportCfg(
1028 hndl->pInstObj,
1029 (Cal_VPort_t *) cmdArgs,
1030 *(uint32_t *) arg);
1031 }
1032 else
1033 {
1034 rtnVal = FVID2_EBADARGS;
1035 }
1036 break;
1037 case IOCTL_CAL_HAL_SET_BYSOUT_CFG:
1038 if(NULL != cmdArgs)
1039 {
1040 rtnVal = CalSetBysOutCfg(
1041 hndl->pInstObj,
1042 (Cal_BysOut_t *) cmdArgs,
1043 *(uint32_t *) arg);
1044 }
1045 else
1046 {
1047 rtnVal = FVID2_EBADARGS;
1048 }
1049 break;
1051 case IOCTL_CAL_HAL_LINE_EVENT_CFG:
1052 if(NULL != cmdArgs)
1053 {
1054 rtnVal = CalSetLineEventCfg(hndl->pInstObj,
1055 (Cal_HalLineEventCfg_t *) cmdArgs);
1056 }
1057 else
1058 {
1059 rtnVal = FVID2_EBADARGS;
1060 }
1061 break;
1063 default:
1064 rtnVal = FVID2_EUNSUPPORTED_CMD;
1065 break;
1066 }
1067 }
1069 return (rtnVal);
1070 }
1072 uint32_t Cal_halIsBysOutEof(Cal_HalHandle handle)
1073 {
1074 uint32_t rtnVal = 0;
1075 uint32_t baseAddr;
1076 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
1078 if ((NULL == hndl) || (NULL == hndl->pInstObj) ||
1079 (0U == hndl->pInstObj->baseAddr) || (0x0 == hndl->pInstObj->openCnt))
1080 {
1081 rtnVal = 0;
1082 }
1083 else
1084 {
1085 baseAddr = hndl->pInstObj->baseAddr;
1086 rtnVal = (HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U)) &
1087 CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ3_MASK) >> CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ3_SHIFT;
1088 }
1090 return (rtnVal);
1091 }
1093 void Cal_halClearVportEof(Cal_HalHandle handle)
1094 {
1095 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
1096 uint32_t baseAddr;
1097 uint32_t regVal;
1099 if ((NULL == hndl) || (NULL == hndl->pInstObj) ||
1100 (0U == hndl->pInstObj->baseAddr) || (0x0 == hndl->pInstObj->openCnt))
1101 {
1102 /* Do Nothing */
1103 }
1104 else
1105 {
1106 baseAddr = hndl->pInstObj->baseAddr;
1107 regVal = HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U));
1108 regVal |= CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_MASK;
1109 HW_WR_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U), regVal);
1110 }
1111 }
1113 uint32_t Cal_halIsVportEof(Cal_HalHandle handle)
1114 {
1115 uint32_t rtnVal = 0;
1116 Cal_HalObj_t *hndl = (Cal_HalObj_t *) handle;
1117 uint32_t baseAddr;
1119 if ((NULL == hndl) || (NULL == hndl->pInstObj) ||
1120 (0U == hndl->pInstObj->baseAddr) || (0x0 == hndl->pInstObj->openCnt))
1121 {
1122 rtnVal = 0;
1123 }
1124 else
1125 {
1126 baseAddr = hndl->pInstObj->baseAddr;
1127 rtnVal = (HW_RD_REG32(baseAddr + CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW(0U)) &
1128 CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_MASK) >> CSL_CAL_C2IRQ_HL_IRQSTATUS_RAW_IRQ2_SHIFT;
1129 }
1131 return (rtnVal);
1132 }
1134 static Cal_HalPlatformData_t gCalHalPlatformData =
1135 {(CSL_CAL_PER_CNT), NULL};
1137 Cal_HalPlatformData_t *Cal_halGetPlatformData(void)
1138 {
1139 Cal_HalPlatformData_t *platData = NULL;
1141 {
1142 gCalHalPlatformData.calInstPrms = &gCalHalInstParams[0U];
1143 platData = &gCalHalPlatformData;
1144 }
1145 return (platData);
1146 }
1148 /**************************Function Separator**********************************/
1150 static int32_t CalReset(uint32_t baseAddr)
1151 {
1152 int32_t rtnVal = FVID2_SOK;
1153 volatile uint32_t reg, timeOut;
1155 GT_assert(CalTrace, (0U != baseAddr));
1156 timeOut = 0xFFFFU;
1157 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG);
1159 reg &= ~((uint32_t) CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_MASK);
1160 reg |= CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_MASK & ((uint32_t) CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_NO <<
1161 CSL_CAL_C2CTL_HL_SYSCONFIG_IDLEMODE_SHIFT);
1163 reg |= CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK;
1164 HW_WR_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG, reg);
1166 while(timeOut)
1167 {
1168 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2CTL_HL_SYSCONFIG);
1169 if(CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK !=
1170 (reg & CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK))
1171 {
1172 break;
1173 }
1175 timeOut--;
1176 }
1178 /* If reset is not done, timeOut will be zero, so only one
1179 condition check required here
1180 If reset is done, this condition is anyway false. */
1181 if((reg & CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK) ==
1182 CSL_CAL_C2CTL_HL_SYSCONFIG_SOFTRESET_MASK)
1183 {
1184 /* Reset did not complete. We would require an PRCM reset now! */
1185 rtnVal = FVID2_ETIMEOUT;
1186 }
1187 return rtnVal;
1188 }
1190 /**************************Function Separator**********************************/
1192 static int32_t CalCfgInstWrDma(
1193 uint32_t baseAddr, const Cal_HalInstCfg_t *pCfg)
1194 {
1195 volatile uint32_t reg;
1196 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_CTRL);
1197 reg &= ~(CSL_CAL_C2VID_CTRL_POSTED_WRITES_MASK | CSL_CAL_C2VID_CTRL_TAGCNT_MASK |
1198 CSL_CAL_C2VID_CTRL_BURSTSIZE_MASK | CSL_CAL_C2VID_CTRL_MFLAGL_MASK |
1199 CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK | CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK |
1200 CSL_CAL_C2VID_CTRL_MFLAGH_MASK);
1202 reg |= CSL_CAL_C2VID_CTRL_MFLAGH_MASK & (pCfg->mFlagH << CSL_CAL_C2VID_CTRL_MFLAGH_SHIFT);
1204 if((uint32_t)TRUE == pCfg->rdDmaStall)
1205 {
1206 reg |= CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK;
1207 }
1209 if((uint32_t)TRUE == pCfg->pwrScpClk)
1210 {
1211 reg |= CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK;
1212 }
1214 reg |= CSL_CAL_C2VID_CTRL_MFLAGL_MASK & (pCfg->mFlagL << CSL_CAL_C2VID_CTRL_MFLAGL_SHIFT);
1216 reg |= CSL_CAL_C2VID_CTRL_BURSTSIZE_MASK &
1217 (pCfg->dmaBurstSize << CSL_CAL_C2VID_CTRL_BURSTSIZE_SHIFT);
1219 reg |= CSL_CAL_C2VID_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CSL_CAL_C2VID_CTRL_TAGCNT_SHIFT);
1221 if((uint32_t)TRUE == pCfg->postedWrites)
1222 {
1223 reg |= CSL_CAL_C2VID_CTRL_POSTED_WRITES_MASK;
1224 }
1226 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_CTRL, reg);
1228 return FVID2_SOK;
1229 }
1231 /**************************Function Separator**********************************/
1233 static int32_t CalCfgInstLanePpiCfg(uint32_t baseAddr, Cal_HalInstCfg_t *pCfg)
1234 {
1235 uint32_t offset, idx;
1236 volatile uint32_t reg;
1237 Cal_CmplxIoCfg_t *pCmplxIoCfg;
1238 int32_t rtnVal = FVID2_SOK;
1240 GT_assert(CalTrace, (NULL != pCfg));
1241 GT_assert(CalTrace, (CSL_CAL_PPI_CNT >= pCfg->numPpiInst));
1242 GT_assert(CalTrace, (CSL_CAL_CMPLXIO_CNT >= pCfg->numCmplxIoInst));
1244 /* Lane Config */
1245 offset = 0x0;
1246 for(idx = 0; idx < pCfg->numCmplxIoInst; idx++)
1247 {
1248 pCmplxIoCfg = &pCfg->cmplxIoCfg[idx];
1250 /* Setup the polarity of lanes */
1251 if((uint32_t)TRUE == pCmplxIoCfg->enable)
1252 {
1253 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
1254 reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK |
1255 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK |
1256 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK |
1257 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK |
1258 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK);
1259 reg &= ~(CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK |
1260 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK |
1261 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK |
1262 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK |
1263 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK);
1264 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK &
1265 pCmplxIoCfg->clockLane.position;
1266 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK &
1267 (pCmplxIoCfg->data1Lane.position <<
1268 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POSITION_SHIFT);
1269 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK &
1270 (pCmplxIoCfg->data2Lane.position <<
1271 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POSITION_SHIFT);
1272 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK &
1273 (pCmplxIoCfg->data3Lane.position <<
1274 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POSITION_SHIFT);
1275 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK &
1276 (pCmplxIoCfg->data4Lane.position <<
1277 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POSITION_SHIFT);
1279 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK &
1280 (pCmplxIoCfg->clockLane.pol <<
1281 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_CLOCK_POL_SHIFT);
1282 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK &
1283 (pCmplxIoCfg->data1Lane.pol <<
1284 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA1_POL_SHIFT);
1285 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK &
1286 (pCmplxIoCfg->data2Lane.pol <<
1287 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA2_POL_SHIFT);
1288 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK &
1289 (pCmplxIoCfg->data3Lane.pol <<
1290 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA3_POL_SHIFT);
1291 reg |= CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK &
1292 (pCmplxIoCfg->data4Lane.pol <<
1293 CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG_DATA4_POL_SHIFT);
1294 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx), reg);
1296 /* Dummy read to wait for SCP write to complete */
1297 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_COMPLEXIO_CFG(idx));
1298 }
1299 }
1300 /* PPI Config */
1301 offset = 0x0;
1302 for(idx = 0; idx < pCfg->numPpiInst; idx++)
1303 {
1304 if((uint32_t)FALSE != pCfg->ppiCfg[idx].enable)
1305 {
1306 offset = pCfg->ppiCfg[idx].instance;
1307 if(CSL_CAL_PPI_CNT < offset)
1308 {
1309 rtnVal = FVID2_EBADARGS;
1310 break;
1311 }
1313 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
1314 reg &= ~((uint32_t) (CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK |
1315 CSL_CAL_C2PPI_CSI2_PPI_CTRL_FRAME_MASK |
1316 CSL_CAL_C2PPI_CSI2_PPI_CTRL_ECC_EN_MASK));
1318 if((uint32_t)TRUE == pCfg->ppiCfg[idx].ecc)
1319 {
1320 reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_ECC_EN_MASK;
1321 }
1322 if((uint32_t)TRUE == pCfg->ppiCfg[idx].frame)
1323 {
1324 reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_FRAME_MASK;
1325 }
1326 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset), reg);
1328 #ifndef ENABLE_PPI_WHEN_STARTING
1329 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset));
1330 reg |= CSL_CAL_C2PPI_CSI2_PPI_CTRL_IF_EN_MASK;
1331 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_PPI_CTRL(offset), reg);
1332 #endif /* ENABLE_PPI_WHEN_STARTING */
1333 }
1334 }
1335 return (rtnVal);
1336 }
1338 /**************************Function Separator**********************************/
1340 static int32_t CalResetApplyInstConfig(const Cal_HalObj_t *pHndl,
1341 Cal_HalInstCfg_t *pCfg,
1342 Cal_HalMode_t mode,
1343 uint32_t enPhy)
1344 {
1345 int32_t rtnVal = FVID2_SOK;
1346 Cal_HalInstObj_t *pInst = NULL;
1347 volatile uint32_t reg, baseAddr;
1349 GT_assert(CalTrace, (NULL != pHndl));
1350 GT_assert(CalTrace, (NULL != pCfg));
1351 GT_assert(CalTrace, (NULL != pHndl->pInstObj));
1353 pInst = pHndl->pInstObj;
1354 GT_assert(CalTrace, (0U != pInst->baseAddr));
1355 baseAddr = pInst->baseAddr;
1357 /* In Case of M2M mode,
1358 * . Reset CAL
1359 * . Apply M2M specifics
1360 * In Case of capture via CSI2 / LVDS (CPI)
1361 * . Reset CAL
1362 * . Configure generic CAL / DMA write config
1363 * . Configure lane and PPI
1364 * . Enable Clock to PHY and Reset the same
1365 */
1366 /* . Reset CAL */
1367 rtnVal = CalReset(baseAddr);
1368 /* . Apply M2M config */
1369 if((FVID2_SOK == rtnVal) && (CAL_HAL_MODE_M2M == mode))
1370 {
1371 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_CTRL);
1372 reg &= ~(CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK | CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK |
1373 CSL_CAL_C2VID_CTRL_TAGCNT_MASK);
1375 if((uint32_t)TRUE == pCfg->rdDmaStall)
1376 {
1377 reg |= CSL_CAL_C2VID_CTRL_RD_DMA_STALL_MASK;
1378 }
1379 if((uint32_t)TRUE == pCfg->pwrScpClk)
1380 {
1381 reg |= CSL_CAL_C2VID_CTRL_PWRSCPCLK_MASK;
1382 }
1384 reg |= CSL_CAL_C2VID_CTRL_TAGCNT_MASK & (pCfg->tagCnt << CSL_CAL_C2VID_CTRL_TAGCNT_SHIFT);
1386 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_CTRL, reg);
1387 }
1388 else if(CAL_HAL_MODE_CAPTURE == mode)
1389 {
1390 GT_assert(CalTrace, (0U != pInst->phy0BaseAddress));
1391 /* Important to configure RD DMA stall config, as m2m mode will not be
1392 * worried about this, but write will definitely be */
1393 rtnVal = CalCfgInstWrDma(baseAddr, pCfg);
1395 if(FVID2_SOK == rtnVal)
1396 {
1397 rtnVal = CalCfgInstLanePpiCfg(baseAddr, pCfg);
1398 }
1400 if((FVID2_SOK == rtnVal) && ((uint32_t)TRUE == enPhy))
1401 {
1402 rtnVal = Cal_halPhyEnClockAndReset(baseAddr,
1403 pInst->phy0BaseAddress,
1404 pInst->phy1BaseAddress,
1405 pCfg);
1406 }
1407 }
1408 else if(CAL_HAL_MODE_CMPLXIO_CTRL == mode)
1409 {
1410 /* TBD */
1411 rtnVal = FVID2_EBADARGS;
1412 }
1413 else
1414 {
1415 rtnVal = FVID2_EBADARGS;
1416 }
1418 return (rtnVal);
1419 }
1421 /**************************Function Separator**********************************/
1423 static int32_t CalSetCfg(const Cal_HalObj_t *hndl, const Cal_HalCfg_t *cfg)
1424 {
1425 /*
1426 * .Configure Capture
1427 * .Configure M2M
1428 * .Configure Complex IO TODO TBD
1429 */
1430 int32_t rtnVal = FVID2_SOK;
1432 GT_assert(CalTrace, (NULL != hndl));
1433 GT_assert(CalTrace, (NULL != cfg));
1434 GT_assert(CalTrace, (NULL != hndl->pInstObj));
1436 if(0x0 == hndl->pInstObj->openCnt)
1437 {
1438 rtnVal = FVID2_EBADARGS;
1439 }
1441 if(FVID2_SOK == rtnVal)
1442 {
1443 if(CAL_HAL_MODE_CAPTURE == hndl->mode)
1444 {
1445 rtnVal = CalSetCfgForMode(hndl->pInstObj, cfg, hndl->mode);
1446 }
1447 else if(CAL_HAL_MODE_M2M == hndl->mode)
1448 {
1449 rtnVal = CalSetCfgForMode(hndl->pInstObj, cfg, hndl->mode);
1450 }
1451 else if(CAL_HAL_MODE_CMPLXIO_CTRL == hndl->mode)
1452 {
1453 GT_assert(CalTrace, ((uint32_t)FALSE));
1454 /* TODO TBD implement complex IO config apply */
1455 }
1456 else
1457 {
1458 /* Wrong mode, but why? */
1459 rtnVal = FVID2_EBADARGS;
1460 }
1461 }
1463 return FVID2_SOK;
1464 }
1466 /**************************Function Separator**********************************/
1468 static int32_t CalSetCfgForMode(const Cal_HalInstObj_t *pInst,
1469 const Cal_HalCfg_t *cfg,
1470 Cal_HalMode_t mode)
1471 {
1472 int32_t rtnVal = FVID2_SOK;
1473 uint32_t baseAddr, cId, idx;
1474 volatile uint32_t reg;
1475 Cal_HalDmaVcCfg_t *pDmaCfg = (Cal_HalDmaVcCfg_t *) cfg->pDmaVcCfg;
1477 GT_assert(CalTrace, (NULL != pInst));
1478 GT_assert(CalTrace, (NULL != cfg));
1479 GT_assert(CalTrace, (NULL != pDmaCfg));
1481 baseAddr = pInst->baseAddr;
1483 /* Ensure there are no pending reads */
1484 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
1485 if(((reg & CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK) == CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK) &&
1486 (CAL_HAL_MODE_M2M == mode))
1487 {
1488 rtnVal = FVID2_EAGAIN;
1489 }
1491 for(idx = 0; ((FVID2_SOK == rtnVal) && (idx < cfg->numCPortId)); idx++)
1492 {
1493 cId = cfg->cportId[idx];
1494 GT_assert(CalTrace, (CAL_CAPT_MAX_STREAMS > cId));
1496 if(((uint32_t)TRUE == pDmaCfg->isCsi2VcCfgValid[idx]) &&
1497 (CAL_HAL_MODE_CAPTURE == mode))
1498 {
1499 rtnVal = CalCsi2VcCfg(pInst, &pDmaCfg->csi2VcCfg[idx], cId);
1500 }
1501 if((uint32_t)TRUE == cfg->isPixProcCfgValid[idx])
1502 {
1503 rtnVal = CalSetPixProcCfg(pInst, &cfg->pixProcCfg[idx], cId);
1504 }
1505 if((uint32_t)TRUE == pDmaCfg->isWrDmaCfgValid[idx])
1506 {
1507 /* CFG WR DMA */
1508 rtnVal = CalSetWrDmaCfg(pInst, &pDmaCfg->wrDmaCfg[idx], cId);
1509 }
1510 if((uint32_t)TRUE == cfg->isBysOutCfgValid[idx])
1511 {
1512 /* CFG BYS Out */
1513 rtnVal = CalSetBysOutCfg(pInst, &cfg->bysOutCfg[idx], cId);
1514 }
1515 if((uint32_t)TRUE == cfg->isBysInCfgValid[idx])
1516 {
1517 /* CFG BYS In */
1518 if((uint32_t)TRUE == cfg->bysInEnable[idx])
1519 {
1520 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2);
1521 reg &= ~((uint32_t) CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTIN_MASK);
1522 reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTIN_MASK & cId;
1523 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2, reg);
1525 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
1526 reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_BYSINEN_MASK;
1527 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
1528 }
1529 else
1530 {
1531 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
1532 reg &= ~CSL_CAL_C2VID_BYS_CTRL1_BC1_BYSINEN_MASK;
1533 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
1534 }
1535 }
1536 if((uint32_t)TRUE == cfg->isVportCfgValid[idx])
1537 {
1538 /* CFG VP in */
1539 rtnVal = CalSetVportCfg(pInst, &cfg->vportCfg[idx], cId);
1540 }
1541 if((uint32_t)TRUE == pDmaCfg->isRdDmaCfgValid[idx])
1542 {
1543 /* CFG Read DMA */
1544 rtnVal = CalSetRdDmaCfg(pInst, &pDmaCfg->rdDmaCfg[idx], cId);
1545 }
1546 }
1548 return rtnVal;
1549 }
1551 /**************************Function Separator**********************************/
1553 static int32_t CalCsi2VcCfg(const Cal_HalInstObj_t *pInst,
1554 const Cal_HalCsi2VcCfg_t *cfg,
1555 uint32_t cportId)
1556 {
1557 int32_t rtnVal = FVID2_SOK;
1558 uint32_t baseAddr, instance, context;
1559 volatile uint32_t reg;
1561 GT_assert(CalTrace, (NULL != pInst));
1562 GT_assert(CalTrace, (NULL != cfg));
1564 baseAddr = pInst->baseAddr;
1565 instance = cfg->instance;
1566 context = cfg->contextToBeUsed;
1567 GT_assert(CalTrace, (CAL_CAPT_MAX_STREAMS > context));
1568 GT_assert(CalTrace, ((0x0U == instance) || (0x1U == instance)));
1570 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_CTX0(instance) + (context * 4U));
1572 reg &= ~(CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_MASK |
1573 CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_MASK |
1574 CSL_CAL_C2PPI_CSI2_CTX0_CTX0_PACK_MODE_MASK | CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_MASK);
1576 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_MASK & (cfg->lines << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_LINES_SHIFT);
1578 /* TODO Remove the hard-coding, get appropriate macros */
1579 if((cfg->dt < 0x17) && (cfg->dt != 0x1))
1580 {
1581 /* When receiving non-pixel data would be packed between FS and FE.
1582 * no notion of LS & LE.
1583 * else
1584 * Pixel typically line boundaries is specified. Data is packed between
1585 * LS & LE.
1586 */
1587 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_PACK_MODE_MASK;
1588 }
1590 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_MASK & (cfg->att << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_ATT_SHIFT);
1591 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_MASK & (cportId << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_CPORT_SHIFT);
1592 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_MASK & (cfg->virtualChanNum <<
1593 CSL_CAL_C2PPI_CSI2_CTX0_CTX0_VC_SHIFT);
1594 reg |= CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_MASK & (cfg->dt << CSL_CAL_C2PPI_CSI2_CTX0_CTX0_DT_SHIFT);
1596 HW_WR_REG32(baseAddr + CSL_CAL_C2PPI_CSI2_CTX0(instance) + (context * 4U), reg);
1597 return (rtnVal);
1598 }
1600 /**************************Function Separator**********************************/
1602 static int32_t CalSetPixProcCfg(const Cal_HalInstObj_t *pInst,
1603 const Cal_PixProc_t *cfg, uint32_t cportId)
1604 {
1605 int32_t rtnVal = FVID2_SOK;
1606 uint32_t baseAddr, context;
1607 uint32_t extract;
1608 volatile uint32_t reg;
1610 GT_assert(CalTrace, (NULL != pInst));
1611 GT_assert(CalTrace, (NULL != cfg));
1613 baseAddr = pInst->baseAddr;
1614 context = cfg->contextToBeUsed;
1615 extract = cfg->extract;
1616 extract--;
1618 if(context >= CSL_CAL_PIX_PROC_CTX_CNT)
1619 {
1620 rtnVal = FVID2_EINVALID_PARAMS;
1621 }
1622 else
1623 {
1624 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
1625 reg &= ~((uint32_t) CSL_CAL_C2PIX_PIX_PROC_EN_MASK);
1626 HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
1628 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
1629 reg &= ~(CSL_CAL_C2PIX_PIX_PROC_EXTRACT_MASK | CSL_CAL_C2PIX_PIX_PROC_DPCMD_MASK |
1630 CSL_CAL_C2PIX_PIX_PROC_DPCME_MASK | CSL_CAL_C2PIX_PIX_PROC_PACK_MASK |
1631 CSL_CAL_C2PIX_PIX_PROC_CPORT_MASK);
1633 GT_assert(CalTrace, (CAL_PIX_EXRCT_MIN != cfg->extract));
1634 GT_assert(CalTrace, (CAL_PIX_EXRCT_MAX >= cfg->extract));
1635 reg |= CSL_CAL_C2PIX_PIX_PROC_EXTRACT_MASK &
1636 ((extract) << CSL_CAL_C2PIX_PIX_PROC_EXTRACT_SHIFT);
1638 reg |= CSL_CAL_C2PIX_PIX_PROC_DPCMD_MASK &
1639 (cfg->decCodec << CSL_CAL_C2PIX_PIX_PROC_DPCMD_SHIFT);
1641 reg |= CSL_CAL_C2PIX_PIX_PROC_DPCME_MASK &
1642 (cfg->encCodec << CSL_CAL_C2PIX_PIX_PROC_DPCME_SHIFT);
1644 reg |= CSL_CAL_C2PIX_PIX_PROC_PACK_MASK & (cfg->pack << CSL_CAL_C2PIX_PIX_PROC_PACK_SHIFT);
1645 reg |= CSL_CAL_C2PIX_PIX_PROC_CPORT_MASK & (cportId << CSL_CAL_C2PIX_PIX_PROC_CPORT_SHIFT);
1647 HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
1649 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
1650 if((uint32_t)TRUE == cfg->enableDpcmInitContext)
1651 {
1652 reg |= CSL_CAL_C2VID_RD_DMA_CTRL_INIT_MASK;
1653 GT_assert(CalTrace, (0U != cfg->addr));
1654 }
1655 else
1656 {
1657 reg &= ~((uint32_t) CSL_CAL_C2VID_RD_DMA_CTRL_INIT_MASK);
1658 }
1659 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
1661 if((uint32_t)TRUE == cfg->enableDpcmInitContext)
1662 {
1663 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_ADDR);
1664 reg &= ~CSL_CAL_C2VID_RD_DMA_INIT_ADDR_DIA_ADDR_MASK;
1665 reg |= CSL_CAL_C2VID_RD_DMA_INIT_ADDR_DIA_ADDR_MASK & cfg->addr;
1666 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_ADDR, reg);
1668 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_OFST);
1669 reg &= ~CSL_CAL_C2VID_RD_DMA_INIT_OFST_DIO_OFST_MASK;
1670 reg |= CSL_CAL_C2VID_RD_DMA_INIT_OFST_DIO_OFST_MASK & cfg->offSet;
1671 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_INIT_OFST, reg);
1672 }
1674 /* Enable Pixel Processing, as a last step */
1675 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context));
1676 reg |= CSL_CAL_C2PIX_PIX_PROC_EN_MASK;
1677 HW_WR_REG32(baseAddr + CSL_CAL_C2PIX_PIX_PROC(context), reg);
1678 }
1680 return rtnVal;
1681 }
1683 /**************************Function Separator**********************************/
1685 static int32_t CalSetBysOutCfg(const Cal_HalInstObj_t *pInst,
1686 const Cal_BysOut_t *cfg, uint32_t cportId)
1687 {
1688 uint32_t baseAddr;
1689 volatile uint32_t reg;
1691 GT_assert(CalTrace, (NULL != pInst));
1692 GT_assert(CalTrace, (NULL != cfg));
1694 baseAddr = pInst->baseAddr;
1695 GT_assert(CalTrace, (0U != baseAddr));
1697 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1);
1698 reg &= ~CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_MASK;
1699 if((uint32_t)TRUE == cfg->enable)
1700 {
1701 reg &= ~(CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_MASK | CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK);
1703 reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_MASK &
1704 (cfg->pixClock << CSL_CAL_C2VID_BYS_CTRL1_BC1_PCLK_SHIFT);
1706 reg |= CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_MASK &
1707 (cfg->xBlk << CSL_CAL_C2VID_BYS_CTRL1_BC1_XBLK_SHIFT);
1709 reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK &
1710 (cfg->yBlk << CSL_CAL_C2VID_BYS_CTRL1_BC1_YBLK_SHIFT);
1711 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
1713 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2);
1714 reg &= ~((uint32_t) (CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_MASK |
1715 CSL_CAL_C2VID_BYS_CTRL2_BC2_DUPLICATEDDATA_MASK |
1716 CSL_CAL_C2VID_BYS_CTRL2_BC2_FREERUNNING_MASK));
1717 if((uint32_t)TRUE == cfg->freeRun)
1718 {
1719 reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_FREERUNNING_MASK;
1720 }
1722 if((uint32_t)TRUE == cfg->copyStreamToEncode)
1723 {
1724 reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_DUPLICATEDDATA_MASK;
1725 }
1727 reg |= CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_MASK &
1728 (cportId << CSL_CAL_C2VID_BYS_CTRL2_BC2_CPORTOUT_SHIFT);
1730 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL2, reg);
1731 }
1732 else
1733 {
1734 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_BYS_CTRL1, reg);
1735 }
1737 return FVID2_SOK;
1738 }
1740 /**************************Function Separator**********************************/
1742 static int32_t CalSetVportCfg(const Cal_HalInstObj_t *pInst,
1743 const Cal_VPort_t *cfg,
1744 uint32_t cportId)
1745 {
1746 uint32_t baseAddr;
1747 volatile uint32_t reg;
1749 GT_assert(CalTrace, (NULL != pInst));
1750 GT_assert(CalTrace, (NULL != cfg));
1752 baseAddr = pInst->baseAddr;
1753 GT_assert(CalTrace, (0U != baseAddr));
1755 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1);
1756 reg &= ~CSL_CAL_C2VID_VPORT_CTRL1_VC1_PCLK_MASK;
1757 if((uint32_t)TRUE == cfg->enable)
1758 {
1759 reg &= ~(CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_MASK | CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK |
1760 CSL_CAL_C2VID_VPORT_CTRL1_VC1_WIDTH_MASK);
1762 reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_PCLK_MASK & cfg->pixClock;
1764 reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_MASK &
1765 (cfg->xBlk << CSL_CAL_C2VID_VPORT_CTRL1_VC1_XBLK_SHIFT);
1767 reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_MASK &
1768 (cfg->yBlk << CSL_CAL_C2VID_VPORT_CTRL1_VC1_YBLK_SHIFT);
1770 if(0x0U != cfg->width)
1771 {
1772 reg |= CSL_CAL_C2VID_VPORT_CTRL1_VC1_WIDTH_MASK;
1773 }
1774 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1, reg);
1776 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL2);
1777 reg &=
1778 ~(CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_MASK | CSL_CAL_C2VID_VPORT_CTRL2_VC2_FSM_RESET_MASK |
1779 CSL_CAL_C2VID_VPORT_CTRL2_VC2_FS_RESETS_MASK |
1780 CSL_CAL_C2VID_VPORT_CTRL2_VC2_FREERUNNING_MASK |
1781 CSL_CAL_C2VID_VPORT_CTRL2_VC2_CPORT_MASK);
1783 reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_CPORT_MASK & cportId;
1785 if((uint32_t)TRUE == cfg->freeRun)
1786 {
1787 reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_FREERUNNING_MASK;
1788 }
1790 if((uint32_t)TRUE == cfg->fsReset)
1791 {
1792 reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_FS_RESETS_MASK;
1793 }
1795 reg |= CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_MASK &
1796 (cfg->rdyThr << CSL_CAL_C2VID_VPORT_CTRL2_VC2_RDY_THR_SHIFT);
1798 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL2, reg);
1799 }
1800 else
1801 {
1802 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_VPORT_CTRL1, reg);
1803 }
1805 return FVID2_SOK;
1806 }
1808 /**************************Function Separator**********************************/
1810 static int32_t CalSetRdDmaCfg(const Cal_HalInstObj_t *pInst,
1811 const Cal_HalRdDmaCfg_t *cfg,
1812 uint32_t cportId)
1813 {
1814 uint32_t baseAddr;
1815 volatile uint32_t reg;
1817 GT_assert(CalTrace, (NULL != pInst));
1818 GT_assert(CalTrace, (NULL != cfg));
1820 baseAddr = pInst->baseAddr;
1821 GT_assert(CalTrace, (0U != baseAddr));
1823 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL);
1824 reg &= ~CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_MASK;
1826 if((uint32_t)TRUE == cfg->enable)
1827 {
1828 reg &= ~((uint32_t) (CSL_CAL_C2VID_RD_DMA_CTRL_GO_MASK |
1829 CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_MASK |
1830 CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_MASK));
1832 reg |= CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_MASK &
1833 (cfg->bwLimit << CSL_CAL_C2VID_RD_DMA_CTRL_BW_LIMITER_SHIFT);
1835 reg |= CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_MASK &
1836 (cfg->ocpTagCnt << CSL_CAL_C2VID_RD_DMA_CTRL_OCP_TAG_CNT_SHIFT);
1838 reg |= CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_MASK &
1839 (cfg->pixClock << CSL_CAL_C2VID_RD_DMA_CTRL_PCLK_SHIFT);
1841 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
1843 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL2);
1845 reg &= ~(CSL_CAL_C2VID_RD_DMA_CTRL2_CIRC_MODE_MASK |
1846 CSL_CAL_C2VID_RD_DMA_CTRL2_CIRC_SIZE_MASK |
1847 CSL_CAL_C2VID_RD_DMA_CTRL2_ICM_CSTART_MASK |
1848 CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_MASK |
1849 CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK);
1850 reg |= CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK &
1851 (cfg->bysOutLeWait << CSL_CAL_C2VID_RD_DMA_CTRL2_BYSOUT_LE_WAIT_SHIFT);
1853 reg |= CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_MASK &
1854 (cfg->ySkipMode << CSL_CAL_C2VID_RD_DMA_CTRL2_RD_PATTERN_SHIFT);
1856 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL2, reg);
1858 CalSetRdDmaFrameCfg(pInst, &cfg->format);
1859 }
1860 else
1861 {
1862 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_CTRL, reg);
1863 }
1864 return FVID2_SOK;
1865 }
1867 /**************************Function Separator**********************************/
1869 static int32_t CalSetRdDmaFrameCfg(const Cal_HalInstObj_t *pInst,
1870 const Fvid2_Format *cfg)
1871 {
1872 uint32_t baseAddr;
1873 uint32_t hSize;
1874 volatile uint32_t reg;
1876 GT_assert(CalTrace, (NULL != pInst));
1877 GT_assert(CalTrace, (NULL != cfg));
1879 baseAddr = pInst->baseAddr;
1880 GT_assert(CalTrace, (0U != baseAddr));
1883 if ((int32_t) TRUE == Fvid2_isDataFmtRgb32bit(cfg->dataFormat))
1884 {
1885 hSize = ((cfg->width * 4U) / 8U);
1886 }
1887 else if ((int32_t) TRUE == Fvid2_isDataFmtRgb24bit(cfg->dataFormat))
1888 {
1889 hSize = ((cfg->width * 3U) / 8U);
1890 }
1891 else if ((int32_t) TRUE == Fvid2_isDataFmtRgb16bit(cfg->dataFormat))
1892 {
1893 hSize = ((cfg->width * 2U) / 8U);
1894 }
1895 else if((int32_t) TRUE == Fvid2_isDataFmtYuv422I(cfg->dataFormat))
1896 {
1897 if(FVID2_CCSF_BITS8_PACKED == cfg->ccsFormat)
1898 {
1899 hSize = ((cfg->width * 2U) / 8U);
1900 }
1901 else if((FVID2_CCSF_BITS10_UNPACKED16 == cfg->ccsFormat) ||
1902 (FVID2_CCSF_BITS12_UNPACKED16 == cfg->ccsFormat) ||
1903 (FVID2_CCSF_BITS16_PACKED == cfg->ccsFormat))
1904 {
1905 hSize = ((cfg->width * 4U) / 8U);
1906 }
1907 else
1908 {
1909 hSize = cfg->width / 8U;
1910 }
1911 }
1912 else
1913 {
1914 hSize = cfg->width / 8U;
1915 }
1917 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_XSIZE);
1918 reg &= ~CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK;
1919 /* Require to specify the number of 64 bits read, essentially
1920 * total bits / 64 or byte count / 8 */
1921 reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK & ((hSize) << CSL_CAL_C2VID_RD_DMA_XSIZE_XSIZE_SHIFT);
1922 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_XSIZE, reg);
1924 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_YSIZE);
1925 reg &= ~CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_MASK;
1926 reg |= CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_MASK & (cfg->height << CSL_CAL_C2VID_RD_DMA_YSIZE_YSIZE_SHIFT);
1927 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_YSIZE, reg);
1929 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST);
1930 reg &= ~CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK;
1931 reg |= (CSL_CAL_C2VID_RD_DMA_PIX_OFST_OFST_MASK & cfg->pitch[0U]);
1933 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_RD_DMA_PIX_OFST, reg);
1935 return FVID2_SOK;
1936 }
1939 /**************************Function Separator**********************************/
1941 /**
1942 * \brief Applies DMA Write configurations.
1943 *
1944 * \param pInst Pointer to instance object.
1945 * \param cfg Valid configuration for DMA Write.
1946 *
1947 * \return FVID2_SOK on success else error code.
1948 *
1949 **/
1950 static int32_t CalSetWrDmaCfg(const Cal_HalInstObj_t *pInst,
1951 const Cal_HalWrDmaCfg_t *cfg,
1952 uint32_t cportId)
1953 {
1954 uint32_t baseAddr, context;
1955 volatile uint32_t reg;
1957 GT_assert(CalTrace, (NULL != pInst));
1958 GT_assert(CalTrace, (NULL != cfg));
1960 baseAddr = pInst->baseAddr;
1961 context = cfg->contextToBeUsed;
1962 GT_assert(CalTrace, (0U != baseAddr));
1963 GT_assert(CalTrace, (CAL_CAPT_MAX_STREAMS > context));
1965 reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(context));
1966 reg &= ~(CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_MASK |
1967 CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_MASK |
1968 CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_MASK | CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK);
1970 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK & cfg->mode;
1972 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_MASK &
1973 (cfg->ySkipMode << CSL_CAL_WR_DMA_WR_DMA_CTRL_WR_PATTERN_SHIFT);
1975 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_MASK &
1976 (cfg->stream << CSL_CAL_WR_DMA_WR_DMA_CTRL_DTAG_SHIFT);
1978 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_MASK &
1979 (cportId << CSL_CAL_WR_DMA_WR_DMA_CTRL_CPORT_SHIFT);
1981 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_MASK &
1982 (cfg->stallM2MRd << CSL_CAL_WR_DMA_WR_DMA_CTRL_STALL_RD_DMA_SHIFT);
1984 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_MASK &
1985 (cfg->format.height << CSL_CAL_WR_DMA_WR_DMA_CTRL_YSIZE_SHIFT);
1986 HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(context), reg);
1988 reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_OFST(context));
1989 reg &= ~CSL_CAL_WR_DMA_WR_DMA_OFST_OFST_MASK;
1990 /* No support for circular mode as of now */
1991 reg &= ~(CSL_CAL_WR_DMA_WR_DMA_OFST_CIRC_MODE_MASK | CSL_CAL_WR_DMA_WR_DMA_OFST_CIRC_SIZE_MASK);
1992 /* Shifting is not required */
1993 reg |= CSL_CAL_WR_DMA_WR_DMA_OFST_OFST_MASK & cfg->format.pitch[0];
1994 HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_OFST(context), reg);
1996 reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_XSIZE(context));
1997 reg &= ~(CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK | CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_MASK);
1998 reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_MASK &
1999 (cfg->xPixelSkip << CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSKIP_SHIFT);
2001 reg |= CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_MASK &
2002 (cfg->format.width << CSL_CAL_WR_DMA_WR_DMA_XSIZE_XSIZE_SHIFT);
2003 HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_XSIZE(context), reg);
2005 return FVID2_SOK;
2006 }
2008 /**************************Function Separator**********************************/
2010 static int32_t calSetWrDmaMode(const Cal_HalInstObj_t *pInstObj,
2011 const Cal_HalDmaVcCfg_t *pDmaCfg)
2012 {
2013 volatile uint32_t reg;
2014 uint32_t baseAddr, instance, i;
2016 baseAddr = pInstObj->baseAddr;
2017 for(i = 0; i < pDmaCfg->numCPortId; i++)
2018 {
2019 if((uint32_t)TRUE == pDmaCfg->isWrDmaCfgValid[i])
2020 {
2021 instance = pDmaCfg->wrDmaCfg[i].contextToBeUsed;
2022 reg = HW_RD_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(instance));
2023 reg &= ~((uint32_t) CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK);
2025 reg |= CSL_CAL_WR_DMA_WR_DMA_CTRL_MODE_MASK &
2026 pDmaCfg->wrDmaCfg[i].mode;
2028 HW_WR_REG32(baseAddr + CSL_CAL_WR_DMA_WR_DMA_CTRL(instance), reg);
2029 }
2030 }
2032 return (FVID2_SOK);
2033 }
2035 /**************************Function Separator**********************************/
2037 static int32_t CalSetLineEventCfg(const Cal_HalInstObj_t *pInstObj,
2038 const Cal_HalLineEventCfg_t *plnEvtCfg)
2039 {
2040 volatile uint32_t reg;
2041 uint32_t baseAddr, cportId, i;
2043 baseAddr = pInstObj->baseAddr;
2044 for(i = 0; i < plnEvtCfg->numCPortId; i++)
2045 {
2046 cportId = plnEvtCfg->cportId[i];
2047 reg = HW_RD_REG32(baseAddr + CSL_CAL_C2VID_LINE_NUMBER_EVT);
2049 reg &= ~((uint32_t)CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_MASK);
2050 reg &= ~CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_MASK;
2052 reg |= CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_MASK &
2053 (cportId << CSL_CAL_C2VID_LINE_NUMBER_EVT_CPORT_SHIFT);
2055 reg |= CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_MASK &
2056 (plnEvtCfg->lineNumber[cportId] << CSL_CAL_C2VID_LINE_NUMBER_EVT_LINE_SHIFT);
2058 HW_WR_REG32(baseAddr + CSL_CAL_C2VID_LINE_NUMBER_EVT, reg);
2059 }
2060 return (FVID2_SOK);
2061 }
2063 /**************************Function Separator**********************************/