124a4a922759e2b7e91bed0f382e7a98d0797af2
1 /*
2 * hw_mcanss.h
3 *
4 * Register-level header file for MCANSS2P0
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35 #ifndef HW_MCANSS_H_
36 #define HW_MCANSS_H_
38 #include <ti/csl/csl_mcan.h>
39 #include <ti/csl/csl_soc.h>
41 #ifdef __cplusplus
42 extern "C"
43 {
44 #endif
48 /****************************************************************************************************
49 * User Definitions
50 ****************************************************************************************************/
51 /* MCAN IP related Macros */
52 #define MCAN_TX_BUFFER_MAX_NUM (32U)
53 #define MCAN_RX_BUFFER_MAX_NUM (64U)
54 #define MCAN_RX_FIFO_0_MAX_NUM (64U)
55 #define MCAN_RX_FIFO_1_MAX_NUM (64U)
57 /* TDA3xx - MCAL Related macros */
58 #define MCAN_TX_MB_MAX_NUM (32U)
59 #define MCAN_RX_MB_MAX_NUM (32U)
61 /****************************************************************************************************
62 * Register Definitions
63 ****************************************************************************************************/
64 /* Platform specific MCANA base address */
65 #define MCAN_BASE_ADDRESS (CSL_MSS_MCANA_CFG_U_BASE)
67 /* MCAN instance 0 offset */
68 #define MCAN_ECC_MEM_OFFSET (0xA7A000U)
69 #define MCAN_CFG_WRAP_OFFSET (0xA7C800U)
70 #define MCAN_CFG_CORE_OFFSET (0xA7CA00U)
72 /* MCAN instance 1 offset */
73 #define MCANB_ECC_MEM_OFFSET (CSL_MSS_MCANB_ECC_U_BASE - CSL_MSS_MCANA_ECC_U_BASE)
74 #define MCANB_CFG_WRAP_OFFSET (CSL_MSS_MCANB_CFG_U_BASE - CSL_MSS_MCANA_CFG_U_BASE)
75 #define MCANB_CFG_CORE_OFFSET (0xD9DE00U)
77 #define RAM_MEM_OFFSET (0x0U)
79 #define MCAN_MCANSS_PID(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
80 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x00) : \
81 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x00))
83 #define MCAN_MCANSS_CTRL(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
84 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x04U) : \
85 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x04U))
87 #define MCAN_MCANSS_STAT(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
88 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x08U) : \
89 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x08U))
91 #define MCAN_MCANSS_ICS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
92 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x0CU) : \
93 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x0CU))
95 #define MCAN_MCANSS_IRS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
96 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x10U) : \
97 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x10U))
99 #define MCAN_MCANSS_IECS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
100 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x14U) : \
101 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x14U))
103 #define MCAN_MCANSS_IE(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
104 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x18U) : \
105 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x18U))
107 #define MCAN_MCANSS_IES(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
108 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x1CU) : \
109 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x1CU))
111 #define MCAN_MCANSS_EOI(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
112 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x20U) : \
113 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x20U))
115 #define MCAN_MCANSS_EXT_TS_PRESCALER(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
116 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x24U) : \
117 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x24U))
119 #define MCAN_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
120 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x28U) : \
121 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x28U))
123 #define MCAN_ECC_EOI(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
124 (baseAddress + MCAN_CFG_WRAP_OFFSET + 0x80U) : \
125 (baseAddress + MCANB_CFG_WRAP_OFFSET + 0x80U))
127 #define MCAN_CREL(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
128 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x0U) : \
129 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x0U))
131 #define MCAN_ENDN(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
132 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x4U) : \
133 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x4U))
135 #define MCAN_CUST(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
136 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x8U) : \
137 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x8U))
139 #define MCAN_DBTP(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
140 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xCU) : \
141 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xCU))
143 #define MCAN_TEST(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
144 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x10U) : \
145 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x10U))
147 #define MCAN_RWD(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
148 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x14U) : \
149 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x14U))
151 #define MCAN_CCCR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
152 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x18U) : \
153 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x18U))
155 #define MCAN_NBTP(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
156 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x1cU) : \
157 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x1cU))
159 #define MCAN_TSCC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
160 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x20U) : \
161 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x20U))
163 #define MCAN_TSCV(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
164 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x24U) : \
165 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x24U))
167 #define MCAN_TOCC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
168 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x28U) : \
169 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x28U))
171 #define MCAN_TOCV(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
172 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x2cU) : \
173 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x2cU))
175 #define MCAN_ECR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
176 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x40U) : \
177 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x40U))
179 #define MCAN_PSR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
180 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x44U) : \
181 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x44U))
183 #define MCAN_TDCR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
184 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x48U) : \
185 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x48U))
187 #define MCAN_IR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
188 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x50U) : \
189 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x50U))
191 #define MCAN_IE(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
192 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x54U) : \
193 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x54U))
195 #define MCAN_ILS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
196 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x58U) : \
197 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x58U))
199 #define MCAN_ILE(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
200 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x5CU) : \
201 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x5CU))
203 #define MCAN_GFC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
204 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x80U) : \
205 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x80U))
207 #define MCAN_SIDFC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
208 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x84U) : \
209 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x84U))
211 #define MCAN_XIDFC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
212 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x88U) : \
213 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x88U))
215 #define MCAN_XIDAM(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
216 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x90U) : \
217 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x90U))
219 #define MCAN_HPMS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
220 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x94U) : \
221 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x94U))
223 #define MCAN_NDAT1(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
224 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x98U) : \
225 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x98U))
227 #define MCAN_NDAT2(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
228 (baseAddress + MCAN_CFG_CORE_OFFSET + 0x9CU) : \
229 (baseAddress + MCANB_CFG_CORE_OFFSET + 0x9CU))
231 #define MCAN_RXF0C(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
232 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xA0U) : \
233 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xA0U))
235 #define MCAN_RXF0S(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
236 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xA4U) : \
237 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xA4U))
239 #define MCAN_RXF0A(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
240 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xA8U) : \
241 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xA8U))
243 #define MCAN_RXBC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
244 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xACU) : \
245 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xACU))
247 #define MCAN_RXF1C(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
248 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xB0U) : \
249 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xB0U))
251 #define MCAN_RXF1S(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
252 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xB4U) : \
253 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xB4U))
255 #define MCAN_RXF1A(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
256 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xB8U) : \
257 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xB8U))
259 #define MCAN_RXESC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
260 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xBCU) : \
261 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xBCU))
263 #define MCAN_TXBC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
264 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xC0U) : \
265 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xC0U))
267 #define MCAN_TXFQS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
268 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xC4U) : \
269 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xC4U))
271 #define MCAN_TXESC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
272 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xC8U) : \
273 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xC8U))
275 #define MCAN_TXBRP(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
276 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xCCU) : \
277 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xCCU))
279 #define MCAN_TXBAR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
280 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xD0U) : \
281 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xD0U))
283 #define MCAN_TXBCR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
284 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xD4U) : \
285 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xD4U))
287 #define MCAN_TXBTO(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
288 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xD8U) : \
289 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xD8U))
291 #define MCAN_TXBCF(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
292 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xDCU) : \
293 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xDCU))
295 #define MCAN_TXBTIE(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
296 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xE0U) : \
297 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xE0U))
299 #define MCAN_TXBCIE(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
300 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xE4U) : \
301 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xE4U))
303 #define MCAN_TXEFC(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
304 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xF0U) : \
305 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xF0U))
307 #define MCAN_TXEFS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
308 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xF4U) : \
309 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xF4U))
311 #define MCAN_TXEFA(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
312 (baseAddress + MCAN_CFG_CORE_OFFSET + 0xF8U) : \
313 (baseAddress + MCANB_CFG_CORE_OFFSET + 0xF8U))
315 #define MCAN_ECC_AGGR_REVISION(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
316 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x0) : \
317 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x0))
319 #define MCAN_ECC_AGGR_VECTOR(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
320 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x08U) : \
321 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x08U))
323 #define MCAN_ECC_AGGR_MISC_STATUS(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
324 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x0CU) : \
325 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x0CU))
327 #define MCAN_ECC_AGGR_WRAP_REVISION(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
328 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x10U) : \
329 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x10U))
331 #define MCAN_ECC_AGGR_CONTROL(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
332 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x14U) : \
333 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x14U))
335 #define MCAN_ECC_AGGR_ERROR_CTRL1(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
336 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x18U) : \
337 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x18U))
339 #define MCAN_ECC_AGGR_ERROR_CTRL2(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
340 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x1CU) : \
341 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x1CU))
343 #define MCAN_ECC_AGGR_ERROR_STATUS1(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
344 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x20U) : \
345 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x20U))
347 #define MCAN_ECC_AGGR_ERROR_STATUS2(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
348 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x24U) : \
349 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x24U))
351 #define MCAN_ECC_AGGR_SEC_EOI_REG(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
352 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x3CU) : \
353 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x3CU))
355 #define MCAN_ECC_AGGR_SEC_STATUS_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
356 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x40U) : \
357 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x40U))
359 #define MCAN_ECC_AGGR_SEC_ENABLE_SET_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
360 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x80U) : \
361 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x80U))
363 #define MCAN_ECC_AGGR_SEC_ENABLE_CLR_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
364 (baseAddress + MCAN_ECC_MEM_OFFSET + 0xC0U) : \
365 (baseAddress + MCANB_ECC_MEM_OFFSET + 0xC0U))
367 #define MCAN_ECC_AGGR_DED_EOI_REG(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
368 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x13CU) : \
369 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x13CU))
371 #define MCAN_ECC_AGGR_DED_STATUS_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
372 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x140U) : \
373 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x140U))
375 #define MCAN_ECC_AGGR_DED_ENABLE_SET_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
376 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x180U) : \
377 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x180U))
379 #define MCAN_ECC_AGGR_DED_ENABLE_CLR_REG0(baseAddress) ((baseAddress) == MCAN_BASE_ADDRESS ? \
380 (baseAddress + MCAN_ECC_MEM_OFFSET + 0x1C0U) : \
381 (baseAddress + MCANB_ECC_MEM_OFFSET + 0x1C0U))
383 #define MCAN_MCAN_MSG_MEM (RAM_MEM_OFFSET)
386 /****************************************************************************************************
387 * Field Definition Macros
388 ****************************************************************************************************/
390 #define MCAN_MCANSS_PID_MINOR_SHIFT (0U)
391 #define MCAN_MCANSS_PID_MINOR_MASK (0x0000003fU)
393 #define MCAN_MCANSS_PID_CUSTOM_SHIFT (6U)
394 #define MCAN_MCANSS_PID_CUSTOM_MASK (0x000000c0U)
396 #define MCAN_MCANSS_PID_MAJOR_SHIFT (8U)
397 #define MCAN_MCANSS_PID_MAJOR_MASK (0x00000700U)
399 #define MCAN_MCANSS_PID_RTL_SHIFT (11U)
400 #define MCAN_MCANSS_PID_RTL_MASK (0x0000f800U)
402 #define MCAN_MCANSS_PID_MODULE_ID_SHIFT (16U)
403 #define MCAN_MCANSS_PID_MODULE_ID_MASK (0x0fff0000U)
405 #define MCAN_MCANSS_PID_BU_SHIFT (28U)
406 #define MCAN_MCANSS_PID_BU_MASK (0x30000000U)
408 #define MCAN_MCANSS_PID_SCHEME_SHIFT (30U)
409 #define MCAN_MCANSS_PID_SCHEME_MASK (0xc0000000U)
411 #define MCAN_MCANSS_CTRL_RESET_SHIFT (0U)
412 #define MCAN_MCANSS_CTRL_RESET_MASK (0x00000001U)
414 #define MCAN_MCANSS_CTRL_CLKFACK_SHIFT (1U)
415 #define MCAN_MCANSS_CTRL_CLKFACK_MASK (0x00000002U)
416 #define MCAN_MCANSS_CTRL_CLKFACK_DISABLE (0U)
417 #define MCAN_MCANSS_CTRL_CLKFACK_ENABLE (1U)
419 #define MCAN_MCANSS_CTRL_EMUFACK_SHIFT (2U)
420 #define MCAN_MCANSS_CTRL_EMUFACK_MASK (0x00000004U)
421 #define MCAN_MCANSS_CTRL_EMUFACK_DISABLE (0U)
422 #define MCAN_MCANSS_CTRL_EMUFACK_ENABLE (1U)
424 #define MCAN_MCANSS_CTRL_EMUEN_SHIFT (3U)
425 #define MCAN_MCANSS_CTRL_EMUEN_MASK (0x00000008U)
426 #define MCAN_MCANSS_CTRL_EMUEN_DISABLE (0U)
427 #define MCAN_MCANSS_CTRL_EMUEN_ENABLE (1U)
429 #define MCAN_MCANSS_CTRL_WAKEUPREQEN_SHIFT (4U)
430 #define MCAN_MCANSS_CTRL_WAKEUPREQEN_MASK (0x00000010U)
431 #define MCAN_MCANSS_CTRL_WAKEUPREQEN_DISABLE (0U)
432 #define MCAN_MCANSS_CTRL_WAKEUPREQEN_ENABLE (1U)
434 #define MCAN_MCANSS_CTRL_AUTOWAKEUP_SHIFT (5U)
435 #define MCAN_MCANSS_CTRL_AUTOWAKEUP_MASK (0x00000020U)
436 #define MCAN_MCANSS_CTRL_AUTOWAKEUP_DISABLE (0U)
437 #define MCAN_MCANSS_CTRL_AUTOWAKEUP_ENABLE (1U)
439 #define MCAN_MCANSS_CTRL_EXT_TS_CNTR_EN_SHIFT (6U)
440 #define MCAN_MCANSS_CTRL_EXT_TS_CNTR_EN_MASK (0x00000040U)
442 #define MCAN_MCANSS_STAT_RESET_SHIFT (0U)
443 #define MCAN_MCANSS_STAT_RESET_MASK (0x00000001U)
445 #define MCAN_MCANSS_STAT_MEM_INIT_DONE_SHIFT (1U)
446 #define MCAN_MCANSS_STAT_MEM_INIT_DONE_MASK (0x00000002U)
448 #define MCAN_MCANSS_STAT_ENABLE_FDOE_SHIFT (2U)
449 #define MCAN_MCANSS_STAT_ENABLE_FDOE_MASK (0x00000004U)
451 #define MCAN_MCANSS_ICS_EXT_TS_CNTR_OVFL_SHIFT (0U)
452 #define MCAN_MCANSS_ICS_EXT_TS_CNTR_OVFL_MASK (0x00000001U)
454 #define MCAN_MCANSS_IRS_EXT_TS_CNTR_OVFL_SHIFT (0U)
455 #define MCAN_MCANSS_IRS_EXT_TS_CNTR_OVFL_MASK (0x00000001U)
457 #define MCAN_MCANSS_IECS_EXT_TS_CNTR_OVFL_SHIFT (0U)
458 #define MCAN_MCANSS_IECS_EXT_TS_CNTR_OVFL_MASK (0x00000001U)
460 #define MCAN_MCANSS_IE_EXT_TS_CNTR_OVFL_SHIFT (0U)
461 #define MCAN_MCANSS_IE_EXT_TS_CNTR_OVFL_MASK (0x00000001U)
463 #define MCAN_MCANSS_IES_EXT_TS_CNTR_OVFL_SHIFT (0U)
464 #define MCAN_MCANSS_IES_EXT_TS_CNTR_OVFL_MASK (0x00000001U)
466 #define MCAN_MCANSS_EOI_SHIFT (0U)
467 #define MCAN_MCANSS_EOI_MASK (0x000000ffU)
469 #define MCAN_MCANSS_EXT_TS_PRESCALER_SHIFT (0U)
470 #define MCAN_MCANSS_EXT_TS_PRESCALER_MASK (0x00ffffffU)
472 #define MCAN_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_SHIFT (0U)
473 #define MCAN_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_MASK (0x0000001fU)
475 #define MCAN_ECC_EOI_SHIFT (8U)
476 #define MCAN_ECC_EOI_MASK (0x00000100U)
478 #define MCAN_CREL_DAY_SHIFT (0U)
479 #define MCAN_CREL_DAY_MASK (0x000000ffU)
481 #define MCAN_CREL_MON_SHIFT (8U)
482 #define MCAN_CREL_MON_MASK (0x0000ff00U)
484 #define MCAN_CREL_YEAR_SHIFT (16U)
485 #define MCAN_CREL_YEAR_MASK (0x000f0000U)
487 #define MCAN_CREL_SUBSTEP_SHIFT (20U)
488 #define MCAN_CREL_SUBSTEP_MASK (0x00f00000U)
490 #define MCAN_CREL_STEP_SHIFT (24U)
491 #define MCAN_CREL_STEP_MASK (0x0f000000U)
493 #define MCAN_CREL_REL_SHIFT (28U)
494 #define MCAN_CREL_REL_MASK (0xf0000000U)
496 #define MCAN_ENDN_ETV_SHIFT (0U)
497 #define MCAN_ENDN_ETV_MASK (0xffffffffU)
499 #define MCAN_DBTP_DSJW_SHIFT (0U)
500 #define MCAN_DBTP_DSJW_MASK (0x0000000fU)
502 #define MCAN_DBTP_DTSEG2_SHIFT (4U)
503 #define MCAN_DBTP_DTSEG2_MASK (0x000000f0U)
505 #define MCAN_DBTP_DTSEG1_SHIFT (8U)
506 #define MCAN_DBTP_DTSEG1_MASK (0x00001f00U)
508 #define MCAN_DBTP_DBRP_SHIFT (16U)
509 #define MCAN_DBTP_DBRP_MASK (0x001f0000U)
511 #define MCAN_DBTP_TDC_SHIFT (23U)
512 #define MCAN_DBTP_TDC_MASK (0x00800000U)
513 #define MCAN_DBTP_TDC_DISABLE (0U)
514 #define MCAN_DBTP_TDC_ENABLE (1U)
516 #define MCAN_TEST_LBCK_SHIFT (4U)
517 #define MCAN_TEST_LBCK_MASK (0x00000010U)
519 #define MCAN_TEST_TX_SHIFT (5U)
520 #define MCAN_TEST_TX_MASK (0x00000060U)
522 #define MCAN_TEST_RX_SHIFT (7U)
523 #define MCAN_TEST_RX_MASK (0x00000080U)
525 #define MCAN_RWD_WDC_SHIFT (0U)
526 #define MCAN_RWD_WDC_MASK (0x000000ffU)
527 #define MCAN_RWD_WDC_DISABLE (0U)
529 #define MCAN_RWD_WDV_SHIFT (8U)
530 #define MCAN_RWD_WDV_MASK (0x0000ff00U)
532 #define MCAN_CCCR_INIT_SHIFT (0U)
533 #define MCAN_CCCR_INIT_MASK (0x00000001U)
534 #define MCAN_CCCR_INIT_MODE_NORMAL (0U)
535 #define MCAN_CCCR_INIT_MODE_INIT (1U)
537 #define MCAN_CCCR_CCE_SHIFT (1U)
538 #define MCAN_CCCR_CCE_MASK (0x00000002U)
540 #define MCAN_CCCR_ASM_SHIFT (2U)
541 #define MCAN_CCCR_ASM_MASK (0x00000004U)
543 #define MCAN_CCCR_CSA_SHIFT (3U)
544 #define MCAN_CCCR_CSA_MASK (0x00000008U)
545 #define MCAN_CCCR_CSA_NO_ACK (0U)
546 #define MCAN_CCCR_CSA_ACK (1U)
548 #define MCAN_CCCR_CSR_SHIFT (4U)
549 #define MCAN_CCCR_CSR_MASK (0x00000010U)
551 #define MCAN_CCCR_MON_SHIFT (5U)
552 #define MCAN_CCCR_MON_MASK (0x00000020U)
554 #define MCAN_CCCR_DAR_SHIFT (6U)
555 #define MCAN_CCCR_DAR_MASK (0x00000040U)
556 #define MCAN_CCCR_DAR_DISABLE (0U)
557 #define MCAN_CCCR_DAR_ENABLE (1U)
559 #define MCAN_CCCR_TEST_SHIFT (7U)
560 #define MCAN_CCCR_TEST_MASK (0x00000080U)
562 #define MCAN_CCCR_FDOE_SHIFT (8U)
563 #define MCAN_CCCR_FDOE_MASK (0x00000100U)
564 #define MCAN_CCCR_FDOE_DISABLE (0U)
565 #define MCAN_CCCR_FDOE_ENABLE (1U)
567 #define MCAN_CCCR_BRSE_SHIFT (9U)
568 #define MCAN_CCCR_BRSE_MASK (0x00000200U)
569 #define MCAN_CCCR_BRSE_DISABLE (0U)
570 #define MCAN_CCCR_BRSE_ENABLE (1U)
572 #define MCAN_CCCR_PXHD_SHIFT (12U)
573 #define MCAN_CCCR_PXHD_MASK (0x00001000U)
574 #define MCAN_CCCR_PXHD_DISABLE (1U)
575 #define MCAN_CCCR_PXHD_ENABLE (0U)
577 #define MCAN_CCCR_EFBI_SHIFT (13U)
578 #define MCAN_CCCR_EFBI_MASK (0x00002000U)
579 #define MCAN_CCCR_EFBI_DISABLE (0U)
580 #define MCAN_CCCR_EFBI_ENABLE (1U)
582 #define MCAN_CCCR_TXP_SHIFT (14U)
583 #define MCAN_CCCR_TXP_MASK (0x00004000U)
584 #define MCAN_CCCR_TXP_DISABLE (0U)
585 #define MCAN_CCCR_TXP_ENABLE (1U)
587 #define MCAN_NBTP_NTSEG2_SHIFT (0U)
588 #define MCAN_NBTP_NTSEG2_MASK (0x0000007fU)
590 #define MCAN_NBTP_NTSEG1_SHIFT (8U)
591 #define MCAN_NBTP_NTSEG1_MASK (0x0000ff00U)
593 #define MCAN_NBTP_NBRP_SHIFT (16U)
594 #define MCAN_NBTP_NBRP_MASK (0x01ff0000U)
596 #define MCAN_NBTP_NSJW_SHIFT (25U)
597 #define MCAN_NBTP_NSJW_MASK (0xfe000000U)
599 #define MCAN_TSCC_TSS_SHIFT (0U)
600 #define MCAN_TSCC_TSS_MASK (0x00000003U)
602 #define MCAN_TSCC_TCP_SHIFT (16U)
603 #define MCAN_TSCC_TCP_MASK (0x000f0000U)
605 #define MCAN_TSCV_TSC_SHIFT (0U)
606 #define MCAN_TSCV_TSC_MASK (0x0000ffffU)
608 #define MCAN_TOCC_ETOC_SHIFT (0U)
609 #define MCAN_TOCC_ETOC_MASK (0x00000001U)
611 #define MCAN_TOCC_TOS_SHIFT (1U)
612 #define MCAN_TOCC_TOS_MASK (0x00000006U)
614 #define MCAN_TOCC_TOP_SHIFT (16U)
615 #define MCAN_TOCC_TOP_MASK (0xffff0000U)
617 #define MCAN_TOCV_TOC_SHIFT (0U)
618 #define MCAN_TOCV_TOC_MASK (0x0000ffffU)
620 #define MCAN_ECR_TEC_SHIFT (0U)
621 #define MCAN_ECR_TEC_MASK (0x000000ffU)
623 #define MCAN_ECR_REC_SHIFT (8U)
624 #define MCAN_ECR_REC_MASK (0x00007f00U)
626 #define MCAN_ECR_RP_SHIFT (15U)
627 #define MCAN_ECR_RP_MASK (0x00008000U)
629 #define MCAN_ECR_CEL_SHIFT (16U)
630 #define MCAN_ECR_CEL_MASK (0x00ff0000U)
632 #define MCAN_PSR_LEC_SHIFT (0U)
633 #define MCAN_PSR_LEC_MASK (0x00000007U)
635 #define MCAN_PSR_ACT_SHIFT (3U)
636 #define MCAN_PSR_ACT_MASK (0x00000018U)
638 #define MCAN_PSR_EP_SHIFT (5U)
639 #define MCAN_PSR_EP_MASK (0x00000020U)
641 #define MCAN_PSR_EW_SHIFT (6U)
642 #define MCAN_PSR_EW_MASK (0x00000040U)
644 #define MCAN_PSR_BO_SHIFT (7U)
645 #define MCAN_PSR_BO_MASK (0x00000080U)
646 #define MCAN_PSR_BO_NO_BUS_OFF (0U)
647 #define MCAN_PSR_BO_BUS_OFF (1U)
649 #define MCAN_PSR_DLEC_SHIFT (8U)
650 #define MCAN_PSR_DLEC_MASK (0x00000700U)
652 #define MCAN_PSR_RESI_SHIFT (11U)
653 #define MCAN_PSR_RESI_MASK (0x00000800U)
655 #define MCAN_PSR_RBRS_SHIFT (12U)
656 #define MCAN_PSR_RBRS_MASK (0x00001000U)
658 #define MCAN_PSR_RFDF_SHIFT (13U)
659 #define MCAN_PSR_RFDF_MASK (0x00002000U)
661 #define MCAN_PSR_PXE_SHIFT (14U)
662 #define MCAN_PSR_PXE_MASK (0x00004000U)
664 #define MCAN_PSR_TDCV_SHIFT (16U)
665 #define MCAN_PSR_TDCV_MASK (0x007f0000U)
667 #define MCAN_TDCR_TDCF_SHIFT (0U)
668 #define MCAN_TDCR_TDCF_MASK (0x0000007fU)
670 #define MCAN_TDCR_TDCO_SHIFT (8U)
671 #define MCAN_TDCR_TDCO_MASK (0x00007f00U)
673 #define MCAN_IR_RF0N_SHIFT (0U)
674 #define MCAN_IR_RF0N_MASK (0x00000001U)
676 #define MCAN_IR_RF0W_SHIFT (1U)
677 #define MCAN_IR_RF0W_MASK (0x00000002U)
679 #define MCAN_IR_RF0F_SHIFT (2U)
680 #define MCAN_IR_RF0F_MASK (0x00000004U)
682 #define MCAN_IR_RF0L_SHIFT (3U)
683 #define MCAN_IR_RF0L_MASK (0x00000008U)
685 #define MCAN_IR_RF1N_SHIFT (4U)
686 #define MCAN_IR_RF1N_MASK (0x00000010U)
688 #define MCAN_IR_RF1W_SHIFT (5U)
689 #define MCAN_IR_RF1W_MASK (0x00000020U)
691 #define MCAN_IR_RF1F_SHIFT (6U)
692 #define MCAN_IR_RF1F_MASK (0x00000040U)
694 #define MCAN_IR_RF1L_SHIFT (7U)
695 #define MCAN_IR_RF1L_MASK (0x00000080U)
697 #define MCAN_IR_HPM_SHIFT (8U)
698 #define MCAN_IR_HPM_MASK (0x00000100U)
700 #define MCAN_IR_TC_SHIFT (9U)
701 #define MCAN_IR_TC_MASK (0x00000200U)
703 #define MCAN_IR_TCF_SHIFT (10U)
704 #define MCAN_IR_TCF_MASK (0x00000400U)
706 #define MCAN_IR_TFE_SHIFT (11U)
707 #define MCAN_IR_TFE_MASK (0x00000800U)
709 #define MCAN_IR_TEFN_SHIFT (12U)
710 #define MCAN_IR_TEFN_MASK (0x00001000U)
712 #define MCAN_IR_TEFW_SHIFT (13U)
713 #define MCAN_IR_TEFW_MASK (0x00002000U)
715 #define MCAN_IR_TEFF_SHIFT (14U)
716 #define MCAN_IR_TEFF_MASK (0x00004000U)
718 #define MCAN_IR_TEFL_SHIFT (15U)
719 #define MCAN_IR_TEFL_MASK (0x00008000U)
721 #define MCAN_IR_TSW_SHIFT (16U)
722 #define MCAN_IR_TSW_MASK (0x00010000U)
724 #define MCAN_IR_MRAF_SHIFT (17U)
725 #define MCAN_IR_MRAF_MASK (0x00020000U)
727 #define MCAN_IR_TOO_SHIFT (18U)
728 #define MCAN_IR_TOO_MASK (0x00040000U)
730 #define MCAN_IR_DRX_SHIFT (19U)
731 #define MCAN_IR_DRX_MASK (0x00080000U)
733 #define MCAN_IR_BEC_SHIFT (20U)
734 #define MCAN_IR_BEC_MASK (0x00100000U)
736 #define MCAN_IR_BEU_SHIFT (21U)
737 #define MCAN_IR_BEU_MASK (0x00200000U)
739 #define MCAN_IR_ELO_SHIFT (22U)
740 #define MCAN_IR_ELO_MASK (0x00400000U)
742 #define MCAN_IR_EP_SHIFT (23U)
743 #define MCAN_IR_EP_MASK (0x00800000U)
745 #define MCAN_IR_EW_SHIFT (24U)
746 #define MCAN_IR_EW_MASK (0x01000000U)
748 #define MCAN_IR_BO_SHIFT (25U)
749 #define MCAN_IR_BO_MASK (0x02000000U)
751 #define MCAN_IR_WDI_SHIFT (26U)
752 #define MCAN_IR_WDI_MASK (0x04000000U)
754 #define MCAN_IR_PEA_SHIFT (27U)
755 #define MCAN_IR_PEA_MASK (0x08000000U)
757 #define MCAN_IR_PED_SHIFT (28U)
758 #define MCAN_IR_PED_MASK (0x10000000U)
760 #define MCAN_IR_ARA_SHIFT (29U)
761 #define MCAN_IR_ARA_MASK (0x20000000U)
763 #define MCAN_IE_RF0NE_SHIFT (0U)
764 #define MCAN_IE_RF0NE_MASK (0x00000001U)
766 #define MCAN_IE_RF0WE_SHIFT (1U)
767 #define MCAN_IE_RF0WE_MASK (0x00000002U)
769 #define MCAN_IE_RF0FE_SHIFT (2U)
770 #define MCAN_IE_RF0FE_MASK (0x00000004U)
772 #define MCAN_IE_RF0LE_SHIFT (3U)
773 #define MCAN_IE_RF0LE_MASK (0x00000008U)
775 #define MCAN_IE_RF1NE_SHIFT (4U)
776 #define MCAN_IE_RF1NE_MASK (0x00000010U)
778 #define MCAN_IE_RF1WE_SHIFT (5U)
779 #define MCAN_IE_RF1WE_MASK (0x00000020U)
781 #define MCAN_IE_RF1FE_SHIFT (6U)
782 #define MCAN_IE_RF1FE_MASK (0x00000040U)
784 #define MCAN_IE_RF1LE_SHIFT (7U)
785 #define MCAN_IE_RF1LE_MASK (0x00000080U)
787 #define MCAN_IE_HPME_SHIFT (8U)
788 #define MCAN_IE_HPME_MASK (0x00000100U)
790 #define MCAN_IE_TCE_SHIFT (9U)
791 #define MCAN_IE_TCE_MASK (0x00000200U)
793 #define MCAN_IE_TCFE_SHIFT (10U)
794 #define MCAN_IE_TCFE_MASK (0x00000400U)
796 #define MCAN_IE_TFEE_SHIFT (11U)
797 #define MCAN_IE_TFEE_MASK (0x00000800U)
799 #define MCAN_IE_TEFNE_SHIFT (12U)
800 #define MCAN_IE_TEFNE_MASK (0x00001000U)
802 #define MCAN_IE_TEFWE_SHIFT (13U)
803 #define MCAN_IE_TEFWE_MASK (0x00002000U)
805 #define MCAN_IE_TEFFE_SHIFT (14U)
806 #define MCAN_IE_TEFFE_MASK (0x00004000U)
808 #define MCAN_IE_TEFLE_SHIFT (15U)
809 #define MCAN_IE_TEFLE_MASK (0x00008000U)
811 #define MCAN_IE_TSWE_SHIFT (16U)
812 #define MCAN_IE_TSWE_MASK (0x00010000U)
814 #define MCAN_IE_MRAFE_SHIFT (17U)
815 #define MCAN_IE_MRAFE_MASK (0x00020000U)
817 #define MCAN_IE_TOOE_SHIFT (18U)
818 #define MCAN_IE_TOOE_MASK (0x00040000U)
820 #define MCAN_IE_DRX_SHIFT (19U)
821 #define MCAN_IE_DRX_MASK (0x00080000U)
823 #define MCAN_IE_BECE_SHIFT (20U)
824 #define MCAN_IE_BECE_MASK (0x00100000U)
826 #define MCAN_IE_BEUE_SHIFT (21U)
827 #define MCAN_IE_BEUE_MASK (0x00200000U)
829 #define MCAN_IE_ELOE_SHIFT (22U)
830 #define MCAN_IE_ELOE_MASK (0x00400000U)
832 #define MCAN_IE_EPE_SHIFT (23U)
833 #define MCAN_IE_EPE_MASK (0x00800000U)
835 #define MCAN_IE_EWE_SHIFT (24U)
836 #define MCAN_IE_EWE_MASK (0x01000000U)
838 #define MCAN_IE_BOE_SHIFT (25U)
839 #define MCAN_IE_BOE_MASK (0x02000000U)
841 #define MCAN_IE_WDIE_SHIFT (26U)
842 #define MCAN_IE_WDIE_MASK (0x04000000U)
844 #define MCAN_IE_PEAE_SHIFT (27U)
845 #define MCAN_IE_PEAE_MASK (0x08000000U)
847 #define MCAN_IE_PEDE_SHIFT (28U)
848 #define MCAN_IE_PEDE_MASK (0x10000000U)
850 #define MCAN_IE_ARAE_SHIFT (29U)
851 #define MCAN_IE_ARAE_MASK (0x20000000U)
853 #define MCAN_ILS_RF0NL_SHIFT (0U)
854 #define MCAN_ILS_RF0NL_MASK (0x00000001U)
856 #define MCAN_ILS_RF0WL_SHIFT (1U)
857 #define MCAN_ILS_RF0WL_MASK (0x00000002U)
859 #define MCAN_ILS_RF0FL_SHIFT (2U)
860 #define MCAN_ILS_RF0FL_MASK (0x00000004U)
862 #define MCAN_ILS_RF0LL_SHIFT (3U)
863 #define MCAN_ILS_RF0LL_MASK (0x00000008U)
865 #define MCAN_ILS_RF1NL_SHIFT (4U)
866 #define MCAN_ILS_RF1NL_MASK (0x00000010U)
868 #define MCAN_ILS_RF1WL_SHIFT (5U)
869 #define MCAN_ILS_RF1WL_MASK (0x00000020U)
871 #define MCAN_ILS_RF1FL_SHIFT (6U)
872 #define MCAN_ILS_RF1FL_MASK (0x00000040U)
874 #define MCAN_ILS_RF1LL_SHIFT (7U)
875 #define MCAN_ILS_RF1LL_MASK (0x00000080U)
877 #define MCAN_ILS_HPML_SHIFT (8U)
878 #define MCAN_ILS_HPML_MASK (0x00000100U)
880 #define MCAN_ILS_TCL_SHIFT (9U)
881 #define MCAN_ILS_TCL_MASK (0x00000200U)
883 #define MCAN_ILS_TCFL_SHIFT (10U)
884 #define MCAN_ILS_TCFL_MASK (0x00000400U)
886 #define MCAN_ILS_TFEL_SHIFT (11U)
887 #define MCAN_ILS_TFEL_MASK (0x00000800U)
889 #define MCAN_ILS_TEFNL_SHIFT (12U)
890 #define MCAN_ILS_TEFNL_MASK (0x00001000U)
892 #define MCAN_ILS_TEFWL_SHIFT (13U)
893 #define MCAN_ILS_TEFWL_MASK (0x00002000U)
895 #define MCAN_ILS_TEFFL_SHIFT (14U)
896 #define MCAN_ILS_TEFFL_MASK (0x00004000U)
898 #define MCAN_ILS_TEFLL_SHIFT (15U)
899 #define MCAN_ILS_TEFLL_MASK (0x00008000U)
901 #define MCAN_ILS_TSWL_SHIFT (16U)
902 #define MCAN_ILS_TSWL_MASK (0x00010000U)
904 #define MCAN_ILS_MRAFL_SHIFT (17U)
905 #define MCAN_ILS_MRAFL_MASK (0x00020000U)
907 #define MCAN_ILS_TOOL_SHIFT (18U)
908 #define MCAN_ILS_TOOL_MASK (0x00040000U)
910 #define MCAN_ILS_DRXL_SHIFT (19U)
911 #define MCAN_ILS_DRXL_MASK (0x00080000U)
913 #define MCAN_ILS_BECL_SHIFT (20U)
914 #define MCAN_ILS_BECL_MASK (0x00100000U)
916 #define MCAN_ILS_BEUL_SHIFT (21U)
917 #define MCAN_ILS_BEUL_MASK (0x00200000U)
919 #define MCAN_ILS_ELOL_SHIFT (22U)
920 #define MCAN_ILS_ELOL_MASK (0x00400000U)
922 #define MCAN_ILS_EPL_SHIFT (23U)
923 #define MCAN_ILS_EPL_MASK (0x00800000U)
925 #define MCAN_ILS_EWL_SHIFT (24U)
926 #define MCAN_ILS_EWL_MASK (0x01000000U)
928 #define MCAN_ILS_BOL_SHIFT (25U)
929 #define MCAN_ILS_BOL_MASK (0x02000000U)
931 #define MCAN_ILS_WDIL_SHIFT (26U)
932 #define MCAN_ILS_WDIL_MASK (0x04000000U)
934 #define MCAN_ILS_PEAL_SHIFT (27U)
935 #define MCAN_ILS_PEAL_MASK (0x08000000U)
937 #define MCAN_ILS_PEDL_SHIFT (28U)
938 #define MCAN_ILS_PEDL_MASK (0x10000000U)
940 #define MCAN_ILS_ARAL_SHIFT (29U)
941 #define MCAN_ILS_ARAL_MASK (0x20000000U)
943 #define MCAN_ILE_EINT0_SHIFT (0U)
944 #define MCAN_ILE_EINT0_MASK (0x00000001U)
946 #define MCAN_ILE_EINT1_SHIFT (1U)
947 #define MCAN_ILE_EINT1_MASK (0x00000002U)
949 #define MCAN_GFC_RRFE_SHIFT (0U)
950 #define MCAN_GFC_RRFE_MASK (0x00000001U)
952 #define MCAN_GFC_RRFS_SHIFT (1U)
953 #define MCAN_GFC_RRFS_MASK (0x00000002U)
955 #define MCAN_GFC_ANFE_SHIFT (2U)
956 #define MCAN_GFC_ANFE_MASK (0x0000000cU)
958 #define MCAN_GFC_ANFS_SHIFT (4U)
959 #define MCAN_GFC_ANFS_MASK (0x00000030U)
961 #define MCAN_SIDFC_FLSSA_SHIFT (2U)
962 #define MCAN_SIDFC_FLSSA_MASK (0x0000fffcU)
964 #define MCAN_SIDFC_LSS_SHIFT (16U)
965 #define MCAN_SIDFC_LSS_MASK (0x00ff0000U)
967 #define MCAN_XIDFC_FLESA_SHIFT (2U)
968 #define MCAN_XIDFC_FLESA_MASK (0x0000fffcU)
970 #define MCAN_XIDFC_LSE_SHIFT (16U)
971 #define MCAN_XIDFC_LSE_MASK (0x007f0000U)
973 #define MCAN_XIDAM_EIDM_SHIFT (0U)
974 #define MCAN_XIDAM_EIDM_MASK (0x1fffffffU)
976 #define MCAN_HPMS_BIDX_SHIFT (0U)
977 #define MCAN_HPMS_BIDX_MASK (0x0000003fU)
979 #define MCAN_HPMS_MSI_SHIFT (6U)
980 #define MCAN_HPMS_MSI_MASK (0x000000c0U)
982 #define MCAN_HPMS_FIDX_SHIFT (8U)
983 #define MCAN_HPMS_FIDX_MASK (0x00007f00U)
985 #define MCAN_HPMS_FLST_SHIFT (15U)
986 #define MCAN_HPMS_FLST_MASK (0x00008000U)
988 #define MCAN_NDAT1_ND0_SHIFT (0U)
989 #define MCAN_NDAT1_ND0_MASK (0x00000001U)
991 #define MCAN_NDAT1_ND1_SHIFT (1U)
992 #define MCAN_NDAT1_ND1_MASK (0x00000002U)
994 #define MCAN_NDAT1_ND2_SHIFT (2U)
995 #define MCAN_NDAT1_ND2_MASK (0x00000004U)
997 #define MCAN_NDAT1_ND3_SHIFT (3U)
998 #define MCAN_NDAT1_ND3_MASK (0x00000008U)
1000 #define MCAN_NDAT1_ND4_SHIFT (4U)
1001 #define MCAN_NDAT1_ND4_MASK (0x00000010U)
1003 #define MCAN_NDAT1_ND5_SHIFT (5U)
1004 #define MCAN_NDAT1_ND5_MASK (0x00000020U)
1006 #define MCAN_NDAT1_ND6_SHIFT (6U)
1007 #define MCAN_NDAT1_ND6_MASK (0x00000040U)
1009 #define MCAN_NDAT1_ND7_SHIFT (7U)
1010 #define MCAN_NDAT1_ND7_MASK (0x00000080U)
1012 #define MCAN_NDAT1_ND8_SHIFT (8U)
1013 #define MCAN_NDAT1_ND8_MASK (0x00000100U)
1015 #define MCAN_NDAT1_ND9_SHIFT (9U)
1016 #define MCAN_NDAT1_ND9_MASK (0x00000200U)
1018 #define MCAN_NDAT1_ND10_SHIFT (10U)
1019 #define MCAN_NDAT1_ND10_MASK (0x00000400U)
1021 #define MCAN_NDAT1_ND11_SHIFT (11U)
1022 #define MCAN_NDAT1_ND11_MASK (0x00000800U)
1024 #define MCAN_NDAT1_ND12_SHIFT (12U)
1025 #define MCAN_NDAT1_ND12_MASK (0x00001000U)
1027 #define MCAN_NDAT1_ND13_SHIFT (13U)
1028 #define MCAN_NDAT1_ND13_MASK (0x00002000U)
1030 #define MCAN_NDAT1_ND14_SHIFT (14U)
1031 #define MCAN_NDAT1_ND14_MASK (0x00004000U)
1033 #define MCAN_NDAT1_ND15_SHIFT (15U)
1034 #define MCAN_NDAT1_ND15_MASK (0x00008000U)
1036 #define MCAN_NDAT1_ND16_SHIFT (16U)
1037 #define MCAN_NDAT1_ND16_MASK (0x00010000U)
1039 #define MCAN_NDAT1_ND17_SHIFT (17U)
1040 #define MCAN_NDAT1_ND17_MASK (0x00020000U)
1042 #define MCAN_NDAT1_ND18_SHIFT (18U)
1043 #define MCAN_NDAT1_ND18_MASK (0x00040000U)
1045 #define MCAN_NDAT1_ND19_SHIFT (19U)
1046 #define MCAN_NDAT1_ND19_MASK (0x00080000U)
1048 #define MCAN_NDAT1_ND20_SHIFT (20U)
1049 #define MCAN_NDAT1_ND20_MASK (0x00100000U)
1051 #define MCAN_NDAT1_ND21_SHIFT (21U)
1052 #define MCAN_NDAT1_ND21_MASK (0x00200000U)
1054 #define MCAN_NDAT1_ND22_SHIFT (22U)
1055 #define MCAN_NDAT1_ND22_MASK (0x00400000U)
1057 #define MCAN_NDAT1_ND23_SHIFT (23U)
1058 #define MCAN_NDAT1_ND23_MASK (0x00800000U)
1060 #define MCAN_NDAT1_ND24_SHIFT (24U)
1061 #define MCAN_NDAT1_ND24_MASK (0x01000000U)
1063 #define MCAN_NDAT1_ND25_SHIFT (25U)
1064 #define MCAN_NDAT1_ND25_MASK (0x02000000U)
1066 #define MCAN_NDAT1_ND26_SHIFT (26U)
1067 #define MCAN_NDAT1_ND26_MASK (0x04000000U)
1069 #define MCAN_NDAT1_ND27_SHIFT (27U)
1070 #define MCAN_NDAT1_ND27_MASK (0x08000000U)
1072 #define MCAN_NDAT1_ND28_SHIFT (28U)
1073 #define MCAN_NDAT1_ND28_MASK (0x10000000U)
1075 #define MCAN_NDAT1_ND29_SHIFT (29U)
1076 #define MCAN_NDAT1_ND29_MASK (0x20000000U)
1078 #define MCAN_NDAT1_ND30_SHIFT (30U)
1079 #define MCAN_NDAT1_ND30_MASK (0x40000000U)
1081 #define MCAN_NDAT1_ND31_SHIFT (31U)
1082 #define MCAN_NDAT1_ND31_MASK (0x80000000U)
1084 #define MCAN_NDAT2_ND32_SHIFT (0U)
1085 #define MCAN_NDAT2_ND32_MASK (0x00000001U)
1087 #define MCAN_NDAT2_ND33_SHIFT (1U)
1088 #define MCAN_NDAT2_ND33_MASK (0x00000002U)
1090 #define MCAN_NDAT2_ND34_SHIFT (2U)
1091 #define MCAN_NDAT2_ND34_MASK (0x00000004U)
1093 #define MCAN_NDAT2_ND35_SHIFT (3U)
1094 #define MCAN_NDAT2_ND35_MASK (0x00000008U)
1096 #define MCAN_NDAT2_ND36_SHIFT (4U)
1097 #define MCAN_NDAT2_ND36_MASK (0x00000010U)
1099 #define MCAN_NDAT2_ND37_SHIFT (5U)
1100 #define MCAN_NDAT2_ND37_MASK (0x00000020U)
1102 #define MCAN_NDAT2_ND38_SHIFT (6U)
1103 #define MCAN_NDAT2_ND38_MASK (0x00000040U)
1105 #define MCAN_NDAT2_ND39_SHIFT (7U)
1106 #define MCAN_NDAT2_ND39_MASK (0x00000080U)
1108 #define MCAN_NDAT2_ND40_SHIFT (8U)
1109 #define MCAN_NDAT2_ND40_MASK (0x00000100U)
1111 #define MCAN_NDAT2_ND41_SHIFT (9U)
1112 #define MCAN_NDAT2_ND41_MASK (0x00000200U)
1114 #define MCAN_NDAT2_ND42_SHIFT (10U)
1115 #define MCAN_NDAT2_ND42_MASK (0x00000400U)
1117 #define MCAN_NDAT2_ND43_SHIFT (11U)
1118 #define MCAN_NDAT2_ND43_MASK (0x00000800U)
1120 #define MCAN_NDAT2_ND44_SHIFT (12U)
1121 #define MCAN_NDAT2_ND44_MASK (0x00001000U)
1123 #define MCAN_NDAT2_ND45_SHIFT (13U)
1124 #define MCAN_NDAT2_ND45_MASK (0x00002000U)
1126 #define MCAN_NDAT2_ND46_SHIFT (14U)
1127 #define MCAN_NDAT2_ND46_MASK (0x00004000U)
1129 #define MCAN_NDAT2_ND47_SHIFT (15U)
1130 #define MCAN_NDAT2_ND47_MASK (0x00008000U)
1132 #define MCAN_NDAT2_ND48_SHIFT (16U)
1133 #define MCAN_NDAT2_ND48_MASK (0x00010000U)
1135 #define MCAN_NDAT2_ND49_SHIFT (17U)
1136 #define MCAN_NDAT2_ND49_MASK (0x00020000U)
1138 #define MCAN_NDAT2_ND50_SHIFT (18U)
1139 #define MCAN_NDAT2_ND50_MASK (0x00040000U)
1141 #define MCAN_NDAT2_ND51_SHIFT (19U)
1142 #define MCAN_NDAT2_ND51_MASK (0x00080000U)
1144 #define MCAN_NDAT2_ND52_SHIFT (20U)
1145 #define MCAN_NDAT2_ND52_MASK (0x00100000U)
1147 #define MCAN_NDAT2_ND53_SHIFT (21U)
1148 #define MCAN_NDAT2_ND53_MASK (0x00200000U)
1150 #define MCAN_NDAT2_ND54_SHIFT (22U)
1151 #define MCAN_NDAT2_ND54_MASK (0x00400000U)
1153 #define MCAN_NDAT2_ND55_SHIFT (23U)
1154 #define MCAN_NDAT2_ND55_MASK (0x00800000U)
1156 #define MCAN_NDAT2_ND56_SHIFT (24U)
1157 #define MCAN_NDAT2_ND56_MASK (0x01000000U)
1159 #define MCAN_NDAT2_ND57_SHIFT (25U)
1160 #define MCAN_NDAT2_ND57_MASK (0x02000000U)
1162 #define MCAN_NDAT2_ND58_SHIFT (26U)
1163 #define MCAN_NDAT2_ND58_MASK (0x04000000U)
1165 #define MCAN_NDAT2_ND59_SHIFT (27U)
1166 #define MCAN_NDAT2_ND59_MASK (0x08000000U)
1168 #define MCAN_NDAT2_ND60_SHIFT (28U)
1169 #define MCAN_NDAT2_ND60_MASK (0x10000000U)
1171 #define MCAN_NDAT2_ND61_SHIFT (29U)
1172 #define MCAN_NDAT2_ND61_MASK (0x20000000U)
1174 #define MCAN_NDAT2_ND62_SHIFT (30U)
1175 #define MCAN_NDAT2_ND62_MASK (0x40000000U)
1177 #define MCAN_NDAT2_ND63_SHIFT (31U)
1178 #define MCAN_NDAT2_ND63_MASK (0x80000000U)
1180 #define MCAN_RXF0C_F0SA_SHIFT (2U)
1181 #define MCAN_RXF0C_F0SA_MASK (0x0000fffcU)
1183 #define MCAN_RXF0C_F0S_SHIFT (16U)
1184 #define MCAN_RXF0C_F0S_MASK (0x007f0000U)
1186 #define MCAN_RXF0C_F0WM_SHIFT (24U)
1187 #define MCAN_RXF0C_F0WM_MASK (0x7f000000U)
1189 #define MCAN_RXF0C_F0OM_SHIFT (31U)
1190 #define MCAN_RXF0C_F0OM_MASK (0x80000000U)
1192 #define MCAN_RXF0S_F0FL_SHIFT (0U)
1193 #define MCAN_RXF0S_F0FL_MASK (0x0000007fU)
1195 #define MCAN_RXF0S_F0GI_SHIFT (8U)
1196 #define MCAN_RXF0S_F0GI_MASK (0x00003f00U)
1198 #define MCAN_RXF0S_F0PI_SHIFT (16U)
1199 #define MCAN_RXF0S_F0PI_MASK (0x003f0000U)
1201 #define MCAN_RXF0S_F0F_SHIFT (24U)
1202 #define MCAN_RXF0S_F0F_MASK (0x01000000U)
1204 #define MCAN_RXF0S_RF0L_SHIFT (25U)
1205 #define MCAN_RXF0S_RF0L_MASK (0x02000000U)
1207 #define MCAN_RXF0A_F0AI_SHIFT (0U)
1208 #define MCAN_RXF0A_F0AI_MASK (0x0000003fU)
1210 #define MCAN_RXBC_RBSA_SHIFT (2U)
1211 #define MCAN_RXBC_RBSA_MASK (0x0000fffcU)
1213 #define MCAN_RXF1C_F1SA_SHIFT (2U)
1214 #define MCAN_RXF1C_F1SA_MASK (0x0000fffcU)
1216 #define MCAN_RXF1C_F1S_SHIFT (16U)
1217 #define MCAN_RXF1C_F1S_MASK (0x007f0000U)
1219 #define MCAN_RXF1C_F1WM_SHIFT (24U)
1220 #define MCAN_RXF1C_F1WM_MASK (0x7f000000U)
1222 #define MCAN_RXF1C_F1OM_SHIFT (31U)
1223 #define MCAN_RXF1C_F1OM_MASK (0x80000000U)
1225 #define MCAN_RXF1S_F1FL_SHIFT (0U)
1226 #define MCAN_RXF1S_F1FL_MASK (0x0000007fU)
1228 #define MCAN_RXF1S_F1GI_SHIFT (8U)
1229 #define MCAN_RXF1S_F1GI_MASK (0x00003f00U)
1231 #define MCAN_RXF1S_F1PI_SHIFT (16U)
1232 #define MCAN_RXF1S_F1PI_MASK (0x003f0000U)
1234 #define MCAN_RXF1S_F1F_SHIFT (24U)
1235 #define MCAN_RXF1S_F1F_MASK (0x01000000U)
1237 #define MCAN_RXF1S_RF1L_SHIFT (25U)
1238 #define MCAN_RXF1S_RF1L_MASK (0x02000000U)
1240 #define MCAN_RXF1S_DMS_SHIFT (30U)
1241 #define MCAN_RXF1S_DMS_MASK (0xc0000000U)
1243 #define MCAN_RXF1A_F1AI_SHIFT (0U)
1244 #define MCAN_RXF1A_F1AI_MASK (0x0000003fU)
1246 #define MCAN_RXESC_F0DS_SHIFT (0U)
1247 #define MCAN_RXESC_F0DS_MASK (0x00000007U)
1249 #define MCAN_RXESC_F1DS_SHIFT (4U)
1250 #define MCAN_RXESC_F1DS_MASK (0x00000070U)
1252 #define MCAN_RXESC_RBDS_SHIFT (8U)
1253 #define MCAN_RXESC_RBDS_MASK (0x00000700U)
1255 #define MCAN_TXBC_TBSA_SHIFT (2U)
1256 #define MCAN_TXBC_TBSA_MASK (0x0000fffcU)
1258 #define MCAN_TXBC_NDTB_SHIFT (16U)
1259 #define MCAN_TXBC_NDTB_MASK (0x003f0000U)
1261 #define MCAN_TXBC_TFQS_SHIFT (24U)
1262 #define MCAN_TXBC_TFQS_MASK (0x3f000000U)
1264 #define MCAN_TXBC_TFQM_SHIFT (30U)
1265 #define MCAN_TXBC_TFQM_MASK (0x40000000U)
1267 #define MCAN_TXFQS_TFFL_SHIFT (0U)
1268 #define MCAN_TXFQS_TFFL_MASK (0x0000003fU)
1270 #define MCAN_TXFQS_TFGI_SHIFT (8U)
1271 #define MCAN_TXFQS_TFGI_MASK (0x00001f00U)
1273 #define MCAN_TXFQS_TFQPI_SHIFT (16U)
1274 #define MCAN_TXFQS_TFQPI_MASK (0x001f0000U)
1276 #define MCAN_TXFQS_TFQF_SHIFT (21U)
1277 #define MCAN_TXFQS_TFQF_MASK (0x00200000U)
1279 #define MCAN_TXESC_TBDS_SHIFT (0U)
1280 #define MCAN_TXESC_TBDS_MASK (0x00000007U)
1282 #define MCAN_TXBRP_TRP0_SHIFT (0U)
1283 #define MCAN_TXBRP_TRP0_MASK (0x00000001U)
1285 #define MCAN_TXBRP_TRP1_SHIFT (1U)
1286 #define MCAN_TXBRP_TRP1_MASK (0x00000002U)
1288 #define MCAN_TXBRP_TRP2_SHIFT (2U)
1289 #define MCAN_TXBRP_TRP2_MASK (0x00000004U)
1291 #define MCAN_TXBRP_TRP3_SHIFT (3U)
1292 #define MCAN_TXBRP_TRP3_MASK (0x00000008U)
1294 #define MCAN_TXBRP_TRP4_SHIFT (4U)
1295 #define MCAN_TXBRP_TRP4_MASK (0x00000010U)
1297 #define MCAN_TXBRP_TRP5_SHIFT (5U)
1298 #define MCAN_TXBRP_TRP5_MASK (0x00000020U)
1300 #define MCAN_TXBRP_TRP6_SHIFT (6U)
1301 #define MCAN_TXBRP_TRP6_MASK (0x00000040U)
1303 #define MCAN_TXBRP_TRP7_SHIFT (7U)
1304 #define MCAN_TXBRP_TRP7_MASK (0x00000080U)
1306 #define MCAN_TXBRP_TRP8_SHIFT (8U)
1307 #define MCAN_TXBRP_TRP8_MASK (0x00000100U)
1309 #define MCAN_TXBRP_TRP9_SHIFT (9U)
1310 #define MCAN_TXBRP_TRP9_MASK (0x00000200U)
1312 #define MCAN_TXBRP_TRP10_SHIFT (10U)
1313 #define MCAN_TXBRP_TRP10_MASK (0x00000400U)
1315 #define MCAN_TXBRP_TRP11_SHIFT (11U)
1316 #define MCAN_TXBRP_TRP11_MASK (0x00000800U)
1318 #define MCAN_TXBRP_TRP12_SHIFT (12U)
1319 #define MCAN_TXBRP_TRP12_MASK (0x00001000U)
1321 #define MCAN_TXBRP_TRP13_SHIFT (13U)
1322 #define MCAN_TXBRP_TRP13_MASK (0x00002000U)
1324 #define MCAN_TXBRP_TRP14_SHIFT (14U)
1325 #define MCAN_TXBRP_TRP14_MASK (0x00004000U)
1327 #define MCAN_TXBRP_TRP15_SHIFT (15U)
1328 #define MCAN_TXBRP_TRP15_MASK (0x00008000U)
1330 #define MCAN_TXBRP_TRP16_SHIFT (16U)
1331 #define MCAN_TXBRP_TRP16_MASK (0x00010000U)
1333 #define MCAN_TXBRP_TRP17_SHIFT (17U)
1334 #define MCAN_TXBRP_TRP17_MASK (0x00020000U)
1336 #define MCAN_TXBRP_TRP18_SHIFT (18U)
1337 #define MCAN_TXBRP_TRP18_MASK (0x00040000U)
1339 #define MCAN_TXBRP_TRP19_SHIFT (19U)
1340 #define MCAN_TXBRP_TRP19_MASK (0x00080000U)
1342 #define MCAN_TXBRP_TRP20_SHIFT (20U)
1343 #define MCAN_TXBRP_TRP20_MASK (0x00100000U)
1345 #define MCAN_TXBRP_TRP21_SHIFT (21U)
1346 #define MCAN_TXBRP_TRP21_MASK (0x00200000U)
1348 #define MCAN_TXBRP_TRP22_SHIFT (22U)
1349 #define MCAN_TXBRP_TRP22_MASK (0x00400000U)
1351 #define MCAN_TXBRP_TRP23_SHIFT (23U)
1352 #define MCAN_TXBRP_TRP23_MASK (0x00800000U)
1354 #define MCAN_TXBRP_TRP24_SHIFT (24U)
1355 #define MCAN_TXBRP_TRP24_MASK (0x01000000U)
1357 #define MCAN_TXBRP_TRP25_SHIFT (25U)
1358 #define MCAN_TXBRP_TRP25_MASK (0x02000000U)
1360 #define MCAN_TXBRP_TRP26_SHIFT (26U)
1361 #define MCAN_TXBRP_TRP26_MASK (0x04000000U)
1363 #define MCAN_TXBRP_TRP27_SHIFT (27U)
1364 #define MCAN_TXBRP_TRP27_MASK (0x08000000U)
1366 #define MCAN_TXBRP_TRP28_SHIFT (28U)
1367 #define MCAN_TXBRP_TRP28_MASK (0x10000000U)
1369 #define MCAN_TXBRP_TRP29_SHIFT (29U)
1370 #define MCAN_TXBRP_TRP29_MASK (0x20000000U)
1372 #define MCAN_TXBRP_TRP30_SHIFT (30U)
1373 #define MCAN_TXBRP_TRP30_MASK (0x40000000U)
1375 #define MCAN_TXBRP_TRP31_SHIFT (31U)
1376 #define MCAN_TXBRP_TRP31_MASK (0x80000000U)
1378 #define MCAN_TXBAR_AR0_SHIFT (0U)
1379 #define MCAN_TXBAR_AR0_MASK (0x00000001U)
1381 #define MCAN_TXBAR_AR1_SHIFT (1U)
1382 #define MCAN_TXBAR_AR1_MASK (0x00000002U)
1384 #define MCAN_TXBAR_AR2_SHIFT (2U)
1385 #define MCAN_TXBAR_AR2_MASK (0x00000004U)
1387 #define MCAN_TXBAR_AR3_SHIFT (3U)
1388 #define MCAN_TXBAR_AR3_MASK (0x00000008U)
1390 #define MCAN_TXBAR_AR4_SHIFT (4U)
1391 #define MCAN_TXBAR_AR4_MASK (0x00000010U)
1393 #define MCAN_TXBAR_AR5_SHIFT (5U)
1394 #define MCAN_TXBAR_AR5_MASK (0x00000020U)
1396 #define MCAN_TXBAR_AR6_SHIFT (6U)
1397 #define MCAN_TXBAR_AR6_MASK (0x00000040U)
1399 #define MCAN_TXBAR_AR7_SHIFT (7U)
1400 #define MCAN_TXBAR_AR7_MASK (0x00000080U)
1402 #define MCAN_TXBAR_AR8_SHIFT (8U)
1403 #define MCAN_TXBAR_AR8_MASK (0x00000100U)
1405 #define MCAN_TXBAR_AR9_SHIFT (9U)
1406 #define MCAN_TXBAR_AR9_MASK (0x00000200U)
1408 #define MCAN_TXBAR_AR10_SHIFT (10U)
1409 #define MCAN_TXBAR_AR10_MASK (0x00000400U)
1411 #define MCAN_TXBAR_AR11_SHIFT (11U)
1412 #define MCAN_TXBAR_AR11_MASK (0x00000800U)
1414 #define MCAN_TXBAR_AR12_SHIFT (12U)
1415 #define MCAN_TXBAR_AR12_MASK (0x00001000U)
1417 #define MCAN_TXBAR_AR13_SHIFT (13U)
1418 #define MCAN_TXBAR_AR13_MASK (0x00002000U)
1420 #define MCAN_TXBAR_AR14_SHIFT (14U)
1421 #define MCAN_TXBAR_AR14_MASK (0x00004000U)
1423 #define MCAN_TXBAR_AR15_SHIFT (15U)
1424 #define MCAN_TXBAR_AR15_MASK (0x00008000U)
1426 #define MCAN_TXBAR_AR16_SHIFT (16U)
1427 #define MCAN_TXBAR_AR16_MASK (0x00010000U)
1429 #define MCAN_TXBAR_AR17_SHIFT (17U)
1430 #define MCAN_TXBAR_AR17_MASK (0x00020000U)
1432 #define MCAN_TXBAR_AR18_SHIFT (18U)
1433 #define MCAN_TXBAR_AR18_MASK (0x00040000U)
1435 #define MCAN_TXBAR_AR19_SHIFT (19U)
1436 #define MCAN_TXBAR_AR19_MASK (0x00080000U)
1438 #define MCAN_TXBAR_AR20_SHIFT (20U)
1439 #define MCAN_TXBAR_AR20_MASK (0x00100000U)
1441 #define MCAN_TXBAR_AR21_SHIFT (21U)
1442 #define MCAN_TXBAR_AR21_MASK (0x00200000U)
1444 #define MCAN_TXBAR_AR22_SHIFT (22U)
1445 #define MCAN_TXBAR_AR22_MASK (0x00400000U)
1447 #define MCAN_TXBAR_AR23_SHIFT (23U)
1448 #define MCAN_TXBAR_AR23_MASK (0x00800000U)
1450 #define MCAN_TXBAR_AR24_SHIFT (24U)
1451 #define MCAN_TXBAR_AR24_MASK (0x01000000U)
1453 #define MCAN_TXBAR_AR25_SHIFT (25U)
1454 #define MCAN_TXBAR_AR25_MASK (0x02000000U)
1456 #define MCAN_TXBAR_AR26_SHIFT (26U)
1457 #define MCAN_TXBAR_AR26_MASK (0x04000000U)
1459 #define MCAN_TXBAR_AR27_SHIFT (27U)
1460 #define MCAN_TXBAR_AR27_MASK (0x08000000U)
1462 #define MCAN_TXBAR_AR28_SHIFT (28U)
1463 #define MCAN_TXBAR_AR28_MASK (0x10000000U)
1465 #define MCAN_TXBAR_AR29_SHIFT (29U)
1466 #define MCAN_TXBAR_AR29_MASK (0x20000000U)
1468 #define MCAN_TXBAR_AR30_SHIFT (30U)
1469 #define MCAN_TXBAR_AR30_MASK (0x40000000U)
1471 #define MCAN_TXBAR_AR31_SHIFT (31U)
1472 #define MCAN_TXBAR_AR31_MASK (0x80000000U)
1474 #define MCAN_TXBCR_CR0_SHIFT (0U)
1475 #define MCAN_TXBCR_CR0_MASK (0x00000001U)
1477 #define MCAN_TXBCR_CR1_SHIFT (1U)
1478 #define MCAN_TXBCR_CR1_MASK (0x00000002U)
1480 #define MCAN_TXBCR_CR2_SHIFT (2U)
1481 #define MCAN_TXBCR_CR2_MASK (0x00000004U)
1483 #define MCAN_TXBCR_CR3_SHIFT (3U)
1484 #define MCAN_TXBCR_CR3_MASK (0x00000008U)
1486 #define MCAN_TXBCR_CR4_SHIFT (4U)
1487 #define MCAN_TXBCR_CR4_MASK (0x00000010U)
1489 #define MCAN_TXBCR_CR5_SHIFT (5U)
1490 #define MCAN_TXBCR_CR5_MASK (0x00000020U)
1492 #define MCAN_TXBCR_CR6_SHIFT (6U)
1493 #define MCAN_TXBCR_CR6_MASK (0x00000040U)
1495 #define MCAN_TXBCR_CR7_SHIFT (7U)
1496 #define MCAN_TXBCR_CR7_MASK (0x00000080U)
1498 #define MCAN_TXBCR_CR8_SHIFT (8U)
1499 #define MCAN_TXBCR_CR8_MASK (0x00000100U)
1501 #define MCAN_TXBCR_CR9_SHIFT (9U)
1502 #define MCAN_TXBCR_CR9_MASK (0x00000200U)
1504 #define MCAN_TXBCR_CR10_SHIFT (10U)
1505 #define MCAN_TXBCR_CR10_MASK (0x00000400U)
1507 #define MCAN_TXBCR_CR11_SHIFT (11U)
1508 #define MCAN_TXBCR_CR11_MASK (0x00000800U)
1510 #define MCAN_TXBCR_CR12_SHIFT (12U)
1511 #define MCAN_TXBCR_CR12_MASK (0x00001000U)
1513 #define MCAN_TXBCR_CR13_SHIFT (13U)
1514 #define MCAN_TXBCR_CR13_MASK (0x00002000U)
1516 #define MCAN_TXBCR_CR14_SHIFT (14U)
1517 #define MCAN_TXBCR_CR14_MASK (0x00004000U)
1519 #define MCAN_TXBCR_CR15_SHIFT (15U)
1520 #define MCAN_TXBCR_CR15_MASK (0x00008000U)
1522 #define MCAN_TXBCR_CR16_SHIFT (16U)
1523 #define MCAN_TXBCR_CR16_MASK (0x00010000U)
1525 #define MCAN_TXBCR_CR17_SHIFT (17U)
1526 #define MCAN_TXBCR_CR17_MASK (0x00020000U)
1528 #define MCAN_TXBCR_CR18_SHIFT (18U)
1529 #define MCAN_TXBCR_CR18_MASK (0x00040000U)
1531 #define MCAN_TXBCR_CR19_SHIFT (19U)
1532 #define MCAN_TXBCR_CR19_MASK (0x00080000U)
1534 #define MCAN_TXBCR_CR20_SHIFT (20U)
1535 #define MCAN_TXBCR_CR20_MASK (0x00100000U)
1537 #define MCAN_TXBCR_CR21_SHIFT (21U)
1538 #define MCAN_TXBCR_CR21_MASK (0x00200000U)
1540 #define MCAN_TXBCR_CR22_SHIFT (22U)
1541 #define MCAN_TXBCR_CR22_MASK (0x00400000U)
1543 #define MCAN_TXBCR_CR23_SHIFT (23U)
1544 #define MCAN_TXBCR_CR23_MASK (0x00800000U)
1546 #define MCAN_TXBCR_CR24_SHIFT (24U)
1547 #define MCAN_TXBCR_CR24_MASK (0x01000000U)
1549 #define MCAN_TXBCR_CR25_SHIFT (25U)
1550 #define MCAN_TXBCR_CR25_MASK (0x02000000U)
1552 #define MCAN_TXBCR_CR26_SHIFT (26U)
1553 #define MCAN_TXBCR_CR26_MASK (0x04000000U)
1555 #define MCAN_TXBCR_CR27_SHIFT (27U)
1556 #define MCAN_TXBCR_CR27_MASK (0x08000000U)
1558 #define MCAN_TXBCR_CR28_SHIFT (28U)
1559 #define MCAN_TXBCR_CR28_MASK (0x10000000U)
1561 #define MCAN_TXBCR_CR29_SHIFT (29U)
1562 #define MCAN_TXBCR_CR29_MASK (0x20000000U)
1564 #define MCAN_TXBCR_CR30_SHIFT (30U)
1565 #define MCAN_TXBCR_CR30_MASK (0x40000000U)
1567 #define MCAN_TXBCR_CR31_SHIFT (31U)
1568 #define MCAN_TXBCR_CR31_MASK (0x80000000U)
1570 #define MCAN_TXBTO_TO0_SHIFT (0U)
1571 #define MCAN_TXBTO_TO0_MASK (0x00000001U)
1573 #define MCAN_TXBTO_TO1_SHIFT (1U)
1574 #define MCAN_TXBTO_TO1_MASK (0x00000002U)
1576 #define MCAN_TXBTO_TO2_SHIFT (2U)
1577 #define MCAN_TXBTO_TO2_MASK (0x00000004U)
1579 #define MCAN_TXBTO_TO3_SHIFT (3U)
1580 #define MCAN_TXBTO_TO3_MASK (0x00000008U)
1582 #define MCAN_TXBTO_TO4_SHIFT (4U)
1583 #define MCAN_TXBTO_TO4_MASK (0x00000010U)
1585 #define MCAN_TXBTO_TO5_SHIFT (5U)
1586 #define MCAN_TXBTO_TO5_MASK (0x00000020U)
1588 #define MCAN_TXBTO_TO6_SHIFT (6U)
1589 #define MCAN_TXBTO_TO6_MASK (0x00000040U)
1591 #define MCAN_TXBTO_TO7_SHIFT (7U)
1592 #define MCAN_TXBTO_TO7_MASK (0x00000080U)
1594 #define MCAN_TXBTO_TO8_SHIFT (8U)
1595 #define MCAN_TXBTO_TO8_MASK (0x00000100U)
1597 #define MCAN_TXBTO_TO9_SHIFT (9U)
1598 #define MCAN_TXBTO_TO9_MASK (0x00000200U)
1600 #define MCAN_TXBTO_TO10_SHIFT (10U)
1601 #define MCAN_TXBTO_TO10_MASK (0x00000400U)
1603 #define MCAN_TXBTO_TO11_SHIFT (11U)
1604 #define MCAN_TXBTO_TO11_MASK (0x00000800U)
1606 #define MCAN_TXBTO_TO12_SHIFT (12U)
1607 #define MCAN_TXBTO_TO12_MASK (0x00001000U)
1609 #define MCAN_TXBTO_TO13_SHIFT (13U)
1610 #define MCAN_TXBTO_TO13_MASK (0x00002000U)
1612 #define MCAN_TXBTO_TO14_SHIFT (14U)
1613 #define MCAN_TXBTO_TO14_MASK (0x00004000U)
1615 #define MCAN_TXBTO_TO15_SHIFT (15U)
1616 #define MCAN_TXBTO_TO15_MASK (0x00008000U)
1618 #define MCAN_TXBTO_TO16_SHIFT (16U)
1619 #define MCAN_TXBTO_TO16_MASK (0x00010000U)
1621 #define MCAN_TXBTO_TO17_SHIFT (17U)
1622 #define MCAN_TXBTO_TO17_MASK (0x00020000U)
1624 #define MCAN_TXBTO_TO18_SHIFT (18U)
1625 #define MCAN_TXBTO_TO18_MASK (0x00040000U)
1627 #define MCAN_TXBTO_TO19_SHIFT (19U)
1628 #define MCAN_TXBTO_TO19_MASK (0x00080000U)
1630 #define MCAN_TXBTO_TO20_SHIFT (20U)
1631 #define MCAN_TXBTO_TO20_MASK (0x00100000U)
1633 #define MCAN_TXBTO_TO21_SHIFT (21U)
1634 #define MCAN_TXBTO_TO21_MASK (0x00200000U)
1636 #define MCAN_TXBTO_TO22_SHIFT (22U)
1637 #define MCAN_TXBTO_TO22_MASK (0x00400000U)
1639 #define MCAN_TXBTO_TO23_SHIFT (23U)
1640 #define MCAN_TXBTO_TO23_MASK (0x00800000U)
1642 #define MCAN_TXBTO_TO24_SHIFT (24U)
1643 #define MCAN_TXBTO_TO24_MASK (0x01000000U)
1645 #define MCAN_TXBTO_TO25_SHIFT (25U)
1646 #define MCAN_TXBTO_TO25_MASK (0x02000000U)
1648 #define MCAN_TXBTO_TO26_SHIFT (26U)
1649 #define MCAN_TXBTO_TO26_MASK (0x04000000U)
1651 #define MCAN_TXBTO_TO27_SHIFT (27U)
1652 #define MCAN_TXBTO_TO27_MASK (0x08000000U)
1654 #define MCAN_TXBTO_TO28_SHIFT (28U)
1655 #define MCAN_TXBTO_TO28_MASK (0x10000000U)
1657 #define MCAN_TXBTO_TO29_SHIFT (29U)
1658 #define MCAN_TXBTO_TO29_MASK (0x20000000U)
1660 #define MCAN_TXBTO_TO30_SHIFT (30U)
1661 #define MCAN_TXBTO_TO30_MASK (0x40000000U)
1663 #define MCAN_TXBTO_TO31_SHIFT (31U)
1664 #define MCAN_TXBTO_TO31_MASK (0x80000000U)
1666 #define MCAN_TXBCF_CF0_SHIFT (0U)
1667 #define MCAN_TXBCF_CF0_MASK (0x00000001U)
1669 #define MCAN_TXBCF_CF1_SHIFT (1U)
1670 #define MCAN_TXBCF_CF1_MASK (0x00000002U)
1672 #define MCAN_TXBCF_CF2_SHIFT (2U)
1673 #define MCAN_TXBCF_CF2_MASK (0x00000004U)
1675 #define MCAN_TXBCF_CF3_SHIFT (3U)
1676 #define MCAN_TXBCF_CF3_MASK (0x00000008U)
1678 #define MCAN_TXBCF_CF4_SHIFT (4U)
1679 #define MCAN_TXBCF_CF4_MASK (0x00000010U)
1681 #define MCAN_TXBCF_CF5_SHIFT (5U)
1682 #define MCAN_TXBCF_CF5_MASK (0x00000020U)
1684 #define MCAN_TXBCF_CF6_SHIFT (6U)
1685 #define MCAN_TXBCF_CF6_MASK (0x00000040U)
1687 #define MCAN_TXBCF_CF7_SHIFT (7U)
1688 #define MCAN_TXBCF_CF7_MASK (0x00000080U)
1690 #define MCAN_TXBCF_CF8_SHIFT (8U)
1691 #define MCAN_TXBCF_CF8_MASK (0x00000100U)
1693 #define MCAN_TXBCF_CF9_SHIFT (9U)
1694 #define MCAN_TXBCF_CF9_MASK (0x00000200U)
1696 #define MCAN_TXBCF_CF10_SHIFT (10U)
1697 #define MCAN_TXBCF_CF10_MASK (0x00000400U)
1699 #define MCAN_TXBCF_CF11_SHIFT (11U)
1700 #define MCAN_TXBCF_CF11_MASK (0x00000800U)
1702 #define MCAN_TXBCF_CF12_SHIFT (12U)
1703 #define MCAN_TXBCF_CF12_MASK (0x00001000U)
1705 #define MCAN_TXBCF_CF13_SHIFT (13U)
1706 #define MCAN_TXBCF_CF13_MASK (0x00002000U)
1708 #define MCAN_TXBCF_CF14_SHIFT (14U)
1709 #define MCAN_TXBCF_CF14_MASK (0x00004000U)
1711 #define MCAN_TXBCF_CF15_SHIFT (15U)
1712 #define MCAN_TXBCF_CF15_MASK (0x00008000U)
1714 #define MCAN_TXBCF_CF16_SHIFT (16U)
1715 #define MCAN_TXBCF_CF16_MASK (0x00010000U)
1717 #define MCAN_TXBCF_CF17_SHIFT (17U)
1718 #define MCAN_TXBCF_CF17_MASK (0x00020000U)
1720 #define MCAN_TXBCF_CF18_SHIFT (18U)
1721 #define MCAN_TXBCF_CF18_MASK (0x00040000U)
1723 #define MCAN_TXBCF_CF19_SHIFT (19U)
1724 #define MCAN_TXBCF_CF19_MASK (0x00080000U)
1726 #define MCAN_TXBCF_CF20_SHIFT (20U)
1727 #define MCAN_TXBCF_CF20_MASK (0x00100000U)
1729 #define MCAN_TXBCF_CF21_SHIFT (21U)
1730 #define MCAN_TXBCF_CF21_MASK (0x00200000U)
1732 #define MCAN_TXBCF_CF22_SHIFT (22U)
1733 #define MCAN_TXBCF_CF22_MASK (0x00400000U)
1735 #define MCAN_TXBCF_CF23_SHIFT (23U)
1736 #define MCAN_TXBCF_CF23_MASK (0x00800000U)
1738 #define MCAN_TXBCF_CF24_SHIFT (24U)
1739 #define MCAN_TXBCF_CF24_MASK (0x01000000U)
1741 #define MCAN_TXBCF_CF25_SHIFT (25U)
1742 #define MCAN_TXBCF_CF25_MASK (0x02000000U)
1744 #define MCAN_TXBCF_CF26_SHIFT (26U)
1745 #define MCAN_TXBCF_CF26_MASK (0x04000000U)
1747 #define MCAN_TXBCF_CF27_SHIFT (27U)
1748 #define MCAN_TXBCF_CF27_MASK (0x08000000U)
1750 #define MCAN_TXBCF_CF28_SHIFT (28U)
1751 #define MCAN_TXBCF_CF28_MASK (0x10000000U)
1753 #define MCAN_TXBCF_CF29_SHIFT (29U)
1754 #define MCAN_TXBCF_CF29_MASK (0x20000000U)
1756 #define MCAN_TXBCF_CF30_SHIFT (30U)
1757 #define MCAN_TXBCF_CF30_MASK (0x40000000U)
1759 #define MCAN_TXBCF_CF31_SHIFT (31U)
1760 #define MCAN_TXBCF_CF31_MASK (0x80000000U)
1762 #define MCAN_TXBTIE_TIE0_SHIFT (0U)
1763 #define MCAN_TXBTIE_TIE0_MASK (0x00000001U)
1765 #define MCAN_TXBTIE_TIE1_SHIFT (1U)
1766 #define MCAN_TXBTIE_TIE1_MASK (0x00000002U)
1768 #define MCAN_TXBTIE_TIE2_SHIFT (2U)
1769 #define MCAN_TXBTIE_TIE2_MASK (0x00000004U)
1771 #define MCAN_TXBTIE_TIE3_SHIFT (3U)
1772 #define MCAN_TXBTIE_TIE3_MASK (0x00000008U)
1774 #define MCAN_TXBTIE_TIE4_SHIFT (4U)
1775 #define MCAN_TXBTIE_TIE4_MASK (0x00000010U)
1777 #define MCAN_TXBTIE_TIE5_SHIFT (5U)
1778 #define MCAN_TXBTIE_TIE5_MASK (0x00000020U)
1780 #define MCAN_TXBTIE_TIE6_SHIFT (6U)
1781 #define MCAN_TXBTIE_TIE6_MASK (0x00000040U)
1783 #define MCAN_TXBTIE_TIE7_SHIFT (7U)
1784 #define MCAN_TXBTIE_TIE7_MASK (0x00000080U)
1786 #define MCAN_TXBTIE_TIE8_SHIFT (8U)
1787 #define MCAN_TXBTIE_TIE8_MASK (0x00000100U)
1789 #define MCAN_TXBTIE_TIE9_SHIFT (9U)
1790 #define MCAN_TXBTIE_TIE9_MASK (0x00000200U)
1792 #define MCAN_TXBTIE_TIE10_SHIFT (10U)
1793 #define MCAN_TXBTIE_TIE10_MASK (0x00000400U)
1795 #define MCAN_TXBTIE_TIE11_SHIFT (11U)
1796 #define MCAN_TXBTIE_TIE11_MASK (0x00000800U)
1798 #define MCAN_TXBTIE_TIE12_SHIFT (12U)
1799 #define MCAN_TXBTIE_TIE12_MASK (0x00001000U)
1801 #define MCAN_TXBTIE_TIE13_SHIFT (13U)
1802 #define MCAN_TXBTIE_TIE13_MASK (0x00002000U)
1804 #define MCAN_TXBTIE_TIE14_SHIFT (14U)
1805 #define MCAN_TXBTIE_TIE14_MASK (0x00004000U)
1807 #define MCAN_TXBTIE_TIE15_SHIFT (15U)
1808 #define MCAN_TXBTIE_TIE15_MASK (0x00008000U)
1810 #define MCAN_TXBTIE_TIE16_SHIFT (16U)
1811 #define MCAN_TXBTIE_TIE16_MASK (0x00010000U)
1813 #define MCAN_TXBTIE_TIE17_SHIFT (17U)
1814 #define MCAN_TXBTIE_TIE17_MASK (0x00020000U)
1816 #define MCAN_TXBTIE_TIE18_SHIFT (18U)
1817 #define MCAN_TXBTIE_TIE18_MASK (0x00040000U)
1819 #define MCAN_TXBTIE_TIE19_SHIFT (19U)
1820 #define MCAN_TXBTIE_TIE19_MASK (0x00080000U)
1822 #define MCAN_TXBTIE_TIE20_SHIFT (20U)
1823 #define MCAN_TXBTIE_TIE20_MASK (0x00100000U)
1825 #define MCAN_TXBTIE_TIE21_SHIFT (21U)
1826 #define MCAN_TXBTIE_TIE21_MASK (0x00200000U)
1828 #define MCAN_TXBTIE_TIE22_SHIFT (22U)
1829 #define MCAN_TXBTIE_TIE22_MASK (0x00400000U)
1831 #define MCAN_TXBTIE_TIE23_SHIFT (23U)
1832 #define MCAN_TXBTIE_TIE23_MASK (0x00800000U)
1834 #define MCAN_TXBTIE_TIE24_SHIFT (24U)
1835 #define MCAN_TXBTIE_TIE24_MASK (0x01000000U)
1837 #define MCAN_TXBTIE_TIE25_SHIFT (25U)
1838 #define MCAN_TXBTIE_TIE25_MASK (0x02000000U)
1840 #define MCAN_TXBTIE_TIE26_SHIFT (26U)
1841 #define MCAN_TXBTIE_TIE26_MASK (0x04000000U)
1843 #define MCAN_TXBTIE_TIE27_SHIFT (27U)
1844 #define MCAN_TXBTIE_TIE27_MASK (0x08000000U)
1846 #define MCAN_TXBTIE_TIE28_SHIFT (28U)
1847 #define MCAN_TXBTIE_TIE28_MASK (0x10000000U)
1849 #define MCAN_TXBTIE_TIE29_SHIFT (29U)
1850 #define MCAN_TXBTIE_TIE29_MASK (0x20000000U)
1852 #define MCAN_TXBTIE_TIE30_SHIFT (30U)
1853 #define MCAN_TXBTIE_TIE30_MASK (0x40000000U)
1855 #define MCAN_TXBTIE_TIE31_SHIFT (31U)
1856 #define MCAN_TXBTIE_TIE31_MASK (0x80000000U)
1858 #define MCAN_TXBCIE_CFIE0_SHIFT (0U)
1859 #define MCAN_TXBCIE_CFIE0_MASK (0x00000001U)
1861 #define MCAN_TXBCIE_CFIE1_SHIFT (1U)
1862 #define MCAN_TXBCIE_CFIE1_MASK (0x00000002U)
1864 #define MCAN_TXBCIE_CFIE2_SHIFT (2U)
1865 #define MCAN_TXBCIE_CFIE2_MASK (0x00000004U)
1867 #define MCAN_TXBCIE_CFIE3_SHIFT (3U)
1868 #define MCAN_TXBCIE_CFIE3_MASK (0x00000008U)
1870 #define MCAN_TXBCIE_CFIE4_SHIFT (4U)
1871 #define MCAN_TXBCIE_CFIE4_MASK (0x00000010U)
1873 #define MCAN_TXBCIE_CFIE5_SHIFT (5U)
1874 #define MCAN_TXBCIE_CFIE5_MASK (0x00000020U)
1876 #define MCAN_TXBCIE_CFIE6_SHIFT (6U)
1877 #define MCAN_TXBCIE_CFIE6_MASK (0x00000040U)
1879 #define MCAN_TXBCIE_CFIE7_SHIFT (7U)
1880 #define MCAN_TXBCIE_CFIE7_MASK (0x00000080U)
1882 #define MCAN_TXBCIE_CFIE8_SHIFT (8U)
1883 #define MCAN_TXBCIE_CFIE8_MASK (0x00000100U)
1885 #define MCAN_TXBCIE_CFIE9_SHIFT (9U)
1886 #define MCAN_TXBCIE_CFIE9_MASK (0x00000200U)
1888 #define MCAN_TXBCIE_CFIE10_SHIFT (10U)
1889 #define MCAN_TXBCIE_CFIE10_MASK (0x00000400U)
1891 #define MCAN_TXBCIE_CFIE11_SHIFT (11U)
1892 #define MCAN_TXBCIE_CFIE11_MASK (0x00000800U)
1894 #define MCAN_TXBCIE_CFIE12_SHIFT (12U)
1895 #define MCAN_TXBCIE_CFIE12_MASK (0x00001000U)
1897 #define MCAN_TXBCIE_CFIE13_SHIFT (13U)
1898 #define MCAN_TXBCIE_CFIE13_MASK (0x00002000U)
1900 #define MCAN_TXBCIE_CFIE14_SHIFT (14U)
1901 #define MCAN_TXBCIE_CFIE14_MASK (0x00004000U)
1903 #define MCAN_TXBCIE_CFIE15_SHIFT (15U)
1904 #define MCAN_TXBCIE_CFIE15_MASK (0x00008000U)
1906 #define MCAN_TXBCIE_CFIE16_SHIFT (16U)
1907 #define MCAN_TXBCIE_CFIE16_MASK (0x00010000U)
1909 #define MCAN_TXBCIE_CFIE17_SHIFT (17U)
1910 #define MCAN_TXBCIE_CFIE17_MASK (0x00020000U)
1912 #define MCAN_TXBCIE_CFIE18_SHIFT (18U)
1913 #define MCAN_TXBCIE_CFIE18_MASK (0x00040000U)
1915 #define MCAN_TXBCIE_CFIE19_SHIFT (19U)
1916 #define MCAN_TXBCIE_CFIE19_MASK (0x00080000U)
1918 #define MCAN_TXBCIE_CFIE20_SHIFT (20U)
1919 #define MCAN_TXBCIE_CFIE20_MASK (0x00100000U)
1921 #define MCAN_TXBCIE_CFIE21_SHIFT (21U)
1922 #define MCAN_TXBCIE_CFIE21_MASK (0x00200000U)
1924 #define MCAN_TXBCIE_CFIE22_SHIFT (22U)
1925 #define MCAN_TXBCIE_CFIE22_MASK (0x00400000U)
1927 #define MCAN_TXBCIE_CFIE23_SHIFT (23U)
1928 #define MCAN_TXBCIE_CFIE23_MASK (0x00800000U)
1930 #define MCAN_TXBCIE_CFIE24_SHIFT (24U)
1931 #define MCAN_TXBCIE_CFIE24_MASK (0x01000000U)
1933 #define MCAN_TXBCIE_CFIE25_SHIFT (25U)
1934 #define MCAN_TXBCIE_CFIE25_MASK (0x02000000U)
1936 #define MCAN_TXBCIE_CFIE26_SHIFT (26U)
1937 #define MCAN_TXBCIE_CFIE26_MASK (0x04000000U)
1939 #define MCAN_TXBCIE_CFIE27_SHIFT (27U)
1940 #define MCAN_TXBCIE_CFIE27_MASK (0x08000000U)
1942 #define MCAN_TXBCIE_CFIE28_SHIFT (28U)
1943 #define MCAN_TXBCIE_CFIE28_MASK (0x10000000U)
1945 #define MCAN_TXBCIE_CFIE29_SHIFT (29U)
1946 #define MCAN_TXBCIE_CFIE29_MASK (0x20000000U)
1948 #define MCAN_TXBCIE_CFIE30_SHIFT (30U)
1949 #define MCAN_TXBCIE_CFIE30_MASK (0x40000000U)
1951 #define MCAN_TXBCIE_CFIE31_SHIFT (31U)
1952 #define MCAN_TXBCIE_CFIE31_MASK (0x80000000U)
1954 #define MCAN_TXEFC_EFSA_SHIFT (2U)
1955 #define MCAN_TXEFC_EFSA_MASK (0x0000fffcU)
1957 #define MCAN_TXEFC_EFS_SHIFT (16U)
1958 #define MCAN_TXEFC_EFS_MASK (0x003f0000U)
1960 #define MCAN_TXEFC_EFWM_SHIFT (24U)
1961 #define MCAN_TXEFC_EFWM_MASK (0x3f000000U)
1963 #define MCAN_TXEFS_EFFL_SHIFT (0U)
1964 #define MCAN_TXEFS_EFFL_MASK (0x0000003fU)
1966 #define MCAN_TXEFS_EFGI_SHIFT (8U)
1967 #define MCAN_TXEFS_EFGI_MASK (0x00001f00U)
1969 #define MCAN_TXEFS_EFPI_SHIFT (16U)
1970 #define MCAN_TXEFS_EFPI_MASK (0x001f0000U)
1972 #define MCAN_TXEFS_EFF_SHIFT (24U)
1973 #define MCAN_TXEFS_EFF_MASK (0x01000000U)
1975 #define MCAN_TXEFS_TEFL_SHIFT (25U)
1976 #define MCAN_TXEFS_TEFL_MASK (0x02000000U)
1978 #define MCAN_TXEFA_EFAI_SHIFT (0U)
1979 #define MCAN_TXEFA_EFAI_MASK (0x0000001fU)
1981 #define MCAN_ECC_AGGR_REVISION_SCHEME_SHIFT (30U)
1982 #define MCAN_ECC_AGGR_REVISION_SCHEME_MASK (0xc0000000U)
1984 #define MCAN_ECC_AGGR_REVISION_BU_SHIFT (28U)
1985 #define MCAN_ECC_AGGR_REVISION_BU_MASK (0x30000000U)
1987 #define MCAN_ECC_AGGR_REVISION_MODULE_ID_SHIFT (16U)
1988 #define MCAN_ECC_AGGR_REVISION_MODULE_ID_MASK (0x0fff0000U)
1990 #define MCAN_ECC_AGGR_REVISION_REVRTL_SHIFT (11U)
1991 #define MCAN_ECC_AGGR_REVISION_REVRTL_MASK (0x0000f800U)
1993 #define MCAN_ECC_AGGR_REVISION_REVMAJ_SHIFT (8U)
1994 #define MCAN_ECC_AGGR_REVISION_REVMAJ_MASK (0x00000700U)
1996 #define MCAN_ECC_AGGR_REVISION_CUSTOM_SHIFT (6U)
1997 #define MCAN_ECC_AGGR_REVISION_CUSTOM_MASK (0x000000c0U)
1999 #define MCAN_ECC_AGGR_REVISION_REVMIN_SHIFT (0U)
2000 #define MCAN_ECC_AGGR_REVISION_REVMIN_MASK (0x0000003fU)
2002 #define MCAN_ECC_AGGR_VECTOR_SHIFT (0U)
2003 #define MCAN_ECC_AGGR_VECTOR_MASK (0x000007ffU)
2005 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (15U)
2006 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)
2008 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (16U)
2009 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00ff0000U)
2011 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (24U)
2012 #define MCAN_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)
2014 #define MCAN_ECC_AGGR_MISC_STATUS_NUM_RAMS_SHIFT (0U)
2015 #define MCAN_ECC_AGGR_MISC_STATUS_NUM_RAMS_MASK (0x000007ffU)
2017 #define MCAN_ECC_AGGR_WRAP_REVISION_SCHEME_SHIFT (30U)
2018 #define MCAN_ECC_AGGR_WRAP_REVISION_SCHEME_MASK (0xc0000000U)
2020 #define MCAN_ECC_AGGR_WRAP_REVISION_BU_SHIFT (28U)
2021 #define MCAN_ECC_AGGR_WRAP_REVISION_BU_MASK (0x30000000U)
2023 #define MCAN_ECC_AGGR_WRAP_REVISION_MODULE_ID_SHIFT (16U)
2024 #define MCAN_ECC_AGGR_WRAP_REVISION_MODULE_ID_MASK (0x0fff0000U)
2026 #define MCAN_ECC_AGGR_WRAP_REVISION_REVRTL_SHIFT (11U)
2027 #define MCAN_ECC_AGGR_WRAP_REVISION_REVRTL_MASK (0x0000f800U)
2029 #define MCAN_ECC_AGGR_WRAP_REVISION_REVMAJ_SHIFT (8U)
2030 #define MCAN_ECC_AGGR_WRAP_REVISION_REVMAJ_MASK (0x00000700U)
2032 #define MCAN_ECC_AGGR_WRAP_REVISION_CUSTOM_SHIFT (6U)
2033 #define MCAN_ECC_AGGR_WRAP_REVISION_CUSTOM_MASK (0x000000c0U)
2035 #define MCAN_ECC_AGGR_WRAP_REVISION_REVMIN_SHIFT (0U)
2036 #define MCAN_ECC_AGGR_WRAP_REVISION_REVMIN_MASK (0x0000003fU)
2038 #define MCAN_ECC_AGGR_CONTROL_ECC_ENABLE_SHIFT (0U)
2039 #define MCAN_ECC_AGGR_CONTROL_ECC_ENABLE_MASK (0x00000001U)
2040 #define MCAN_ECC_AGGR_CONTROL_ECC_ENABLE_DISABLE (0U)
2041 #define MCAN_ECC_AGGR_CONTROL_ECC_ENABLE_ENABLE (1U)
2043 #define MCAN_ECC_AGGR_CONTROL_ECC_CHECK_SHIFT (1U)
2044 #define MCAN_ECC_AGGR_CONTROL_ECC_CHECK_MASK (0x00000002U)
2045 #define MCAN_ECC_AGGR_CONTROL_ECC_CHECK_DISABLE (0U)
2046 #define MCAN_ECC_AGGR_CONTROL_ECC_CHECK_ENABLE (1U)
2048 #define MCAN_ECC_AGGR_CONTROL_ENABLE_RMW_SHIFT (2U)
2049 #define MCAN_ECC_AGGR_CONTROL_ENABLE_RMW_MASK (0x00000004U)
2050 #define MCAN_ECC_AGGR_CONTROL_ENABLE_RMW_DISABLE (0U)
2051 #define MCAN_ECC_AGGR_CONTROL_ENABLE_RMW_ENABLE (1U)
2053 #define MCAN_ECC_AGGR_CONTROL_FORCE_SEC_SHIFT (3U)
2054 #define MCAN_ECC_AGGR_CONTROL_FORCE_SEC_MASK (0x00000008U)
2056 #define MCAN_ECC_AGGR_CONTROL_FORCE_DED_SHIFT (4U)
2057 #define MCAN_ECC_AGGR_CONTROL_FORCE_DED_MASK (0x00000010U)
2059 #define MCAN_ECC_AGGR_CONTROL_FORCE_N_ROW_SHIFT (5U)
2060 #define MCAN_ECC_AGGR_CONTROL_FORCE_N_ROW_MASK (0x00000020U)
2062 #define MCAN_ECC_AGGR_CONTROL_ERROR_ONCE_SHIFT (6U)
2063 #define MCAN_ECC_AGGR_CONTROL_ERROR_ONCE_MASK (0x00000040U)
2065 #define MCAN_ECC_AGGR_ERROR_CTRL1_ECC_ROW_SHIFT (0U)
2066 #define MCAN_ECC_AGGR_ERROR_CTRL1_ECC_ROW_MASK (0x0000ffffU)
2068 #define MCAN_ECC_AGGR_ERROR_CTRL1_ECC_BIT1_SHIFT (16U)
2069 #define MCAN_ECC_AGGR_ERROR_CTRL1_ECC_BIT1_MASK (0xffff0000U)
2071 #define MCAN_ECC_AGGR_ERROR_CTRL2_ECC_BIT2_SHIFT (0U)
2072 #define MCAN_ECC_AGGR_ERROR_CTRL2_ECC_BIT2_MASK (0x0000ffffU)
2074 #ifdef SOC_XWR68XX
2075 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_SEC_SHIFT (0U)
2076 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_SEC_MASK (0x00000003U)
2078 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_DED_SHIFT (2U)
2079 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_DED_MASK (0x0000000CU)
2081 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_SEC_SHIFT (8U)
2082 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_SEC_MASK (0x00000300U)
2084 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_DED_SHIFT (10U)
2085 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_DED_MASK (0x00000C00U)
2087 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_OTHER_SHIFT (12U)
2088 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_OTHER_MASK (0x000001000U)
2090 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_BIT1_SHIFT (16U)
2091 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_BIT1_MASK (0xffff0000U)
2093 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_ROW_SHIFT (0U)
2094 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_ROW_MASK (0xffffffffU)
2095 #else
2096 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_SEC_SHIFT (0U)
2097 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_SEC_MASK (0x00000001U)
2099 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_DED_SHIFT (1U)
2100 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_DED_MASK (0x00000002U)
2102 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_SEC_SHIFT (8U)
2103 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_SEC_MASK (0x00000100U)
2105 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_DED_SHIFT (9U)
2106 #define MCAN_ECC_AGGR_ERROR_STATUS1_CLR_ECC_DED_MASK (0x00000200U)
2108 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_ROW_SHIFT (16U)
2109 #define MCAN_ECC_AGGR_ERROR_STATUS1_ECC_ROW_MASK (0xffff0000U)
2111 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_BIT1_SHIFT (0U)
2112 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_BIT1_MASK (0x0000ffffU)
2114 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_BIT2_SHIFT (16U)
2115 #define MCAN_ECC_AGGR_ERROR_STATUS2_ECC_BIT2_MASK (0xffff0000U)
2116 #endif
2118 #define MCAN_ECC_AGGR_SEC_EOI_REG_WR_SHIFT (0U)
2119 #define MCAN_ECC_AGGR_SEC_EOI_REG_WR_MASK (0x00000001U)
2121 #define MCAN_ECC_AGGR_SEC_STATUS_REG0_MSGMEM_PEND_SHIFT (0U)
2122 #define MCAN_ECC_AGGR_SEC_STATUS_REG0_MSGMEM_PEND_MASK (0x00000001U)
2124 #define MCAN_ECC_AGGR_SEC_ENABLE_SET_REG0_MSGMEM_SHIFT (0U)
2125 #define MCAN_ECC_AGGR_SEC_ENABLE_SET_REG0_MSGMEM_MASK (0x00000001U)
2127 #define MCAN_ECC_AGGR_SEC_ENABLE_CLR_REG0_MSGMEM_SHIFT (0U)
2128 #define MCAN_ECC_AGGR_SEC_ENABLE_CLR_REG0_MSGMEM_MASK (0x00000001U)
2130 #define MCAN_ECC_AGGR_DED_EOI_REG_WR_SHIFT (0U)
2131 #define MCAN_ECC_AGGR_DED_EOI_REG_WR_MASK (0x00000001U)
2133 #define MCAN_ECC_AGGR_DED_STATUS_REG0_MSGMEM_PEND_SHIFT (0U)
2134 #define MCAN_ECC_AGGR_DED_STATUS_REG0_MSGMEM_PEND_MASK (0x00000001U)
2136 #define MCAN_ECC_AGGR_DED_ENABLE_SET_REG0_MSGMEM_SHIFT (0U)
2137 #define MCAN_ECC_AGGR_DED_ENABLE_SET_REG0_MSGMEM_MASK (0x00000001U)
2139 #define MCAN_ECC_AGGR_DED_ENABLE_CLR_REG0_MSGMEM_SHIFT (0U)
2140 #define MCAN_ECC_AGGR_DED_ENABLE_CLR_REG0_MSGMEM_MASK (0x00000001U)
2142 #define MCAN_MCAN_MSG_MEM_SHIFT (0U)
2143 #define MCAN_MCAN_MSG_MEM_MASK (0xffffffffU)
2145 /* User defined ranges */
2146 #define MCAN_DBTP_DSJW_MAX (0xFU)
2147 #define MCAN_DBTP_DTSEG2_MAX (0xFU)
2148 #define MCAN_DBTP_DTSEG1_MAX (0x1FU)
2149 #define MCAN_DBTP_DBRP_MAX (0x1FU)
2151 #define MCAN_NBTP_NSJW_MAX (0x7FU)
2152 #define MCAN_NBTP_NTSEG2_MAX (0x7FU)
2153 #define MCAN_NBTP_NTSEG1_MAX (0xFFU)
2154 #define MCAN_NBTP_NBRP_MAX (0x1FFU)
2156 #define MCAN_RWD_WDC_MAX (0xFFU)
2158 #define MCAN_TDCR_TDCF_MAX (0x7FU)
2159 #define MCAN_TDCR_TDCO_MAX (0x7FU)
2161 #define MCAN_XIDAM_EIDM_MAX (0x1FFFFFFFU)
2163 #define MCAN_TSCC_TCP_MAX (0xFU)
2165 #define MCAN_TOCC_TOP_MAX (0xFFFFU)
2167 #define MCAN_NDAT1_CLEAR (0xFFFFFFFFU)
2168 #define MCAN_NDAT2_CLEAR (0xFFFFFFFFU)
2170 #ifdef __cplusplus
2171 }
2172 #endif
2174 #endif /* HW_MCANSS_H_ */