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55 READ_RGMII_CFG .macro rtmp, speed_flags
56 TM_DISABLE
57 lbco &rtmp, c9, 0x4, 4
58 and rtmp.b0, rtmp.b0, f_mask_o ; takes only speed/duplex related bits
59 and speed_flags, speed_flags, f_mask_a ; clean old status
60 or speed_flags, speed_flags, rtmp.b0
61 TM_ENABLE
62 .endm
64 ; most likely IPG and backoff is the same timer
65 ; so, we will need only one macro
66 if_ipg_not_expired .macro then_go
67 ; TODO check IPG
68 ; if not expired jmp then_go
69 qbbc $1, GRegs.speed_f, f_wait_ipg
70 ldi32 r2, FW_CONFIG
71 lbbo &r3, r2, TX_IPG, 4 ;
72 lbco &r4, c11, 0x0c, 4 ; read cycle count
73 qbgt then_go, r4, r3 ; not expired yet
74 clr GRegs.speed_f, GRegs.speed_f, f_wait_ipg
75 $1:
76 .endm
78 ; touch r2, r3, r4
79 reset_cycle_cnt .macro
80 lbco &r2, c11, 0x0, 4 ; disable cycle counter
81 clr r2.t3
82 sbco &r2, c11, 0x0, 4
83 zero &r3, 4 ; reset cycle counter
84 sbco &r3, c11, 0xc, 4
85 set r2.t3 ; enable cycle counter
86 sbco &r2, c11, 0x0, 4
87 .endm
89 IPG_10MBPS .set 2400 ; (12 * 8 * 100) nsec / 4
90 IPG_10MBPS7 .set 3800 ; ((12 + 7) * 8 * 100) nsec / 4
91 IPG_10MBPS_ADJ .set 600 ; (3 * 8 * 100) / 4
92 IPG_100MBPS_ADJ .set 60 ; (3 * 8 * 10) / 4
94 start_backoff_timer .macro num
95 reset_cycle_cnt
96 mov r2, num
97 qbge $3, r2, 9
98 ldi r2, 9
99 $3: ldi r3, 1 ; create mask
100 not r3, r3 ;
101 lsl r3, r3, r2 ;
102 not r3, r3 ;
103 GET_IEP_CNT r4 ;
104 xor r4.w0, r4.w0, r4.w2
105 ldi32 r2, FW_CONFIG ; read value from SEED
106 lbbo &r5, r2, CFG_SEED, 4 ; get seed
107 xor r4, r4, r5 ; xor time with seed
108 and r4, r4, r3 ; mask with backoff interval
109 qbbc $1, GRegs.speed_f, f_100mbps
110 ; for 100 mbps multiply on 5.12 usec (r4 << 7)
111 lsl r3, r4, 7
112 ldi r5, IPG_100MBPS_ADJ ;
113 qba $2
114 $1: ; for 10 mbps multiply on 51.2 usec (r4 << 10) + (r4 << 8)
115 lsl r3, r4, 10
116 lsl r4, r4, 8
117 add r3, r3, r4
118 ; for 10 MBPS we need to maintain IPG manually
119 ; so if r3 is 0 then set it to 9.6 usec
120 qbne $2, r3, 0
121 ldi r3, IPG_10MBPS
122 $2: ldi r5, IPG_10MBPS_ADJ ;
123 add r3, r3, r5
124 sbbo &r3, r2, TX_IPG, 4 ; store it to TX_IPG
125 set GRegs.speed_f, GRegs.speed_f, f_wait_ipg
126 .endm
128 start_ipg_timer .macro
129 reset_cycle_cnt
130 ldi32 r2, FW_CONFIG ;
131 ldi r4, IPG_10MBPS7
132 sbbo &r4, r2, TX_IPG, 4 ; store it to TX_IPG
133 set GRegs.speed_f, GRegs.speed_f, f_wait_ipg
134 .endm
137 ; read 8bytes from smem offset to reg and reg+1
138 ; we use r0
139 read_bd_from_smem .macro reg, offset
140 ldi32 r0, FW_CONFIG + offset
141 lbbo ®, r0, 0, 8
142 .endm
144 write_bd_to_smem .macro reg, offset
145 ldi32 r0, FW_CONFIG + offset
146 sbbo ®, r0, 0, 8
147 .endm
149 update_col_status .macro
150 .if $defined("SLICE0")
151 lbco &r2, c27, 0x38, 4
152 .else
153 lbco &r2, c27, 0x3c, 4
154 .endif
155 qbbc $1, r2, 1
156 set GRegs.speed_f, GRegs.speed_f, f_col_detected
157 $1:
158 .endm
160 read_col_status .macro reg
161 .if $defined("SLICE0")
162 lbco ®, c27, 0x38, 4
163 .else
164 lbco ®, c27, 0x3c, 4
165 .endif
166 .endm