463d7521ce78046853ea410ce5f2e0ba365f92dd
[processor-sdk/pdk.git] / packages / ti / drv / emac / firmware / icss_dualmac / src / rxl2_txl2.asm
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55 ;Basic Ethernet rx/tx firmware==> TASK MANAGER + S&F MODE {{{1
56 ;/ modified by DAL
57 ;TXL2 version
58 ; 'new' rxl2 mode, so eof handling is different
59 ; defines for config
60 ; RGMII: set up for RGMII mode
61 ; MII : set up for MII mode (RX ok, TX not tested)
62 ; SLICE0 or SLICE1 must be defined (but not both)
63 ; WAIT_FOR_DEBUGGER: wait for debugger to attach
64 ; VLAN_ENABLED
65 ; PSILOOP
66 DATA_ONLY .set 1 ;control path moved to RTU
68 ; sanity check ;{{{1
69 .if $isdefed("SLICE0") & $isdefed("SLICE1")
70 cant have SLICE0 and SLICE1
71 .endif
72 .if !$isdefed("SLICE0") & !$isdefed("SLICE1")
73 must have slice0 or slice1 defined
74 .endif
76 ; includes {{{1
77 .include "regs.h"
78 .include "portq.h"
79 .include "reg_alias.h"
80 .include "smem.h"
81 .include "bsram_pru.h"
82 .include "spin.h"
83 .include "xfr2vbus_widget.h"
84 .include "xfr2psi_widget.h"
85 .include "basicio.h"
86 .include "tm.h"
87 .include "rx.h"
88 .include "tx.h"
89 .include "filter.h"
90 .include "lebe.h"
91 .include "ipc.h"
92 .include "psiloop.h"
93 .include "iep.h"
94 .include "psisandf.h"
96 loop_here .macro
97 here?: jmp here?
98 .endm
100 ; slice0 vs slice1 {{{1
101 .if $isdefed("SLICE0")
102 .asg MII_RXCFG0_ADDR, MII_RXCFGn_ADDR
103 .asg 0x8, GPCFGn_REG
104 .asg FDB_XID_PORT0_RES, FDB_XID_PORTn_RES
105 .asg MII_PRE_CNT0, MII_PRE_CNTn
106 .else
107 .asg MII_RXCFG1_ADDR, MII_RXCFGn_ADDR
108 .asg 0xc, GPCFGn_REG
109 .asg FDB_XID_PORT1_RES, FDB_XID_PORTn_RES
110 .asg MII_PRE_CNT1, MII_PRE_CNTn
111 .endif
112 ;slice0 controls tx1 if switch, tx0 otherwise
113 ;slice1 controls tx0 if switch, tx1 otherwise
114 .if $isdefed("SLICE0")
115 .asg MII_TXCFG0_ADDR, MII_TXCFGn_ADDR
116 .asg MII_TXIPG0_ADDR, MII_TXIPGn_ADDR
117 .else
118 .asg MII_TXCFG1_ADDR, MII_TXCFGn_ADDR
119 .asg MII_TXIPG1_ADDR, MII_TXIPGn_ADDR
120 .endif
122 ; Enable RX L2 pru0 & rx
123 enable_rx_l2 .macro
124 ldi32 r28, MII_RXCFGn_ADDR
125 lbbo &r11, r28, 0, 4
126 set r11.t4 ;rx l2 enable
127 set r11.t0 ;rx enable
128 set r11.t9 ;rx_eof_sclr_dis0
129 set r11.t1 ;make tx eof visible in r31, bit16
130 sbbo &r11, r28, 0, 4
131 .endm
133 long_preamble_firewall_disable .macro
134 ldi32 r28, MII_PRE_CNTn
135 lbbo &r11, r28, 0, 4
136 and r11.b0, r11.b0, 0x0f
137 sbbo &r11, r28, 0, 4
138 .endm
140 gpcfg_reg_config .macro
141 ldi32 r28, PRUSS1_CFG_PRU_OFFSET
142 lbbo &r11, r28, GPCFGn_REG, 4
143 set r11.t1
144 set r11.t0
145 set r11.t27
146 sbbo &r11, r28, GPCFGn_REG, 4
147 .endm
149 mii_tx_config .macro
150 ldi32 r28, MII_TXCFGn_ADDR
151 lbbo &r11, r28, 0, 4
152 set r11.t0 ;enable txl1
153 set r11.t11 ;tx_32_mode en
154 set r11.t1 ;tx_auto_preamble
155 ;set mux
156 .if $isdefed("SLICE0")
157 clr r11.t8
158 .else
159 set r11.t8
160 .endif
161 ldi r11.b2, 0 ;set tx start delay to 0!!!
162 clr r11.t25
163 clr r11.t24
164 sbbo &r11, r28, 0, 4
165 .endm
167 set_tx_ipg .macro
168 ;change ipg to 88 ns (22 250mhz clocks)
169 ldi32 r28, MII_TXIPGn_ADDR
170 lbbo &r11, r28, 0, 4
171 ldi r11, 0x16 ; min IPG for testing (CCLINK)
172 sbbo &r11, r28, 0, 4
173 .endm
175 icss_g_config .macro
176 ; **for now let slice0 do txl2 & port mode config (ICSS_G register) for both sides {{{2
177 ;TX Config TXl2 - icss_g register
178 ldi32 r28, ICSS_G
179 lbbo &r11, r28, 0, 4
180 set r11.t1
181 set r11.t0
182 set r11.t2 ;rx_l2_g_en
184 .if $isdefed("RGMII")
185 set r11.t3
186 clr r11.t4
187 set r11.t5
188 clr r11.t6
189 .endif
190 .if $isdefed("MII")
191 clr r11.t3
192 clr r11.t4
193 clr r11.t5
194 clr r11.t6
195 .endif
196 sbbo &r11, r28, 0, 4
197 .endm
199 wait4debugger .macro
200 .if $isdefed("WAIT_FOR_DEBUGGER")
201 ldi32 r11, 0
202 $1: qbeq $1, r11, 0
203 .endif
204 .endm
206 ; Code starts {{{1
207 .retain ; Required forbuilding .out with assembly file
208 .retainrefs ; Required forbuilding .out with assembly file
209 .sect ".text:Start"
210 .global Start
212 Start:
213 TM_DISABLE
214 zero &r0, 124
215 P2P_IPC_ZAP ;zap IPC area
216 xout XFR2VBUS_XID_READ0, &r18, 4 ;disable xfr2vbus autoread mode
217 xout XFR2VBUS_XID_READ1, &r18, 4 ;
219 ;Initialization: set up RX & TX MII stuff.
220 enable_rx_l2
221 long_preamble_firewall_disable
222 gpcfg_reg_config ; 0x0800_0003
223 mii_tx_config
224 set_tx_ipg
225 icss_g_config
227 wait4debugger
229 set r31, r31, 18 ;RX reset
230 ;setup BSRAM
231 BSRAM_ZERO_BANK r1
233 ;SETUP portQ for to-host traffic, in order to do sandf PSI
234 PSIQ_CREATE
236 ;set up PSI INFO, CONTROL, STATUS TEMPLATES
237 .if $isdefed("SLICE0")
238 PSI_SETUP_INFO PSI_INFO_SLOT, 1
239 .else
240 PSI_SETUP_INFO PSI_INFO_SLOT, 2
241 .endif
242 PSI_SETUP_STATUS PSI_STATUS_SLOT
244 ;VA we should start here
245 ldi GRegs.pkt_cnt.x, 0
247 ;START RX/TX of 1 packet burst ; {{{1
248 RX:
249 RX_TASK_INIT
250 ;setup taskmanager
251 TM_PRU_CONFIG RX_SOF, RX_B0, RX_B1, RX_BN, RX_EOF, TX_NOP, TX_NOP, TX_FIFO, TX_EOF, RXTX_ERR
252 TM_ENABLE
253 set r31.t18 ;RX reset
254 ldi r18, 0
255 xout 40, &r18, 4 ;set tx fifo mode
257 ;read in global state
258 ldi GRegs.pkt_cnt.x, 0
259 ldi GRegs.tx.b.state, 0
260 ldi GRegs.rx.x, 0
261 ldi GRegs.snf.b.wr_cur, MINPS
262 ldi GRegs.snf.b.rd_cur, MINPS
263 ldi r30, 1522 ;todo - make a parameter
264 ldi32 r10, FW_CONFIG
265 lbbo &r2, r10, CFG_N_BURST, 4
267 ; set pru ready status
268 ldi32 r0, PRU_READY
269 sbbo &r0, r10, CFG_STATUS, 4
270 ; wait rtu ready
271 ldi32 r1, RTU_READY
272 wait_rtu_ready:
273 lbbo &r0, r10, CFG_RTU_STATUS, 4
274 qbne wait_rtu_ready, r0, r1
275 ; let's go
277 ;-------------------------------------------------------------------
278 ;BG TASK: r24-r29 are global ;{{{1
279 ;-------------------------------------------------------------------------
280 zero &r18, 24
281 mov BgRegs.borg_limit, r2 ; GS_NBURST ;
283 ;================================
284 ; BG LOOP: stay here until we see
285 ; GRegs.pkt_cnt.w.tx == BgRegs.borg_limit if in borg mode
286 ; until cmd cancel seen
287 ;=================================
288 bg_loop:
289 add BgRegs.bg_cnt, BgRegs.bg_cnt, 1 ;loop count
290 ;can we exit?
291 qbeq skip_chk, BgRegs.borg_limit, 0
292 qbeq bg_done, GRegs.pkt_cnt.w.tx, BgRegs.borg_limit ; done
293 skip_chk:
294 ; if RTU started shutdown process - disable TM and loop forever
295 ldi32 r0, FW_CONFIG
296 ldi32 r1, RTU_STARTED_SHUTDOWN
297 lbbo &r9, r0, CFG_RTU_STATUS, 4
298 qbne skip_chk01, r9, r1
299 ;disable xfr2vbus autoread mode
300 ldi32 r18, 0
301 xout XFR2VBUS_XID_READ0, &r18, 4
302 xout XFR2VBUS_XID_READ1, &r18, 4
304 ; if we are here, we can place debug error code somewere in the SMEM
305 TM_DISABLE
306 ldi32 r1, PRU_STOPPED
307 sbbo &r1, r0, CFG_STATUS, 4
308 loop_here
310 skip_chk01:
311 ;-----------------------
312 ;schedule TX2HOST?
313 ;----------------------
314 ; do nothing if widget is full!!
315 xin XID_PSI_S, &r1,8
316 qbbc scheduler, r2,TB_WRITE
317 qbeq th_schedule0, BgRegs.psi2h_active, 0
318 ; active 2host
319 PSISANDF_TX bg_to_host2, scheduler
320 bg_to_host2: ;go again
321 xin XID_PSI_S, &r1,8
322 qbbc scheduler, r2,TB_WRITE
323 PSISANDF_TX scheduler, scheduler
324 jmp scheduler ;just in case
325 th_schedule0:
326 qbeq scheduler, GRegs.psiq.b.num_elem, 0
327 ; have new packet to send
328 TM_DISABLE
329 PSIQ_POP
330 TM_ENABLE
331 ;r2 = flow | len r3 = starting read index
332 PSISANDF_TX_INIT2 r2, r3
334 ;-----------------------
335 ;schedule TX2WIRE ?
336 ;----------------------
337 scheduler:
338 TM_DISABLE
339 qbeq bg_schedule0, GRegs.tx.b.state, TX_S_IDLE ;if tx state is idle, check IPC for new descriptor
340 qbeq bg_schedule1, GRegs.tx.b.state, TX_S_ERR ;if tx state is idle, check IPC for new descriptor
341 .if $isdefed("PSILOOP")
342 qbeq bg_schedulePL, GRegs.tx.b.state, TX_S_LOOP ;if psi loopback
343 .endif
345 ;TX ACTIVE.
346 sched_done:
347 TM_ENABLE
348 jmp bg_loop
350 bg_schedule0:
351 ;non PSA case only check expected next dma
352 qbbs bg_chk1, GRegs.tx.b.flags, f_next_dma
353 ;check dma0
354 PRU_IPC_RX_CH0Q sched_done, r2, XFR2VBUS_XID_READ0
355 ; have new packet in r2= len-flags
356 .if $isdefed("PSILOOP")
357 PSILOOP_TX_INIT r2, XFR2VBUS_XID_READ0
358 ;don't pingpong with PSILOOP!
359 .else
360 TX_TASK_INIT2_shell r2
361 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
362 .endif
363 TM_ENABLE
364 jmp bg_loop
365 bg_chk1:
366 ;check 2nd dma
367 PRU_IPC_RX_CH0Q sched_done, r3, XFR2VBUS_XID_READ1
368 TX_TASK_INIT2_shell r3
369 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
370 TM_ENABLE
371 jmp bg_loop
373 bg_schedule1:
374 ;error case (underflow)
375 ;todo
376 ldi GRegs.tx.b.state, TX_S_IDLE
377 TM_ENABLE
378 jmp bg_loop
379 .if $isdefed("PSILOOP")
380 bg_schedulePL:
381 ;psi loopback
382 flip_tx_r10_r23
383 PSILOOP_TX_POLL XFR2VBUS_XID_READ0, psi_poll_done, psi_poll_done
384 psi_poll_done:
385 flip_tx_r10_r23
386 TM_ENABLE
387 jmp bg_loop
388 .endif
390 ;-------------------------------------
391 ; done with packets.
392 ;-------------------------------------
393 bg_done:
395 ;save bg info: bg loops, txstate, rxstate, (pkt counts)
396 PAGE_RESTORE BG_STATE, 32
397 mov r2, BgRegs.bg_cnt
398 mov r3, GRegs.tx.x
399 mov r4, GRegs.rx.x
400 mov r5, GRegs.pkt_cnt.x
401 PAGE_SAVEQ
403 ;update result area (length)
404 ldi32 r1, FW_CONFIG
405 sbbo &r2, r1, CFG_OUT, 20
406 ldi32 r2, 0x10000001
407 sbbo &r2, r1, CFG_STATUS, 4
408 loop_here
410 ;-------------------------------------------------------------------------
411 ;end BG task
412 ;-------------------------------------------------------------------------
414 ;---------------------------------------------------------------------
415 ; TX_EOF EvENT {{{1
416 ;----------------------------------------------------------------------
417 TX_EOF:
418 qbne tx_underflow, GRegs.tx.b.state, TX_S_W_EOF
419 ; TX TS processing
420 flip_tx_r0_r23
421 qbbc no_tx_ts, TxRegs.ds_flags, 5 ; we don't need tx_ts
422 GET_PKT_TX_TS r2
423 ldi32 r10, FW_CONFIG + TX_TS_BASE
424 sbbo &r2, r10, 0, 8
425 SPIN_TOG_LOCK_LOC PRU_RTU_TX_TS_READY
426 no_tx_ts:
427 flip_tx_r0_r23
429 ;-----------------------------
430 ;Legit EOF. Restore registers
431 ;-----------------------------
432 legit_tx_eof:
433 flip_tx_r0_r23
434 qbbs teof_chk1, GRegs.tx.b.flags, f_next_dma
435 ;check dma0
436 PRU_IPC_RX_CH0Q no_new_tx, r2, XFR2VBUS_XID_READ0
437 ; have new packet in r2= len-flags
438 TX_TASK_INIT2 r2
439 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
440 jmp tx_eof_on_deck_done
441 teof_chk1:
442 ;check 2nd dma
443 PRU_IPC_RX_CH0Q no_new_tx, r3, XFR2VBUS_XID_READ1
444 TX_TASK_INIT2 r3
445 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
447 ;started next pkt, terminate task
448 tx_eof_on_deck_done:
449 TM_YIELD
450 ;these next 2 instructions are done in delayed branch fashion
451 flip_tx_r0_r23
452 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
453 loop_here
455 ;---------------------------------------------
456 ;eof w/ no new packet to TX
457 ;---------------------------------------------
458 no_new_tx:
459 ldi GRegs.tx.b.state, TX_S_IDLE
460 TM_YIELD
461 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
462 flip_tx_r0_r23
463 loop_here
465 ;------exception cases------
466 ;underflow case:
467 tx_underflow:
468 ldi GRegs.tx.b.state, TX_S_ERR
469 TM_YIELD
470 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
471 loop_here
473 ;---------------------------------------------------------------------
474 ; ENd TX_EOF
475 ;----------------------------------------------------------------------
477 ;---------------------------------------------------------------------
478 ; TX_FIFO EVENT {{{1
479 ;----------------------------------------------------------------------
480 TX_FIFO:
481 qbeq handle_portq, GRegs.tx.b.state, TX_S_ACTIVE
482 ;ignore rest
483 TM_YIELD
484 loop_here
486 ;----------------------
487 ; FROM PORTQ CASE
488 ;----------------------
489 handle_portq:
490 flip_tx_r0_r23
491 ;
492 ;check to see if need to preempt!
493 ; conditions: preempt enabled on port and pkt is preemptible
494 ; and enuf bytes sent and enuf bytes left and
495 ; (hold set or Express Frame waiting )
496 ;if not preemptible pkt skip all
497 qbbs skip_preempt, TxRegs.ds_flags, 4 ; R_TX_D1.f_desc_express
498 qbne skip_preempt, TxRegs.pp_ppok, PPOK
499 qbbs do_preempt, GRegs.tx.b.flags, f_tx_hold
500 qbbs do_preempt, GRegs.tx.b.flags, f_tx_efq
501 qbbc skip_preempt, GRegs.tx.b.flags, f_tx_efqd
502 do_preempt:
503 END_TX_MCRC ;send MCRC
504 mov TxRegs.stash_ds_flags, TxRegs.ds_flags
505 mov TxRegs.stash_tx_len, GRegs.tx.b.len
507 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_tx_stash ;so we know
508 ldi GRegs.tx.b.state, TX_S_W_PEOF
509 TM_YIELD
510 flip_tx_r0_r23
511 add TxRegs.pp_count, TxRegs.pp_count, 1
512 loop_here
514 skip_preempt:
515 ;assume data is here
516 TX_FILL_FIFO XFR2VBUS_XID_READ0
517 TM_YIELD
518 flip_tx_r0_r23
519 loop_here
521 ;-------------------------------------------------------------------------
522 ; End TX_FIFO EVENT
523 ;-------------------------------------------------------------------------
525 ;-------------------------------------------------------------------------
526 ;RXTX_ERR EVENT ; {{{1
527 ; assume rx issue.
528 ; reset rxl2 fifo
529 ; hopefully that cleans things up
530 ; need to see what else needs to be done
531 RXTX_ERR:
532 flip_tx_r0_r23
533 qbne rx_err?, GRegs.tx.b.state, TX_S_ERR
534 ; wait DMA ir complete
535 qbbs $3, TxRegs.ds_flags, 4
536 $1: xin XFR2VBUS_XID_READ0, &r18, 4
537 qbeq $2, r18.w0, 0x5
538 qbeq $2, r18, 0
539 qba $1
540 $2: nop
541 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ0
542 nop
543 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ0
544 SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
545 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
546 jmp $5
547 $3: xin XFR2VBUS_XID_READ1, &r18, 4
548 qbeq $4, r18.w0, 0x5
549 qbeq $4, r18, 0
550 qba $3
551 $4: nop
552 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ1
553 nop
554 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ1
555 SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
556 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
557 $5:
558 set r31.t30; TX_RESET
559 nop
560 nop
561 ;set TX to TX_S_IDLE
562 ldi GRegs.tx.b.state, TX_S_IDLE
563 qba rxtx_err_exit
564 rx_err?
565 ldi r11.b3, 0x80
566 xout 22, &r11, 4
567 set r31.t22 ; clear rx eof (why isnt it bit 20?)
568 ldi r7, 1 ;indicate we drop
569 ;for now assume it is the RXL1 overflowing for next frame
570 ;todo: how to check to see if it is for this frame??
571 ldi GRegs.rx.b.state, RX_STATE_OVER0
572 rxtx_err_exit:
573 TM_YIELD
574 flip_tx_r0_r23
575 loop_here
577 ;-------------------------------------------------------------------------
578 ; Dummy: TX_NOP {{{1
579 ;-------------------------------------------------------------------------
580 TX_NOP:
581 TM_YIELD
582 loop_here
583 ;----------------------------------------------------------------------
584 ; Dummy: END TX_NOP
585 ;-------------------------------------------------------------------------
587 ;---------------------------------------------------------------
588 ; RX TASK, State 1: RX SOF {{{1
589 ;--------------------------------------------------------------
590 RX_SOF:
591 ;turn off RX_SOF
592 TM_YIELD
593 loop_here
594 ;---------------------------------------------------------------
595 ; END RX TASK, State 1
596 ;--------------------------------------------------------------
598 NBTR .set 32
599 ;---------------------------------------------------------------
600 ; RX TASK, State 2: RX_B0 {{{1
601 ;--------------------------------------------------------------
602 RX_B0:
603 flip_rx_r0_r23
605 ;BRING IN THE DATA
606 xin RXL2_BANK0, &r2, NBTR
607 ldi RxRegs.aux_flags, 1
608 qbeq rxb0_already_over, GRegs.rx.b.state, RX_STATE_OVER0
610 ldi GRegs.rx.x, 0x180 ;fresh state=1, (sof flag set)
611 P_W32_S rxb0_full ;stash pkt bytes in bs slot but don't start
613 jmp rx_b0_done
615 ;some error/exception cases handling here
616 rxb0_full: ;psi fifo in bsram full
617 P_W32_ABORT
618 ldi GRegs.rx.x, 0x7F80
619 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt, 1
620 jmp rx_b0_done
622 rxb0_already_over:
623 ldi GRegs.rx.x, 0x7F80
624 ;todo: bump stats
626 rx_b0_done:
627 TM_YIELD
628 flip_rx_r0_r23
629 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32 ;hopefully this gets executed!!
630 loop_here
631 ;---------------------------------------------------------------
632 ; END RX TASK, State 2
633 ;--------------------------------------------------------------
635 ;---------------------------------------------------------------
636 ; RX TASK, State 3: RX_B1 {{{1
637 ;--------------------------------------------------------------
638 RX_B1:
639 flip_rx_r0_r23
640 qbeq skip_b1, GRegs.rx.b.state, RX_STATE_DROP
641 ;!!better be here!!
642 ;r5.b0 = route info
643 ;r5.b1 = fid
644 ;r5.w2 = index
645 ;r6 = buffer ptr for s&f
646 ldi r0.b1, 0
647 stall_loop:
648 PRU_IPC_RX_CH1
649 qbbs got_ipc, r5.b0, f_rx_sof
650 add r0.b1, r0.b1, 1
651 qbne stall_loop, r0.b1, RB1_STALL_LIMIT
652 ldi GRegs.rx.b.state, RX_STATE_DROP ;stall limit reached
653 jmp rb1_ipc_done
654 got_ipc:
655 mov GRegs.rx.b.flags, r5.b0 ;forwarding info we got from RTU
656 PRU_IPC_RX_CH1_CLRB7 ;clear bit so we know we got it
657 mov RxRegs.pq_cur, r6 ;save buffer pointer (may not use) ;=flow in MAC
659 rb1_ipc_done:
660 xin RXL2_BANK1, &r2, 32 ;bring in data (r2-r9)
661 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
662 set RxRegs.aux_flags, RxRegs.aux_flags, f_b1_seen
664 TM_DISABLE
665 qbbc b1_rx_path1a, GRegs.rx.b.flags, f_tohost
666 P_W32 rxb1_full ;stash pkt bytes in bs slot
667 jmp rx_b1_done
668 rxb1_full:
669 ldi GRegs.rx.x, 0x7F80
670 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
671 b1_rx_path1a:
672 P_W32_ABORT ;abort the stashing of pkt in BS (for PSI)
673 rx_b1_done:
674 TM_ENABLE
675 b1_exit:TM_YIELD
676 flip_rx_r0_r23
677 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
678 loop_here
680 skip_b1:xin RXL2_BANK1, &r2, 32 ;error case. just read in data and drop
681 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
682 jmp b1_exit
683 ;---------------------------------------------------------------
684 ; END RX TASK, State 3
685 ;--------------------------------------------------------------
687 ;---------------------------------------------------------------
688 ; RX TASK, State 4: RX_BN {{{1
689 ;--------------------------------------------------------------
690 RX_BN:
691 flip_rx_r0_r23
692 ;check for overflow/drop or pkt too long
693 qbne pkt_ok, GRegs.rx.b.state, RX_STATE_DROP
694 ;errors:
695 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
696 qbbs rx_bnerr_sideB, RxRegs.aux_flags, f_fh
697 ;side A
698 xin RXL2_BANK0, &r2, 32
699 jmp rx_bn_done
700 rx_bnerr_sideB:
701 ;side B
702 xin RXL2_BANK1, &r2, 32
703 jmp rx_bn_done
704 rxbn_full:
705 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
706 P_W32_ABORT
707 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
708 jmp rx_bn_done
710 ;take pkt, all good
711 pkt_ok: qbbs rx_bn_sideB, RxRegs.aux_flags, f_fh
712 xin RXL2_BANK0, &r2, 32
713 set RxRegs.aux_flags, RxRegs.aux_flags, f_fh
714 jmp bn_cont1
715 rx_bn_sideB:
716 xin RXL2_BANK1, &r2, 32
717 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
718 bn_cont1:
719 qbbc rx_bn_done, GRegs.rx.x, 0
720 P_W32 rxbn_full
721 rx_bn_done:
722 TM_YIELD
723 flip_rx_r0_r23
724 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
725 loop_here
726 ;---------------------------------------------------------------
727 ; END RX TASK, State 4
728 ;--------------------------------------------------------------
730 ;---------------------------------------------------------------
731 ; RX TASK, State 5: RX_EOF {{{1
732 ;--------------------------------------------------------------
733 RX_EOF:
734 TM_DISABLE
735 flip_rx_r0_r23
736 qbeq no_rx_sof, GRegs.rx.b.state, RX_STATE_DROP
737 qbbc no_rx_sof, GRegs.rx.b.flags, f_rx_sof
738 ldi r0.w0, 0x3310
739 and r0.w0, r31.w2, r0.w0
740 qbne beof_rx_err, r0.b0, 0x10 ;check for rx errors
741 qbbs rx_beof_sideB, RxRegs.aux_flags, f_fh
743 ;side A, r18 and r0.b0 has length
744 RX_EOF_RCV_BANK0
745 ldi r11.b3, 0x80
746 xout 22, &r11, 4
747 set r31.t22 ; clear rx eof (why isnt it bit 20?)
748 mov RxRegs.res1, r0.b0
749 jmp rx_beof_cont0
751 rx_beof_sideB:
752 ;side B, r18 and r0.b0 has length
753 RX_EOF_RCV_BANK1
754 ldi r11.b3, 0x80
755 xout 22, &r11, 4
756 set r31.t22 ; clear rx eof (why isnt it bit 20?)
757 add RxRegs.res1, r0.b0, 32
759 rx_beof_cont0:
760 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, r0.b0
761 qbbc rx_eof_done, GRegs.rx.b.flags, f_tohost
762 ;check for pkt to long
763 qbge th_pkt_ok, GRegs.rx.b.pkt_len, r30.w0
764 add r30.w2, r30.w2,1 ; max error (like crc)
765 P_W32_ABORT
766 jmp rx_eof_done
767 th_pkt_ok:
768 ; push 32 to bsram fifo (not all will be valid)
769 P_W32 rxeof_noroom
770 ; push 'descriptor' to local queue. will be popped by bg task
771 mov r2.w2, RxRegs.pq_cur ;flow
772 mov r2.w0, GRegs.rx.b.pkt_len
773 mov r3, GRegs.snf.x ;bsram fifo position (maybe not necessary)
774 ;to do add rxtx timestamp
775 PSIQ_PUSH rxeof_qfull
777 rx_eof_done:
778 ; check for runt packet
779 qble rx_eof_done_b, GRegs.rx.b.pkt_len, 64
780 set r31.t18 ;reset RX_fifo
782 rx_eof_done_b:
783 TM_ENABLE
784 flip_rx_r0_r23
785 TM_YIELD
786 ldi GRegs.rx.s.fl_n_state, 0
787 add GRegs.pkt_cnt.w.rx, GRegs.pkt_cnt.w.rx, 1 ;also should tell bg #of pkts we have procesed
788 loop_here
790 ;----------------------------
791 ; bad frame, error handling
792 ;-----------------------------
793 rxeof_noroom:
794 rxeof_qfull:
795 P_W32_ABORT
796 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
797 jmp rx_eof_done
799 beof_rx_err:
800 no_rx_sof:
801 ;saw no sof before eof or other such issues
802 ldi r11.b3, 0x80
803 xout 22, &r11, 4
804 set r31, r31, 22 ; clear rx eof (why isnt it bit 20?)
805 jmp rx_eof_done
806 ;---------------------------------------------------------------
807 ; END RX TASK, State 5
808 ;--------------------------------------------------------------
810 .include "resource_table.h"