[processor-sdk/pdk.git] / packages / ti / drv / emac / firmware / icss_dualmac / src / rxl2_txl2.asm
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55 ;Basic Ethernet rx/tx firmware==> TASK MANAGER + S&F MODE {{{1
56 ;/ modified by DAL
57 ;TXL2 version
58 ; 'new' rxl2 mode, so eof handling is different
59 ; defines for config
60 ; RGMII: set up for RGMII mode
61 ; MII : set up for MII mode (RX ok, TX not tested)
62 ; SLICE0 or SLICE1 must be defined (but not both)
63 ; WAIT_FOR_DEBUGGER: wait for debugger to attach
64 ; VLAN_ENABLED
65 ; PSILOOP
66 DATA_ONLY .set 1 ;control path moved to RTU
68 ; sanity check ;{{{1
69 .if $isdefed("SLICE0") & $isdefed("SLICE1")
70 cant have SLICE0 and SLICE1
71 .endif
72 .if !$isdefed("SLICE0") & !$isdefed("SLICE1")
73 must have slice0 or slice1 defined
74 .endif
76 ; includes {{{1
77 .include "regs.h"
78 .include "portq.h"
79 .include "reg_alias.h"
80 .include "smem.h"
81 .include "bsram_pru.h"
82 .include "spin.h"
83 .include "xfr2vbus_widget.h"
84 .include "xfr2psi_widget.h"
85 .include "basicio.h"
86 .include "tm.h"
87 .include "rx.h"
88 .include "tx.h"
89 .include "filter.h"
90 .include "lebe.h"
91 .include "ipc.h"
92 .include "psiloop.h"
93 .include "iep.h"
94 .include "psisandf.h"
96 loop_here .macro
97 here?: jmp here?
98 .endm
100 ; slice0 vs slice1 {{{1
101 .if $isdefed("SLICE0")
102 .asg MII_RXCFG0_ADDR, MII_RXCFGn_ADDR
103 .asg 0x8, GPCFGn_REG
104 .asg FDB_XID_PORT0_RES, FDB_XID_PORTn_RES
105 .asg MII_PRE_CNT0, MII_PRE_CNTn
106 .else
107 .asg MII_RXCFG1_ADDR, MII_RXCFGn_ADDR
108 .asg 0xc, GPCFGn_REG
109 .asg FDB_XID_PORT1_RES, FDB_XID_PORTn_RES
110 .asg MII_PRE_CNT1, MII_PRE_CNTn
111 .endif
112 ;slice0 controls tx1 if switch, tx0 otherwise
113 ;slice1 controls tx0 if switch, tx1 otherwise
114 .if $isdefed("SLICE0")
115 .asg MII_TXCFG0_ADDR, MII_TXCFGn_ADDR
116 .asg MII_TXIPG0_ADDR, MII_TXIPGn_ADDR
117 .else
118 .asg MII_TXCFG1_ADDR, MII_TXCFGn_ADDR
119 .asg MII_TXIPG1_ADDR, MII_TXIPGn_ADDR
120 .endif
122 ; Enable RX L2 pru0 & rx
123 enable_rx_l2 .macro
124 ldi32 r28, MII_RXCFGn_ADDR
125 lbbo &r11, r28, 0, 4
126 set r11.t4 ;rx l2 enable
127 set r11.t0 ;rx enable
128 set r11.t9 ;rx_eof_sclr_dis0
129 set r11.t1 ;make tx eof visible in r31, bit16
130 sbbo &r11, r28, 0, 4
131 .endm
133 long_preamble_firewall_disable .macro
134 ldi32 r28, MII_PRE_CNTn
135 lbbo &r11, r28, 0, 4
136 and r11.b0, r11.b0, 0x0f
137 sbbo &r11, r28, 0, 4
138 .endm
140 gpcfg_reg_config .macro
141 ldi32 r28, PRUSS1_CFG_PRU_OFFSET
142 lbbo &r11, r28, GPCFGn_REG, 4
143 set r11.t1
144 set r11.t0
145 set r11.t27
146 sbbo &r11, r28, GPCFGn_REG, 4
147 .endm
149 mii_tx_config .macro
150 ldi32 r28, MII_TXCFGn_ADDR
151 lbbo &r11, r28, 0, 4
152 set r11.t0 ;enable txl1
153 set r11.t11 ;tx_32_mode en
154 set r11.t1 ;tx_auto_preamble
155 ;set mux
156 .if $isdefed("SLICE0")
157 clr r11.t8
158 .else
159 set r11.t8
160 .endif
161 ldi r11.b2, 0 ;set tx start delay to 0!!!
162 clr r11.t25
163 clr r11.t24
164 sbbo &r11, r28, 0, 4
165 .endm
167 set_tx_ipg .macro
168 ;change ipg to 88 ns (22 250mhz clocks)
169 ldi32 r28, MII_TXIPGn_ADDR
170 lbbo &r11, r28, 0, 4
171 ldi r11, 0x16 ; min IPG for testing (CCLINK)
172 sbbo &r11, r28, 0, 4
173 .endm
175 icss_g_config .macro
176 ; **for now let slice0 do txl2 & port mode config (ICSS_G register) for both sides {{{2
177 ;TX Config TXl2 - icss_g register
178 ldi32 r28, ICSS_G
179 lbbo &r11, r28, 0, 4
180 set r11.t1
181 set r11.t0
182 set r11.t2 ;rx_l2_g_en
184 .if $isdefed("RGMII")
185 set r11.t3
186 clr r11.t4
187 set r11.t5
188 clr r11.t6
189 .endif
190 .if $isdefed("MII")
191 clr r11.t3
192 clr r11.t4
193 clr r11.t5
194 clr r11.t6
195 .endif
196 sbbo &r11, r28, 0, 4
197 .endm
199 wait4debugger .macro
200 .if $isdefed("WAIT_FOR_DEBUGGER")
201 ldi32 r11, 0
202 $1: qbeq $1, r11, 0
203 .endif
204 .endm
206 ; Code starts {{{1
207 .retain ; Required forbuilding .out with assembly file
208 .retainrefs ; Required forbuilding .out with assembly file
209 .sect ".text:Start"
210 .global Start
212 Start:
213 TM_DISABLE
214 zero &r0, 124
215 P2P_IPC_ZAP ;zap IPC area
216 xout XFR2VBUS_XID_READ0, &r18, 4 ;disable xfr2vbus autoread mode
217 xout XFR2VBUS_XID_READ1, &r18, 4 ;
219 ;Initialization: set up RX & TX MII stuff.
220 enable_rx_l2
221 long_preamble_firewall_disable
222 gpcfg_reg_config ; 0x0800_0003
223 mii_tx_config
224 set_tx_ipg
225 icss_g_config
227 wait4debugger
229 set r31, r31, 18 ;RX reset
230 ;setup BSRAM
231 BSRAM_ZERO_BANK r1
233 ;SETUP portQ for to-host traffic, in order to do sandf PSI
234 PSIQ_CREATE
236 ;set up PSI INFO, CONTROL, STATUS TEMPLATES
237 .if $isdefed("SLICE0")
238 PSI_SETUP_INFO PSI_INFO_SLOT, 1
239 .else
240 PSI_SETUP_INFO PSI_INFO_SLOT, 2
241 .endif
242 PSI_SETUP_STATUS PSI_STATUS_SLOT
244 ;VA we should start here
245 ldi GRegs.pkt_cnt.x, 0
247 ;START RX/TX of 1 packet burst ; {{{1
248 RX:
249 RX_TASK_INIT
250 ;setup taskmanager
251 TM_PRU_CONFIG RX_SOF, RX_B0, RX_B1, RX_BN, RX_EOF, TX_NOP, TX_NOP, TX_FIFO, TX_EOF, RXTX_ERR
252 TM_ENABLE
253 set r31.t18 ;RX reset
254 ldi r18, 0
255 xout 40, &r18, 4 ;set tx fifo mode
257 ;read in global state
258 ldi GRegs.pkt_cnt.x, 0
259 ldi GRegs.tx.b.state, 0
260 ldi GRegs.rx.x, 0
261 ldi GRegs.snf.b.wr_cur, MINPS
262 ldi GRegs.snf.b.rd_cur, MINPS
263 ldi r30, 1522 ;todo - make a parameter
264 ldi32 r10, FW_CONFIG
265 lbbo &r2, r10, CFG_N_BURST, 4
267 ; set pru ready status
268 ldi32 r0, PRU_READY
269 sbbo &r0, r10, CFG_STATUS, 4
270 ; wait rtu ready
271 ldi32 r1, RTU_READY
272 wait_rtu_ready:
273 lbbo &r0, r10, CFG_RTU_STATUS, 4
274 qbne wait_rtu_ready, r0, r1
275 ; let's go
277 ;-------------------------------------------------------------------
278 ;BG TASK: r24-r29 are global ;{{{1
279 ;-------------------------------------------------------------------------
280 zero &r18, 24
281 mov BgRegs.borg_limit, r2 ; GS_NBURST ;
283 ;================================
284 ; BG LOOP: stay here until we see
285 ; GRegs.pkt_cnt.w.tx == BgRegs.borg_limit if in borg mode
286 ; until cmd cancel seen
287 ;=================================
288 bg_loop:
289 add BgRegs.bg_cnt, BgRegs.bg_cnt, 1 ;loop count
290 ;can we exit?
291 qbeq skip_chk, BgRegs.borg_limit, 0
292 qbeq bg_done, GRegs.pkt_cnt.w.tx, BgRegs.borg_limit ; done
293 skip_chk:
294 ; if RTU started shutdown process - disable TM and loop forever
295 ldi32 r0, FW_CONFIG
296 ldi32 r1, RTU_STARTED_SHUTDOWN
297 lbbo &r9, r0, CFG_RTU_STATUS, 4
298 qbne skip_chk01, r9, r1
299 ;disable xfr2vbus autoread mode
300 ldi32 r18, 0
301 xout XFR2VBUS_XID_READ0, &r18, 4
302 xout XFR2VBUS_XID_READ1, &r18, 4
304 PSI_ABORT
305 ; if we are here, we can place debug error code somewere in the SMEM
306 TM_DISABLE
307 ldi32 r1, PRU_STOPPED
308 sbbo &r1, r0, CFG_STATUS, 4
309 loop_here
311 skip_chk01:
312 ;-----------------------
313 ;schedule TX2HOST?
314 ;----------------------
315 ; do nothing if widget is full!!
316 xin XID_PSI_S, &r1,8
317 qbbc scheduler, r2,TB_WRITE
318 qbeq th_schedule0, BgRegs.psi2h_active, 0
319 ; active 2host
320 PSISANDF_TX bg_to_host2, scheduler
321 bg_to_host2: ;go again
322 xin XID_PSI_S, &r1,8
323 qbbc scheduler, r2,TB_WRITE
324 PSISANDF_TX scheduler, scheduler
325 jmp scheduler ;just in case
326 th_schedule0:
327 qbeq scheduler, GRegs.psiq.b.num_elem, 0
328 ; have new packet to send
329 TM_DISABLE
330 PSIQ_POP
331 TM_ENABLE
332 ;r2 = flow | len r3 = starting read index
333 PSISANDF_TX_INIT2 r2, r3
335 ;-----------------------
336 ;schedule TX2WIRE ?
337 ;----------------------
338 scheduler:
339 TM_DISABLE
340 qbeq bg_schedule0, GRegs.tx.b.state, TX_S_IDLE ;if tx state is idle, check IPC for new descriptor
341 qbeq bg_schedule1, GRegs.tx.b.state, TX_S_ERR ;if tx state is idle, check IPC for new descriptor
342 .if $isdefed("PSILOOP")
343 qbeq bg_schedulePL, GRegs.tx.b.state, TX_S_LOOP ;if psi loopback
344 .endif
346 ;TX ACTIVE.
347 sched_done:
348 TM_ENABLE
349 jmp bg_loop
351 bg_schedule0:
352 ;non PSA case only check expected next dma
353 qbbs bg_chk1, GRegs.tx.b.flags, f_next_dma
354 ;check dma0
355 PRU_IPC_RX_CH0Q sched_done, r2, XFR2VBUS_XID_READ0
356 ; have new packet in r2= len-flags
357 .if $isdefed("PSILOOP")
358 PSILOOP_TX_INIT r2, XFR2VBUS_XID_READ0
359 ;don't pingpong with PSILOOP!
360 .else
361 TX_TASK_INIT2_shell r2
362 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
363 .endif
364 TM_ENABLE
365 jmp bg_loop
366 bg_chk1:
367 ;check 2nd dma
368 PRU_IPC_RX_CH0Q sched_done, r3, XFR2VBUS_XID_READ1
369 TX_TASK_INIT2_shell r3
370 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
371 TM_ENABLE
372 jmp bg_loop
374 bg_schedule1:
375 ;error case (underflow)
376 ;todo
377 ldi GRegs.tx.b.state, TX_S_IDLE
378 TM_ENABLE
379 jmp bg_loop
380 .if $isdefed("PSILOOP")
381 bg_schedulePL:
382 ;psi loopback
383 flip_tx_r10_r23
384 PSILOOP_TX_POLL XFR2VBUS_XID_READ0, psi_poll_done, psi_poll_done
385 psi_poll_done:
386 flip_tx_r10_r23
387 TM_ENABLE
388 jmp bg_loop
389 .endif
391 ;-------------------------------------
392 ; done with packets.
393 ;-------------------------------------
394 bg_done:
396 ;save bg info: bg loops, txstate, rxstate, (pkt counts)
397 PAGE_RESTORE BG_STATE, 32
398 mov r2, BgRegs.bg_cnt
399 mov r3, GRegs.tx.x
400 mov r4, GRegs.rx.x
401 mov r5, GRegs.pkt_cnt.x
402 PAGE_SAVEQ
404 ;update result area (length)
405 ldi32 r1, FW_CONFIG
406 sbbo &r2, r1, CFG_OUT, 20
407 ldi32 r2, 0x10000001
408 sbbo &r2, r1, CFG_STATUS, 4
409 loop_here
411 ;-------------------------------------------------------------------------
412 ;end BG task
413 ;-------------------------------------------------------------------------
415 ;---------------------------------------------------------------------
416 ; TX_EOF EvENT {{{1
417 ;----------------------------------------------------------------------
418 TX_EOF:
419 qbne tx_underflow, GRegs.tx.b.state, TX_S_W_EOF
420 ; TX TS processing
421 flip_tx_r0_r23
422 qbbc no_tx_ts, TxRegs.ds_flags, 5 ; we don't need tx_ts
423 GET_PKT_TX_TS r2
424 ldi32 r10, FW_CONFIG + TX_TS_BASE
425 sbbo &r2, r10, 0, 8
426 SPIN_TOG_LOCK_LOC PRU_RTU_TX_TS_READY
427 no_tx_ts:
428 flip_tx_r0_r23
430 ;-----------------------------
431 ;Legit EOF. Restore registers
432 ;-----------------------------
433 legit_tx_eof:
434 flip_tx_r0_r23
435 qbbs teof_chk1, GRegs.tx.b.flags, f_next_dma
436 ;check dma0
437 PRU_IPC_RX_CH0Q no_new_tx, r2, XFR2VBUS_XID_READ0
438 ; have new packet in r2= len-flags
439 TX_TASK_INIT2 r2
440 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
441 jmp tx_eof_on_deck_done
442 teof_chk1:
443 ;check 2nd dma
444 PRU_IPC_RX_CH0Q no_new_tx, r3, XFR2VBUS_XID_READ1
445 TX_TASK_INIT2 r3
446 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
448 ;started next pkt, terminate task
449 tx_eof_on_deck_done:
450 TM_YIELD
451 ;these next 2 instructions are done in delayed branch fashion
452 flip_tx_r0_r23
453 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
454 loop_here
456 ;---------------------------------------------
457 ;eof w/ no new packet to TX
458 ;---------------------------------------------
459 no_new_tx:
460 ldi GRegs.tx.b.state, TX_S_IDLE
461 TM_YIELD
462 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
463 flip_tx_r0_r23
464 loop_here
466 ;------exception cases------
467 ;underflow case:
468 tx_underflow:
469 ldi GRegs.tx.b.state, TX_S_ERR
470 TM_YIELD
471 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
472 loop_here
474 ;---------------------------------------------------------------------
475 ; ENd TX_EOF
476 ;----------------------------------------------------------------------
478 ;---------------------------------------------------------------------
479 ; TX_FIFO EVENT {{{1
480 ;----------------------------------------------------------------------
481 TX_FIFO:
482 qbeq handle_portq, GRegs.tx.b.state, TX_S_ACTIVE
483 ;ignore rest
484 TM_YIELD
485 loop_here
487 ;----------------------
488 ; FROM PORTQ CASE
489 ;----------------------
490 handle_portq:
491 flip_tx_r0_r23
492 ;
493 ;check to see if need to preempt!
494 ; conditions: preempt enabled on port and pkt is preemptible
495 ; and enuf bytes sent and enuf bytes left and
496 ; (hold set or Express Frame waiting )
497 ;if not preemptible pkt skip all
498 qbbs skip_preempt, TxRegs.ds_flags, 4 ; R_TX_D1.f_desc_express
499 qbne skip_preempt, TxRegs.pp_ppok, PPOK
500 qbbs do_preempt, GRegs.tx.b.flags, f_tx_hold
501 qbbs do_preempt, GRegs.tx.b.flags, f_tx_efq
502 qbbc skip_preempt, GRegs.tx.b.flags, f_tx_efqd
503 do_preempt:
504 END_TX_MCRC ;send MCRC
505 mov TxRegs.stash_ds_flags, TxRegs.ds_flags
506 mov TxRegs.stash_tx_len, GRegs.tx.b.len
508 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_tx_stash ;so we know
509 ldi GRegs.tx.b.state, TX_S_W_PEOF
510 TM_YIELD
511 flip_tx_r0_r23
512 add TxRegs.pp_count, TxRegs.pp_count, 1
513 loop_here
515 skip_preempt:
516 ;assume data is here
517 TX_FILL_FIFO XFR2VBUS_XID_READ0
518 TM_YIELD
519 flip_tx_r0_r23
520 loop_here
522 ;-------------------------------------------------------------------------
523 ; End TX_FIFO EVENT
524 ;-------------------------------------------------------------------------
526 ;-------------------------------------------------------------------------
527 ;RXTX_ERR EVENT ; {{{1
528 ; assume rx issue.
529 ; reset rxl2 fifo
530 ; hopefully that cleans things up
531 ; need to see what else needs to be done
532 RXTX_ERR:
533 flip_tx_r0_r23
534 qbne rx_err?, GRegs.tx.b.state, TX_S_ERR
535 ; wait DMA ir complete
536 qbbs $3, TxRegs.ds_flags, 4
537 $1: xin XFR2VBUS_XID_READ0, &r18, 4
538 qbeq $2, r18.w0, 0x5
539 qbeq $2, r18, 0
540 qba $1
541 $2: nop
542 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ0
543 nop
544 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ0
545 SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
546 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
547 jmp $5
548 $3: xin XFR2VBUS_XID_READ1, &r18, 4
549 qbeq $4, r18.w0, 0x5
550 qbeq $4, r18, 0
551 qba $3
552 $4: nop
553 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ1
554 nop
555 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ1
556 SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
557 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
558 $5:
559 set r31.t30; TX_RESET
560 nop
561 nop
562 ;set TX to TX_S_IDLE
563 ldi GRegs.tx.b.state, TX_S_IDLE
564 qba rxtx_err_exit
565 rx_err?
566 ldi r11.b3, 0x80
567 xout 22, &r11, 4
568 set r31.t22 ; clear rx eof (why isnt it bit 20?)
569 ldi r7, 1 ;indicate we drop
570 ;for now assume it is the RXL1 overflowing for next frame
571 ;todo: how to check to see if it is for this frame??
572 ldi GRegs.rx.b.state, RX_STATE_OVER0
573 rxtx_err_exit:
574 TM_YIELD
575 flip_tx_r0_r23
576 loop_here
578 ;-------------------------------------------------------------------------
579 ; Dummy: TX_NOP {{{1
580 ;-------------------------------------------------------------------------
581 TX_NOP:
582 TM_YIELD
583 loop_here
584 ;----------------------------------------------------------------------
585 ; Dummy: END TX_NOP
586 ;-------------------------------------------------------------------------
588 ;---------------------------------------------------------------
589 ; RX TASK, State 1: RX SOF {{{1
590 ;--------------------------------------------------------------
591 RX_SOF:
592 ;turn off RX_SOF
593 TM_YIELD
594 loop_here
595 ;---------------------------------------------------------------
596 ; END RX TASK, State 1
597 ;--------------------------------------------------------------
599 NBTR .set 32
600 ;---------------------------------------------------------------
601 ; RX TASK, State 2: RX_B0 {{{1
602 ;--------------------------------------------------------------
603 RX_B0:
604 flip_rx_r0_r23
606 ;BRING IN THE DATA
607 xin RXL2_BANK0, &r2, NBTR
608 ldi RxRegs.aux_flags, 1
609 qbeq rxb0_already_over, GRegs.rx.b.state, RX_STATE_OVER0
611 ldi GRegs.rx.x, 0x180 ;fresh state=1, (sof flag set)
612 P_W32_S rxb0_full ;stash pkt bytes in bs slot but don't start
614 jmp rx_b0_done
616 ;some error/exception cases handling here
617 rxb0_full: ;psi fifo in bsram full
618 P_W32_ABORT
619 ldi GRegs.rx.x, 0x7F80
620 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt, 1
621 jmp rx_b0_done
623 rxb0_already_over:
624 ldi GRegs.rx.x, 0x7F80
625 ;todo: bump stats
627 rx_b0_done:
628 TM_YIELD
629 flip_rx_r0_r23
630 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32 ;hopefully this gets executed!!
631 loop_here
632 ;---------------------------------------------------------------
633 ; END RX TASK, State 2
634 ;--------------------------------------------------------------
636 ;---------------------------------------------------------------
637 ; RX TASK, State 3: RX_B1 {{{1
638 ;--------------------------------------------------------------
639 RX_B1:
640 flip_rx_r0_r23
641 qbeq skip_b1, GRegs.rx.b.state, RX_STATE_DROP
642 ;!!better be here!!
643 ;r5.b0 = route info
644 ;r5.b1 = fid
645 ;r5.w2 = index
646 ;r6 = buffer ptr for s&f
647 ldi r0.b1, 0
648 stall_loop:
649 PRU_IPC_RX_CH1
650 qbbs got_ipc, r5.b0, f_rx_sof
651 add r0.b1, r0.b1, 1
652 qbne stall_loop, r0.b1, RB1_STALL_LIMIT
653 ldi GRegs.rx.b.state, RX_STATE_DROP ;stall limit reached
654 jmp rb1_ipc_done
655 got_ipc:
656 mov GRegs.rx.b.flags, r5.b0 ;forwarding info we got from RTU
657 PRU_IPC_RX_CH1_CLRB7 ;clear bit so we know we got it
658 mov RxRegs.pq_cur, r6 ;save buffer pointer (may not use) ;=flow in MAC
660 rb1_ipc_done:
661 xin RXL2_BANK1, &r2, 32 ;bring in data (r2-r9)
662 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
663 set RxRegs.aux_flags, RxRegs.aux_flags, f_b1_seen
665 TM_DISABLE
666 qbbc b1_rx_path1a, GRegs.rx.b.flags, f_tohost
667 P_W32 rxb1_full ;stash pkt bytes in bs slot
668 jmp rx_b1_done
669 rxb1_full:
670 ldi GRegs.rx.x, 0x7F80
671 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
672 b1_rx_path1a:
673 P_W32_ABORT ;abort the stashing of pkt in BS (for PSI)
674 rx_b1_done:
675 TM_ENABLE
676 b1_exit:TM_YIELD
677 flip_rx_r0_r23
678 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
679 loop_here
681 skip_b1:xin RXL2_BANK1, &r2, 32 ;error case. just read in data and drop
682 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
683 jmp b1_exit
684 ;---------------------------------------------------------------
685 ; END RX TASK, State 3
686 ;--------------------------------------------------------------
688 ;---------------------------------------------------------------
689 ; RX TASK, State 4: RX_BN {{{1
690 ;--------------------------------------------------------------
691 RX_BN:
692 flip_rx_r0_r23
693 ;check for overflow/drop or pkt too long
694 qbne pkt_ok, GRegs.rx.b.state, RX_STATE_DROP
695 ;errors:
696 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
697 qbbs rx_bnerr_sideB, RxRegs.aux_flags, f_fh
698 ;side A
699 xin RXL2_BANK0, &r2, 32
700 jmp rx_bn_done
701 rx_bnerr_sideB:
702 ;side B
703 xin RXL2_BANK1, &r2, 32
704 jmp rx_bn_done
705 rxbn_full:
706 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
707 P_W32_ABORT
708 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
709 jmp rx_bn_done
711 ;take pkt, all good
712 pkt_ok: qbbs rx_bn_sideB, RxRegs.aux_flags, f_fh
713 xin RXL2_BANK0, &r2, 32
714 set RxRegs.aux_flags, RxRegs.aux_flags, f_fh
715 jmp bn_cont1
716 rx_bn_sideB:
717 xin RXL2_BANK1, &r2, 32
718 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
719 bn_cont1:
720 qbbc rx_bn_done, GRegs.rx.x, 0
721 P_W32 rxbn_full
722 rx_bn_done:
723 TM_YIELD
724 flip_rx_r0_r23
725 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
726 loop_here
727 ;---------------------------------------------------------------
728 ; END RX TASK, State 4
729 ;--------------------------------------------------------------
731 ;---------------------------------------------------------------
732 ; RX TASK, State 5: RX_EOF {{{1
733 ;--------------------------------------------------------------
734 RX_EOF:
735 TM_DISABLE
736 flip_rx_r0_r23
737 qbeq no_rx_sof, GRegs.rx.b.state, RX_STATE_DROP
738 qbbc no_rx_sof, GRegs.rx.b.flags, f_rx_sof
739 ldi r0.w0, 0x3310
740 and r0.w0, r31.w2, r0.w0
741 qbne beof_rx_err, r0.b0, 0x10 ;check for rx errors
742 qbbs rx_beof_sideB, RxRegs.aux_flags, f_fh
744 ;side A, r18 and r0.b0 has length
745 RX_EOF_RCV_BANK0
746 ldi r11.b3, 0x80
747 xout 22, &r11, 4
748 set r31.t22 ; clear rx eof (why isnt it bit 20?)
749 mov RxRegs.res1, r0.b0
750 jmp rx_beof_cont0
752 rx_beof_sideB:
753 ;side B, r18 and r0.b0 has length
754 RX_EOF_RCV_BANK1
755 ldi r11.b3, 0x80
756 xout 22, &r11, 4
757 set r31.t22 ; clear rx eof (why isnt it bit 20?)
758 add RxRegs.res1, r0.b0, 32
760 rx_beof_cont0:
761 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, r0.b0
762 qbbc rx_eof_done, GRegs.rx.b.flags, f_tohost
763 ;check for pkt to long
764 qbge th_pkt_ok, GRegs.rx.b.pkt_len, r30.w0
765 add r30.w2, r30.w2,1 ; max error (like crc)
766 P_W32_ABORT
767 jmp rx_eof_done
768 th_pkt_ok:
769 ; push 32 to bsram fifo (not all will be valid)
770 P_W32 rxeof_noroom
771 ; push 'descriptor' to local queue. will be popped by bg task
772 mov r2.w2, RxRegs.pq_cur ;flow
773 mov r2.w0, GRegs.rx.b.pkt_len
774 mov r3, GRegs.snf.x ;bsram fifo position (maybe not necessary)
775 ;to do add rxtx timestamp
776 PSIQ_PUSH rxeof_qfull
778 rx_eof_done:
779 ; check for runt packet
780 qble rx_eof_done_b, GRegs.rx.b.pkt_len, 64
781 set r31.t18 ;reset RX_fifo
783 rx_eof_done_b:
784 TM_ENABLE
785 flip_rx_r0_r23
786 TM_YIELD
787 ldi GRegs.rx.s.fl_n_state, 0
788 add GRegs.pkt_cnt.w.rx, GRegs.pkt_cnt.w.rx, 1 ;also should tell bg #of pkts we have procesed
789 loop_here
791 ;----------------------------
792 ; bad frame, error handling
793 ;-----------------------------
794 rxeof_noroom:
795 rxeof_qfull:
796 P_W32_ABORT
797 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
798 jmp rx_eof_done
800 beof_rx_err:
801 no_rx_sof:
802 ;saw no sof before eof or other such issues
803 ldi r11.b3, 0x80
804 xout 22, &r11, 4
805 set r31, r31, 22 ; clear rx eof (why isnt it bit 20?)
806 jmp rx_eof_done
807 ;---------------------------------------------------------------
808 ; END RX TASK, State 5
809 ;--------------------------------------------------------------
811 .include "resource_table.h"