[processor-sdk/pdk.git] / packages / ti / drv / emac / firmware / icss_dualmac / src / rxl2_txl2.asm
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55 ;Basic Ethernet rx/tx firmware==> TASK MANAGER + S&F MODE {{{1
56 ;/ modified by DAL
57 ;TXL2 version
58 ; 'new' rxl2 mode, so eof handling is different
59 ; defines for config
60 ; RGMII: set up for RGMII mode
61 ; MII : set up for MII mode (RX ok, TX not tested)
62 ; SLICE0 or SLICE1 must be defined (but not both)
63 ; WAIT_FOR_DEBUGGER: wait for debugger to attach
64 ; VLAN_ENABLED
65 DATA_ONLY .set 1 ;control path moved to RTU
67 ; sanity check ;{{{1
68 .if $isdefed("SLICE0") & $isdefed("SLICE1")
69 cant have SLICE0 and SLICE1
70 .endif
71 .if !$isdefed("SLICE0") & !$isdefed("SLICE1")
72 must have slice0 or slice1 defined
73 .endif
75 ; includes {{{1
76 .include "regs.h"
77 .include "portq.h"
78 .include "reg_alias.h"
79 .include "smem.h"
80 .include "bsram_pru.h"
81 .include "spin.h"
82 .include "xfr2vbus_widget.h"
83 .include "xfr2psi_widget.h"
84 .include "basicio.h"
85 .include "tm.h"
86 .include "rx.h"
87 .include "tx.h"
88 .include "filter.h"
89 .include "lebe.h"
90 .include "ipc.h"
91 .include "iep.h"
92 .include "psisandf.h"
94 loop_here .macro
95 here?: jmp here?
96 .endm
98 ; slice0 vs slice1 {{{1
99 .if $isdefed("SLICE0")
100 .asg MII_RXCFG0_ADDR, MII_RXCFGn_ADDR
101 .asg 0x8, GPCFGn_REG
102 .asg FDB_XID_PORT0_RES, FDB_XID_PORTn_RES
103 .asg MII_PRE_CNT0, MII_PRE_CNTn
104 .else
105 .asg MII_RXCFG1_ADDR, MII_RXCFGn_ADDR
106 .asg 0xc, GPCFGn_REG
107 .asg FDB_XID_PORT1_RES, FDB_XID_PORTn_RES
108 .asg MII_PRE_CNT1, MII_PRE_CNTn
109 .endif
110 ;slice0 controls tx1 if switch, tx0 otherwise
111 ;slice1 controls tx0 if switch, tx1 otherwise
112 .if $isdefed("SLICE0")
113 .asg MII_TXCFG0_ADDR, MII_TXCFGn_ADDR
114 .asg MII_TXIPG0_ADDR, MII_TXIPGn_ADDR
115 .else
116 .asg MII_TXCFG1_ADDR, MII_TXCFGn_ADDR
117 .asg MII_TXIPG1_ADDR, MII_TXIPGn_ADDR
118 .endif
120 ; Enable RX L2 pru0 & rx
121 enable_rx_l2 .macro
122 ldi32 r28, MII_RXCFGn_ADDR
123 lbbo &r11, r28, 0, 4
124 set r11.t4 ;rx l2 enable
125 set r11.t0 ;rx enable
126 set r11.t9 ;rx_eof_sclr_dis0
127 set r11.t1 ;make tx eof visible in r31, bit16
128 sbbo &r11, r28, 0, 4
129 .endm
131 long_preamble_firewall_disable .macro
132 ldi32 r28, MII_PRE_CNTn
133 lbbo &r11, r28, 0, 4
134 and r11.b0, r11.b0, 0x0f
135 sbbo &r11, r28, 0, 4
136 .endm
138 gpcfg_reg_config .macro
139 ldi32 r28, PRUSS1_CFG_PRU_OFFSET
140 lbbo &r11, r28, GPCFGn_REG, 4
141 set r11.t1
142 set r11.t0
143 set r11.t27
144 sbbo &r11, r28, GPCFGn_REG, 4
145 .endm
147 mii_tx_config .macro
148 ldi32 r28, MII_TXCFGn_ADDR
149 lbbo &r11, r28, 0, 4
150 set r11.t0 ;enable txl1
151 set r11.t11 ;tx_32_mode en
152 set r11.t1 ;tx_auto_preamble
153 ;set mux
154 .if $isdefed("SLICE0")
155 clr r11.t8
156 .else
157 set r11.t8
158 .endif
159 ldi r11.b2, 0 ;set tx start delay to 0!!!
160 clr r11.t25
161 clr r11.t24
162 sbbo &r11, r28, 0, 4
163 .endm
165 set_tx_ipg .macro
166 ;change ipg to 88 ns (22 250mhz clocks)
167 ldi32 r28, MII_TXIPGn_ADDR
168 lbbo &r11, r28, 0, 4
169 ldi r11, 0x16 ; min IPG for testing (CCLINK)
170 sbbo &r11, r28, 0, 4
171 .endm
173 icss_g_config .macro
174 ; **for now let slice0 do txl2 & port mode config (ICSS_G register) for both sides {{{2
175 ;TX Config TXl2 - icss_g register
176 ldi32 r28, ICSS_G
177 lbbo &r11, r28, 0, 4
178 set r11.t1
179 set r11.t0
180 set r11.t2 ;rx_l2_g_en
182 .if $isdefed("RGMII")
183 set r11.t3
184 clr r11.t4
185 set r11.t5
186 clr r11.t6
187 .endif
188 .if $isdefed("MII")
189 clr r11.t3
190 clr r11.t4
191 clr r11.t5
192 clr r11.t6
193 .endif
194 sbbo &r11, r28, 0, 4
195 .endm
197 wait4debugger .macro
198 .if $isdefed("WAIT_FOR_DEBUGGER")
199 ldi32 r11, 0
200 $1: qbeq $1, r11, 0
201 .endif
202 .endm
204 ; Code starts {{{1
205 .retain ; Required forbuilding .out with assembly file
206 .retainrefs ; Required forbuilding .out with assembly file
207 .sect ".text:Start"
208 .global Start
210 Start:
211 TM_DISABLE
212 zero &r0, 124
213 P2P_IPC_ZAP ;zap IPC area
214 xout XFR2VBUS_XID_READ0, &r18, 4 ;disable xfr2vbus autoread mode
215 xout XFR2VBUS_XID_READ1, &r18, 4 ;
217 ;Initialization: set up RX & TX MII stuff.
218 enable_rx_l2
219 long_preamble_firewall_disable
220 gpcfg_reg_config ; 0x0800_0003
221 mii_tx_config
222 set_tx_ipg
223 icss_g_config
225 wait4debugger
227 set r31, r31, 18 ;RX reset
228 ;setup BSRAM
229 BSRAM_ZERO_BANK r1
231 ;SETUP portQ for to-host traffic, in order to do sandf PSI
232 PSIQ_CREATE
234 ;set up PSI INFO, CONTROL, STATUS TEMPLATES
235 .if $isdefed("SLICE0")
236 PSI_SETUP_INFO PSI_INFO_SLOT, 1
237 .else
238 PSI_SETUP_INFO PSI_INFO_SLOT, 2
239 .endif
240 PSI_SETUP_STATUS PSI_STATUS_SLOT
242 ;VA we should start here
243 ldi GRegs.pkt_cnt.x, 0
245 ;START RX/TX of 1 packet burst ; {{{1
246 RX:
247 RX_TASK_INIT
248 ;setup taskmanager
249 TM_PRU_CONFIG RX_SOF, RX_B0, RX_B1, RX_BN, RX_EOF, TX_NOP, TX_NOP, TX_FIFO, TX_EOF, RXTX_ERR
250 TM_ENABLE
251 set r31.t18 ;RX reset
252 ldi r18, 0
253 xout 40, &r18, 4 ;set tx fifo mode
255 ;read in global state
256 ldi GRegs.pkt_cnt.x, 0
257 ldi GRegs.tx.b.state, 0
258 ldi GRegs.rx.x, 0
259 ldi GRegs.snf.b.wr_cur, MINPS
260 ldi GRegs.snf.b.rd_cur, MINPS
261 ldi r30, 1522 ;todo - make a parameter
262 ldi32 r10, FW_CONFIG
264 ; set pru ready status
265 ldi32 r0, PRU_READY
266 sbbo &r0, r10, CFG_STATUS, 4
267 ; wait rtu ready
268 ldi32 r1, RTU_READY
269 wait_rtu_ready:
270 lbbo &r0, r10, CFG_RTU_STATUS, 4
271 qbne wait_rtu_ready, r0, r1
272 ; let's go
274 ;-------------------------------------------------------------------
275 ;BG TASK: r24-r29 are global ;{{{1
276 ;-------------------------------------------------------------------------
277 zero &r18, 24
279 ;================================
280 ; BG LOOP: until cmd cancel seen
281 ;================================
282 bg_loop:
283 add BgRegs.bg_cnt, BgRegs.bg_cnt, 1 ;loop count
284 ; if RTU started shutdown process - disable TM and loop forever
285 ldi32 r0, FW_CONFIG
286 ldi32 r1, RTU_STARTED_SHUTDOWN
287 lbbo &r9, r0, CFG_RTU_STATUS, 4
288 qbne skip_chk01, r9, r1
289 ;disable xfr2vbus autoread mode
290 ldi32 r18, 0
291 xout XFR2VBUS_XID_READ0, &r18, 4
292 xout XFR2VBUS_XID_READ1, &r18, 4
294 PSI_ABORT
295 ; if we are here, we can place debug error code somewere in the SMEM
296 TM_DISABLE
297 ldi32 r1, PRU_STOPPED
298 sbbo &r1, r0, CFG_STATUS, 4
299 loop_here
301 skip_chk01:
302 ;-----------------------
303 ;schedule TX2HOST?
304 ;----------------------
305 ; do nothing if widget is full!!
306 xin XID_PSI_S, &r1,8
307 qbbc scheduler, r2,TB_WRITE
308 qbeq th_schedule0, BgRegs.psi2h_active, 0
309 ; active 2host
310 PSISANDF_TX bg_to_host2, scheduler
311 bg_to_host2: ;go again
312 xin XID_PSI_S, &r1,8
313 qbbc scheduler, r2,TB_WRITE
314 PSISANDF_TX scheduler, scheduler
315 jmp scheduler ;just in case
316 th_schedule0:
317 qbeq scheduler, GRegs.psiq.b.num_elem, 0
318 ; have new packet to send
319 TM_DISABLE
320 PSIQ_POP
321 TM_ENABLE
322 ;r2 = flow | len r3 = starting read index
323 PSISANDF_TX_INIT2 r2, r3
325 ;-----------------------
326 ;schedule TX2WIRE ?
327 ;----------------------
328 scheduler:
329 TM_DISABLE
330 qbeq bg_schedule0, GRegs.tx.b.state, TX_S_IDLE ;if tx state is idle, check IPC for new descriptor
331 qbne sched_done, GRegs.tx.b.state, TX_S_ERR ;if tx state is idle, check IPC for new descriptor
332 ;error case (underflow)
333 ;todo
334 ldi GRegs.tx.b.state, TX_S_IDLE
335 sched_done:
336 TM_ENABLE
337 jmp bg_loop
339 bg_schedule0:
340 ;non PSA case only check expected next dma
341 qbbs bg_chk1, GRegs.tx.b.flags, f_next_dma
342 ;check dma0
343 PRU_IPC_RX_CH0Q sched_done, r2, XFR2VBUS_XID_READ0
344 ; have new packet in r2= len-flags
345 TX_TASK_INIT2_shell r2
346 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
347 TM_ENABLE
348 jmp bg_loop
349 bg_chk1:
350 ;check 2nd dma
351 PRU_IPC_RX_CH0Q sched_done, r3, XFR2VBUS_XID_READ1
352 TX_TASK_INIT2_shell r3
353 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
354 TM_ENABLE
355 jmp bg_loop
357 ;-------------------------------------
358 ; done with packets.
359 ;-------------------------------------
360 bg_done:
362 ;save bg info: bg loops, txstate, rxstate, (pkt counts)
363 PAGE_RESTORE BG_STATE, 32
364 mov r2, BgRegs.bg_cnt
365 mov r3, GRegs.tx.x
366 mov r4, GRegs.rx.x
367 mov r5, GRegs.pkt_cnt.x
368 PAGE_SAVEQ
370 ;update result area (length)
371 ldi32 r1, FW_CONFIG
372 sbbo &r2, r1, CFG_OUT, 20
373 ldi32 r2, 0x10000001
374 sbbo &r2, r1, CFG_STATUS, 4
375 loop_here
377 ;-------------------------------------------------------------------------
378 ;end BG task
379 ;-------------------------------------------------------------------------
381 ;---------------------------------------------------------------------
382 ; TX_EOF EvENT {{{1
383 ;---------------------------------------------------------------------
384 TX_EOF:
385 qbne tx_underflow, GRegs.tx.b.state, TX_S_W_EOF
386 ; TX TS processing
387 flip_tx_r0_r23
388 qbbc no_tx_ts, TxRegs.ds_flags, 5 ; we don't need tx_ts
389 GET_PKT_TX_TS r2
390 ldi32 r10, FW_CONFIG + TX_TS_BASE
391 sbbo &r2, r10, 0, 8
392 SPIN_TOG_LOCK_LOC PRU_RTU_TX_TS_READY
393 no_tx_ts:
394 qbbs teof_chk1, GRegs.tx.b.flags, f_next_dma
395 PRU_IPC_RX_CH0Q no_new_tx, r2, XFR2VBUS_XID_READ0
396 TX_TASK_INIT2 r2
397 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
398 jmp tx_eof_on_deck_done
399 teof_chk1:
400 PRU_IPC_RX_CH0Q no_new_tx, r3, XFR2VBUS_XID_READ1
401 TX_TASK_INIT2 r3
402 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
404 tx_eof_on_deck_done:
405 TM_YIELD
406 flip_tx_r0_r23
407 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
408 loop_here
410 no_new_tx:
411 ldi GRegs.tx.b.state, TX_S_IDLE
412 qba tx_eof_on_deck_done
414 ;------exception cases------
415 tx_underflow:
416 ldi GRegs.tx.b.state, TX_S_ERR
417 TM_YIELD
418 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
419 loop_here
421 ;---------------------------------------------------------------------
422 ; ENd TX_EOF
423 ;----------------------------------------------------------------------
425 ;---------------------------------------------------------------------
426 ; TX_FIFO EVENT {{{1
427 ;----------------------------------------------------------------------
428 TX_FIFO:
429 qbeq handle_portq, GRegs.tx.b.state, TX_S_ACTIVE
430 TM_YIELD
431 loop_here
433 handle_portq:
434 flip_tx_r0_r23
435 TX_FILL_FIFO XFR2VBUS_XID_READ0
436 TM_YIELD
437 flip_tx_r0_r23
438 loop_here
440 ;-------------------------------------------------------------------------
441 ;RXTX_ERR EVENT ; {{{1
442 ; assume rx issue.
443 ; reset rxl2 fifo
444 ; hopefully that cleans things up
445 ; need to see what else needs to be done
446 RXTX_ERR:
447 flip_tx_r0_r23
448 qbne rx_err?, GRegs.tx.b.state, TX_S_ERR
449 ; wait DMA ir complete
450 qbbs $3, TxRegs.ds_flags, 4
451 $1: xin XFR2VBUS_XID_READ0, &r18, 4
452 qbeq $2, r18.w0, 0x5
453 qbeq $2, r18, 0
454 qba $1
455 $2: nop
456 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ0
457 nop
458 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ0
459 SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
460 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
461 jmp $5
462 $3: xin XFR2VBUS_XID_READ1, &r18, 4
463 qbeq $4, r18.w0, 0x5
464 qbeq $4, r18, 0
465 qba $3
466 $4: nop
467 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ1
468 nop
469 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ1
470 SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
471 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
472 $5:
473 set r31.t30; TX_RESET
474 nop
475 nop
476 ;set TX to TX_S_IDLE
477 ldi GRegs.tx.b.state, TX_S_IDLE
478 qba rxtx_err_exit
479 rx_err?
480 ldi r11.b3, 0x80
481 xout 22, &r11, 4
482 set r31.t22 ; clear rx eof (why isnt it bit 20?)
483 ldi r7, 1 ;indicate we drop
484 ;for now assume it is the RXL1 overflowing for next frame
485 ;todo: how to check to see if it is for this frame??
486 ldi GRegs.rx.b.state, RX_STATE_OVER0
487 rxtx_err_exit:
488 TM_YIELD
489 flip_tx_r0_r23
490 loop_here
492 ;-------------------------------------------------------------------------
493 ; Dummy: TX_NOP {{{1
494 ;-------------------------------------------------------------------------
495 TX_NOP:
496 TM_YIELD
497 loop_here
498 ;----------------------------------------------------------------------
499 ; Dummy: END TX_NOP
500 ;-------------------------------------------------------------------------
502 ;---------------------------------------------------------------
503 ; RX TASK, State 1: RX SOF {{{1
504 ;--------------------------------------------------------------
505 RX_SOF:
506 ;turn off RX_SOF
507 TM_YIELD
508 loop_here
509 ;---------------------------------------------------------------
510 ; END RX TASK, State 1
511 ;--------------------------------------------------------------
513 NBTR .set 32
514 ;---------------------------------------------------------------
515 ; RX TASK, State 2: RX_B0 {{{1
516 ;--------------------------------------------------------------
517 RX_B0:
518 flip_rx_r0_r23
520 ;BRING IN THE DATA
521 xin RXL2_BANK0, &r2, NBTR
522 ldi RxRegs.aux_flags, 1
523 qbeq rxb0_already_over, GRegs.rx.b.state, RX_STATE_OVER0
525 ldi GRegs.rx.x, 0x180 ;fresh state=1, (sof flag set)
526 P_W32_S rxb0_full ;stash pkt bytes in bs slot but don't start
528 jmp rx_b0_done
530 ;some error/exception cases handling here
531 rxb0_full: ;psi fifo in bsram full
532 P_W32_ABORT
533 ldi GRegs.rx.x, 0x7F80
534 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt, 1
535 jmp rx_b0_done
537 rxb0_already_over:
538 ldi GRegs.rx.x, 0x7F80
539 ;todo: bump stats
541 rx_b0_done:
542 TM_YIELD
543 flip_rx_r0_r23
544 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32 ;hopefully this gets executed!!
545 loop_here
546 ;---------------------------------------------------------------
547 ; END RX TASK, State 2
548 ;--------------------------------------------------------------
550 ;---------------------------------------------------------------
551 ; RX TASK, State 3: RX_B1 {{{1
552 ;--------------------------------------------------------------
553 RX_B1:
554 flip_rx_r0_r23
555 qbeq skip_b1, GRegs.rx.b.state, RX_STATE_DROP
556 ;!!better be here!!
557 ;r5.b0 = route info
558 ;r5.b1 = fid
559 ;r5.w2 = index
560 ;r6 = buffer ptr for s&f
561 ldi r0.b1, 0
562 stall_loop:
563 PRU_IPC_RX_CH1
564 qbbs got_ipc, r5.b0, f_rx_sof
565 add r0.b1, r0.b1, 1
566 qbne stall_loop, r0.b1, RB1_STALL_LIMIT
567 ldi GRegs.rx.b.state, RX_STATE_DROP ;stall limit reached
568 jmp rb1_ipc_done
569 got_ipc:
570 mov GRegs.rx.b.flags, r5.b0 ;forwarding info we got from RTU
571 PRU_IPC_RX_CH1_CLRB7 ;clear bit so we know we got it
572 mov RxRegs.pq_cur, r6 ;save buffer pointer (may not use) ;=flow in MAC
574 rb1_ipc_done:
575 xin RXL2_BANK1, &r2, 32 ;bring in data (r2-r9)
576 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
577 set RxRegs.aux_flags, RxRegs.aux_flags, f_b1_seen
579 TM_DISABLE
580 qbbc b1_rx_path1a, GRegs.rx.b.flags, f_tohost
581 P_W32 rxb1_full ;stash pkt bytes in bs slot
582 jmp rx_b1_done
583 rxb1_full:
584 ldi GRegs.rx.x, 0x7F80
585 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
586 b1_rx_path1a:
587 P_W32_ABORT ;abort the stashing of pkt in BS (for PSI)
588 rx_b1_done:
589 TM_ENABLE
590 b1_exit:TM_YIELD
591 flip_rx_r0_r23
592 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
593 loop_here
595 skip_b1:xin RXL2_BANK1, &r2, 32 ;error case. just read in data and drop
596 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
597 jmp b1_exit
598 ;---------------------------------------------------------------
599 ; END RX TASK, State 3
600 ;--------------------------------------------------------------
602 ;---------------------------------------------------------------
603 ; RX TASK, State 4: RX_BN {{{1
604 ;--------------------------------------------------------------
605 RX_BN:
606 flip_rx_r0_r23
607 ;check for overflow/drop or pkt too long
608 qbne pkt_ok, GRegs.rx.b.state, RX_STATE_DROP
609 ;errors:
610 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
611 qbbs rx_bnerr_sideB, RxRegs.aux_flags, f_fh
612 ;side A
613 xin RXL2_BANK0, &r2, 32
614 jmp rx_bn_done
615 rx_bnerr_sideB:
616 ;side B
617 xin RXL2_BANK1, &r2, 32
618 jmp rx_bn_done
619 rxbn_full:
620 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
621 P_W32_ABORT
622 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
623 jmp rx_bn_done
625 ;take pkt, all good
626 pkt_ok: qbbs rx_bn_sideB, RxRegs.aux_flags, f_fh
627 xin RXL2_BANK0, &r2, 32
628 set RxRegs.aux_flags, RxRegs.aux_flags, f_fh
629 jmp bn_cont1
630 rx_bn_sideB:
631 xin RXL2_BANK1, &r2, 32
632 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
633 bn_cont1:
634 qbbc rx_bn_done, GRegs.rx.x, 0
635 P_W32 rxbn_full
636 rx_bn_done:
637 TM_YIELD
638 flip_rx_r0_r23
639 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
640 loop_here
641 ;---------------------------------------------------------------
642 ; END RX TASK, State 4
643 ;--------------------------------------------------------------
645 ;---------------------------------------------------------------
646 ; RX TASK, State 5: RX_EOF {{{1
647 ;--------------------------------------------------------------
648 RX_EOF:
649 TM_DISABLE
650 flip_rx_r0_r23
651 qbeq no_rx_sof, GRegs.rx.b.state, RX_STATE_DROP
652 qbbc no_rx_sof, GRegs.rx.b.flags, f_rx_sof
653 ldi r0.w0, 0x3310
654 and r0.w0, r31.w2, r0.w0
655 qbne beof_rx_err, r0.b0, 0x10 ;check for rx errors
656 qbbs rx_beof_sideB, RxRegs.aux_flags, f_fh
658 ;side A, r18 and r0.b0 has length
659 RX_EOF_RCV_BANK0
660 ldi r11.b3, 0x80
661 xout 22, &r11, 4
662 set r31.t22 ; clear rx eof (why isnt it bit 20?)
663 mov RxRegs.res1, r0.b0
664 jmp rx_beof_cont0
666 rx_beof_sideB:
667 ;side B, r18 and r0.b0 has length
668 RX_EOF_RCV_BANK1
669 ldi r11.b3, 0x80
670 xout 22, &r11, 4
671 set r31.t22 ; clear rx eof (why isnt it bit 20?)
672 add RxRegs.res1, r0.b0, 32
674 rx_beof_cont0:
675 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, r0.b0
676 qbbc rx_eof_done, GRegs.rx.b.flags, f_tohost
677 ;check for pkt to long
678 qbge th_pkt_ok, GRegs.rx.b.pkt_len, r30.w0
679 add r30.w2, r30.w2,1 ; max error (like crc)
680 P_W32_ABORT
681 jmp rx_eof_done
682 th_pkt_ok:
683 ; push 32 to bsram fifo (not all will be valid)
684 P_W32 rxeof_noroom
685 ; push 'descriptor' to local queue. will be popped by bg task
686 mov r2.w2, RxRegs.pq_cur ;flow
687 mov r2.w0, GRegs.rx.b.pkt_len
688 mov r3, GRegs.snf.x ;bsram fifo position (maybe not necessary)
689 ;to do add rxtx timestamp
690 PSIQ_PUSH rxeof_qfull
692 rx_eof_done:
693 ; check for runt packet
694 qble rx_eof_done_b, GRegs.rx.b.pkt_len, 64
695 set r31.t18 ;reset RX_fifo
697 rx_eof_done_b:
698 TM_ENABLE
699 flip_rx_r0_r23
700 TM_YIELD
701 ldi GRegs.rx.s.fl_n_state, 0
702 add GRegs.pkt_cnt.w.rx, GRegs.pkt_cnt.w.rx, 1 ;also should tell bg #of pkts we have procesed
703 loop_here
705 ;----------------------------
706 ; bad frame, error handling
707 ;-----------------------------
708 rxeof_noroom:
709 rxeof_qfull:
710 P_W32_ABORT
711 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
712 jmp rx_eof_done
714 beof_rx_err:
715 no_rx_sof:
716 ;saw no sof before eof or other such issues
717 ldi r11.b3, 0x80
718 xout 22, &r11, 4
719 set r31, r31, 22 ; clear rx eof (why isnt it bit 20?)
720 jmp rx_eof_done
721 ;---------------------------------------------------------------
722 ; END RX TASK, State 5
723 ;--------------------------------------------------------------
725 .include "resource_table.h"