ede1607610cb3763ba9aae2b1a1d19bc5e763cf4
[processor-sdk/pdk.git] / packages / ti / drv / emac / firmware / icss_dualmac / src / rxl2_txl2.asm
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55 ;Basic Ethernet rx/tx firmware==> TASK MANAGER + S&F MODE {{{1
56 ;/ modified by DAL
57 ;TXL2 version
58 ; 'new' rxl2 mode, so eof handling is different
59 ; defines for config
60 ; RGMII: set up for RGMII mode
61 ; MII : set up for MII mode (RX ok, TX not tested)
62 ; SLICE0 or SLICE1 must be defined (but not both)
63 ; WAIT_FOR_DEBUGGER: wait for debugger to attach
64 ; VLAN_ENABLED
65 DATA_ONLY .set 1 ;control path moved to RTU
67 ; sanity check ;{{{1
68 .if $isdefed("SLICE0") & $isdefed("SLICE1")
69 cant have SLICE0 and SLICE1
70 .endif
71 .if !$isdefed("SLICE0") & !$isdefed("SLICE1")
72 must have slice0 or slice1 defined
73 .endif
75 ; includes {{{1
76 .include "regs.h"
77 .include "portq.h"
78 .include "reg_alias.h"
79 .include "smem.h"
80 .include "bsram_pru.h"
81 .include "spin.h"
82 .include "xfr2vbus_widget.h"
83 .include "xfr2psi_widget.h"
84 .include "basicio.h"
85 .include "tm.h"
86 .include "rx.h"
87 .include "tx.h"
88 .include "filter.h"
89 .include "lebe.h"
90 .include "ipc.h"
91 .include "iep.h"
92 .include "psisandf.h"
93 .include "hd_helper.h"
94 .include "pa_stat.h"
96 loop_here .macro
97 here?: jmp here?
98 .endm
100 ; slice0 vs slice1 {{{1
101 .if $isdefed("SLICE0")
102 .asg MII_RXCFG0_ADDR, MII_RXCFGn_ADDR
103 .asg 0x8, GPCFGn_REG
104 .asg FDB_XID_PORT0_RES, FDB_XID_PORTn_RES
105 .asg MII_PRE_CNT0, MII_PRE_CNTn
106 .else
107 .asg MII_RXCFG1_ADDR, MII_RXCFGn_ADDR
108 .asg 0xc, GPCFGn_REG
109 .asg FDB_XID_PORT1_RES, FDB_XID_PORTn_RES
110 .asg MII_PRE_CNT1, MII_PRE_CNTn
111 .endif
112 ;slice0 controls tx1 if switch, tx0 otherwise
113 ;slice1 controls tx0 if switch, tx1 otherwise
114 .if $isdefed("SLICE0")
115 .asg MII_TXCFG0_ADDR, MII_TXCFGn_ADDR
116 .asg MII_TXIPG0_ADDR, MII_TXIPGn_ADDR
117 .else
118 .asg MII_TXCFG1_ADDR, MII_TXCFGn_ADDR
119 .asg MII_TXIPG1_ADDR, MII_TXIPGn_ADDR
120 .endif
122 ; Enable RX L2 pru0 & rx
123 enable_rx_l2 .macro
124 ldi32 r28, MII_RXCFGn_ADDR
125 lbbo &r11, r28, 0, 4
126 set r11.t4 ;rx l2 enable
127 set r11.t0 ;rx enable
128 set r11.t9 ;rx_eof_sclr_dis0
129 set r11.t1 ;make tx eof visible in r31, bit16
130 sbbo &r11, r28, 0, 4
131 .endm
133 long_preamble_firewall_disable .macro
134 ldi32 r28, MII_PRE_CNTn
135 lbbo &r11, r28, 0, 4
136 and r11.b0, r11.b0, 0x0f
137 sbbo &r11, r28, 0, 4
138 .endm
140 gpcfg_reg_config .macro
141 ldi32 r28, PRUSS1_CFG_PRU_OFFSET
142 lbbo &r11, r28, GPCFGn_REG, 4
143 set r11.t1
144 set r11.t0
145 set r11.t27
146 sbbo &r11, r28, GPCFGn_REG, 4
147 .endm
149 mii_tx_config .macro
150 ldi32 r28, MII_TXCFGn_ADDR
151 lbbo &r11, r28, 0, 4
152 set r11.t0 ;enable txl1
153 set r11.t11 ;tx_32_mode en
154 set r11.t1 ;tx_auto_preamble
155 ;set mux
156 .if $isdefed("SLICE0")
157 clr r11.t8
158 .else
159 set r11.t8
160 .endif
161 ldi r11.b2, 0 ;set tx start delay to 0!!!
162 clr r11.t25
163 clr r11.t24
164 sbbo &r11, r28, 0, 4
165 .endm
167 set_tx_ipg .macro
168 ;change ipg to 88 ns (22 250mhz clocks)
169 ldi32 r28, MII_TXIPGn_ADDR
170 lbbo &r11, r28, 0, 4
171 ldi r11, 0x16 ; min IPG for testing (CCLINK)
172 sbbo &r11, r28, 0, 4
173 .endm
175 icss_g_config .macro
176 ; **for now let slice0 do txl2 & port mode config (ICSS_G register) for both sides {{{2
177 ;TX Config TXl2 - icss_g register
178 ldi32 r28, ICSS_G
179 lbbo &r11, r28, 0, 4
180 set r11.t1
181 set r11.t0
182 set r11.t2 ;rx_l2_g_en
184 .if $isdefed("RGMII")
185 set r11.t3
186 clr r11.t4
187 set r11.t5
188 clr r11.t6
189 .endif
190 .if $isdefed("MII")
191 clr r11.t3
192 clr r11.t4
193 clr r11.t5
194 clr r11.t6
195 .endif
196 sbbo &r11, r28, 0, 4
197 .endm
199 wait4debugger .macro
200 .if $isdefed("WAIT_FOR_DEBUGGER")
201 ldi32 r11, 0
202 $1: qbeq $1, r11, 0
203 .endif
204 .endm
206 ; we need to read DMA back only if there is ongoing transfer
207 ; assume when we read DMA status it shouldn't be 0,
208 ; otherwise let's think it is already stopped
209 flush_dma .macro unit
210 XFR2VBUS_CANCEL_READ_AUTO_64_CMD unit
211 nop
212 $1: xin unit, &r18, 4
213 qbeq $2, r18.w0, 0
214 qbne $1, r18.w0, 0x5
215 XFR2VBUS_READ64_RESULT unit
216 $2:
217 .endm
219 stop_tx_due_colission .macro
220 qbbc $1, GRegs.tx.b.flags, f_next_dma
221 flush_dma XFR2VBUS_XID_READ0
222 qba $2 ;
223 $1: flush_dma XFR2VBUS_XID_READ1
224 $2: set r31, r31, 29 ;tx.eof
225 set GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
226 ldi GRegs.tx.b.state, TX_S_W_EOF
227 .endm
229 restart_transmission .macro
230 ; OK we need to restart transmition of the same packet
231 ; use the same dma, which was used for the packet
232 ; !!!! we come here with TM disabled
233 qbbc retr_1, GRegs.tx.b.flags, f_next_dma
234 read_bd_from_smem r2, BD_OFS_0
235 XFR2VBUS_ISSUE_READ_AUTO_64_CMD XFR2VBUS_XID_READ0, r2, ADDR_HI
236 TM_ENABLE
237 XFR2VBUS_WAIT4READY XFR2VBUS_XID_READ0
238 qba retr_2
239 retr_1:
240 read_bd_from_smem r2, BD_OFS_1
241 XFR2VBUS_ISSUE_READ_AUTO_64_CMD XFR2VBUS_XID_READ1, r2, ADDR_HI
242 TM_ENABLE
243 XFR2VBUS_WAIT4READY XFR2VBUS_XID_READ1
245 retr_2: TM_DISABLE
246 TX_TASK_INIT2_shell r3
247 TM_ENABLE
248 .endm
250 ; Code starts {{{1
251 .retain ; Required forbuilding .out with assembly file
252 .retainrefs ; Required forbuilding .out with assembly file
253 .sect ".text:Start"
254 .global Start
256 Start:
257 TM_DISABLE
258 ldi32 r0, 0x80000000 ;TODO: driver has to enable PA_STAT
259 ldi32 r1, 0x3c000
260 sbbo &r0, r1, 8, 4
262 zero &r0, 124
263 P2P_IPC_ZAP ;zap IPC area
264 xout XFR2VBUS_XID_READ0, &r18, 4 ;disable xfr2vbus autoread mode
265 xout XFR2VBUS_XID_READ1, &r18, 4 ;
267 ;Initialization: set up RX & TX MII stuff.
268 enable_rx_l2
269 long_preamble_firewall_disable
270 gpcfg_reg_config ; 0x0800_0003
271 mii_tx_config
272 set_tx_ipg
273 icss_g_config
275 wait4debugger
277 set r31, r31, 18 ;RX reset
278 ;setup BSRAM
279 BSRAM_ZERO_BANK r1
281 ;SETUP portQ for to-host traffic, in order to do sandf PSI
282 PSIQ_CREATE
284 ;set up PSI INFO, CONTROL, STATUS TEMPLATES
285 .if $isdefed("SLICE0")
286 PSI_SETUP_INFO PSI_INFO_SLOT, 1
287 .else
288 PSI_SETUP_INFO PSI_INFO_SLOT, 2
289 .endif
290 PSI_SETUP_STATUS PSI_STATUS_SLOT
292 ;VA we should start here
293 ldi GRegs.pkt_cnt.x, 0
295 ;START RX/TX of 1 packet burst ; {{{1
296 RX:
297 RX_TASK_INIT
298 ;setup taskmanager
299 TM_PRU_CONFIG RX_SOF, RX_B0, RX_B1, RX_BN, RX_EOF, TX_NOP, TX_NOP, TX_FIFO, TX_EOF, RXTX_ERR
300 TM_ENABLE
301 set r31.t18 ;RX reset
302 ldi r18, 0
303 xout 40, &r18, 4 ;set tx fifo mode
305 ;read in global state
306 ldi GRegs.pkt_cnt.x, 0
307 ldi GRegs.tx.b.state, 0
308 ldi GRegs.rx.x, 0
309 ldi GRegs.snf.b.wr_cur, MINPS
310 ldi GRegs.snf.b.rd_cur, MINPS
311 ldi r30, 1522 ;todo - make a parameter
312 ldi32 r10, FW_CONFIG
314 ; set pru ready status
315 ldi32 r0, PRU_READY
316 sbbo &r0, r10, CFG_STATUS, 4
317 ; wait rtu ready
318 ldi32 r1, RTU_READY
319 wait_rtu_ready:
320 lbbo &r0, r10, CFG_RTU_STATUS, 4
321 qbne wait_rtu_ready, r0, r1
322 ; let's go
324 ;-------------------------------------------------------------------
325 ;BG TASK: r24-r29 are global ;{{{1
326 ;-------------------------------------------------------------------------
327 zero &r18, 24
329 ldi GRegs.ret_cnt, 0
330 ;================================
331 ; BG LOOP: until cmd cancel seen
332 ;================================
333 bg_loop:
334 add BgRegs.bg_cnt, BgRegs.bg_cnt, 1 ;loop count
335 ; if RTU started shutdown process - disable TM and loop forever
336 ldi32 r0, FW_CONFIG
337 ldi32 r1, RTU_STARTED_SHUTDOWN
338 lbbo &r9, r0, CFG_RTU_STATUS, 4
339 qbne skip_chk01, r9, r1
340 ;disable xfr2vbus autoread mode
341 ldi32 r18, 0
342 xout XFR2VBUS_XID_READ0, &r18, 4
343 xout XFR2VBUS_XID_READ1, &r18, 4
345 ; if we are here, we can place debug error code somewere in the SMEM
346 TM_DISABLE
347 ldi32 r1, PRU_STOPPED
348 sbbo &r1, r0, CFG_STATUS, 4
349 loop_here
351 skip_chk01:
352 ;-----------------------
353 ;schedule TX2HOST?
354 ;----------------------
355 ; do nothing if widget is full!!
356 xin XID_PSI_S, &r1,8
357 qbbc scheduler, r2,TB_WRITE
358 qbeq th_schedule0, BgRegs.psi2h_active, 0
359 ; active 2host
360 PSISANDF_TX bg_to_host2, scheduler
361 bg_to_host2: ;go again
362 xin XID_PSI_S, &r1,8
363 qbbc scheduler, r2,TB_WRITE
364 PSISANDF_TX scheduler, scheduler
365 jmp scheduler ;just in case
366 th_schedule0:
367 qbeq scheduler, GRegs.psiq.b.num_elem, 0
368 ; have new packet to send
369 TM_DISABLE
370 PSIQ_POP
371 TM_ENABLE
372 ;r2 = flow | len r3 = starting read index
373 PSISANDF_TX_INIT2 r2, r3
375 ;-----------------------
376 ;schedule TX2WIRE ?
377 ;----------------------
378 scheduler:
379 READ_RGMII_CFG r2, GRegs.speed_f ; update speed/duplex fields
380 qbbs sch_10, GRegs.speed_f, f_half_d ; don't check col if full duplex
381 ; if TX is idle and colission is set, probably it is from the
382 ; previouse packet. Just wait
383 read_col_status r2
384 qbne sch_05, GRegs.tx.b.state, TX_S_IDLE ; TODO: check error case
385 qbbs bg_loop, r2, 1 ; still active
386 sch_05: qbbc sch_10, r2, 1 ;
387 ; we came here if TX is active and collission is detected
388 ; we need to cancel the current TX and schedule retransmission
389 qbbs sch_10, GRegs.speed_f, f_stopped_due_col ; don't stop twice
390 TM_DISABLE
391 set GRegs.speed_f, GRegs.speed_f, f_col_detected
392 flip_tx_r0_r23
393 stop_tx_due_colission
394 flip_tx_r0_r23
395 TM_ENABLE
396 sch_10:
397 TM_DISABLE
398 ;if tx state is idle, check IPC for new descriptor
399 qbeq bg_schedule0, GRegs.tx.b.state, TX_S_IDLE
400 qbne sched_done, GRegs.tx.b.state, TX_S_ERR
401 ;error case (underflow)
402 ;todo
403 ldi GRegs.tx.b.state, TX_S_IDLE
404 sched_done:
405 TM_ENABLE
406 jmp bg_loop
408 bg_schedule0:
409 ldi GRegs.tx_blk, 0
410 clr GRegs.speed_f, GRegs.speed_f, f_col_detected
411 clr GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
412 qbbs bg_new_pkt, GRegs.speed_f, f_1gbps ; process as usual
413 qbbc bg_half_duplex, GRegs.speed_f, f_half_d ;
414 bg_schedule1:
415 qbbs bg_new_pkt, GRegs.speed_f, f_100mbps ;
416 if_ipg_not_expired sched_done
417 qba bg_new_pkt
419 bg_half_duplex:
420 qbne sched_done, GRegs.rx.b.state, RX_STATE_IDLE ; we have active RX,don't start TX
421 qbeq bg_schedule1, GRegs.ret_cnt, 0 ; just new packet
422 if_ipg_not_expired sched_done
423 restart_transmission
424 jmp bg_loop
426 bg_new_pkt:
427 ldi GRegs.ret_cnt, 0
428 qbbs bg_chk1, GRegs.tx.b.flags, f_next_dma
429 PRU_IPC_RX_CH0Q sched_done, r2, XFR2VBUS_XID_READ0
430 TX_TASK_INIT2_shell r2
431 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
432 TM_ENABLE
433 jmp bg_loop
434 bg_chk1:
435 PRU_IPC_RX_CH0Q sched_done, r3, XFR2VBUS_XID_READ1
436 TX_TASK_INIT2_shell r3
437 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
438 TM_ENABLE
439 jmp bg_loop
441 ;-------------------------------------
442 ; done with packets.
443 ;-------------------------------------
444 bg_done:
446 ;save bg info: bg loops, txstate, rxstate, (pkt counts)
447 PAGE_RESTORE BG_STATE, 32
448 mov r2, BgRegs.bg_cnt
449 mov r3, GRegs.tx.x
450 mov r4, GRegs.rx.x
451 mov r5, GRegs.pkt_cnt.x
452 PAGE_SAVEQ
454 ;update result area (length)
455 ldi32 r1, FW_CONFIG
456 sbbo &r2, r1, CFG_OUT, 20
457 ldi32 r2, 0x10000001
458 sbbo &r2, r1, CFG_STATUS, 4
459 loop_here
461 ;-------------------------------------------------------------------------
462 ;end BG task
463 ;-------------------------------------------------------------------------
465 ;---------------------------------------------------------------------
466 ; TX_EOF EvENT {{{1
467 ;---------------------------------------------------------------------
468 TX_EOF:
469 qbne tx_underflow, GRegs.tx.b.state, TX_S_W_EOF
470 flip_tx_r0_r23
471 qbbs tx_proc_col, GRegs.speed_f, f_stopped_due_col
472 ; TX TS processing
473 qbbc no_tx_ts, TxRegs.ds_flags, 5 ; we don't need tx_ts
474 GET_PKT_TX_TS r2
475 ldi32 r10, FW_CONFIG + TX_TS_BASE
476 sbbo &r2, r10, 0, 8
477 SPIN_TOG_LOCK_LOC PRU_RTU_TX_TS_READY
478 no_tx_ts:
479 ; if half duplex IPC to RTU
480 qbbs tx_eof_0, GRegs.speed_f, f_half_d
481 qbbs tx_eof_ipc1, GRegs.tx.b.flags, f_next_dma
482 SPIN_TOG_LOCK_LOC PRU_RTU_EOD_P_FLAG
483 qba tx_eof_0
484 tx_eof_ipc1:
485 SPIN_TOG_LOCK_LOC PRU_RTU_EOD_E_FLAG
486 ; we don't check if the next packet scheduled for 10Mbps
487 tx_eof_0:
488 qbbs tx_eof_1, GRegs.speed_f, f_1gbps
489 qbbc no_new_tx_10mbps, GRegs.speed_f, f_100mbps
490 tx_eof_1:
491 ldi GRegs.tx_blk, 0
492 clr GRegs.speed_f, GRegs.speed_f, f_col_detected
493 clr GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
494 ldi GRegs.ret_cnt, 0
496 qbbs teof_chk1, GRegs.tx.b.flags, f_next_dma
497 PRU_IPC_RX_CH0Q no_new_tx, r2, XFR2VBUS_XID_READ0
498 TX_TASK_INIT2 r2
499 set GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
500 jmp tx_eof_on_deck_done
501 teof_chk1:
502 PRU_IPC_RX_CH0Q no_new_tx, r3, XFR2VBUS_XID_READ1
503 TX_TASK_INIT2 r3
504 clr GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
506 tx_eof_on_deck_done:
507 TM_YIELD
508 flip_tx_r0_r23
509 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
510 loop_here
512 no_new_tx_10mbps:
513 ldi GRegs.tx_blk, 0
514 clr GRegs.speed_f, GRegs.speed_f, f_col_detected
515 clr GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
516 ldi GRegs.ret_cnt, 0
517 start_ipg_timer
519 no_new_tx:
520 ldi GRegs.tx.b.state, TX_S_IDLE
521 qba tx_eof_on_deck_done
522 ;
523 ; we came here due to collision, so we are in half duplex mode.
524 ; We either retranssmit or drop the packet
525 ;
526 tx_proc_col:
527 m_inc_stat r1.b0, TX_COL_RETRIES
528 qble txp_max_retry, GRegs.ret_cnt, 16 ; todo: define
529 qblt txp_max_retry, GRegs.tx_blk, 2 ; TODO: update for late col
530 start_backoff_timer GRegs.ret_cnt
531 add GRegs.ret_cnt, GRegs.ret_cnt, 1
532 qba no_new_tx
533 txp_max_retry:
534 m_inc_stat r1.b0, TX_COL_DROPPED
535 qbbs txp_max_01, GRegs.tx.b.flags, f_next_dma
536 SPIN_TOG_LOCK_LOC PRU_RTU_EOD_P_FLAG
537 qba txp_max_02
538 txp_max_01:
539 SPIN_TOG_LOCK_LOC PRU_RTU_EOD_E_FLAG
540 txp_max_02:
541 start_ipg_timer
542 ldi GRegs.ret_cnt, 0
543 qbbc no_new_tx_10mbps, GRegs.speed_f, f_100mbps
544 qba no_new_tx
546 ;------exception cases------
547 tx_underflow:
548 ldi GRegs.tx.b.state, TX_S_ERR
549 TM_YIELD
550 add GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
551 loop_here
553 ;---------------------------------------------------------------------
554 ; ENd TX_EOF
555 ;----------------------------------------------------------------------
557 ;---------------------------------------------------------------------
558 ; TX_FIFO EVENT {{{1
559 ;----------------------------------------------------------------------
560 TX_FIFO:
561 qbeq handle_portq, GRegs.tx.b.state, TX_S_ACTIVE
562 TM_YIELD
563 loop_here
565 handle_portq:
566 flip_tx_r0_r23
567 add GRegs.tx_blk, GRegs.tx_blk, 1
568 qbbs tx_fifo1, GRegs.speed_f, f_half_d
569 qbbs txf_90, GRegs.speed_f, f_stopped_due_col ; don't stop twice
571 update_col_status
572 qbbc tx_fifo1, GRegs.speed_f, f_col_detected
573 ; collision was detected, we need to stop pushing to TXL2
574 stop_tx_due_colission
575 qba txf_90
577 tx_fifo1:
578 TX_FILL_FIFO XFR2VBUS_XID_READ0
579 txf_90: TM_YIELD
580 flip_tx_r0_r23
581 loop_here
583 ;-------------------------------------------------------------------------
584 ;RXTX_ERR EVENT ; {{{1
585 ; assume rx issue.
586 ; reset rxl2 fifo
587 ; hopefully that cleans things up
588 ; need to see what else needs to be done
589 RXTX_ERR:
590 flip_tx_r0_r23
591 qbne rx_err?, GRegs.tx.b.state, TX_S_ERR
592 ; wait DMA ir complete
593 qbbs $3, TxRegs.ds_flags, 4
594 $1: xin XFR2VBUS_XID_READ0, &r18, 4
595 qbeq $2, r18.w0, 0x5
596 qbeq $2, r18, 0
597 qba $1
598 $2: nop
599 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ0
600 nop
601 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ0
602 SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
603 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
604 jmp $5
605 $3: xin XFR2VBUS_XID_READ1, &r18, 4
606 qbeq $4, r18.w0, 0x5
607 qbeq $4, r18, 0
608 qba $3
609 $4: nop
610 XFR2VBUS_CANCEL_READ_AUTO_64_CMD XFR2VBUS_XID_READ1
611 nop
612 XFR2VBUS_READ64_RESULT XFR2VBUS_XID_READ1
613 SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
614 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
615 $5:
616 set r31.t30; TX_RESET
617 nop
618 nop
619 ;set TX to TX_S_IDLE
620 ldi GRegs.tx.b.state, TX_S_IDLE
621 qba rxtx_err_exit
622 rx_err?
623 ldi r11.b3, 0x80
624 xout 22, &r11, 4
625 set r31.t22 ; clear rx eof (why isnt it bit 20?)
626 ldi r7, 1 ;indicate we drop
627 ;for now assume it is the RXL1 overflowing for next frame
628 ;todo: how to check to see if it is for this frame??
629 ldi GRegs.rx.b.state, RX_STATE_OVER0
630 rxtx_err_exit:
631 TM_YIELD
632 flip_tx_r0_r23
633 loop_here
635 ;-------------------------------------------------------------------------
636 ; Dummy: TX_NOP {{{1
637 ;-------------------------------------------------------------------------
638 TX_NOP:
639 TM_YIELD
640 loop_here
641 ;----------------------------------------------------------------------
642 ; Dummy: END TX_NOP
643 ;-------------------------------------------------------------------------
645 ;---------------------------------------------------------------
646 ; RX TASK, State 1: RX SOF {{{1
647 ;--------------------------------------------------------------
648 RX_SOF:
649 ;turn off RX_SOF
650 TM_YIELD
651 loop_here
652 ;---------------------------------------------------------------
653 ; END RX TASK, State 1
654 ;--------------------------------------------------------------
656 NBTR .set 32
657 ;---------------------------------------------------------------
658 ; RX TASK, State 2: RX_B0 {{{1
659 ;--------------------------------------------------------------
660 RX_B0:
661 flip_rx_r0_r23
663 ;BRING IN THE DATA
664 xin RXL2_BANK0, &r2, NBTR
665 ldi RxRegs.aux_flags, 1
666 qbeq rxb0_already_over, GRegs.rx.b.state, RX_STATE_OVER0
668 ldi GRegs.rx.x, 0x180 ;fresh state=1, (sof flag set)
669 P_W32_S rxb0_full ;stash pkt bytes in bs slot but don't start
671 jmp rx_b0_done
673 ;some error/exception cases handling here
674 rxb0_full: ;psi fifo in bsram full
675 P_W32_ABORT
676 ldi GRegs.rx.x, 0x7F80
677 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt, 1
678 jmp rx_b0_done
680 rxb0_already_over:
681 ldi GRegs.rx.x, 0x7F80
682 ;todo: bump stats
684 rx_b0_done:
685 TM_YIELD
686 flip_rx_r0_r23
687 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32 ;hopefully this gets executed!!
688 loop_here
689 ;---------------------------------------------------------------
690 ; END RX TASK, State 2
691 ;--------------------------------------------------------------
693 ;---------------------------------------------------------------
694 ; RX TASK, State 3: RX_B1 {{{1
695 ;--------------------------------------------------------------
696 RX_B1:
697 flip_rx_r0_r23
698 qbeq skip_b1, GRegs.rx.b.state, RX_STATE_DROP
699 ;!!better be here!!
700 ;r5.b0 = route info
701 ;r5.b1 = fid
702 ;r5.w2 = index
703 ;r6 = buffer ptr for s&f
704 ldi r0.b1, 0
705 stall_loop:
706 PRU_IPC_RX_CH1
707 qbbs got_ipc, r5.b0, f_rx_sof
708 add r0.b1, r0.b1, 1
709 qbne stall_loop, r0.b1, RB1_STALL_LIMIT
710 ldi GRegs.rx.b.state, RX_STATE_DROP ;stall limit reached
711 jmp rb1_ipc_done
712 got_ipc:
713 mov GRegs.rx.b.flags, r5.b0 ;forwarding info we got from RTU
714 PRU_IPC_RX_CH1_CLRB7 ;clear bit so we know we got it
715 mov RxRegs.pq_cur, r6 ;save buffer pointer (may not use) ;=flow in MAC
717 rb1_ipc_done:
718 xin RXL2_BANK1, &r2, 32 ;bring in data (r2-r9)
719 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
720 set RxRegs.aux_flags, RxRegs.aux_flags, f_b1_seen
722 TM_DISABLE
723 qbbc b1_rx_path1a, GRegs.rx.b.flags, f_tohost
724 P_W32 rxb1_full ;stash pkt bytes in bs slot
725 jmp rx_b1_done
726 rxb1_full:
727 ldi GRegs.rx.x, 0x7F80
728 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
729 b1_rx_path1a:
730 P_W32_ABORT ;abort the stashing of pkt in BS (for PSI)
731 rx_b1_done:
732 TM_ENABLE
733 b1_exit:TM_YIELD
734 flip_rx_r0_r23
735 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
736 loop_here
738 skip_b1:xin RXL2_BANK1, &r2, 32 ;error case. just read in data and drop
739 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
740 jmp b1_exit
741 ;---------------------------------------------------------------
742 ; END RX TASK, State 3
743 ;--------------------------------------------------------------
745 ;---------------------------------------------------------------
746 ; RX TASK, State 4: RX_BN {{{1
747 ;--------------------------------------------------------------
748 RX_BN:
749 flip_rx_r0_r23
750 ;check for overflow/drop or pkt too long
751 qbne pkt_ok, GRegs.rx.b.state, RX_STATE_DROP
752 ;errors:
753 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
754 qbbs rx_bnerr_sideB, RxRegs.aux_flags, f_fh
755 ;side A
756 xin RXL2_BANK0, &r2, 32
757 jmp rx_bn_done
758 rx_bnerr_sideB:
759 ;side B
760 xin RXL2_BANK1, &r2, 32
761 jmp rx_bn_done
762 rxbn_full:
763 ldi GRegs.rx.x, 0x7f80 ;indicate we need to drop
764 P_W32_ABORT
765 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
766 jmp rx_bn_done
768 ;take pkt, all good
769 pkt_ok: qbbs rx_bn_sideB, RxRegs.aux_flags, f_fh
770 xin RXL2_BANK0, &r2, 32
771 set RxRegs.aux_flags, RxRegs.aux_flags, f_fh
772 jmp bn_cont1
773 rx_bn_sideB:
774 xin RXL2_BANK1, &r2, 32
775 clr RxRegs.aux_flags, RxRegs.aux_flags, f_fh
776 bn_cont1:
777 qbbc rx_bn_done, GRegs.rx.x, 0
778 P_W32 rxbn_full
779 rx_bn_done:
780 TM_YIELD
781 flip_rx_r0_r23
782 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, 32
783 loop_here
784 ;---------------------------------------------------------------
785 ; END RX TASK, State 4
786 ;--------------------------------------------------------------
788 ;---------------------------------------------------------------
789 ; RX TASK, State 5: RX_EOF {{{1
790 ;--------------------------------------------------------------
791 RX_EOF:
792 TM_DISABLE
793 flip_rx_r0_r23
794 qbeq no_rx_sof, GRegs.rx.b.state, RX_STATE_DROP
795 qbbc no_rx_sof, GRegs.rx.b.flags, f_rx_sof
796 ldi r0.w0, 0x3310
797 and r0.w0, r31.w2, r0.w0
798 qbne beof_rx_err, r0.b0, 0x10 ;check for rx errors
799 qbbs rx_beof_sideB, RxRegs.aux_flags, f_fh
801 ;side A, r18 and r0.b0 has length
802 RX_EOF_RCV_BANK0
803 ldi r11.b3, 0x80
804 xout 22, &r11, 4
805 set r31.t22 ; clear rx eof (why isnt it bit 20?)
806 mov RxRegs.res1, r0.b0
807 jmp rx_beof_cont0
809 rx_beof_sideB:
810 ;side B, r18 and r0.b0 has length
811 RX_EOF_RCV_BANK1
812 ldi r11.b3, 0x80
813 xout 22, &r11, 4
814 set r31.t22 ; clear rx eof (why isnt it bit 20?)
815 add RxRegs.res1, r0.b0, 32
817 rx_beof_cont0:
818 add GRegs.rx.b.pkt_len, GRegs.rx.b.pkt_len, r0.b0
819 qbbc rx_eof_done, GRegs.rx.b.flags, f_tohost
820 ;check for pkt to long
821 qbge th_pkt_ok, GRegs.rx.b.pkt_len, r30.w0
822 add r30.w2, r30.w2,1 ; max error (like crc)
823 P_W32_ABORT
824 jmp rx_eof_done
825 th_pkt_ok:
826 ; push 32 to bsram fifo (not all will be valid)
827 P_W32 rxeof_noroom
828 ; push 'descriptor' to local queue. will be popped by bg task
829 mov r2.w2, RxRegs.pq_cur ;flow
830 mov r2.w0, GRegs.rx.b.pkt_len
831 mov r3, GRegs.snf.x ;bsram fifo position (maybe not necessary)
832 ;to do add rxtx timestamp
833 PSIQ_PUSH rxeof_qfull
835 rx_eof_done:
836 ; check for runt packet
837 qble rx_eof_done_b, GRegs.rx.b.pkt_len, 64
838 set r31.t18 ;reset RX_fifo
840 rx_eof_done_b:
841 TM_ENABLE
842 flip_rx_r0_r23
843 TM_YIELD
844 ldi GRegs.rx.s.fl_n_state, 0
845 add GRegs.pkt_cnt.w.rx, GRegs.pkt_cnt.w.rx, 1 ;also should tell bg #of pkts we have procesed
846 loop_here
848 ;----------------------------
849 ; bad frame, error handling
850 ;-----------------------------
851 rxeof_noroom:
852 rxeof_qfull:
853 P_W32_ABORT
854 add GRegs.snf.b.dbg_cnt, GRegs.snf.b.dbg_cnt,1
855 jmp rx_eof_done
857 beof_rx_err:
858 no_rx_sof:
859 ;saw no sof before eof or other such issues
860 ldi r11.b3, 0x80
861 xout 22, &r11, 4
862 set r31, r31, 22 ; clear rx eof (why isnt it bit 20?)
863 jmp rx_eof_done
864 ;---------------------------------------------------------------
865 ; END RX TASK, State 5
866 ;--------------------------------------------------------------
868 .include "resource_table.h"