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55 ;-------------------------------------
56 ;File: tx.h
57 ;Purpose: tx defines & macros
58 ;--------------------------------------
60 ;for TX_Q
61 ; see bsram_pru.h for slot/size
63 ;need_to_preempt
64 ;(f_tx_hold || f_tx_efq ) && f_pp_active && TX_S_ACTIVE && f_frame_preemptible && (PP_afs_tx> PP_afs_rem) &&(tx_len>64)
66 ;macros to end tx
68 ;end w/ CRC
69 END_TX_CRC .macro
70 ldi r31.w2, 0x2c00 ; (TX_EOF + TX_CRC_HI + TX_CRC_LO)
71 .endm
73 ;#define END_TX_NOCRC mov r31.w2, 0x2000 ; (TX_EOF )
75 ;end w/o crc
76 END_TX_NOCRC .macro
77 set r31.t29;tx.eof
78 .endm
80 ;end with M-crc (ie preempt this pkt)
81 END_TX_MCRC .macro
82 ldi r18, 0x80
83 xout 40, &r18, 4
84 .endm
86 ;macro to start Preemptible frame TX
87 TX_START_PRE .macro
88 ldi r18, 0x20;preempt 2
89 xout 40, &r18, 4;set tx fifo mode (premptable, start of frame)
90 .endm
92 ;macros @start to ADDTAG (preempt/no preempt)
93 ADDTAG .macro
94 and r0, r18, r18
95 ldi r18, 1;bit 1 insert tag
96 xout 40, &r18, 4
97 and r18, r0, r0
98 .endm
100 ;macros @start to REMTAG (preempt/no preempt)
101 REMTAG .macro
102 and r0, r18, r18
103 ldi r18, 4;bit 2=remove
104 xout 40, &r18, 4
105 and r18, r0, r0
106 .endm
108 ;super macro to to start of tx frame setup
109 SOP_TAG_STUFF .macro ret_label
110 qbbc chk_rem_tag2?, TxRegs.ds_flags, 1 ;r_desc.f_desc_add_vtag
111 ;todo: write vlan tag to insert into register
112 ldi r18, 1 ;bit 1 insert tag
113 xout 40, &r18, 4
114 jmp ret_label
115 chk_rem_tag2?:
116 qbbc ret_label, TxRegs.ds_flags, 2 ; r_desc.f_desc_rem_vtag
117 ldi r18, 4 ;bit 2=remove
118 xout 40, &r18, 4
119 .endm
121 ;same but for preeptible packet
122 SOP_TAG_STUFF_PP .macro r_desc, ret_label
123 qbbc chk_rem_tag2?, TxRegs.ds_flags, 1 ;r_desc.f_desc_add_vtag
124 ;todo: write vlan tag to insert into register
125 ldi r18, 0x21 ;bit 1 insert PP tag
126 xout 40, &r18, 4
127 jmp ret_label
128 chk_rem_tag2?:
129 qbbc no_tag?, TxRegs.ds_flags, 2 ;r_desc.f_desc_rem_vtag
130 ldi r18, 0x24;bit 2=remove
131 xout 40, &r18, 4 ; remove PP tag
132 jmp ret_label
133 no_tag?:
134 TX_START_PRE
135 .endm
137 ;-------------------------------------
138 ;basic macro to set up TX task from BG
139 ; v2 -> use descriptor from RTU-IPC
140 ; !! before start of tx
141 ; must be run in task disabled state!!
142 ; r_d MUST BE < r10
143 ; note, now only d1 is needed
144 ;------------------------------------
145 TX_TASK_INIT2_shell .macro r_d
146 flip_tx_r10_r23
147 ;do tx init
148 TX_TASK_INIT2 r_d
149 flip_tx_r10_r23
150 .endm
152 ;main macro to initialize TX from s&f IPC 'queue'
153 ; r_d holds descriptor
154 TX_TASK_INIT2 .macro r_d
156 ;temporary
157 mov TxRegs.ds_flags, r_d.w2 ;descriptor2(flags, etc)
158 mov GRegs.tx.b.len, r_d.w0 ;save length we are expecting to transmit
160 ;start things off
161 ;set TX fifo mode according to TX_D1 flags.. todo
162 .if $isdefed("VLAN_ENABLED")
163 qbbc no_pa0?, TxRegs.pp_ppok, f_pp_active
164 qbbs no_pa0?, TxRegs.ds_flags, 4;f_desc_express
165 ldi TxRegs.pp_afs_tx, 0 ;clear bytes sent so far
166 set TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft ;enuf bytes left to preempt
167 clr TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufsent ;NOT enuf bytes sent to preempt yet
168 SOP_TAG_STUFF_PP load_fifo?
169 jmp load_fifo?
170 no_pa0?:
171 SOP_TAG_STUFF load_fifo?
172 .else
173 ;P-pkt
174 qbbc no_pa?, TxRegs.pp_ppok, f_pp_active
175 qbbs no_pa?, TxRegs.ds_flags, 4 ;f_desc_express
176 ldi TxRegs.pp_afs_tx, 0;clear bytes sent so far
177 set TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft ;enuf bytes left to preempt
178 clr TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufsent ;NOT enuf bytes sent to preempt yet
179 TX_START_PRE
180 no_pa?:
181 .endif
182 load_fifo?:
183 ldi GRegs.tx.b.state, TX_S_ACTIVE
184 TX_FILL_FIFO XFR2VBUS_XID_READ0
185 .endm
187 ;------------------------------------
188 ;basic macro for TX fifo filling from MSMC
189 ; portQ
190 ; MUST RUN from TX task register state
191 ;---------------------------------------
192 TX_FILL_FIFO .macro runit
193 .newblock
194 ;read in data (now in r2 -r17) [note: on eop some of this may be garbage]
195 qbbs $2, TxRegs.ds_flags, 4 ; TxRegs.ds_flags.f_desc_read_unit
196 qbge $4, GRegs.tx.b.len, 64
197 XFR2VBUS_WAIT4READY runit
198 XFR2VBUS_READ64_RESULT runit
199 wait1?: xin TXL2, &r19, 4
200 qbne wait1?, r19.b2, 0
201 xout TXL2, &r2, 64
202 jmp $3
203 $2:
204 qbge $5, GRegs.tx.b.len, 64
205 XFR2VBUS_WAIT4READY (runit + 1)
206 XFR2VBUS_READ64_RESULT (runit+1)
207 wait2?: xin TXL2, &r19, 4
208 qbne wait2?, r19.b2, 0
209 xout TXL2, &r2, 64
210 $3:
211 ;output data
212 sub GRegs.tx.b.len, GRegs.tx.b.len, 64
213 qblt $9, GRegs.tx.b.len, 64
214 clr TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft
215 jmp $9
217 $4: ;eop, unit a
218 XFR2VBUS_WAIT4READY runit
219 XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit)
220 nop
221 XFR2VBUS_READ64_RESULT (runit)
222 BN_TX_N GRegs.tx.b.len
223 SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
224 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
225 jmp $6
226 $5: ;eop, unit b
227 XFR2VBUS_WAIT4READY (runit + 1)
228 XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit+1)
229 nop
230 XFR2VBUS_READ64_RESULT (runit+1)
231 BN_TX_N GRegs.tx.b.len
232 SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
233 SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
234 $6:
235 ;close out tx
236 qbbs $7, TxRegs.ds_flags, 0 ;TxRegs.ds_flags.f_desc_do_crc
237 set r31, r31, 29 ;tx.eof
238 jmp $8
240 $7: or r31.b3, r31.b3, 0x2c
241 $8: ldi GRegs.tx.b.state, TX_S_W_EOF
242 $9:
243 .endm