71423991c5ecf9fe926fc76339b4d020c8552359
[processor-sdk/pdk.git] / packages / ti / drv / emac / test / EmacLoopbackTest / test_utils_k3.c
1 /* =============================================================================
2  *   Copyright (c) Texas Instruments Incorporated 2018-2020
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
34 /**
35  *  \file     test_utils_k3.c
36  *
37  *  \brief    This file contains common utility functions used by the emac loopback unit
38  *             test applications.
39  *
40  */
42 #include <string.h>
43 #include <stdio.h>
44 #include <stdint.h>
46 #include <xdc/std.h>
47 #include <xdc/runtime/System.h>
48 #include <xdc/runtime/Memory.h>
49 #include <xdc/runtime/Error.h>
51 #include <ti/sysbios/BIOS.h>
52 #include <ti/sysbios/knl/Task.h>
54 #include <ti/csl/csl_chip.h>
55 #include <ti/csl/cslr_icss.h>
56 /* EMAC Driver Header File. */
57 #include <ti/drv/emac/emac_drv.h>
58 #include <ti/drv/emac/src/emac_osal.h>
59 #include <ti/drv/emac/emac_ioctl.h>
61 #include <ti/drv/emac/src/v5/emac_hwq.h>
63 /* SOC Include Files. */
64 #include <ti/drv/emac/soc/emac_soc_v5.h>
66 /* Test application local header file */
67 #include "ti/drv/emac/test/EmacLoopbackTest/test_loc.h"
69 #include <ti/drv/uart/UART.h>
70 #include <ti/drv/uart/UART_stdio.h>
71 #include <ti/board/board.h>
73 #ifdef SOC_J721E
74 #include <ti/board/src/j721e_evm/include/board_pinmux.h>
75 #include <ti/board/src/j721e_evm/include/board_control.h>
76 #endif
78 #ifdef EMAC_TEST_APP_ICSSG
79 #include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
80 /* PRUSS Driver Header File. */
81 #include <ti/drv/pruss/pruicss.h>
82 #include <ti/drv/pruss/soc/pruicss_v1.h>
83 #endif
86 #ifdef UNITY_INCLUDE_CONFIG_H
87 #include <ti/build/unit-test/Unity/src/unity.h>
88 #include <ti/build/unit-test/config/unity_config.h>
89 #endif
92 extern uint32_t portNum;
93 extern uint32_t endPort;
94 extern int port_en[];
96 /**********************************************************************
97  ************************** Global Variables **************************
98  **********************************************************************/
99 static uint8_t  gAppTestSequenceNumber  = 1;
100 #ifdef EMAC_TEST_APP_ICSSG
102 #define EMAC_ICSSG_DUAL_MAC_FW_BUFER_POOL_SIZE_PG2 0X14000 // 8 BUFFER POOLS EACH 0X2000 BYTES PLUS 0X4000 BYTES FOR RX Q CONTEXT info
103 #define EMAC_ICSSG_BUFFER_POOL_SIZE_PG2 0x2000u
104 #define EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2 8u
106 #ifdef SOC_J721E
107 uint8_t icss_tx_port_queue[2][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_ocmc_mem")));
108 #else
109 #ifdef EMAC_TEST_APP_WITHOUT_DDR
110 /* DDR less test, can only test with 2 ports due to msmc memory constraints */
111 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
112 #else
113 #ifdef EMAC_BENCHMARK
114 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
115 #else /* test all port for DUAL MAC */
116 uint8_t icss_tx_port_queue[6][EMAC_ICSSG_DUAL_MAC_FW_BUFER_POOL_SIZE_PG2] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
117 #endif
118 #endif
119 #endif
121 PRUICSS_Handle prussHandle[EMAC_MAX_ICSS] = {NULL, NULL, NULL};
122 #endif
124 /* PG1.0 macro check */
125 #define APP_TEST_AM65XX_PG1_0_VERSION (0x0BB5A02FU)
127 /* Macro for test failure status return value. */
128 #define APP_TEST_SUCCESS    0
129 #define APP_TEST_FAILURE    -1
131 /* Maxwell PG version */
132 uint32_t gPgVersion;
135 /* semaphore to sync up ICSSG management request and callback response */
136 static SemaphoreP_Handle gAppTestIoctlWaitAckSem;
139 /* Test will use network firmware to verify packet transmission
140   * and reception between 2 physical ICSSG ports, each ICSSG port needs to be connected
141   * to another ICSSG port via ethernet cable.
143   * NOTE that for CPSW port, test will always test loopback mode of operation
144   * with CPSW sub-system.
145   */
147 #ifdef EMAC_TEST_APP_ICSSG
148 /* EMAC firmware header files */
151 #if defined (SOC_AM65XX)
152 /* PG 1.0 Firmware */
153 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii0_bin.h>      /* PDSPcode */
154 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test0_bin.h>             /* PDSP2code */
155 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii1_bin.h>      /* PDSP3code */
156 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test1_bin.h>             /* PDSP4code */
157 #endif
159 /* PG2.0 firmware */
160 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RX_PRU_SLICE0_bin.h>
161 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RX_PRU_SLICE1_bin.h>
162 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RTU0_SLICE0_bin.h>
163 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RTU0_SLICE1_bin.h>
164 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/TX_PRU_SLICE0_bin.h>
165 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/TX_PRU_SLICE1_bin.h>
168 typedef struct {
169     const uint32_t *pru;
170     uint32_t pru_size;
171     const uint32_t *rtu;
172     uint32_t rtu_size;
173     const uint32_t *txpru;
174     uint32_t txpru_size;
175 } app_test_pru_rtu_fw_t;
177 app_test_pru_rtu_fw_t firmware_pg1[2] = {
178 #if defined (SOC_AM65XX)
179     { PDSPcode_0, sizeof(PDSPcode_0), PDSP2code_0, sizeof(PDSP2code_0), NULL, 0},
180     { PDSP3code_0, sizeof(PDSP3code_0), PDSP4code_0, sizeof(PDSP4code_0), NULL, 0}
181 #endif
182 };
183 app_test_pru_rtu_fw_t firmware_pg2[2] = {
184     {
185         RX_PRU_SLICE0_b00, sizeof(RX_PRU_SLICE0_b00), RTU0_SLICE0_b00, sizeof(RTU0_SLICE0_b00), TX_PRU_SLICE0_b00, sizeof(TX_PRU_SLICE0_b00)
186     },
187     {
188         RX_PRU_SLICE1_b00, sizeof(RX_PRU_SLICE1_b00), RTU0_SLICE1_b00, sizeof(RTU0_SLICE1_b00), TX_PRU_SLICE1_b00, sizeof(TX_PRU_SLICE1_b00)
189     }
190 };
191 #endif
193 int32_t app_test_task_init_pruicss(uint32_t portNum);
194 int32_t app_test_task_disable_pruicss(uint32_t portNum);
195 void app_test_wait_mgmt_resp(uint32_t waitTimeMilliSec);
197 uint32_t pollModeEnabled = 0;
198 uint32_t linkStatus = 0;
199 uint32_t initComplete = 0;
200 uint32_t app_test_id = 0;
201 #if defined (EMAC_BENCHMARK)
202 #if defined  (EMAC_TEST_APP_ICSSG)
203 uint32_t app_test_send_port = 4U;
204 uint32_t app_test_recv_port = 4U;
205 #else
206 uint32_t app_test_send_port = 6U;
207 uint32_t app_test_recv_port = 6U;
208 #endif
209 #endif
210 #ifdef _TMS320C6X
211 /* Memory allocated for the packet buffer. This is 128 bytes aligned. */
212 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE];
213 #pragma DATA_ALIGN(app_pkt_buffer, 64)
215 /* Memory allocated for the application control block */
216 #else
217 #ifdef EMAC_TEST_APP_WITHOUT_DDR
218 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64)));
219 #else
220 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64))) __attribute__ ((section (".bss:emac_ddr_mem")));
221 #endif
222 #endif
224 int32_t gFail_count;
226 int32_t testPktClone = 0;
227 #ifndef EMAC_TEST_APP_WITHOUT_DDR
228 #define EMAC_TEST_MAX_CHANS_PER_PORT 4
229 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 9
230 #else
231 #define EMAC_TEST_MAX_CHANS_PER_PORT 1
232 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 3
233 #endif
234 /*
235  * UDMA driver objects
236  */
237 struct Udma_DrvObj      gUdmaDrvObj;
238 struct Udma_ChObj       gUdmaTxChObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT];
239 struct Udma_ChObj       gUdmaRxChObj[EMAC_MAX_PORTS];
240 struct Udma_EventObj    gUdmaRxCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
243 struct Udma_ChObj       gUdmaRxMgmtPsiChObj[EMAC_MAX_PORTS];
244 struct Udma_EventObj    gUdmaRxMgmtPsiCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
246 Udma_DrvHandle          gDrvHandle = NULL;
248 /* Ring parameters*/
249 /*brief Number of ring entries - we can prime this much memcpy operations */
250 #ifdef EMAC_TEST_APP_WITHOUT_DDR
251 #define EMAC_TEST_APP_RING_ENTRIES      (32)
252 #else
253 #define EMAC_TEST_APP_RING_ENTRIES      (128)
254 #endif
255 /* Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
257 #define EMAC_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
258 /* Total ring memory */
260 #define EMAC_TEST_APP_RING_MEM_SIZE     (EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_RING_ENTRY_SIZE)
262 /* UDMA host mode buffer descriptor memory size.    *  Make it multiple of 128 byte alignment */
263 #define EMAC_TEST_APP_DESC_SIZE         (sizeof(CSL_UdmapCppi5HMPD) + (128U - sizeof(CSL_UdmapCppi5HMPD)))
265 /*
266  * UDMA Memories
267  */
268 #ifdef EMAC_TEST_APP_WITHOUT_DDR
269 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
270 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
271 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
272 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
273 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
274 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
275 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
276 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
277 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
278 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
279 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
280 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
281 /* TX/RX ring CPPI descriptor memory */
282 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
283 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
284 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
285 #else
286 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
287                                       __attribute__ ((section (".bss:emac_ddr_mem")));
288 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
289                                       __attribute__ ((section (".bss:emac_ddr_mem")));
290 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
291                                             __attribute__ ((section (".bss:emac_ddr_mem")));
292 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
293                                             __attribute__ ((section (".bss:emac_ddr_mem")));
294 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
295                                         __attribute__ ((section (".bss:emac_ddr_mem")));
296 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
297                                         __attribute__ ((section (".bss:emac_ddr_mem")));
298 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
299                                         __attribute__ ((section (".bss:emac_ddr_mem")));
300 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
301                                       __attribute__ ((section (".bss:emac_ddr_mem")));
302 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
303                                       __attribute__ ((section (".bss:emac_ddr_mem")));
305 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
306                                         __attribute__ ((section (".bss:emac_ddr_mem")));
307 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
308                                          __attribute__ ((section (".bss:emac_ddr_mem")));
309 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
310                                       __attribute__ ((section (".bss:emac_ddr_mem")));
311 /* TX/RX ring CPPI descriptor memory */
312 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
313                                     __attribute__ ((section (".bss:emac_ddr_mem")));
314 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
315                                       __attribute__ ((section (".bss:emac_ddr_mem")));
316 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
317                                   __attribute__ ((section (".bss:emac_ddr_mem")));
319 #endif
323 #ifdef EMAC_TEST_APP_WITHOUT_DDR
324 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
325 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
326 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
327 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
328 #else
329 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
330                                   __attribute__ ((section (".bss:emac_ddr_mem")));
332 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
333                                   __attribute__ ((section (".bss:emac_ddr_mem")));
335 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
336                                   __attribute__ ((section (".bss:emac_ddr_mem")));
338 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
339                                   __attribute__ ((section (".bss:emac_ddr_mem")));
340 #endif
342 uint32_t pkt_rcv_count = 0;
343 static volatile uint32_t pkt_received = 0;
344 static volatile uint32_t timestamp_received = 1;
346 #ifdef UNITY_INCLUDE_CONFIG_H
347 /*
348  *  ======== Unity set up and tear down ========
349  */
350 void setUp(void)
352     /* Do nothing */
355 void tearDown(void)
357     /* Do nothing */
359 #endif
361 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult);
363 /**********************************************************************
364  ****************** Test Configuration Variables **********************
365  **********************************************************************/
368 #define APP_TEST_PKT_SEND_COUNT  16
369 #define APP_TEST_MIN_PKT_SEND_SIZE 60
370 #define APP_TEST_MAX_PKT_SEND_SIZE 1500
372 /* DO NOT CHANGE app_test_uc_pkt UNLESS APP_TEST_PKT_SIZE IS UPDATED */
373 #define APP_TEST_PKT_SIZE       64
374 static uint8_t app_test_uc_pkt[APP_TEST_PKT_SIZE] = {
375     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
376     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
377     0x08, 0x06, 0x00, 0x01,
378     0x08, 0x00, 0x06, 0x04,
379     0x00,0x01,0x01, 0xbb,
380     0xcc, 0xdd, 0xee, 0xff,
381     0xc0, 0xa8, 0x01, 0x16,
382     0x00, 0x00, 0x00, 0x00,
383     0xc0, 0xa8,0x01, 0x02,
384     0x01,0x02,0x03,0x04,
385     0x01,0x02,0x03,0x04,
386     0x01,0x02,0x03,0x04,
387     0x01,0x02,0x03,0x04,
388     0x01,0x02,0x03,0x04,
389     0xfe,0xfe, 0x00, 0x00
390 };
391 static uint8_t app_test_bc_pkt[APP_TEST_PKT_SIZE] = {
392     0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
393     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
394     0x08, 0x06, 0x00, 0x01,
395     0x08, 0x00, 0x06, 0x04,
396     0x00,0x01,0x01, 0xbb,
397     0xcc, 0xdd, 0xee, 0xff,
398     0xc0, 0xa8, 0x01, 0x16,
399     0x00, 0x00, 0x00, 0x00,
400     0xc0, 0xa8,0x01, 0x02,
401     0x01,0x02,0x03,0x04,
402     0x01,0x02,0x03,0x04,
403     0x01,0x02,0x03,0x04,
404     0x01,0x02,0x03,0x04,
405     0x01,0x02,0x03,0x04,
406     0xfe,0xfe, 0x00, 0x00
407 };
409 static uint8_t app_test_mc_pkt[APP_TEST_PKT_SIZE] = {
410     0x01, 0x93, 0x20, 0x21, 0x22, 0x2a,
411     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
412     0x08, 0x06, 0x00, 0x01,
413     0x08, 0x00, 0x06, 0x04,
414     0x00,0x01,0x01, 0xbb,
415     0xcc, 0xdd, 0xee, 0xff,
416     0xc0, 0xa8, 0x01, 0x16,
417     0x00, 0x00, 0x00, 0x00,
418     0xc0, 0xa8,0x01, 0x02,
419     0x01,0x02,0x03,0x04,
420     0x01,0x02,0x03,0x04,
421     0x01,0x02,0x03,0x04,
422     0x01,0x02,0x03,0x04,
423     0x01,0x02,0x03,0x04,
424     0xfe,0xfe, 0x00, 0x00
425 };
427 static uint8_t *pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
429 /**********************************************************************
430  ************************ EMAC TEST FUNCTIONS *************************
431  **********************************************************************/
432 /**
433  *  @b app_queue_pop
434  *  @n
435  *      Dequeues a packet descriptor from an app queue.
436  *
437  *  @param[in]  pq
438  *      Packet queue of type APP_PKT_QUEUE_T .
439  *
440  *  @retval
441  *      EMAC_Pkt popped from the queue.
442  */
443 EMAC_PKT_DESC_T*
444 app_queue_pop
446     uint32_t              port_num,
447     APP_PKT_QUEUE_T*    pq
450     EMAC_PKT_DESC_T*    pPktHdr;
451 #ifndef EMAC_BENCHMARK
452     uintptr_t key;
453 #endif
454     if (!pq->Count)
455     {
456         return 0;
457     }
458 #ifndef EMAC_BENCHMARK
459     key = EMAC_osalHardwareIntDisable();
460 #endif
462     pPktHdr = pq->pHead;
463     if( pPktHdr )
464     {
465         pq->pHead = pPktHdr->pNext;
466         pq->Count--;
467         pPktHdr->pPrev = pPktHdr->pNext = 0;
468     }
469 #ifndef EMAC_BENCHMARK
470     EMAC_osalHardwareIntRestore(key);
471 #endif
473     return( pPktHdr );
476 /**
477  *  @b app_queue_push
478  *  @n
479  *      Enqueues a packet in EMAC_Pkt queue.
480  *
481  *  @param[in]  pq
482  *      Packet queue of type EMAC_PKT_QUEUE_T .
483  *  @param[in]  pPktHdr
484  *      EMAC_PKT_DESC_T type packet to push.
485  *
486  *  @retval
487  *      void
488  */
489 void
490 app_queue_push
492     uint32_t              port_num,
493     APP_PKT_QUEUE_T*    pq,
494     EMAC_PKT_DESC_T*    pPktHdr
497 #ifndef EMAC_BENCHMARK
498     uintptr_t key;
499     key = EMAC_osalHardwareIntDisable();
500 #endif
501     pPktHdr->pNext = 0;
503     if( !pq->pHead )
504     {
505         /* Queue is empty - Initialize it with this one packet */
506         pq->pHead = pPktHdr;
507         pq->pTail = pPktHdr;
508     }
509     else
510     {
511         /* Queue is not empty - Push onto end */
512         pq->pTail->pNext = pPktHdr;
513         pq->pTail        = pPktHdr;
514     }
515     pq->Count++;
516 #ifndef EMAC_BENCHMARK
517     EMAC_osalHardwareIntRestore(key);
518 #endif
521 uint32_t allocCount = 0;
522 uint32_t allocFailed = 0;
523 uint32_t gAppAllocFailure = 0;
525 #ifndef EMAC_TEST_ALLOC_FAIL
526 /**
527  *  @b Description
528  *  @n
529  *      Call back function provided by application for EMAC driver
530  *      to allocate a packet descriptor.
531  *
532  *  @retval
533  *      pointer to the allocated packet descriptor.
534  */
535  EMAC_PKT_DESC_T*
536 app_alloc_pkt
538     uint32_t              port_num,
539     uint32_t              pkt_size
542     EMAC_PKT_DESC_T*    p_pkt_desc = NULL;
543     if (pkt_size <= APP_EMAC_MAX_PKT_SIZE)
544     {
545         /* Get a packet descriptor from the free queue */
546         p_pkt_desc              = app_queue_pop(port_num, &app_mcb.emac_pcb[port_num].freeQueue);
547         if(p_pkt_desc)
548         {
549             p_pkt_desc->AppPrivate  = (uintptr_t)p_pkt_desc;
550             p_pkt_desc->BufferLen   = APP_EMAC_MAX_PKT_SIZE;
551             p_pkt_desc->DataOffset  = 0;
552             p_pkt_desc->pPrev = NULL;
553             p_pkt_desc->pNext = NULL;
554         }
555         else
556             gAppAllocFailure++;
557     }
558     else
559     {
560         UART_printf ("app_alloc_pkt on port %d failed, packet size %d is too big\n", port_num, pkt_size);
561         return NULL;
562     }
563     return p_pkt_desc;
565 #else
566 #endif
568 /**
569  *  @b Description
570  *  @n
571  *      Call back function provided by application for EMAC driver
572  *      to free a packet descriptor.
573  *
574  *  @retval
575  *      None.
576  */
577 void
578 app_free_pkt
580     uint32_t              port_num,
581     EMAC_PKT_DESC_T*    p_pkt_desc
584     /* Free a packet descriptor to the free queue */
585     app_queue_push(port_num, &app_mcb.emac_pcb[port_num].freeQueue,
586                    (EMAC_PKT_DESC_T *)p_pkt_desc->AppPrivate);
591 /**
592 *  @b Description
593 *  @n
594 *      Intialize the application control block, free/rx packet queue.
596 *  @retval
597 *      None.
598 */
599 void
600 app_init(void)
602     uint32_t            i, j;
603     EMAC_PKT_DESC_T*    p_pkt_desc;
604     uint8_t*            pktbuf_ptr;
606     UART_printf ("EMAC loopback test application initialization\n");
608     /* Reset application control block */
609     memset(&app_mcb, 0, sizeof (APP_EMAC_MCB_T));
611 #ifdef _TMS320C6X
612     app_mcb.core_num = CSL_chipReadReg (CSL_CHIP_DNUM);
613 #else
614     app_mcb.core_num = 0;
615 #endif
616     pktbuf_ptr = (uint8_t *) ((uintptr_t) app_pkt_buffer);
617     /* Initialize the free packet queue */
618     for (i=portNum; i <=endPort; i++)
619     {
620         if (!port_en[i])
621             continue;
622 #ifndef EMAC_BENCHMARK
623         for (j=0; j<APP_MAX_PKTS/MAX_NUM_EMAC_PORTS; j++)
624 #else
625         for (j=0; j<(APP_MAX_PKTS); j++)
626 #endif
627         {
628             p_pkt_desc               = &app_mcb.emac_pcb[i].pkt_desc[j];
629             p_pkt_desc->pDataBuffer  = pktbuf_ptr;
630             p_pkt_desc->BufferLen    = APP_EMAC_MAX_PKT_SIZE;
631             app_queue_push( i, &app_mcb.emac_pcb[i].freeQueue, p_pkt_desc );
632             pktbuf_ptr += APP_EMAC_MAX_PKT_SIZE;
633         }
634     }
637 #if defined (EMAC_BENCHMARK)
638 uint32_t app_test_send_fail = 0;
639 uint32_t app_test_alloc_fail = 0;
641 /******************************************************************************
642  * Function: EMAC test loopback packet
643  ******************************************************************************/
644 /**
645  *  @brief  This function is used to loopback the pkt received to sender
646  */
647 void app_test_loopback_pkt(uint32_t portNum, EMAC_PKT_DESC_T* pDesc)
649     EMAC_DRV_ERR_E sentRetVal;
650     uint8_t* temp;
651     EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(portNum, APP_EMAC_MAX_PKT_SIZE);
652     if (p_pkt_desc == NULL)
653     {
654         UART_printf("app_test_loopback_pkt: app alloc pkt failed\n");
655         app_test_alloc_fail++;
656     }
657     else
658     {
659         temp = p_pkt_desc->pDataBuffer; // temp is now buffer
661         p_pkt_desc->pDataBuffer = pDesc->pDataBuffer;
662         pDesc->pDataBuffer = temp;
664         p_pkt_desc->AppPrivate = (uint32_t)p_pkt_desc;
665         p_pkt_desc->ValidLen     = pDesc->PktLength-4;
666         p_pkt_desc->DataOffset   = 0;
667         p_pkt_desc->PktLength    = pDesc->PktLength-4;
668         p_pkt_desc->PktFrags     = 1;
669         p_pkt_desc->pNext = NULL;
670         p_pkt_desc->pPrev = NULL;
671         p_pkt_desc->PktChannel     = 0;
672         p_pkt_desc->PktLength      = pDesc->PktLength-4;
673         sentRetVal = emac_send(portNum, p_pkt_desc);
674         if(sentRetVal != EMAC_DRV_RESULT_OK)
675         {
676             app_test_send_fail++;
677             app_free_pkt(portNum,p_pkt_desc);
678         }
679     }
681 #endif
684 /******************************************************************************
685  * Function: EMAC RX packet call back function
686  ******************************************************************************/
687 /**
688  *  @brief  This function is used to call back the network application when a
689  *          packet is received.
690  */
691 void app_test_rx_pkt_cb(uint32_t port_num, EMAC_PKT_DESC_T* p_desc)
693 #if !defined (EMAC_BENCHMARK)
694     if (memcmp(p_desc->pDataBuffer, pTestPkt, APP_TEST_PKT_SIZE) == 0)
695     {
696         pkt_rcv_count++;
697         if (port_num != EMAC_PORT_CPSW)
698         {
699             UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d, rx timestamp:  0x%x%08x\n",
700                                             port_num,
701                                             p_desc->PktChannel,
702                                             pkt_rcv_count,
703                                             (unsigned int)(p_desc->RxTimeStamp >> 32),
704                                             (unsigned int)(p_desc->RxTimeStamp & 0xFFFFFFFF));
705         }
706         else
707         {
708                     UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d\n",port_num, p_desc->PktChannel, pkt_rcv_count);
709         }
710     }
711     else
712     {
713         UART_printf("app_test_rx_pkt_cb: port %u: ring num %d: packet match failed\n", port_num, p_desc->PktChannel);
714         while(1);
715     }
716     if (p_desc->AppPrivate != 0U)
717     {
718         app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
719     }
720     pkt_received = 1;
721 #else
722     if (p_desc->AppPrivate != 0U)
723     {
724         if (port_num != EMAC_PORT_CPSW)
725         app_test_loopback_pkt(app_test_send_port,p_desc);
726         app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
727         pkt_received = 1;
728     }
729     pkt_rcv_count++;
730 #endif
735 /******************************************************************************
736 * Function: EMAC RX timestamp_response back function
737 ******************************************************************************/
738 /**
739 *  @brief  This function is used to call back the network application when a
740 *          timestamp response packet is receive from ICSSG firmware.
741 */
742 void app_test_ts_response_cb(uint32_t port_num, uint32_t ts_id, uint64_t ts, bool is_valid)
744     UART_printf("app_test_ts_response_cb: port %d: tx timestamp id: 0x%x, tx timestamp: 0x%x%08x is_valid: %d\n",
745                             port_num,
746                             ts_id,
747                             (unsigned int)(ts >> 32),
748                             (unsigned int)(ts& 0xFFFFFFFF),
749                             is_valid);
750     timestamp_received = 1;
753 void app_test_task_poll_pkt (UArg arg0, UArg arg1)
755     uint32_t port = (uint32_t) arg0;
756     linkStatus = 1;
757     while(initComplete == 0)
758     {
759         Task_sleep(1);
760     }
761     UART_printf("polling rx packets on port: %d\n", port);
762     while(1)
763     {
764         if (pollModeEnabled == 0)
765         {
766             emac_poll_pkt(port);
767 #ifndef EMAC_BENCHMARK
768             Task_sleep(5);
769             if (pkt_rcv_count == APP_TEST_PKT_SEND_COUNT)
770                 break;
771 #endif
772         }
773         else
774         {
775             break;
776         }
777     }
779 /**
780 *  @brief  This function is used to call back the network application when a
781 *          config response packet is receive from ICSSG firmware.
782 */
783     void app_test_rx_mgmt_response_cb(uint32_t port_num, EMAC_IOCTL_CMD_RESP_T* pCmdResp)
784     {
785         if (pCmdResp != NULL)
786         {
787             if (pCmdResp->seqNumber == (gAppTestSequenceNumber -1))
788             {
789                 UART_printf("app_test_rx_mgmt_response_cb: port: %d, status: 0x%x, sequence number: 0x%x\n",
790                             port_num, pCmdResp->status, pCmdResp->seqNumber);
791                 if (pCmdResp->respParamsLength)
792                 {
793                     UART_printf("app_test_rx_mgmt_response_cb: port: %d, 0x%x, 0x%x, 0x%x\n",
794                     port_num, pCmdResp->respParams[0],pCmdResp->respParams[1],pCmdResp->respParams[2]);
795                 }
796                 EMAC_osalPostLock(gAppTestIoctlWaitAckSem);
797             }
798             else
799             {
800                 UART_printf("app_test_rx_mgmt_response_cb (incorrect sequence number): port: %d, status: 0x%x, sequence number: 0x%x\n",
801                             port_num, pCmdResp->status, pCmdResp->seqNumber);
802                 if (pCmdResp->respParamsLength)
803                 {
804                     UART_printf("app_test_rx_mgmt_response_cb: port: %d, resp length: 0x%x, 0x%x, 0x%x, 0x%x\n",
805                     port_num,
806                     pCmdResp->respParamsLength,
807                     pCmdResp->respParams[0],
808                     pCmdResp->respParams[1],
809                     pCmdResp->respParams[2]);
810                 }
811                 EMAC_osalPostLock(gAppTestIoctlWaitAckSem);
812             }
813         }
814     }
816 void app_test_task_poll_ctrl (UArg arg0, UArg arg1)
818     uint32_t port = (uint32_t) arg0;
819 #ifdef EMAC_TEST_APP_ICSSG
820     uint32_t mgmtRings =0x7;
821     uint32_t pktRings =0x1ff;
822     uint32_t txRings = 0xf;
823 #else
824     uint32_t mgmtRings =0x0;
825     uint32_t pktRings =0x1;
826     uint32_t txRings = 0x0;
827 #endif
828     linkStatus = 1;
829     while(initComplete == 0)
830     {
831         Task_sleep(1);
832     }
834     UART_printf("polling all pkts on port: %d\n", port);
835     while(1)
836     {
837         if (pollModeEnabled == 1)
838             emac_poll_ctrl(port, pktRings,mgmtRings,txRings);
839         else
840             emac_poll_ctrl(port, 0,EMAC_POLL_RX_MGMT_RING2,txRings);
841         Task_sleep(2);
842     }
845 int32_t emac_send_fail = 0;
848 int32_t app_test_send(uint32_t pNum, uint8_t* pPkt, uint32_t pktChannel, uint32_t pktSize)
850     uint32_t i;
851     static uint32_t pkt_send_count =0;
852     EMAC_DRV_ERR_E sentRetVal;
854     gFail_count = 0;
855     for (i = 0; i < APP_TEST_PKT_SEND_COUNT/2; i++)
856     {
858         EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(pNum, pktSize);
859         if (p_pkt_desc == NULL)
860         {
861             UART_printf("app_test_send: app alloc pkt failed\n");
862             while(1);
863         }
864         memcpy (p_pkt_desc->pDataBuffer, pPkt, pktSize);
865         p_pkt_desc->AppPrivate = (uintptr_t)p_pkt_desc;
866         /* only enable TX timestamp when in poll mode of operation, currently not support for SWITCH use case */
867         if (pollModeEnabled)
868         {
869             if ((pNum != EMAC_CPSW_PORT_NUM))
870             {
871                 p_pkt_desc->Flags = EMAC_PKT_FLAG_TX_TS_REQ;
872                 p_pkt_desc->TxtimestampId = pNum + i;
873                 timestamp_received = 0;
874             }
875         }
876         p_pkt_desc->TxPktTc = i % 8;
877         p_pkt_desc->ValidLen     = pktSize;
878         p_pkt_desc->DataOffset   = 0;
879         p_pkt_desc->PktLength    = pktSize;
880         p_pkt_desc->PktFrags     = 1;
881         p_pkt_desc->pNext = NULL;
882         p_pkt_desc->pPrev = NULL;
883         p_pkt_desc->PktChannel     = pktChannel;
884         p_pkt_desc->PktLength      = pktSize;
885         if (pkt_send_count == 0)
886             Task_sleep (2000);
887         sentRetVal = emac_send(pNum, p_pkt_desc);
888         if(sentRetVal != EMAC_DRV_RESULT_OK)
889         {
890             UART_printf("app_test_send: emac send on port failed with status: : %d: retVal %d, pkt_count: %d\n", pNum, sentRetVal, i+1);
891             app_free_pkt(pNum,p_pkt_desc);
892             emac_send_fail++;
893         }
894         
895 #if !defined(EMAC_BENCHMARK)
896     uint32_t timeout_count = 100;
897     while(((pkt_received == 0) || (timestamp_received == 0)) && (timeout_count-- > 0))
898     {
899         Task_sleep(10);
900     }
901     if (timeout_count == 0)
902     {
903         UART_printf ("app_test_send: receive packet failed with timeout :%d\n", pkt_send_count);
904     }
905 #endif
907         pkt_received = 0;
908         pkt_send_count++;
909         
910     }
911     return gFail_count;
914 void app_test_pkt_clone(void)
916     int32_t status;
917     testPktClone = 1;
918     app_test_id++;
919     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
920     UART_printf("EMAC_UT_%d begin: app_test_pkt_clone\n", app_test_id);
921     status = app_test_send_receive(portNum, endPort,0);
922     if(status == 0)
923         UART_printf("EMAC_UT_%d begin: app_test_pkt_clone passed\n", app_test_id);
924     testPktClone = 0;
927 void app_test_port_mac(void)
929     int32_t status;
930     Task_sleep(500);
931     app_test_id++;
932     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
933     UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC\n", app_test_id);
934     status = app_test_send_receive(portNum, endPort,0);
935     if(status == 0)
936         UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC passed\n", app_test_id);
938     app_test_id++;
939     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
940     UART_printf("EMAC_UT_%d begin: sending BC packet\n", app_test_id);
941     status = app_test_send_receive(portNum, endPort,0);
942     if(status == 0)
943         UART_printf("EMAC_UT_%d begin: sending BC packet passed\n", app_test_id);
945 void app_test_interrrupt_mode(void)
947     app_test_id++;
948     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
949     UART_printf("EMAC_UT_%d begin test interrupt mode\n", app_test_id);
950     app_test_send_receive(portNum, endPort,0);
951     UART_printf("EMAC_UT_%d begin test interrupt mode passed\n", app_test_id);
954 void app_test_tx_chans(void)
956     app_test_id++;
957     uint32_t pNum;
958     uint32_t txChannel;
959     UART_printf("EMAC_UT_%d begin test_multiple tx chans mode\n", app_test_id);
960     for (pNum = portNum; pNum  <= endPort; pNum++)
961     {
962         if (!port_en[pNum])
963             continue;
965         for (txChannel = 0; txChannel < 4;txChannel++)
966         {
967             app_test_send(pNum, pTestPkt, txChannel, APP_TEST_PKT_SIZE);
968         }
969     }
971     UART_printf("EMAC_UT_%d end test_multiple tx chans mode\n", app_test_id);
975 void app_test_poll_mode(void)
977     pollModeEnabled = 1;
978     app_test_id++;
979     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
980     UART_printf("EMAC_UT_%d begin test poll mode\n", app_test_id);
981     app_test_send_receive(portNum, endPort,0);
982     UART_printf("EMAC_UT_%d begin test poll mode passed\n", app_test_id);
985 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult)
987     uint32_t pNum;
988     int32_t status = 0;
989     for (pNum = startP; pNum  <= endP; pNum++)
990     {
991         if (!port_en[pNum])
992             continue;
994         UART_printf("app_test_send_receive: testing port: %d\n", pNum);
995         status = app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
997         if ((pNum == endPort) && (displayResult == 1))
998         {
999             UART_printf("All tests have passed\n");
1000         }
1001     }
1002     return status;
1005 #ifdef EMAC_TEST_APP_ICSSG
1006 #define TX_BUFF_POOL_SIZE 0X1800u
1007 #define TX_BUFF_POOL_TOTAL_DUAL_MAC (TX_BUFF_POOL_SIZE + 0x80) * 8U /* //50176 per PORT, total of 100352 */
1008 void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1010     EMAC_FW_APP_CONFIG *pFwAppCfg;
1011     emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1012     if ((port_num % 2) == 0)
1013     {
1014         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][0]);
1015     }
1016     else
1017     {
1018         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][TX_BUFF_POOL_TOTAL_DUAL_MAC]);
1019     }
1020     pFwAppCfg->txPortQueueHighAddr = 0;
1022     emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1024     /* Need to update the emac configuraiton with  function required by the driver to get the FW configuration to write to shared mem */
1025     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1030 void app_test_setup_fw_dualmac_pg2(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1032     uint32_t i;
1033     EMAC_FW_APP_CONFIG *pFwAppCfg;
1035     emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1036     pFwAppCfg->bufferPoolLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][0]);
1037     pFwAppCfg->bufferPoolHighAddr = 0;
1038     pFwAppCfg->numBufferPool = EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2;
1040     for(i = 0; i < EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2; i++)
1041     {
1042         pFwAppCfg->bufferPoolSize[i] = EMAC_ICSSG_BUFFER_POOL_SIZE_PG2;
1043     }
1045     emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1046     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1048 #endif
1050 void app_test_trace_cb(uint8_t traceLevel, const char* traceString, ...)
1052     if (traceLevel <= UTIL_TRACE_LEVEL_ERR)
1053     {
1054         System_flush();
1055         VaList arg_ptr;
1056         /* print the format string */
1057         va_start(arg_ptr, traceString);
1058         System_vprintf(traceString, arg_ptr);
1059         va_end(arg_ptr);
1060         /* append newline */
1061         System_printf("\n");
1062         System_flush();
1063     }
1066 int32_t app_test_emac_open(uint32_t mode)
1068     EMAC_socGetInitCfg(0, &emac_cfg);
1069     int32_t chanNum = 0;
1070     int32_t subChanNum = 0;
1071     uint32_t pNum;
1072     EMAC_MAC_ADDR_T macTest;
1073     app_test_id++;
1074     UART_printf("EMAC_UT_%d begin, test emac open\n", app_test_id);
1076 #ifdef EMAC_TEST_APP_ICSSG
1077     for (pNum = portNum; pNum <= endPort; pNum++)
1078     {
1079         if (!port_en[pNum])
1080             continue;
1081         app_test_task_disable_pruicss(pNum);
1082     }
1083 #endif
1085     for (pNum = portNum; pNum <= endPort; pNum++)
1086     {
1087         if (!port_en[pNum])
1088             continue;
1089 #if defined(EMAC_TEST_APP_WITHOUT_DDR) || defined(EMAC_BENCHMARK)
1090     emac_cfg.portCfg[pNum].nTxChans = 1U;
1091     emac_cfg.portCfg[pNum].rxChannel.nsubChan = 1U;
1092     emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan = EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT;
1093     emac_cfg.portCfg[pNum].rxChannel2CfgOverPSI.nsubChan = 0;
1094 #endif
1095         for (chanNum = 0; chanNum < emac_cfg.portCfg[pNum].nTxChans; chanNum++)
1096         {
1097             emac_cfg.portCfg[pNum].txChannel[chanNum].chHandle = (void *)&gUdmaTxChObj[pNum][chanNum];
1098             emac_cfg.portCfg[pNum].txChannel[chanNum].freeRingMem= (void*)&gTxRingMem[pNum][chanNum][0];
1099             emac_cfg.portCfg[pNum].txChannel[chanNum].compRingMem= (void*)&gTxCompRingMem[pNum][chanNum][0];
1100             emac_cfg.portCfg[pNum].txChannel[chanNum].hPdMem = (void*)&gUdmapDescRamTx[pNum][chanNum][0];
1101         }
1102         emac_cfg.portCfg[pNum].rxChannel.chHandle = (void *)&gUdmaRxChObj[pNum];
1103         emac_cfg.portCfg[pNum].rxChannel.flowHandle= (void *)&gUdmaFlowHnd[pNum];
1104         /* each subChan is a flow which is required 1 ring pair, subChanNum 0 is used for default flow*/
1105         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannel.nsubChan; subChanNum++)
1106         {
1107             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMem[pNum][subChanNum][0];
1108             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHnd[pNum][subChanNum];
1109             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMem[pNum][subChanNum][0];
1110             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHnd[pNum][subChanNum];
1111             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRx[pNum][subChanNum][0];
1112             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].eventHandle = (void *)&gUdmaRxCqEventObj[pNum][subChanNum];
1113         }
1115         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.chHandle = (void *)&gUdmaRxMgmtPsiChObj[pNum];
1116         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.flowHandle= (void *)&gUdmaFlowHndCfgPsi[pNum];
1117         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan; subChanNum++)
1118         {
1119             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMemCfgPsi[pNum][subChanNum][0];
1120             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHndCfgPsi[pNum][subChanNum];
1121             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMemCfgPsi[pNum][subChanNum][0];
1122             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHndCfgPsi[pNum][subChanNum];
1123             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRxMgmtPsi[pNum][subChanNum][0];
1124             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].eventHandle = (void *)&gUdmaRxMgmtPsiCqEventObj[pNum][subChanNum];
1125         }
1126     }
1128     for (pNum = portNum; pNum <= endPort; pNum++)
1129     {
1130         if (!port_en[pNum])
1131             continue;
1132         if (pNum != EMAC_PORT_CPSW)
1133         {
1135 #ifdef EMAC_TEST_APP_ICSSG
1136             if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1137             {
1138                 app_test_setup_fw_dualmac(pNum, &emac_cfg);
1139             }
1140             else
1141             {
1142                 app_test_setup_fw_dualmac_pg2(pNum, &emac_cfg);
1143             }
1144 #endif
1145         }
1146         EMAC_socSetInitCfg(0, &emac_cfg);
1147         EMAC_socGetInitCfg(0, &emac_cfg);
1149         open_cfg.hwAttrs = (void*)&emac_cfg;
1150         open_cfg.alloc_pkt_cb = app_alloc_pkt;
1151         open_cfg.free_pkt_cb = app_free_pkt;
1152         open_cfg.rx_pkt_cb = app_test_rx_pkt_cb;
1153         open_cfg.tx_ts_cb = app_test_ts_response_cb;
1154         open_cfg.drv_trace_cb = NULL;
1155         open_cfg.rx_mgmt_response_cb = app_test_rx_mgmt_response_cb;
1156         open_cfg.loop_back = 0U;
1157         /* Only need to enbale loopback for CPSW test application and when not doing benchmark testing */
1158 #ifndef EMAC_BENCHMARK
1159         if (pNum == EMAC_PORT_CPSW)
1160         {
1161             open_cfg.loop_back = 1U;
1162         }
1163         open_cfg.num_of_rx_pkt_desc = 8U;
1164         open_cfg.num_of_tx_pkt_desc = 8U;
1165 #else
1166         open_cfg.num_of_rx_pkt_desc = 128U;
1167         open_cfg.num_of_tx_pkt_desc = 128U;
1168 #endif
1169         open_cfg.master_core_flag = 1;
1170         open_cfg.max_pkt_size = APP_EMAC_MAX_PKT_SIZE;
1171         open_cfg.mdio_flag = 1;
1172         open_cfg.num_of_chans = 1;
1173         open_cfg.udmaHandle = (void*)gDrvHandle;
1175         macTest.addr[0] = 0x48;
1176         macTest.addr[1] = 0x93;
1177         macTest.addr[2] = 0xfe;
1178         macTest.addr[3] = 0xfa;
1179         macTest.addr[4] = 0x18;
1180         macTest.addr[5] = 0x44;
1182         open_cfg.p_chan_mac_addr = &chan_cfg[0];
1183         /* Set the channel configuration */
1184         chan_cfg[0].chan_num = 0;
1185         chan_cfg[0].num_of_mac_addrs = 1;
1186         chan_cfg[0].p_mac_addr = & macTest;
1187         open_cfg.mode_of_operation = mode;
1189         if (emac_open(pNum, &open_cfg) == EMAC_DRV_RESULT_OK)
1190         {
1191             UART_printf("main: emac_open sucess for port %d\n", pNum);
1192 #ifdef EMAC_TEST_APP_ICSSG
1193             app_test_task_init_pruicss(pNum);
1194 #endif
1195         }
1196         else
1197         {
1198             UART_printf("main: emac_open failure for port: %d\n",pNum);
1199             return -1;
1200         }
1202     }
1203     UART_printf("EMAC_UT_%d end, test emac open passed\n", app_test_id);
1205     return 0;
1208 int32_t  app_test_emac_close(void)
1210     app_test_id++;
1211     UART_printf("EMAC_UT_%d begin, test emac close\n", app_test_id);
1213     uint32_t pNum;
1214     for (pNum = portNum; pNum  <= endPort; pNum++)
1215     {
1216         if (!port_en[pNum])
1217             continue;
1218         if (emac_close(pNum) == EMAC_DRV_RESULT_OK)
1219         {
1220             UART_printf("app_test_emac_close: emac close for port %d success\n", pNum);
1221         }
1222         else
1223         {
1224             UART_printf("app_test_emac_close: emac close for port %d failed\n", pNum);
1225             return -1;
1226         }
1227     }
1228     UART_printf("EMAC_UT_%d end, test emac close\n", app_test_id);
1229     return 0;
1233 void app_test_config_promiscous_mode(uint32_t enable)
1235     uint32_t pNum;
1236     uint32_t promisEnableFlag = 0;
1237     EMAC_IOCTL_PARAMS params;
1239     if (enable == 1)
1240         promisEnableFlag = 1;
1241     params.ioctlVal = (void*)(&promisEnableFlag);
1243     for (pNum =portNum; pNum  <= endPort; pNum++)
1244     {
1245         if ((!port_en[pNum]) || (pNum == 6))
1246             continue;
1247         emac_ioctl(pNum,EMAC_IOCTL_PROMISCOUS_MODE_CTRL,(void*)(&params));
1248     }
1252 void  app_test_promiscous_mode(void)
1254     app_test_id++;
1255     UART_printf("EMAC_UT_%d begin test promiscous mode\n", app_test_id);
1257     pTestPkt = (uint8_t*)(&app_test_mc_pkt[0]);
1258     app_test_send_receive(portNum, endPort, 0);
1259     UART_printf("app_test_promiscous_mode with MC pkt success\n");
1260     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1261     app_test_send_receive(portNum, endPort, 0);
1262     UART_printf("app_test_promiscous_mode with BC pkt success\n");
1264     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1265     app_test_send_receive(portNum, endPort, 0);
1266     UART_printf("app_test_promiscous_mode with UC  pkt success\n");
1268     UART_printf("EMAC_UT_%d test poll promiscous passed\n", app_test_id);
1271 void emac_test_get_icssg_stats(void)
1273     uint32_t pNum;
1274     EMAC_STATISTICS_ICSSG_T stats;
1275     app_test_id++;
1277     UART_printf("EMAC_UT_%d begin collecting icssg stats\n", app_test_id);
1278     for (pNum = portNum; pNum  <= endPort; pNum++)
1279     {
1280         if (!port_en[pNum])
1281             continue;
1282         memset(&stats, 0, sizeof(EMAC_STATISTICS_ICSSG_T));
1283         if (emac_get_statistics_icssg(pNum, &stats, 0) == EMAC_DRV_RESULT_OK)
1284         {
1285             UART_printf("port:%d: rx packets:          %d, tx packets:        %d\n", pNum, stats.RxGoodFrames, stats.TXGoodFrame);
1286         }
1287         else
1288         {
1289             UART_printf("emac_test_get_icssg_stats: emac_get_statistics_icssg for port %d failed\n", pNum);
1290             while(1);
1291         }
1292     }
1293     UART_printf("EMAC_UT_%d  collecting icssg stats passed\n", app_test_id);
1296 void emac_test_get_cpsw_stats(void)
1298     EMAC_STATISTICS_T stats;
1299     memset(&stats, 0, sizeof(EMAC_STATISTICS_T));
1300     if (!port_en[EMAC_PORT_CPSW])
1301         return;
1302     app_test_id++;
1304     UART_printf("EMAC_UT_%d begin collecting cpsw stats\n", app_test_id);
1305     if (emac_get_statistics(endPort, &stats) == EMAC_DRV_RESULT_OK)
1306     {
1307         UART_printf("port: %d: rx packets: %d, tx packets: %d\n", endPort, stats.RxGoodFrames, stats.TxGoodFrames);
1308     }
1309     else
1310     {
1311         UART_printf("emac_test_get_cpsw_stats: emac_get_statistics for port %d failed\n", endPort);
1312         while(1);
1313     }
1314     UART_printf("EMAC_UT_%d  collecting cpsw stats passed\n", app_test_id);
1318 void app_test_udma_init(void)
1320     int32_t         retVal = UDMA_SOK;
1321     Udma_InitPrms   initPrms;
1322     uint32_t        instId;
1324 #if defined (SOC_AM65XX)
1325 #if defined (EMAC_TEST_APP_CPSW)
1326     /* if A53 and pg 1.0 use mcu navss due to hw errata*/
1327 #if defined (BUILD_MPU1_0)
1328     if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1329     {
1330         instId = UDMA_INST_ID_MCU_0;
1331     }
1332     else
1333     {
1334         instId = UDMA_INST_ID_MAIN_0;
1335     }
1336 #else
1337     instId = UDMA_INST_ID_MCU_0;
1338 #endif
1339 #else
1340     /* icssg use case */
1341     instId = UDMA_INST_ID_MAIN_0;
1342 #endif
1343 #endif
1345 #if defined (SOC_J721E)
1346 #if defined (EMAC_TEST_APP_CPSW)
1347 #if defined (BUILD_MPU1_0)
1348     instId = UDMA_INST_ID_MAIN_0;
1349 #else
1350     instId = UDMA_INST_ID_MCU_0;
1351 #endif
1352 #else
1353     /* icssg use case */
1354     instId = UDMA_INST_ID_MAIN_0;
1355 #endif
1356 #endif
1358     UdmaInitPrms_init(instId, &initPrms);
1360     initPrms.rmInitPrms.numIrIntr = EMAC_MAX_PORTS*8;
1361     initPrms.rmInitPrms.numRxCh = EMAC_MAX_PORTS*4;
1362     initPrms.rmInitPrms.numTxCh= EMAC_MAX_PORTS*4;
1364     initPrms.rmInitPrms.startFreeFlow = 0;
1365     initPrms.rmInitPrms.numFreeFlow = 120;
1367     initPrms.rmInitPrms.startFreeRing= 2;
1368     initPrms.rmInitPrms.numFreeRing = 300;
1370     /* UDMA driver init */
1371     retVal = Udma_init(&gUdmaDrvObj, &initPrms);
1372     if(UDMA_SOK == retVal)
1373     {
1374         gDrvHandle = &gUdmaDrvObj;
1375     }
1378 void app_test_set_port_state_ctrl(uint32_t startP, uint32_t endP)
1380     EMAC_DRV_ERR_E retVal;
1381     EMAC_IOCTL_PARAMS params;
1382     uint32_t pNum;
1384     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1385     {
1386         for (pNum = startP; pNum  <= endP; pNum++)
1387         {
1388             if (!port_en[pNum])
1389                 continue;
1390             params.subCommand = EMAC_IOCTL_PORT_STATE_FORWARD;
1391             params.seqNumber = gAppTestSequenceNumber++;
1392             retVal = emac_ioctl(pNum, EMAC_IOCTL_PORT_STATE_CTRL, &params);
1394             if(retVal != EMAC_DRV_RESULT_IOCTL_IN_PROGRESS)
1395             {
1396                UART_printf("app_test_set_port_state_ctrl:port_num: %d: failed with code %d\n", pNum, retVal);
1397                while (1);
1398             }
1399             else
1400             {
1401                 app_test_wait_mgmt_resp(1000);
1402             }
1403         }
1404     }
1407 void app_test_check_port_link(uint32_t startP, uint32_t endP)
1409     uint32_t pNum;
1410     EMAC_LINK_INFO_T linkInfo;
1411     for (pNum = startP; pNum  <= endP; pNum++)
1412     {
1413         if (!port_en[pNum])
1414             continue;
1415         memset(&linkInfo, 0, sizeof(EMAC_LINK_INFO_T));
1416         do
1417         {
1418             emac_poll(pNum, &linkInfo);
1419             Osal_delay(100);
1420             UART_printf("Link for port %d is DOWN\n", pNum);
1421         } while(linkInfo.link_status == EMAC_LINKSTATUS_NOLINK);
1422         UART_printf("Link for port %d is now UP\n", pNum);
1423     }
1426 #ifdef EMAC_BENCHMARK
1427 void app_test_task_benchmark(UArg arg0, UArg arg1)
1429     Board_STATUS boardInitStatus =0;
1430 #ifdef EMAC_TEST_APP_ICSSG
1431     PRUICSS_Config *prussCfg;
1432 #endif
1434 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1435     Task_sleep(5000);
1436 #endif
1437     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK  | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1439     boardInitStatus = Board_init(cfg);
1440     if (boardInitStatus !=BOARD_SOK)
1441     {
1442         UART_printf("Board_init failure\n");
1443         while(1);
1444     }
1445     UART_printf("Board_init success benchmark\n");
1447     app_init();
1449 #ifdef EMAC_TEST_APP_ICSSG
1450     PRUICSS_socGetInitCfg(&prussCfg);
1451     prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1452     prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1453     if ((prussHandle[0] == NULL) || ((prussHandle[1] == NULL))
1454     {
1455        UART_printf("PRUICSS_create failure\n");
1456         while(1);
1457     }
1458 #if defined(SOC_AM65XX)
1459     prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1460     if (prussHandle[2] == NULL)
1461     {
1462        UART_printf("PRUICSS_create failure\n");
1463        while(1);
1464     }
1466 #endif
1467 #endif
1469     app_test_udma_init();
1471     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1472     {
1473         while(1);
1474     }
1475     app_test_check_port_link(portNum, endPort);
1476     app_test_set_port_state_ctrl(portNum, endPort);
1477     app_test_config_promiscous_mode(1);
1479     initComplete = 1;
1481     UART_printf("app_test_task_benchmark: getting stats\n");
1482     while (1)
1483     {
1484         Task_sleep(1000*60);
1485         emac_test_get_icssg_stats();
1486     }
1488 #endif
1491 #ifdef EMAC_TEST_APP_ICSSG
1493 void test_EMAC_verify_ut_dual_mac_icssg(void)
1495     /* @description:Unit test for ICSSG dual mac use case
1497        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1498                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029,
1499                       PRSDK-7156
1501        @cores: mpu1_0, mcu1_0 */
1502     Board_STATUS boardInitStatus =0;
1503     SemaphoreP_Params emac_app_test_sem_params;
1505 #ifdef EMAC_TEST_APP_ICSSG
1506     PRUICSS_Config *prussCfg;
1507 #endif
1509 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1510     Task_sleep(2000);
1511 #endif
1512     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY | BOARD_INIT_ENETCTRL_ICSS;
1514 #if defined(SOC_J721E)
1515     /* PINMUX config of GESI for ICSSG */
1516     Board_PinmuxConfig_t gesiIcssgPinmux;
1517     Board_pinmuxGetCfg(&gesiIcssgPinmux);
1518     gesiIcssgPinmux.autoCfg = BOARD_PINMUX_CUSTOM;
1519     gesiIcssgPinmux.gesiExp = BOARD_PINMUX_GESI_ICSSG;
1520     Board_pinmuxSetCfg(&gesiIcssgPinmux);
1521 #endif
1522     boardInitStatus = Board_init(cfg);
1523     if (boardInitStatus !=BOARD_SOK)
1524     {
1525         UART_printf("Board_init failure\n");
1526         while(1);
1527     }
1528     UART_printf("Board_init success for UT\n");
1530     gPgVersion = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_JTAGID);
1532     app_init();
1534 #ifdef EMAC_TEST_APP_ICSSG
1535         PRUICSS_socGetInitCfg(&prussCfg);
1536         prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1537         prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1538         if ((prussHandle[0] == NULL) || (prussHandle[1] == NULL))
1539         {
1540            UART_printf("PRUICSS_create failure\n");
1541            while(1);
1542         }
1543 #if defined(SOC_AM65XX)
1544         prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1545         if (prussHandle[2] == NULL)
1546         {
1547            UART_printf("PRUICSS_create failure\n");
1548            while(1);
1549         }
1550 #endif
1551 #endif
1553     EMAC_osalSemParamsInit(&emac_app_test_sem_params);
1554     emac_app_test_sem_params.mode = SemaphoreP_Mode_BINARY;
1555     gAppTestIoctlWaitAckSem =  EMAC_osalCreateBlockingLock(0,&emac_app_test_sem_params);
1557     app_test_udma_init();
1559     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1560     {
1561         pollModeEnabled = 1;
1562         if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1563         {
1564             while(1);
1565         }
1566     }
1567     else
1568     {
1569         if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1570         {
1571             while(1);
1572         }
1573     }
1575     initComplete = 1;
1576     /* Need to poll for link for ICSSG ports as they are port 2 port tests */
1577     /* For standalone CPSW test, we use internal loopback at CPSW-SS */
1578     app_test_check_port_link(portNum, endPort);
1580     app_test_set_port_state_ctrl(portNum, endPort);
1581     /* Test with PORT_MAC address */
1582     app_test_port_mac();
1584     app_test_tx_chans();
1586     app_test_interrrupt_mode();
1588     /* test close -re open sequence */
1589     if(app_test_emac_close() == -1)
1590     {
1591         UART_printf("emac unit test app_test_emac_close failed\n");
1592         while(1);
1593     }
1594     /* re-init the app */
1595     app_init();
1597     /* re-open in polling mode */
1598     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1599     {
1600         while(1);
1601     }
1603     app_test_poll_mode();
1605     app_test_config_promiscous_mode(1);
1606     app_test_promiscous_mode();
1608     emac_test_get_icssg_stats();
1610     UART_printf("All tests have passed\n");
1611 #ifdef UNITY_INCLUDE_CONFIG_H
1612     TEST_PASS();
1613 #endif
1616 #else
1617 void test_EMAC_verify_ut_cpsw(void)
1619     /* @description:Unit test for ICSSG dual mac and CPSW use cases
1621        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1622                       PRSDK-3726, PRSDK-3755, PRSDK-3765, PRSDK-5567
1624        @cores: mpu1_0, mcu1_0 */
1626     Board_STATUS boardInitStatus =0;
1627 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1628         Task_sleep(2000);
1629 #endif
1630         Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ETH_PHY | BOARD_INIT_ENETCTRL_CPSW2G;
1632     boardInitStatus = Board_init(cfg);
1633     if (boardInitStatus !=BOARD_SOK)
1634     {
1635         UART_printf("Board_init failure\n");
1636         while(1);
1637     }
1638     UART_printf("Board_init success for UT\n");
1641     app_init();
1643     app_test_udma_init();
1645     if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1646     {
1647         while(1);
1648     }
1649     initComplete = 1;
1651     /* Test with PORT_MAC address */
1652     app_test_port_mac();
1654     app_test_interrrupt_mode();
1656     /* test close -re open sequence */
1657     if(app_test_emac_close() == -1)
1658     {
1659         UART_printf("emac unit test app_test_emac_close failed\n");
1660         while(1);
1661     }
1662     /* re-init the app */
1663     app_init();
1665     /* re-open in polling mode */
1666     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1667     {
1668         while(1);
1669     }
1671     app_test_poll_mode();
1673     app_test_config_promiscous_mode(1);
1674     app_test_promiscous_mode();
1676     emac_test_get_cpsw_stats();
1678     UART_printf("All tests have passed\n");
1679 #ifdef UNITY_INCLUDE_CONFIG_H
1680     TEST_PASS();
1681 #endif
1684 #endif
1686 #ifdef UNITY_INCLUDE_CONFIG_H
1687 #ifdef EMAC_TEST_APP_ICSSG
1688 void test_Emac_Icssg_TestApp_runner(void)
1690     /* @description: Test runner for EMAC ICSSG tests
1692        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1693                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029
1695        @cores: mpu1_0, mcu1_0 */
1697     UNITY_BEGIN();
1698     RUN_TEST(test_EMAC_verify_ut_dual_mac_icssg);
1699     UNITY_END();
1700     /* Function to print results defined in our unity_config.h file */
1701     print_unityOutputBuffer_usingUARTstdio();
1704 #else
1705 void test_Emac_Cpsw_TestApp_runner(void)
1707     /* @description: Test runner for EMAC CPSW tests
1709        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1710                       PRSDK-3726, PRSDK-3755, PRSDK-3765, PRSDK-5567
1712        @cores: mpu1_0, mcu1_0 */
1714     UNITY_BEGIN();
1715     RUN_TEST(test_EMAC_verify_ut_cpsw);
1716     UNITY_END();
1717     /* Function to print results defined in our unity_config.h file */
1718     print_unityOutputBuffer_usingUARTstdio();
1720 #endif
1721 #endif
1723 void app_test_task_verify_ut_dual_mac_cpsw(UArg arg0, UArg arg1)
1725 #ifdef UNITY_INCLUDE_CONFIG_H
1726 #ifdef EMAC_TEST_APP_ICSSG
1727     test_Emac_Icssg_TestApp_runner();
1728 #else
1729     test_Emac_Cpsw_TestApp_runner();
1730 #endif
1731 #endif
1734 #ifdef EMAC_TEST_APP_ICSSG
1735 /*
1736  *  ======== app_test_task_disable_pruicss========
1737  */
1738 int32_t  app_test_task_disable_pruicss(uint32_t portNum)
1740     PRUICSS_Handle prussDrvHandle;
1741     uint8_t pru_n, rtu_n, txpru_n, slice_n;
1743     if (portNum > EMAC_ICSSG3_PORT1)
1744     {
1745         return -1;
1746     }
1747     prussDrvHandle =prussHandle[portNum >> 1];
1748     slice_n = (portNum & 1);
1749     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1750     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1751     txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1753     if (PRUICSS_pruDisable(prussDrvHandle, pru_n) != 0)
1754         UART_printf("PRUICSS_pruDisable for PRUICCSS_PRU%d failed\n", slice_n);
1756     if (PRUICSS_pruDisable(prussDrvHandle, rtu_n) != 0)
1757         UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1759     /* pg version check: only disable txpru if NOT version PG1.0 */
1760     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1761     {
1762         if (PRUICSS_pruDisable(prussDrvHandle, txpru_n) != 0)
1763             UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1764     }
1766     /* CLEAR SHARED MEM which is used for host/firmware handshake */
1767     PRUICSS_pruInitMemory(prussDrvHandle, PRU_ICSS_SHARED_RAM);
1768     return 0;
1771 /*
1772  *  ======== app_test_task_init_pruicss========
1773  */
1774 int32_t  app_test_task_init_pruicss(uint32_t portNum)
1776     PRUICSS_Handle prussDrvHandle;
1777     uint8_t pru_n, rtu_n, txpru_n, slice_n;
1778     app_test_pru_rtu_fw_t *firmware;
1780     if (portNum > EMAC_ICSSG3_PORT1)
1781     {
1782         return -1;
1783     }
1785     prussDrvHandle =prussHandle[portNum >> 1];
1786     slice_n = (portNum & 1);
1787     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1788     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1789     txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1791     firmware = (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)?firmware_pg1:firmware_pg2;
1793     if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_PRU(slice_n), 0,
1794                                firmware[slice_n].pru, firmware[slice_n].pru_size) == 0)
1795     {
1796          UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_PRU%d failed\n", slice_n);
1797          return -1;
1798     }
1799     if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_RTU(slice_n), 0,
1800                                    firmware[slice_n].rtu, firmware[slice_n].rtu_size) == 0)
1801     {
1802         UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_RTU%d failed\n", slice_n);
1803         return -1;
1804     }
1805     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1806     {
1807         if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_TXPRU(slice_n), 0,
1808                                firmware[slice_n].txpru, firmware[slice_n].txpru_size) == 0)
1809         {
1810             UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_TXPRU%d failed\n", slice_n);
1811             return -1;
1812         }
1813     }
1816     if (PRUICSS_pruEnable(prussDrvHandle, pru_n) != 0)
1817     {
1818         UART_printf("PRUICSS_pruEnable for PRUICCSS_PRU%d failed\n", slice_n);
1819         return -1;
1820     }
1821     if (PRUICSS_pruEnable(prussDrvHandle, rtu_n) != 0)
1822     {
1823         UART_printf("PRUICSS_pruEnable for PRUICCSS_RTU%d failed\n", slice_n);
1824         return -1;
1825     }
1826     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1827     {
1828         if (PRUICSS_pruEnable(prussDrvHandle, txpru_n) != 0)
1829         {
1830             UART_printf("PRUICSS_pruEnable for PRUICCSS_TXPRU%d failed\n", slice_n);
1831             return -1;
1832         }
1833     }
1835     return 0;
1837 #endif
1839 void app_output_log(Char* str, UInt numChar)
1841     if (numChar > 0)
1842     {
1843         UART_printf(str);
1844     }
1849 /*
1850  *  ======== app_test_wait_mgmt_resp ========
1851  */
1852 void app_test_wait_mgmt_resp(uint32_t waitTimeMilliSec)
1854     int32_t retVal = APP_TEST_SUCCESS;
1856     retVal = EMAC_osalPendLock(gAppTestIoctlWaitAckSem, waitTimeMilliSec);
1858     if(SemaphoreP_TIMEOUT == retVal)
1859     {
1860         UART_printf("ERROR: IOCTL management response not received for %u ms, Semaphore_pend timed out! RC: %d\n\r",
1861                     waitTimeMilliSec, retVal);
1862         while (1);
1863     }