PDK-6487: emac: test app updates
[processor-sdk/pdk.git] / packages / ti / drv / emac / test / EmacLoopbackTest / test_utils_k3.c
1 /* =============================================================================
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34 /**
35  *  \file     test_utils_k3.c
36  *
37  *  \brief    This file contains common utility functions used by the emac loopback unit
38  *             test applications.
39  *
40  */
42 #include <string.h>
43 #include <stdio.h>
44 #include <stdint.h>
46 #include <xdc/std.h>
47 #include <xdc/runtime/System.h>
48 #include <xdc/runtime/Memory.h>
49 #include <xdc/runtime/Error.h>
51 #include <ti/sysbios/BIOS.h>
52 #include <ti/sysbios/knl/Task.h>
54 #include <ti/csl/csl_chip.h>
55 #include <ti/csl/cslr_icss.h>
56 /* EMAC Driver Header File. */
57 #include <ti/drv/emac/emac_drv.h>
58 #include <ti/drv/emac/src/emac_osal.h>
59 #include <ti/drv/emac/emac_ioctl.h>
61 #include <ti/drv/emac/src/v5/emac_hwq.h>
63 /* SOC Include Files. */
64 #include <ti/drv/emac/soc/emac_soc_v5.h>
66 /* Test application local header file */
67 #include "ti/drv/emac/test/EmacLoopbackTest/test_loc.h"
69 #include <ti/drv/uart/UART.h>
70 #include <ti/drv/uart/UART_stdio.h>
71 #include <ti/board/board.h>
73 #ifdef SOC_J721E
74 #include <ti/board/src/j721e_evm/include/board_pinmux.h>
75 #include <ti/board/src/j721e_evm/include/board_control.h>
76 #endif
78 #ifdef EMAC_TEST_APP_ICSSG
79 #include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
80 /* PRUSS Driver Header File. */
81 #include <ti/drv/pruss/pruicss.h>
82 #include <ti/drv/pruss/soc/pruicss_v1.h>
83 #endif
86 #ifdef UNITY_INCLUDE_CONFIG_H
87 #include <ti/build/unit-test/Unity/src/unity.h>
88 #include <ti/build/unit-test/config/unity_config.h>
89 #endif
92 extern uint32_t portNum;
93 extern uint32_t endPort;
94 extern int port_en[];
96 #ifdef APP_TEST_ENABLE_POLL_CTRL_TIMER
97 extern SemaphoreP_Handle gAppTestPollCtrlTimerSem;
98 #endif
100 /**********************************************************************
101  ************************** Global Variables **************************
102  **********************************************************************/
103 static uint8_t  gAppTestSequenceNumber  = 1;
104 #ifdef EMAC_TEST_APP_ICSSG
106 #define EMAC_ICSSG_DUAL_MAC_FW_BUFER_POOL_SIZE_PG2 0X14000 // 8 BUFFER POOLS EACH 0X2000 BYTES PLUS 0X4000 BYTES FOR RX Q CONTEXT info
107 #define EMAC_ICSSG_BUFFER_POOL_SIZE_PG2 0x2000u
108 #define EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2 8u
110 #ifdef SOC_J721E
111 uint8_t icss_tx_port_queue[2][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_ocmc_mem")));
112 #else
113 #ifdef EMAC_TEST_APP_WITHOUT_DDR
114 /* DDR less test, can only test with 2 ports due to msmc memory constraints */
115 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
116 #else
117 #ifdef EMAC_BENCHMARK
118 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
119 #else /* test all port for DUAL MAC */
120 uint8_t icss_tx_port_queue[6][EMAC_ICSSG_DUAL_MAC_FW_BUFER_POOL_SIZE_PG2] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
121 #endif
122 #endif
123 #endif
125 PRUICSS_Handle prussHandle[EMAC_MAX_ICSS] = {NULL, NULL, NULL};
126 #endif
128 /* PG1.0 macro check */
129 #define APP_TEST_AM65XX_PG1_0_VERSION (0x0BB5A02FU)
131 /* Macro for test failure status return value. */
132 #define APP_TEST_SUCCESS    0
133 #define APP_TEST_FAILURE    -1
135 /* Maxwell PG version */
136 uint32_t gPgVersion;
139 /* semaphore to sync up ICSSG management request and callback response */
140 static SemaphoreP_Handle gAppTestIoctlWaitAckSem;
143 /* Test will use network firmware to verify packet transmission
144   * and reception between 2 physical ICSSG ports, each ICSSG port needs to be connected
145   * to another ICSSG port via ethernet cable.
147   * NOTE that for CPSW port, test will always test loopback mode of operation
148   * with CPSW sub-system.
149   */
151 #ifdef EMAC_TEST_APP_ICSSG
152 /* EMAC firmware header files */
155 #if defined (SOC_AM65XX)
156 /* PG 1.0 Firmware */
157 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii0_bin.h>      /* PDSPcode */
158 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test0_bin.h>             /* PDSP2code */
159 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii1_bin.h>      /* PDSP3code */
160 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test1_bin.h>             /* PDSP4code */
161 #endif
163 /* PG2.0 firmware */
164 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RX_PRU_SLICE0_bin.h>
165 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RX_PRU_SLICE1_bin.h>
166 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RTU0_SLICE0_bin.h>
167 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/RTU0_SLICE1_bin.h>
168 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/TX_PRU_SLICE0_bin.h>
169 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/TX_PRU_SLICE1_bin.h>
172 typedef struct {
173     const uint32_t *pru;
174     uint32_t pru_size;
175     const uint32_t *rtu;
176     uint32_t rtu_size;
177     const uint32_t *txpru;
178     uint32_t txpru_size;
179 } app_test_pru_rtu_fw_t;
181 app_test_pru_rtu_fw_t firmware_pg1[2] = {
182 #if defined (SOC_AM65XX)
183     { PDSPcode_0, sizeof(PDSPcode_0), PDSP2code_0, sizeof(PDSP2code_0), NULL, 0},
184     { PDSP3code_0, sizeof(PDSP3code_0), PDSP4code_0, sizeof(PDSP4code_0), NULL, 0}
185 #endif
186 };
187 app_test_pru_rtu_fw_t firmware_pg2[2] = {
188     {
189         RX_PRU_SLICE0_b00, sizeof(RX_PRU_SLICE0_b00), RTU0_SLICE0_b00, sizeof(RTU0_SLICE0_b00), TX_PRU_SLICE0_b00, sizeof(TX_PRU_SLICE0_b00)
190     },
191     {
192         RX_PRU_SLICE1_b00, sizeof(RX_PRU_SLICE1_b00), RTU0_SLICE1_b00, sizeof(RTU0_SLICE1_b00), TX_PRU_SLICE1_b00, sizeof(TX_PRU_SLICE1_b00)
193     }
194 };
195 #endif
197 int32_t app_test_task_init_pruicss(uint32_t portNum);
198 int32_t app_test_task_disable_pruicss(uint32_t portNum);
199 void app_test_wait_mgmt_resp(uint32_t waitTimeMilliSec);
201 uint32_t pollModeEnabled = 0;
202 uint32_t initComplete = 0;
203 uint32_t app_test_id = 0;
204 #if defined (EMAC_BENCHMARK)
205 #if defined  (EMAC_TEST_APP_ICSSG)
206 uint32_t app_test_send_port = 4U;
207 uint32_t app_test_recv_port = 4U;
208 #else
209 uint32_t app_test_send_port = 6U;
210 uint32_t app_test_recv_port = 6U;
211 #endif
212 #endif
213 #ifdef _TMS320C6X
214 /* Memory allocated for the packet buffer. This is 128 bytes aligned. */
215 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE];
216 #pragma DATA_ALIGN(app_pkt_buffer, 64)
218 /* Memory allocated for the application control block */
219 #else
220 #ifdef EMAC_TEST_APP_WITHOUT_DDR
221 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64)));
222 #else
223 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64))) __attribute__ ((section (".bss:emac_ddr_mem")));
224 #endif
225 #endif
227 int32_t gFail_count;
229 int32_t testPktClone = 0;
230 #ifndef EMAC_TEST_APP_WITHOUT_DDR
231 #define EMAC_TEST_MAX_CHANS_PER_PORT 4
232 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 9
233 #else
234 #define EMAC_TEST_MAX_CHANS_PER_PORT 1
235 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 3
236 #endif
237 /*
238  * UDMA driver objects
239  */
240 struct Udma_DrvObj      gUdmaDrvObj;
241 struct Udma_ChObj       gUdmaTxChObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT];
242 struct Udma_ChObj       gUdmaRxChObj[EMAC_MAX_PORTS];
243 struct Udma_EventObj    gUdmaRxCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
246 struct Udma_ChObj       gUdmaRxMgmtPsiChObj[EMAC_MAX_PORTS];
247 struct Udma_EventObj    gUdmaRxMgmtPsiCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
249 Udma_DrvHandle          gDrvHandle = NULL;
251 /* Ring parameters*/
252 /*brief Number of ring entries - we can prime this much memcpy operations */
253 #ifdef EMAC_TEST_APP_WITHOUT_DDR
254 #define EMAC_TEST_APP_RING_ENTRIES      (32)
255 #else
256 #define EMAC_TEST_APP_RING_ENTRIES      (128)
257 #endif
258 /* Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
260 #define EMAC_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
261 /* Total ring memory */
263 #define EMAC_TEST_APP_RING_MEM_SIZE     (EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_RING_ENTRY_SIZE)
265 /* UDMA host mode buffer descriptor memory size.    *  Make it multiple of 128 byte alignment */
266 #define EMAC_TEST_APP_DESC_SIZE         (sizeof(CSL_UdmapCppi5HMPD) + (128U - sizeof(CSL_UdmapCppi5HMPD)))
268 /*
269  * UDMA Memories
270  */
271 #ifdef EMAC_TEST_APP_WITHOUT_DDR
272 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
273 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
274 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
275 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
276 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
277 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
278 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
279 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
280 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
281 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
282 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
283 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
284 /* TX/RX ring CPPI descriptor memory */
285 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
286 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
287 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
288 #else
289 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
290                                       __attribute__ ((section (".bss:emac_ddr_mem")));
291 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
292                                       __attribute__ ((section (".bss:emac_ddr_mem")));
293 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
294                                             __attribute__ ((section (".bss:emac_ddr_mem")));
295 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
296                                             __attribute__ ((section (".bss:emac_ddr_mem")));
297 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
298                                         __attribute__ ((section (".bss:emac_ddr_mem")));
299 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
300                                         __attribute__ ((section (".bss:emac_ddr_mem")));
301 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
302                                         __attribute__ ((section (".bss:emac_ddr_mem")));
303 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
304                                       __attribute__ ((section (".bss:emac_ddr_mem")));
305 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
306                                       __attribute__ ((section (".bss:emac_ddr_mem")));
308 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
309                                         __attribute__ ((section (".bss:emac_ddr_mem")));
310 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
311                                          __attribute__ ((section (".bss:emac_ddr_mem")));
312 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
313                                       __attribute__ ((section (".bss:emac_ddr_mem")));
314 /* TX/RX ring CPPI descriptor memory */
315 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
316                                     __attribute__ ((section (".bss:emac_ddr_mem")));
317 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
318                                       __attribute__ ((section (".bss:emac_ddr_mem")));
319 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
320                                   __attribute__ ((section (".bss:emac_ddr_mem")));
322 #endif
326 #ifdef EMAC_TEST_APP_WITHOUT_DDR
327 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
328 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
329 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
330 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
331 #else
332 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
333                                   __attribute__ ((section (".bss:emac_ddr_mem")));
335 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
336                                   __attribute__ ((section (".bss:emac_ddr_mem")));
338 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
339                                   __attribute__ ((section (".bss:emac_ddr_mem")));
341 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
342                                   __attribute__ ((section (".bss:emac_ddr_mem")));
343 #endif
345 uint32_t pkt_rcv_count = 0;
346 static volatile uint32_t pkt_received = 0;
347 static volatile uint32_t timestamp_received = 1;
349 #ifdef UNITY_INCLUDE_CONFIG_H
350 /*
351  *  ======== Unity set up and tear down ========
352  */
353 void setUp(void)
355     /* Do nothing */
358 void tearDown(void)
360     /* Do nothing */
362 #endif
364 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult);
366 /**********************************************************************
367  ****************** Test Configuration Variables **********************
368  **********************************************************************/
371 #define APP_TEST_PKT_SEND_COUNT  16
372 #define APP_TEST_MIN_PKT_SEND_SIZE 60
373 #define APP_TEST_MAX_PKT_SEND_SIZE 1500
375 /* DO NOT CHANGE app_test_uc_pkt UNLESS APP_TEST_PKT_SIZE IS UPDATED */
376 #define APP_TEST_PKT_SIZE       64
377 static uint8_t app_test_uc_pkt[APP_TEST_PKT_SIZE] = {
378     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
379     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
380     0x08, 0x06, 0x00, 0x01,
381     0x08, 0x00, 0x06, 0x04,
382     0x00,0x01,0x01, 0xbb,
383     0xcc, 0xdd, 0xee, 0xff,
384     0xc0, 0xa8, 0x01, 0x16,
385     0x00, 0x00, 0x00, 0x00,
386     0xc0, 0xa8,0x01, 0x02,
387     0x01,0x02,0x03,0x04,
388     0x01,0x02,0x03,0x04,
389     0x01,0x02,0x03,0x04,
390     0x01,0x02,0x03,0x04,
391     0x01,0x02,0x03,0x04,
392     0xfe,0xfe, 0x00, 0x00
393 };
394 static uint8_t app_test_bc_pkt[APP_TEST_PKT_SIZE] = {
395     0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
396     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
397     0x08, 0x06, 0x00, 0x01,
398     0x08, 0x00, 0x06, 0x04,
399     0x00,0x01,0x01, 0xbb,
400     0xcc, 0xdd, 0xee, 0xff,
401     0xc0, 0xa8, 0x01, 0x16,
402     0x00, 0x00, 0x00, 0x00,
403     0xc0, 0xa8,0x01, 0x02,
404     0x01,0x02,0x03,0x04,
405     0x01,0x02,0x03,0x04,
406     0x01,0x02,0x03,0x04,
407     0x01,0x02,0x03,0x04,
408     0x01,0x02,0x03,0x04,
409     0xfe,0xfe, 0x00, 0x00
410 };
412 static uint8_t app_test_mc_pkt[APP_TEST_PKT_SIZE] = {
413     0x01, 0x93, 0x20, 0x21, 0x22, 0x2a,
414     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
415     0x08, 0x06, 0x00, 0x01,
416     0x08, 0x00, 0x06, 0x04,
417     0x00,0x01,0x01, 0xbb,
418     0xcc, 0xdd, 0xee, 0xff,
419     0xc0, 0xa8, 0x01, 0x16,
420     0x00, 0x00, 0x00, 0x00,
421     0xc0, 0xa8,0x01, 0x02,
422     0x01,0x02,0x03,0x04,
423     0x01,0x02,0x03,0x04,
424     0x01,0x02,0x03,0x04,
425     0x01,0x02,0x03,0x04,
426     0x01,0x02,0x03,0x04,
427     0xfe,0xfe, 0x00, 0x00
428 };
430 static uint8_t *pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
432 /**********************************************************************
433  ************************ EMAC TEST FUNCTIONS *************************
434  **********************************************************************/
435 /**
436  *  @b app_queue_pop
437  *  @n
438  *      Dequeues a packet descriptor from an app queue.
439  *
440  *  @param[in]  pq
441  *      Packet queue of type APP_PKT_QUEUE_T .
442  *
443  *  @retval
444  *      EMAC_Pkt popped from the queue.
445  */
446 EMAC_PKT_DESC_T*
447 app_queue_pop
449     uint32_t              port_num,
450     APP_PKT_QUEUE_T*    pq
453     EMAC_PKT_DESC_T*    pPktHdr;
454 #ifndef EMAC_BENCHMARK
455     uintptr_t key;
456 #endif
457     if (!pq->Count)
458     {
459         return 0;
460     }
461 #ifndef EMAC_BENCHMARK
462     key = EMAC_osalHardwareIntDisable();
463 #endif
465     pPktHdr = pq->pHead;
466     if( pPktHdr )
467     {
468         pq->pHead = pPktHdr->pNext;
469         pq->Count--;
470         pPktHdr->pPrev = pPktHdr->pNext = 0;
471     }
472 #ifndef EMAC_BENCHMARK
473     EMAC_osalHardwareIntRestore(key);
474 #endif
476     return( pPktHdr );
479 /**
480  *  @b app_queue_push
481  *  @n
482  *      Enqueues a packet in EMAC_Pkt queue.
483  *
484  *  @param[in]  pq
485  *      Packet queue of type EMAC_PKT_QUEUE_T .
486  *  @param[in]  pPktHdr
487  *      EMAC_PKT_DESC_T type packet to push.
488  *
489  *  @retval
490  *      void
491  */
492 void
493 app_queue_push
495     uint32_t              port_num,
496     APP_PKT_QUEUE_T*    pq,
497     EMAC_PKT_DESC_T*    pPktHdr
500 #ifndef EMAC_BENCHMARK
501     uintptr_t key;
502     key = EMAC_osalHardwareIntDisable();
503 #endif
504     pPktHdr->pNext = 0;
506     if( !pq->pHead )
507     {
508         /* Queue is empty - Initialize it with this one packet */
509         pq->pHead = pPktHdr;
510         pq->pTail = pPktHdr;
511     }
512     else
513     {
514         /* Queue is not empty - Push onto end */
515         pq->pTail->pNext = pPktHdr;
516         pq->pTail        = pPktHdr;
517     }
518     pq->Count++;
519 #ifndef EMAC_BENCHMARK
520     EMAC_osalHardwareIntRestore(key);
521 #endif
524 uint32_t allocCount = 0;
525 uint32_t allocFailed = 0;
526 uint32_t gAppAllocFailure = 0;
528 #ifndef EMAC_TEST_ALLOC_FAIL
529 /**
530  *  @b Description
531  *  @n
532  *      Call back function provided by application for EMAC driver
533  *      to allocate a packet descriptor.
534  *
535  *  @retval
536  *      pointer to the allocated packet descriptor.
537  */
538  EMAC_PKT_DESC_T*
539 app_alloc_pkt
541     uint32_t              port_num,
542     uint32_t              pkt_size
545     EMAC_PKT_DESC_T*    p_pkt_desc = NULL;
546     if (pkt_size <= APP_EMAC_MAX_PKT_SIZE)
547     {
548         /* Get a packet descriptor from the free queue */
549         p_pkt_desc              = app_queue_pop(port_num, &app_mcb.emac_pcb[port_num].freeQueue);
550         if(p_pkt_desc)
551         {
552             p_pkt_desc->AppPrivate  = (uintptr_t)p_pkt_desc;
553             p_pkt_desc->BufferLen   = APP_EMAC_MAX_PKT_SIZE;
554             p_pkt_desc->DataOffset  = 0;
555             p_pkt_desc->pPrev = NULL;
556             p_pkt_desc->pNext = NULL;
557         }
558         else
559             gAppAllocFailure++;
560     }
561     else
562     {
563         UART_printf ("app_alloc_pkt on port %d failed, packet size %d is too big\n", port_num, pkt_size);
564         return NULL;
565     }
566     return p_pkt_desc;
568 #else
569 #endif
571 /**
572  *  @b Description
573  *  @n
574  *      Call back function provided by application for EMAC driver
575  *      to free a packet descriptor.
576  *
577  *  @retval
578  *      None.
579  */
580 void
581 app_free_pkt
583     uint32_t              port_num,
584     EMAC_PKT_DESC_T*    p_pkt_desc
587     /* Free a packet descriptor to the free queue */
588     app_queue_push(port_num, &app_mcb.emac_pcb[port_num].freeQueue,
589                    (EMAC_PKT_DESC_T *)p_pkt_desc->AppPrivate);
594 /**
595 *  @b Description
596 *  @n
597 *      Intialize the application control block, free/rx packet queue.
599 *  @retval
600 *      None.
601 */
602 void
603 app_init(void)
605     uint32_t            i, j;
606     EMAC_PKT_DESC_T*    p_pkt_desc;
607     uint8_t*            pktbuf_ptr;
609     UART_printf ("EMAC loopback test application initialization\n");
611     /* Reset application control block */
612     memset(&app_mcb, 0, sizeof (APP_EMAC_MCB_T));
614 #ifdef _TMS320C6X
615     app_mcb.core_num = CSL_chipReadReg (CSL_CHIP_DNUM);
616 #else
617     app_mcb.core_num = 0;
618 #endif
619     pktbuf_ptr = (uint8_t *) ((uintptr_t) app_pkt_buffer);
620     /* Initialize the free packet queue */
621     for (i=portNum; i <=endPort; i++)
622     {
623         if (!port_en[i])
624             continue;
625 #ifndef EMAC_BENCHMARK
626         for (j=0; j<APP_MAX_PKTS/MAX_NUM_EMAC_PORTS; j++)
627 #else
628         for (j=0; j<(APP_MAX_PKTS); j++)
629 #endif
630         {
631             p_pkt_desc               = &app_mcb.emac_pcb[i].pkt_desc[j];
632             p_pkt_desc->pDataBuffer  = pktbuf_ptr;
633             p_pkt_desc->BufferLen    = APP_EMAC_MAX_PKT_SIZE;
634             app_queue_push( i, &app_mcb.emac_pcb[i].freeQueue, p_pkt_desc );
635             pktbuf_ptr += APP_EMAC_MAX_PKT_SIZE;
636         }
637     }
640 #if defined (EMAC_BENCHMARK)
641 uint32_t app_test_send_fail = 0;
642 uint32_t app_test_alloc_fail = 0;
644 /******************************************************************************
645  * Function: EMAC test loopback packet
646  ******************************************************************************/
647 /**
648  *  @brief  This function is used to loopback the pkt received to sender
649  */
650 void app_test_loopback_pkt(uint32_t portNum, EMAC_PKT_DESC_T* pDesc)
652     EMAC_DRV_ERR_E sentRetVal;
653     uint8_t* temp;
654     EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(portNum, APP_EMAC_MAX_PKT_SIZE);
655     if (p_pkt_desc == NULL)
656     {
657         UART_printf("app_test_loopback_pkt: app alloc pkt failed\n");
658         app_test_alloc_fail++;
659     }
660     else
661     {
662         temp = p_pkt_desc->pDataBuffer; // temp is now buffer
664         p_pkt_desc->pDataBuffer = pDesc->pDataBuffer;
665         pDesc->pDataBuffer = temp;
667         p_pkt_desc->AppPrivate = (uint32_t)p_pkt_desc;
668         p_pkt_desc->ValidLen     = pDesc->PktLength-4;
669         p_pkt_desc->DataOffset   = 0;
670         p_pkt_desc->PktLength    = pDesc->PktLength-4;
671         p_pkt_desc->PktFrags     = 1;
672         p_pkt_desc->pNext = NULL;
673         p_pkt_desc->pPrev = NULL;
674         p_pkt_desc->PktChannel     = 0;
675         p_pkt_desc->PktLength      = pDesc->PktLength-4;
676         sentRetVal = emac_send(portNum, p_pkt_desc);
677         if(sentRetVal != EMAC_DRV_RESULT_OK)
678         {
679             app_test_send_fail++;
680             app_free_pkt(portNum,p_pkt_desc);
681         }
682     }
684 #endif
687 /******************************************************************************
688  * Function: EMAC RX packet call back function
689  ******************************************************************************/
690 /**
691  *  @brief  This function is used to call back the network application when a
692  *          packet is received.
693  */
694 void app_test_rx_pkt_cb(uint32_t port_num, EMAC_PKT_DESC_T* p_desc)
696 #if !defined (EMAC_BENCHMARK)
697     if (memcmp(p_desc->pDataBuffer, pTestPkt, APP_TEST_PKT_SIZE) == 0)
698     {
699         pkt_rcv_count++;
700         if (port_num != EMAC_PORT_CPSW)
701         {
702             UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d, rx timestamp:  0x%x%08x\n",
703                                             port_num,
704                                             p_desc->PktChannel,
705                                             pkt_rcv_count,
706                                             (unsigned int)(p_desc->RxTimeStamp >> 32),
707                                             (unsigned int)(p_desc->RxTimeStamp & 0xFFFFFFFF));
708         }
709         else
710         {
711                     UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d\n",port_num, p_desc->PktChannel, pkt_rcv_count);
712         }
713     }
714     else
715     {
716         UART_printf("app_test_rx_pkt_cb: port %u: ring num %d: packet match failed\n", port_num, p_desc->PktChannel);
717         while(1);
718     }
719     if (p_desc->AppPrivate != 0U)
720     {
721         app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
722     }
723     pkt_received = 1;
724 #else
725     if (p_desc->AppPrivate != 0U)
726     {
727         if (port_num != EMAC_PORT_CPSW)
728         app_test_loopback_pkt(app_test_send_port,p_desc);
729         app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
730         pkt_received = 1;
731     }
732     pkt_rcv_count++;
733 #endif
736 /******************************************************************************
737 * Function: EMAC RX timestamp_response back function
738 ******************************************************************************/
739 /**
740 *  @brief  This function is used to call back the network application when a
741 *          timestamp response packet is receive from ICSSG firmware.
742 */
743 void app_test_ts_response_cb(uint32_t port_num, uint32_t ts_id, uint64_t ts, bool is_valid)
745     UART_printf("app_test_ts_response_cb: port %d: tx timestamp id: 0x%x, tx timestamp: 0x%x%08x is_valid: %d\n",
746                             port_num,
747                             ts_id,
748                             (unsigned int)(ts >> 32),
749                             (unsigned int)(ts& 0xFFFFFFFF),
750                             is_valid);
751     timestamp_received = 1;
754 void app_test_task_poll_pkt (UArg arg0, UArg arg1)
756     uint32_t port = (uint32_t) arg0;
757     while(initComplete == 0)
758     {
759         Task_sleep(1);
760     }
761     UART_printf("polling rx packets on port: %d\n", port);
762     while(1)
763     {
764         if (pollModeEnabled == 0)
765         {
766             emac_poll_pkt(port);
767 #ifndef EMAC_BENCHMARK
768             Task_sleep(5);
769             if (pkt_rcv_count == APP_TEST_PKT_SEND_COUNT)
770                 break;
771 #endif
772         }
773         else
774         {
775             break;
776         }
777     }
779 /**
780 *  @brief  This function is used to call back the network application when a
781 *          config response packet is receive from ICSSG firmware.
782 */
783     void app_test_rx_mgmt_response_cb(uint32_t port_num, EMAC_IOCTL_CMD_RESP_T* pCmdResp)
784     {
785         if (pCmdResp != NULL)
786         {
787             if (pCmdResp->seqNumber == (gAppTestSequenceNumber -1))
788             {
789                 UART_printf("app_test_rx_mgmt_response_cb: port: %d, status: 0x%x, sequence number: 0x%x\n",
790                             port_num, pCmdResp->status, pCmdResp->seqNumber);
791                 if (pCmdResp->respParamsLength)
792                 {
793                     UART_printf("app_test_rx_mgmt_response_cb: port: %d, 0x%x, 0x%x, 0x%x\n",
794                     port_num, pCmdResp->respParams[0],pCmdResp->respParams[1],pCmdResp->respParams[2]);
795                 }
796                 EMAC_osalPostLock(gAppTestIoctlWaitAckSem);
797             }
798             else
799             {
800                 UART_printf("app_test_rx_mgmt_response_cb (incorrect sequence number): port: %d, status: 0x%x, sequence number: 0x%x\n",
801                             port_num, pCmdResp->status, pCmdResp->seqNumber);
802                 if (pCmdResp->respParamsLength)
803                 {
804                     UART_printf("app_test_rx_mgmt_response_cb: port: %d, resp length: 0x%x, 0x%x, 0x%x, 0x%x\n",
805                     port_num,
806                     pCmdResp->respParamsLength,
807                     pCmdResp->respParams[0],
808                     pCmdResp->respParams[1],
809                     pCmdResp->respParams[2]);
810                 }
811                 EMAC_osalPostLock(gAppTestIoctlWaitAckSem);
812             }
813         }
814     }
816 #ifdef APP_TEST_ENABLE_POLL_CTRL_TIMER
817 void app_test_task_poll_ctrl (UArg arg0, UArg arg1)
819     uint32_t pNum = 0;
820 #ifdef EMAC_TEST_APP_ICSSG
821         uint32_t mgmtRings =EMAC_POLL_RX_MGMT_RING2 | EMAC_POLL_RX_MGMT_RING3;
822         uint32_t pktRings =EMAC_POLL_RX_PKT_RING1 | EMAC_POLL_RX_PKT_RING2;
823         uint32_t txRings = EMAC_POLL_TX_COMPLETION_RING_ALL;
824 #else
825         uint32_t mgmtRings =0x0;
826         uint32_t pktRings =EMAC_POLL_RX_PKT_RING1;
827         uint32_t txRings = EMAC_POLL_TX_COMPLETION_RING1;
828 #endif
829     while(initComplete == 0)
830     {
831         Task_sleep(1);
832     }
834     UART_printf("app_test_task_poll_ctrl: timer based polling\n");
835     while(1)
836     {
837         SemaphoreP_pend(gAppTestPollCtrlTimerSem, BIOS_WAIT_FOREVER);
838         
839         for (pNum = portNum; pNum  <= endPort; pNum++)
840         {
841             if (!port_en[pNum])
842                 continue;
843             emac_poll_ctrl (pNum, pktRings, mgmtRings, txRings);
844         }
845     }
847 #else
848 void app_test_task_poll_ctrl (UArg arg0, UArg arg1)
850     uint32_t pNum;
851 #ifdef EMAC_TEST_APP_ICSSG
852     uint32_t mgmtRings =EMAC_POLL_RX_MGMT_RING2 | EMAC_POLL_RX_MGMT_RING3;
853     uint32_t pktRings =EMAC_POLL_RX_PKT_RING1 | EMAC_POLL_RX_PKT_RING2;
854     uint32_t txRings = EMAC_POLL_TX_COMPLETION_RING_ALL;
855 #else
856     uint32_t mgmtRings =0x0;
857     uint32_t pktRings =EMAC_POLL_RX_PKT_RING1;
858     uint32_t txRings = EMAC_POLL_TX_COMPLETION_RING1;
859 #endif
860     while(initComplete == 0)
861     {
862         Task_sleep(1);
863     }
865     UART_printf("app_test_task_poll_ctrl: sleep polling\n");
866     while(1)
867     {
868         for (pNum = portNum; pNum <= endPort; pNum++)
869         {
870             if (!port_en[pNum])
871                 continue;
872             if (pollModeEnabled == 1)
873             {
874                 emac_poll_ctrl(pNum, pktRings,mgmtRings,txRings);
875             }
876             else
877             {
878                 emac_poll_ctrl(pNum, 0,EMAC_POLL_RX_MGMT_RING2,txRings);
879             }
880             Task_sleep(2);
881         }
882     }
885 #endif
887 int32_t emac_send_fail = 0;
890 int32_t app_test_send(uint32_t pNum, uint8_t* pPkt, uint32_t pktChannel, uint32_t pktSize)
892     uint32_t i;
893     static uint32_t pkt_send_count =0;
894     EMAC_DRV_ERR_E sentRetVal;
896     gFail_count = 0;
897     for (i = 0; i < APP_TEST_PKT_SEND_COUNT/2; i++)
898     {
900         EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(pNum, pktSize);
901         if (p_pkt_desc == NULL)
902         {
903             UART_printf("app_test_send: app alloc pkt failed\n");
904             while(1);
905         }
906         memcpy (p_pkt_desc->pDataBuffer, pPkt, pktSize);
907         p_pkt_desc->AppPrivate = (uintptr_t)p_pkt_desc;
908         /* only enable TX timestamp when in poll mode of operation, currently not support for SWITCH use case */
909         if (pollModeEnabled)
910         {
911             if ((pNum != EMAC_CPSW_PORT_NUM))
912             {
913                 p_pkt_desc->Flags = EMAC_PKT_FLAG_TX_TS_REQ;
914                 p_pkt_desc->TxtimestampId = pNum + i;
915                 timestamp_received = 0;
916             }
917         }
918         p_pkt_desc->TxPktTc = i % 8;
919         p_pkt_desc->ValidLen     = pktSize;
920         p_pkt_desc->DataOffset   = 0;
921         p_pkt_desc->PktLength    = pktSize;
922         p_pkt_desc->PktFrags     = 1;
923         p_pkt_desc->pNext = NULL;
924         p_pkt_desc->pPrev = NULL;
925         p_pkt_desc->PktChannel     = pktChannel;
926         p_pkt_desc->PktLength      = pktSize;
927         if (pkt_send_count == 0)
928             Task_sleep (2000);
929         sentRetVal = emac_send(pNum, p_pkt_desc);
930         if(sentRetVal != EMAC_DRV_RESULT_OK)
931         {
932             UART_printf("app_test_send: emac send on port failed with status: : %d: retVal %d, pkt_count: %d\n", pNum, sentRetVal, i+1);
933             app_free_pkt(pNum,p_pkt_desc);
934             emac_send_fail++;
935         }
936         
937 #if !defined(EMAC_BENCHMARK)
938     uint32_t timeout_count = 100;
939     while(((pkt_received == 0) || (timestamp_received == 0)) && (timeout_count-- > 0))
940     {
941         Task_sleep(10);
942     }
943     if (timeout_count == 0)
944     {
945         UART_printf ("app_test_send: receive packet failed with timeout :%d\n", pkt_send_count);
946     }
947 #endif
949         pkt_received = 0;
950         pkt_send_count++;
951         
952     }
953     return gFail_count;
956 void app_test_pkt_clone(void)
958     int32_t status;
959     testPktClone = 1;
960     app_test_id++;
961     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
962     UART_printf("EMAC_UT_%d begin: app_test_pkt_clone\n", app_test_id);
963     status = app_test_send_receive(portNum, endPort,0);
964     if(status == 0)
965         UART_printf("EMAC_UT_%d begin: app_test_pkt_clone passed\n", app_test_id);
966     testPktClone = 0;
969 void app_test_port_mac(void)
971     int32_t status;
972     Task_sleep(500);
973     app_test_id++;
974     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
975     UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC\n", app_test_id);
976     status = app_test_send_receive(portNum, endPort,0);
977     if(status == 0)
978         UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC passed\n", app_test_id);
980     app_test_id++;
981     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
982     UART_printf("EMAC_UT_%d begin: sending BC packet\n", app_test_id);
983     status = app_test_send_receive(portNum, endPort,0);
984     if(status == 0)
985         UART_printf("EMAC_UT_%d begin: sending BC packet passed\n", app_test_id);
987 void app_test_interrrupt_mode(void)
989     app_test_id++;
990     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
991     UART_printf("EMAC_UT_%d begin test interrupt mode\n", app_test_id);
992     app_test_send_receive(portNum, endPort,0);
993     UART_printf("EMAC_UT_%d begin test interrupt mode passed\n", app_test_id);
996 void app_test_tx_chans(void)
998     app_test_id++;
999     uint32_t pNum;
1000     uint32_t txChannel;
1001     UART_printf("EMAC_UT_%d begin test_multiple tx chans mode\n", app_test_id);
1002     for (pNum = portNum; pNum  <= endPort; pNum++)
1003     {
1004         if (!port_en[pNum])
1005             continue;
1007         for (txChannel = 0; txChannel < 4;txChannel++)
1008         {
1009             app_test_send(pNum, pTestPkt, txChannel, APP_TEST_PKT_SIZE);
1010         }
1011     }
1013     UART_printf("EMAC_UT_%d end test_multiple tx chans mode\n", app_test_id);
1017 void app_test_poll_mode(void)
1019     pollModeEnabled = 1;
1020     app_test_id++;
1021     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1022     UART_printf("EMAC_UT_%d begin test poll mode\n", app_test_id);
1023     app_test_send_receive(portNum, endPort,0);
1024     UART_printf("EMAC_UT_%d begin test poll mode passed\n", app_test_id);
1027 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult)
1029     uint32_t pNum;
1030     int32_t status = 0;
1031     for (pNum = startP; pNum  <= endP; pNum++)
1032     {
1033         if (!port_en[pNum])
1034             continue;
1036         UART_printf("app_test_send_receive: testing port: %d\n", pNum);
1037         status = app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1039         if ((pNum == endPort) && (displayResult == 1))
1040         {
1041             UART_printf("All tests have passed\n");
1042         }
1043     }
1044     return status;
1047 #ifdef EMAC_TEST_APP_ICSSG
1048 #define TX_BUFF_POOL_SIZE 0X1800u
1049 #define TX_BUFF_POOL_TOTAL_DUAL_MAC (TX_BUFF_POOL_SIZE + 0x80) * 8U /* //50176 per PORT, total of 100352 */
1050 void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1052     EMAC_FW_APP_CONFIG *pFwAppCfg;
1053     emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1054     if ((port_num % 2) == 0)
1055     {
1056         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][0]);
1057     }
1058     else
1059     {
1060         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][TX_BUFF_POOL_TOTAL_DUAL_MAC]);
1061     }
1062     pFwAppCfg->txPortQueueHighAddr = 0;
1064     emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1066     /* Need to update the emac configuraiton with  function required by the driver to get the FW configuration to write to shared mem */
1067     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1072 void app_test_setup_fw_dualmac_pg2(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1074     uint32_t i;
1075     EMAC_FW_APP_CONFIG *pFwAppCfg;
1077     emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1078     pFwAppCfg->bufferPoolLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num][0]);
1079     pFwAppCfg->bufferPoolHighAddr = 0;
1080     pFwAppCfg->numBufferPool = EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2;
1082     for(i = 0; i < EMAC_ICSSG_MAX_NUM_BUFFER_POOLS_PG2; i++)
1083     {
1084         pFwAppCfg->bufferPoolSize[i] = EMAC_ICSSG_BUFFER_POOL_SIZE_PG2;
1085     }
1087     emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1088     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1090 #endif
1092 void app_test_trace_cb(uint8_t traceLevel, const char* traceString, ...)
1094     if (traceLevel <= UTIL_TRACE_LEVEL_ERR)
1095     {
1096         System_flush();
1097         VaList arg_ptr;
1098         /* print the format string */
1099         va_start(arg_ptr, traceString);
1100         System_vprintf(traceString, arg_ptr);
1101         va_end(arg_ptr);
1102         /* append newline */
1103         System_printf("\n");
1104         System_flush();
1105     }
1108 int32_t app_test_emac_open(uint32_t mode)
1110     EMAC_socGetInitCfg(0, &emac_cfg);
1111     int32_t chanNum = 0;
1112     int32_t subChanNum = 0;
1113     uint32_t pNum;
1114     EMAC_MAC_ADDR_T macTest;
1115     app_test_id++;
1116     UART_printf("EMAC_UT_%d begin, test emac open\n", app_test_id);
1118 #ifdef EMAC_TEST_APP_ICSSG
1119     for (pNum = portNum; pNum <= endPort; pNum++)
1120     {
1121         if (!port_en[pNum])
1122             continue;
1123         app_test_task_disable_pruicss(pNum);
1124     }
1125 #endif
1127     for (pNum = portNum; pNum <= endPort; pNum++)
1128     {
1129         if (!port_en[pNum])
1130             continue;
1131 #if defined(EMAC_TEST_APP_WITHOUT_DDR) || defined(EMAC_BENCHMARK)
1132     emac_cfg.portCfg[pNum].nTxChans = 1U;
1133     emac_cfg.portCfg[pNum].rxChannel.nsubChan = 1U;
1134     emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan = EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT;
1135     emac_cfg.portCfg[pNum].rxChannel2CfgOverPSI.nsubChan = 0;
1136 #endif
1137         for (chanNum = 0; chanNum < emac_cfg.portCfg[pNum].nTxChans; chanNum++)
1138         {
1139             emac_cfg.portCfg[pNum].txChannel[chanNum].chHandle = (void *)&gUdmaTxChObj[pNum][chanNum];
1140             emac_cfg.portCfg[pNum].txChannel[chanNum].freeRingMem= (void*)&gTxRingMem[pNum][chanNum][0];
1141             emac_cfg.portCfg[pNum].txChannel[chanNum].compRingMem= (void*)&gTxCompRingMem[pNum][chanNum][0];
1142             emac_cfg.portCfg[pNum].txChannel[chanNum].hPdMem = (void*)&gUdmapDescRamTx[pNum][chanNum][0];
1143         }
1144         emac_cfg.portCfg[pNum].rxChannel.chHandle = (void *)&gUdmaRxChObj[pNum];
1145         emac_cfg.portCfg[pNum].rxChannel.flowHandle= (void *)&gUdmaFlowHnd[pNum];
1146         /* each subChan is a flow which is required 1 ring pair, subChanNum 0 is used for default flow*/
1147         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannel.nsubChan; subChanNum++)
1148         {
1149             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMem[pNum][subChanNum][0];
1150             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHnd[pNum][subChanNum];
1151             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMem[pNum][subChanNum][0];
1152             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHnd[pNum][subChanNum];
1153             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRx[pNum][subChanNum][0];
1154             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].eventHandle = (void *)&gUdmaRxCqEventObj[pNum][subChanNum];
1155         }
1157         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.chHandle = (void *)&gUdmaRxMgmtPsiChObj[pNum];
1158         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.flowHandle= (void *)&gUdmaFlowHndCfgPsi[pNum];
1159         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan; subChanNum++)
1160         {
1161             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMemCfgPsi[pNum][subChanNum][0];
1162             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHndCfgPsi[pNum][subChanNum];
1163             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMemCfgPsi[pNum][subChanNum][0];
1164             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHndCfgPsi[pNum][subChanNum];
1165             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRxMgmtPsi[pNum][subChanNum][0];
1166             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].eventHandle = (void *)&gUdmaRxMgmtPsiCqEventObj[pNum][subChanNum];
1167         }
1168     }
1170     for (pNum = portNum; pNum <= endPort; pNum++)
1171     {
1172         if (!port_en[pNum])
1173             continue;
1174         if (pNum != EMAC_PORT_CPSW)
1175         {
1177 #ifdef EMAC_TEST_APP_ICSSG
1178             if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1179             {
1180                 app_test_setup_fw_dualmac(pNum, &emac_cfg);
1181             }
1182             else
1183             {
1184                 app_test_setup_fw_dualmac_pg2(pNum, &emac_cfg);
1185             }
1186 #endif
1187         }
1188         EMAC_socSetInitCfg(0, &emac_cfg);
1189         EMAC_socGetInitCfg(0, &emac_cfg);
1191         open_cfg.hwAttrs = (void*)&emac_cfg;
1192         open_cfg.alloc_pkt_cb = app_alloc_pkt;
1193         open_cfg.free_pkt_cb = app_free_pkt;
1194         open_cfg.rx_pkt_cb = app_test_rx_pkt_cb;
1195         open_cfg.tx_ts_cb = app_test_ts_response_cb;
1196         open_cfg.drv_trace_cb = NULL;
1197         open_cfg.rx_mgmt_response_cb = app_test_rx_mgmt_response_cb;
1198         open_cfg.loop_back = 0U;
1199         /* Only need to enbale loopback for CPSW test application and when not doing benchmark testing */
1200 #ifndef EMAC_BENCHMARK
1201         if (pNum == EMAC_PORT_CPSW)
1202         {
1203             open_cfg.loop_back = 1U;
1204         }
1205         open_cfg.num_of_rx_pkt_desc = 8U;
1206         open_cfg.num_of_tx_pkt_desc = 8U;
1207 #else
1208         open_cfg.num_of_rx_pkt_desc = 128U;
1209         open_cfg.num_of_tx_pkt_desc = 128U;
1210 #endif
1211         open_cfg.master_core_flag = 1;
1212         open_cfg.max_pkt_size = APP_EMAC_MAX_PKT_SIZE;
1213         open_cfg.mdio_flag = 1;
1214         open_cfg.num_of_chans = 1;
1215         open_cfg.udmaHandle = (void*)gDrvHandle;
1217         macTest.addr[0] = 0x48;
1218         macTest.addr[1] = 0x93;
1219         macTest.addr[2] = 0xfe;
1220         macTest.addr[3] = 0xfa;
1221         macTest.addr[4] = 0x18;
1222         macTest.addr[5] = 0x44;
1224         open_cfg.p_chan_mac_addr = &chan_cfg[0];
1225         /* Set the channel configuration */
1226         chan_cfg[0].chan_num = 0;
1227         chan_cfg[0].num_of_mac_addrs = 1;
1228         chan_cfg[0].p_mac_addr = & macTest;
1229         open_cfg.mode_of_operation = mode;
1231         if (emac_open(pNum, &open_cfg) == EMAC_DRV_RESULT_OK)
1232         {
1233             UART_printf("main: emac_open sucess for port %d\n", pNum);
1234 #ifdef EMAC_TEST_APP_ICSSG
1235             app_test_task_init_pruicss(pNum);
1236 #endif
1237         }
1238         else
1239         {
1240             UART_printf("main: emac_open failure for port: %d\n",pNum);
1241             return -1;
1242         }
1244     }
1245     UART_printf("EMAC_UT_%d end, test emac open passed\n", app_test_id);
1247     return 0;
1250 int32_t  app_test_emac_close(void)
1252     app_test_id++;
1253     UART_printf("EMAC_UT_%d begin, test emac close\n", app_test_id);
1255     uint32_t pNum;
1256     for (pNum = portNum; pNum  <= endPort; pNum++)
1257     {
1258         if (!port_en[pNum])
1259             continue;
1260         if (emac_close(pNum) == EMAC_DRV_RESULT_OK)
1261         {
1262             UART_printf("app_test_emac_close: emac close for port %d success\n", pNum);
1263         }
1264         else
1265         {
1266             UART_printf("app_test_emac_close: emac close for port %d failed\n", pNum);
1267             return -1;
1268         }
1269     }
1270     UART_printf("EMAC_UT_%d end, test emac close\n", app_test_id);
1271     return 0;
1275 void app_test_config_promiscous_mode(uint32_t enable)
1277     uint32_t pNum;
1278     uint32_t promisEnableFlag = 0;
1279     EMAC_IOCTL_PARAMS params;
1281     if (enable == 1)
1282         promisEnableFlag = 1;
1283     params.ioctlVal = (void*)(&promisEnableFlag);
1285     for (pNum =portNum; pNum  <= endPort; pNum++)
1286     {
1287         if ((!port_en[pNum]) || (pNum == 6))
1288             continue;
1289         emac_ioctl(pNum,EMAC_IOCTL_PROMISCOUS_MODE_CTRL,(void*)(&params));
1290     }
1294 void  app_test_promiscous_mode(void)
1296     app_test_id++;
1297     UART_printf("EMAC_UT_%d begin test promiscous mode\n", app_test_id);
1299     pTestPkt = (uint8_t*)(&app_test_mc_pkt[0]);
1300     app_test_send_receive(portNum, endPort, 0);
1301     UART_printf("app_test_promiscous_mode with MC pkt success\n");
1302     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1303     app_test_send_receive(portNum, endPort, 0);
1304     UART_printf("app_test_promiscous_mode with BC pkt success\n");
1306     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1307     app_test_send_receive(portNum, endPort, 0);
1308     UART_printf("app_test_promiscous_mode with UC  pkt success\n");
1310     UART_printf("EMAC_UT_%d test poll promiscous passed\n", app_test_id);
1313 void emac_test_get_icssg_stats(void)
1315     uint32_t pNum;
1316     EMAC_STATISTICS_ICSSG_T stats;
1317     app_test_id++;
1319     UART_printf("EMAC_UT_%d begin collecting icssg stats\n", app_test_id);
1320     for (pNum = portNum; pNum  <= endPort; pNum++)
1321     {
1322         if (!port_en[pNum])
1323             continue;
1324         memset(&stats, 0, sizeof(EMAC_STATISTICS_ICSSG_T));
1325         if (emac_get_statistics_icssg(pNum, &stats, 0) == EMAC_DRV_RESULT_OK)
1326         {
1327             UART_printf("port:%d: rx packets:          %d, tx packets:        %d\n", pNum, stats.RxGoodFrames, stats.TXGoodFrame);
1328         }
1329         else
1330         {
1331             UART_printf("emac_test_get_icssg_stats: emac_get_statistics_icssg for port %d failed\n", pNum);
1332             while(1);
1333         }
1334     }
1335     UART_printf("EMAC_UT_%d  collecting icssg stats passed\n", app_test_id);
1338 void emac_test_get_cpsw_stats(void)
1340     EMAC_STATISTICS_T stats;
1341     memset(&stats, 0, sizeof(EMAC_STATISTICS_T));
1342     if (!port_en[EMAC_PORT_CPSW])
1343         return;
1344     app_test_id++;
1346     UART_printf("EMAC_UT_%d begin collecting cpsw stats\n", app_test_id);
1347     if (emac_get_statistics(endPort, &stats) == EMAC_DRV_RESULT_OK)
1348     {
1349         UART_printf("port: %d: rx packets: %d, tx packets: %d\n", endPort, stats.RxGoodFrames, stats.TxGoodFrames);
1350     }
1351     else
1352     {
1353         UART_printf("emac_test_get_cpsw_stats: emac_get_statistics for port %d failed\n", endPort);
1354         while(1);
1355     }
1356     UART_printf("EMAC_UT_%d  collecting cpsw stats passed\n", app_test_id);
1360 void app_test_udma_init(void)
1362     int32_t         retVal = UDMA_SOK;
1363     Udma_InitPrms   initPrms;
1364     uint32_t        instId;
1366 #if defined (SOC_AM65XX)
1367 #if defined (EMAC_TEST_APP_CPSW)
1368     /* if A53 and pg 1.0 use mcu navss due to hw errata*/
1369 #if defined (BUILD_MPU1_0)
1370     if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1371     {
1372         instId = UDMA_INST_ID_MCU_0;
1373     }
1374     else
1375     {
1376         instId = UDMA_INST_ID_MAIN_0;
1377     }
1378 #else
1379     instId = UDMA_INST_ID_MCU_0;
1380 #endif
1381 #else
1382     /* icssg use case */
1383     instId = UDMA_INST_ID_MAIN_0;
1384 #endif
1385 #endif
1387 #if defined (SOC_J721E)
1388 #if defined (EMAC_TEST_APP_CPSW)
1389 #if defined (BUILD_MPU1_0)
1390     instId = UDMA_INST_ID_MAIN_0;
1391 #else
1392     instId = UDMA_INST_ID_MCU_0;
1393 #endif
1394 #else
1395     /* icssg use case */
1396     instId = UDMA_INST_ID_MAIN_0;
1397 #endif
1398 #endif
1400     UdmaInitPrms_init(instId, &initPrms);
1402     initPrms.rmInitPrms.numIrIntr = EMAC_MAX_PORTS*8;
1403     initPrms.rmInitPrms.numRxCh = EMAC_MAX_PORTS*4;
1404     initPrms.rmInitPrms.numTxCh= EMAC_MAX_PORTS*4;
1406     initPrms.rmInitPrms.startFreeFlow = 0;
1407     initPrms.rmInitPrms.numFreeFlow = 120;
1409     initPrms.rmInitPrms.startFreeRing= 2;
1410     initPrms.rmInitPrms.numFreeRing = 300;
1412     /* UDMA driver init */
1413     retVal = Udma_init(&gUdmaDrvObj, &initPrms);
1414     if(UDMA_SOK == retVal)
1415     {
1416         gDrvHandle = &gUdmaDrvObj;
1417     }
1420 void app_test_set_port_state_ctrl(uint32_t startP, uint32_t endP)
1422     EMAC_DRV_ERR_E retVal;
1423     EMAC_IOCTL_PARAMS params;
1424     uint32_t pNum;
1426     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1427     {
1428         for (pNum = startP; pNum  <= endP; pNum++)
1429         {
1430             if (!port_en[pNum])
1431                 continue;
1432             params.subCommand = EMAC_IOCTL_PORT_STATE_FORWARD;
1433             params.seqNumber = gAppTestSequenceNumber++;
1434             retVal = emac_ioctl(pNum, EMAC_IOCTL_PORT_STATE_CTRL, &params);
1436             if(retVal != EMAC_DRV_RESULT_IOCTL_IN_PROGRESS)
1437             {
1438                UART_printf("app_test_set_port_state_ctrl:port_num: %d: failed with code %d\n", pNum, retVal);
1439                while (1);
1440             }
1441             else
1442             {
1443                 app_test_wait_mgmt_resp(1000);
1444             }
1445         }
1446     }
1449 void app_test_check_port_link(uint32_t startP, uint32_t endP)
1451     uint32_t pNum;
1452     EMAC_LINK_INFO_T linkInfo;
1453     for (pNum = startP; pNum  <= endP; pNum++)
1454     {
1455         if (!port_en[pNum])
1456             continue;
1457         memset(&linkInfo, 0, sizeof(EMAC_LINK_INFO_T));
1458         do
1459         {
1460             emac_poll(pNum, &linkInfo);
1461             Osal_delay(100);
1462             UART_printf("Link for port %d is DOWN\n", pNum);
1463         } while(linkInfo.link_status == EMAC_LINKSTATUS_NOLINK);
1464         UART_printf("Link for port %d is now UP\n", pNum);
1465     }
1468 #ifdef EMAC_BENCHMARK
1469 void app_test_task_benchmark(UArg arg0, UArg arg1)
1471     Board_STATUS boardInitStatus =0;
1472 #ifdef EMAC_TEST_APP_ICSSG
1473     PRUICSS_Config *prussCfg;
1474 #endif
1476 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1477     Task_sleep(5000);
1478 #endif
1479     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK  | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1481     boardInitStatus = Board_init(cfg);
1482     if (boardInitStatus !=BOARD_SOK)
1483     {
1484         UART_printf("Board_init failure\n");
1485         while(1);
1486     }
1487     UART_printf("Board_init success benchmark\n");
1489     app_init();
1491 #ifdef EMAC_TEST_APP_ICSSG
1492     PRUICSS_socGetInitCfg(&prussCfg);
1493     prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1494     prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1495     if ((prussHandle[0] == NULL) || ((prussHandle[1] == NULL))
1496     {
1497        UART_printf("PRUICSS_create failure\n");
1498         while(1);
1499     }
1500 #if defined(SOC_AM65XX)
1501     prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1502     if (prussHandle[2] == NULL)
1503     {
1504        UART_printf("PRUICSS_create failure\n");
1505        while(1);
1506     }
1508 #endif
1509 #endif
1511     app_test_udma_init();
1513     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1514     {
1515         while(1);
1516     }
1517     app_test_check_port_link(portNum, endPort);
1518     app_test_set_port_state_ctrl(portNum, endPort);
1519     app_test_config_promiscous_mode(1);
1521     initComplete = 1;
1523     UART_printf("app_test_task_benchmark: getting stats\n");
1524     while (1)
1525     {
1526         Task_sleep(1000*60);
1527         emac_test_get_icssg_stats();
1528     }
1530 #endif
1533 #ifdef EMAC_TEST_APP_ICSSG
1535 void test_EMAC_verify_ut_dual_mac_icssg(void)
1537     /* @description:Unit test for ICSSG dual mac use case
1539        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1540                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029,
1541                       PRSDK-7156
1543        @cores: mpu1_0, mcu1_0 */
1544     Board_STATUS boardInitStatus =0;
1545     SemaphoreP_Params emac_app_test_sem_params;
1547 #ifdef EMAC_TEST_APP_ICSSG
1548     PRUICSS_Config *prussCfg;
1549 #endif
1551 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1552     Task_sleep(2000);
1553 #endif
1554     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY | BOARD_INIT_ENETCTRL_ICSS;
1556 #if defined(SOC_J721E)
1557     /* PINMUX config of GESI for ICSSG */
1558     Board_PinmuxConfig_t gesiIcssgPinmux;
1559     Board_pinmuxGetCfg(&gesiIcssgPinmux);
1560     gesiIcssgPinmux.autoCfg = BOARD_PINMUX_CUSTOM;
1561     gesiIcssgPinmux.gesiExp = BOARD_PINMUX_GESI_ICSSG;
1562     Board_pinmuxSetCfg(&gesiIcssgPinmux);
1563 #endif
1564     boardInitStatus = Board_init(cfg);
1565     if (boardInitStatus !=BOARD_SOK)
1566     {
1567         UART_printf("Board_init failure\n");
1568         while(1);
1569     }
1570     UART_printf("Board_init success for UT\n");
1572     gPgVersion = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_JTAGID);
1574     app_init();
1576 #ifdef EMAC_TEST_APP_ICSSG
1577         PRUICSS_socGetInitCfg(&prussCfg);
1578         prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1579         prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1580         if ((prussHandle[0] == NULL) || (prussHandle[1] == NULL))
1581         {
1582            UART_printf("PRUICSS_create failure\n");
1583            while(1);
1584         }
1585 #if defined(SOC_AM65XX)
1586         prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1587         if (prussHandle[2] == NULL)
1588         {
1589            UART_printf("PRUICSS_create failure\n");
1590            while(1);
1591         }
1592 #endif
1593 #endif
1595     EMAC_osalSemParamsInit(&emac_app_test_sem_params);
1596     emac_app_test_sem_params.mode = SemaphoreP_Mode_BINARY;
1597     gAppTestIoctlWaitAckSem =  EMAC_osalCreateBlockingLock(0,&emac_app_test_sem_params);
1599     app_test_udma_init();
1601     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1602     {
1603         pollModeEnabled = 1;
1604         if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1605         {
1606             while(1);
1607         }
1608     }
1609     else
1610     {
1611         if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1612         {
1613             while(1);
1614         }
1615     }
1617     initComplete = 1;
1618     /* Need to poll for link for ICSSG ports as they are port 2 port tests */
1619     /* For standalone CPSW test, we use internal loopback at CPSW-SS */
1620     app_test_check_port_link(portNum, endPort);
1622     app_test_set_port_state_ctrl(portNum, endPort);
1623     /* Test with PORT_MAC address */
1624     app_test_port_mac();
1626     app_test_tx_chans();
1628     app_test_interrrupt_mode();
1630     /* test close -re open sequence */
1631     if(app_test_emac_close() == -1)
1632     {
1633         UART_printf("emac unit test app_test_emac_close failed\n");
1634         while(1);
1635     }
1636     /* re-init the app */
1637     app_init();
1639     /* re-open in polling mode */
1640     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1641     {
1642         while(1);
1643     }
1645     app_test_poll_mode();
1647     app_test_config_promiscous_mode(1);
1648     app_test_promiscous_mode();
1650     emac_test_get_icssg_stats();
1652     UART_printf("All tests have passed\n");
1653 #ifdef UNITY_INCLUDE_CONFIG_H
1654     TEST_PASS();
1655 #endif
1658 #else
1659 void test_EMAC_verify_ut_cpsw(void)
1661     /* @description:Unit test for ICSSG dual mac and CPSW use cases
1663        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1664                       PRSDK-3726, PRSDK-3755, PRSDK-3765, PRSDK-5567
1666        @cores: mpu1_0, mcu1_0 */
1668     Board_STATUS boardInitStatus =0;
1669 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1670         Task_sleep(2000);
1671 #endif
1672         Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ETH_PHY | BOARD_INIT_ENETCTRL_CPSW2G;
1674     boardInitStatus = Board_init(cfg);
1675     if (boardInitStatus !=BOARD_SOK)
1676     {
1677         UART_printf("Board_init failure\n");
1678         while(1);
1679     }
1680     UART_printf("Board_init success for UT\n");
1683     app_init();
1685     app_test_udma_init();
1687     if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1688     {
1689         while(1);
1690     }
1691     initComplete = 1;
1693     /* Test with PORT_MAC address */
1694     app_test_port_mac();
1696     app_test_interrrupt_mode();
1698     /* test close -re open sequence */
1699     if(app_test_emac_close() == -1)
1700     {
1701         UART_printf("emac unit test app_test_emac_close failed\n");
1702         while(1);
1703     }
1704     /* re-init the app */
1705     app_init();
1707     /* re-open in polling mode */
1708     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1709     {
1710         while(1);
1711     }
1713     app_test_poll_mode();
1715     app_test_config_promiscous_mode(1);
1716     app_test_promiscous_mode();
1718     emac_test_get_cpsw_stats();
1720     UART_printf("All tests have passed\n");
1721 #ifdef UNITY_INCLUDE_CONFIG_H
1722     TEST_PASS();
1723 #endif
1726 #endif
1728 #ifdef UNITY_INCLUDE_CONFIG_H
1729 #ifdef EMAC_TEST_APP_ICSSG
1730 void test_Emac_Icssg_TestApp_runner(void)
1732     /* @description: Test runner for EMAC ICSSG tests
1734        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1735                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029
1737        @cores: mpu1_0, mcu1_0 */
1739     UNITY_BEGIN();
1740     RUN_TEST(test_EMAC_verify_ut_dual_mac_icssg);
1741     UNITY_END();
1742     /* Function to print results defined in our unity_config.h file */
1743     print_unityOutputBuffer_usingUARTstdio();
1746 #else
1747 void test_Emac_Cpsw_TestApp_runner(void)
1749     /* @description: Test runner for EMAC CPSW tests
1751        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1752                       PRSDK-3726, PRSDK-3755, PRSDK-3765, PRSDK-5567
1754        @cores: mpu1_0, mcu1_0 */
1756     UNITY_BEGIN();
1757     RUN_TEST(test_EMAC_verify_ut_cpsw);
1758     UNITY_END();
1759     /* Function to print results defined in our unity_config.h file */
1760     print_unityOutputBuffer_usingUARTstdio();
1762 #endif
1763 #endif
1765 void app_test_task_verify_ut_dual_mac_cpsw(UArg arg0, UArg arg1)
1767 #ifdef UNITY_INCLUDE_CONFIG_H
1768 #ifdef EMAC_TEST_APP_ICSSG
1769     test_Emac_Icssg_TestApp_runner();
1770 #else
1771     test_Emac_Cpsw_TestApp_runner();
1772 #endif
1773 #endif
1776 #ifdef EMAC_TEST_APP_ICSSG
1777 /*
1778  *  ======== app_test_task_disable_pruicss========
1779  */
1780 int32_t  app_test_task_disable_pruicss(uint32_t portNum)
1782     PRUICSS_Handle prussDrvHandle;
1783     uint8_t pru_n, rtu_n, txpru_n, slice_n;
1785     if (portNum > EMAC_ICSSG3_PORT1)
1786     {
1787         return -1;
1788     }
1789     prussDrvHandle =prussHandle[portNum >> 1];
1790     slice_n = (portNum & 1);
1791     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1792     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1793     txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1795     if (PRUICSS_pruDisable(prussDrvHandle, pru_n) != 0)
1796         UART_printf("PRUICSS_pruDisable for PRUICCSS_PRU%d failed\n", slice_n);
1798     if (PRUICSS_pruDisable(prussDrvHandle, rtu_n) != 0)
1799         UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1801     /* pg version check: only disable txpru if NOT version PG1.0 */
1802     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1803     {
1804         if (PRUICSS_pruDisable(prussDrvHandle, txpru_n) != 0)
1805             UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1806     }
1808     /* CLEAR SHARED MEM which is used for host/firmware handshake */
1809     PRUICSS_pruInitMemory(prussDrvHandle, PRU_ICSS_SHARED_RAM);
1810     return 0;
1813 /*
1814  *  ======== app_test_task_init_pruicss========
1815  */
1816 int32_t  app_test_task_init_pruicss(uint32_t portNum)
1818     PRUICSS_Handle prussDrvHandle;
1819     uint8_t pru_n, rtu_n, txpru_n, slice_n;
1820     app_test_pru_rtu_fw_t *firmware;
1822     if (portNum > EMAC_ICSSG3_PORT1)
1823     {
1824         return -1;
1825     }
1827     prussDrvHandle =prussHandle[portNum >> 1];
1828     slice_n = (portNum & 1);
1829     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1830     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1831     txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1833     firmware = (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)?firmware_pg1:firmware_pg2;
1835     if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_PRU(slice_n), 0,
1836                                firmware[slice_n].pru, firmware[slice_n].pru_size) == 0)
1837     {
1838          UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_PRU%d failed\n", slice_n);
1839          return -1;
1840     }
1841     if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_RTU(slice_n), 0,
1842                                    firmware[slice_n].rtu, firmware[slice_n].rtu_size) == 0)
1843     {
1844         UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_RTU%d failed\n", slice_n);
1845         return -1;
1846     }
1847     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1848     {
1849         if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_TXPRU(slice_n), 0,
1850                                firmware[slice_n].txpru, firmware[slice_n].txpru_size) == 0)
1851         {
1852             UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_TXPRU%d failed\n", slice_n);
1853             return -1;
1854         }
1855     }
1858     if (PRUICSS_pruEnable(prussDrvHandle, pru_n) != 0)
1859     {
1860         UART_printf("PRUICSS_pruEnable for PRUICCSS_PRU%d failed\n", slice_n);
1861         return -1;
1862     }
1863     if (PRUICSS_pruEnable(prussDrvHandle, rtu_n) != 0)
1864     {
1865         UART_printf("PRUICSS_pruEnable for PRUICCSS_RTU%d failed\n", slice_n);
1866         return -1;
1867     }
1868     if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1869     {
1870         if (PRUICSS_pruEnable(prussDrvHandle, txpru_n) != 0)
1871         {
1872             UART_printf("PRUICSS_pruEnable for PRUICCSS_TXPRU%d failed\n", slice_n);
1873             return -1;
1874         }
1875     }
1877     return 0;
1879 #endif
1881 void app_output_log(Char* str, UInt numChar)
1883     if (numChar > 0)
1884     {
1885         UART_printf(str);
1886     }
1891 /*
1892  *  ======== app_test_wait_mgmt_resp ========
1893  */
1894 void app_test_wait_mgmt_resp(uint32_t waitTimeMilliSec)
1896     int32_t retVal = APP_TEST_SUCCESS;
1898     retVal = EMAC_osalPendLock(gAppTestIoctlWaitAckSem, waitTimeMilliSec);
1900     if(SemaphoreP_TIMEOUT == retVal)
1901     {
1902         UART_printf("ERROR: IOCTL management response not received for %u ms, Semaphore_pend timed out! RC: %d\n\r",
1903                     waitTimeMilliSec, retVal);
1904         while (1);
1905     }