1 /* =============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2018-2020
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file test_utils_k3.c
36 *
37 * \brief This file contains common utility functions used by the emac loopback unit
38 * test applications.
39 *
40 */
42 #include <string.h>
43 #include <stdio.h>
44 #include <stdint.h>
46 #include <xdc/std.h>
47 #include <xdc/runtime/System.h>
48 #include <xdc/runtime/Memory.h>
49 #include <xdc/runtime/Error.h>
51 #include <ti/sysbios/BIOS.h>
52 #include <ti/sysbios/knl/Task.h>
54 #include <ti/csl/csl_chip.h>
55 #include <ti/csl/cslr_icss.h>
56 /* EMAC Driver Header File. */
57 #include <ti/drv/emac/emac_drv.h>
59 #include <ti/drv/emac/src/emac_osal.h>
60 #include <ti/drv/emac/emac_ioctl.h>
61 /* SOC Include Files. */
62 #include <ti/drv/emac/soc/emac_soc_v5.h>
64 /* Test application local header file */
65 #include "ti/drv/emac/test/EmacLoopbackTest/test_loc.h"
67 #include <ti/drv/uart/UART.h>
68 #include <ti/drv/uart/UART_stdio.h>
69 #include <ti/board/board.h>
71 #ifdef SOC_J721E
72 #include <ti/board/src/j721e_evm/include/board_pinmux.h>
73 #include <ti/board/src/j721e_evm/include/board_control.h>
74 #endif
76 #ifdef EMAC_TEST_APP_ICSSG
77 #include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
78 #include <ti/drv/emac/firmware/icss_switch/config/emac_fw_config_switch.h>
79 /* PRUSS Driver Header File. */
80 #include <ti/drv/pruss/pruicss.h>
81 #include <ti/drv/pruss/soc/pruicss_v1.h>
82 #endif
85 #ifdef UNITY_INCLUDE_CONFIG_H
86 #include <ti/build/unit-test/Unity/src/unity.h>
87 #include <ti/build/unit-test/config/unity_config.h>
88 #endif
91 extern uint32_t portNum;
92 extern uint32_t endPort;
93 extern int port_en[];
95 /**********************************************************************
96 ************************** Global Variables **************************
97 **********************************************************************/
99 #ifdef SOC_J721E
100 uint8_t icss_tx_port_queue[2][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_ocmc_mem")));
101 #else
102 #ifdef EMAC_TEST_APP_WITHOUT_DDR
103 /* DDR less test, can only test with 2 ports due to msmc memory constraints */
104 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
105 #else
106 #ifdef EMAC_BENCHMARK
107 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
108 #else /* test all port for DUAL MAC */
109 uint8_t icss_tx_port_queue[3][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
110 #endif
111 #endif
112 #endif
114 uint32_t interposerCardPresent = 0;
116 #ifdef EMAC_TEST_APP_ICSSG
117 PRUICSS_Handle prussHandle[EMAC_MAX_ICSS] = {NULL, NULL, NULL};
118 int hs_index[EMAC_MAX_ICSS * EMAC_MAC_PORTS_PER_ICSS]; //one per icss slice
119 #endif
122 #define APP_TEST_AM65XX_PG1_0_VERSION (0x0BB5A02FU)
124 /* Maxwell PG version */
125 uint32_t gPgVersion;
128 /* Test will use network firmware to verify packet transmission
129 * and reception between 2 physical ICSSG ports, each ICSSG port needs to be connected
130 * to another ICSSG port via ethernet cable.
132 * NOTE that for CPSW port, test will always test loopback mode of operation
133 * with CPSW sub-system.
134 */
136 #ifdef EMAC_TEST_APP_ICSSG
137 /* EMAC firmware header files */
141 /* PG 1.0 Firmware */
142 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii0_bin.h> /* PDSPcode */
143 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test0_bin.h> /* PDSP2code */
144 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii1_bin.h> /* PDSP3code */
145 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test1_bin.h> /* PDSP4code */
148 /* PG2.0 firmware */
149 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/rxl2_rgmii0_bin.h> /* PDSPcode */
150 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/rtu_test0_bin.h> /* PDSP2code */
151 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/rxl2_rgmii1_bin.h> /* PDSP3code */
152 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/rtu_test1_bin.h> /* PDSP4code */
153 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/txl2_rgmii0_bin.h> /* PDSP5code */
154 #include <ti/drv/emac/firmware/icss_dualmac/bin_pg2/txl2_rgmii1_bin.h> /* PDSP6code */
156 typedef struct {
157 const uint32_t *pru;
158 uint32_t pru_size;
159 const uint32_t *rtu;
160 uint32_t rtu_size;
161 const uint32_t *txpru;
162 uint32_t txpru_size;
163 } app_test_pru_rtu_fw_t;
165 app_test_pru_rtu_fw_t firmware_pg1[2] = {
166 { PDSPcode_0, sizeof(PDSPcode_0), PDSP2code_0, sizeof(PDSP2code_0), NULL, 0},
167 { PDSP3code_0, sizeof(PDSP3code_0), PDSP4code_0, sizeof(PDSP4code_0), NULL, 0}
168 };
170 app_test_pru_rtu_fw_t firmware_pg2[2] = {
171 { PDSPcode_0_PG2, sizeof(PDSPcode_0_PG2), PDSP2code_0_PG2, sizeof(PDSP2code_0_PG2), PDSP5code_0_PG2, sizeof(PDSP5code_0_PG2)},
172 { PDSP3code_0_PG2, sizeof(PDSP3code_0_PG2), PDSP4code_0_PG2, sizeof(PDSP4code_0_PG2), PDSP6code_0_PG2, sizeof(PDSP6code_0_PG2)}
173 };
175 #endif
177 int32_t app_test_task_init_pruicss(uint32_t portNum);
178 int32_t app_test_task_disable_pruicss(uint32_t portNum);
183 uint32_t pollModeEnabled = 0;
184 uint32_t linkStatus = 0;
185 uint32_t initComplete = 0;
186 uint32_t app_test_id = 0;
187 #if defined (EMAC_BENCHMARK)
188 #if defined (EMAC_TEST_APP_ICSSG)
189 uint32_t app_test_send_port = 4U;
190 uint32_t app_test_recv_port = 4U;
191 #else
192 uint32_t app_test_send_port = 6U;
193 uint32_t app_test_recv_port = 6U;
194 #endif
195 #endif
196 #ifdef _TMS320C6X
197 /* Memory allocated for the packet buffer. This is 128 bytes aligned. */
198 uint8_t app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE];
199 #pragma DATA_ALIGN(app_pkt_buffer, 64)
201 /* Memory allocated for the application control block */
202 #else
203 #ifdef EMAC_TEST_APP_WITHOUT_DDR
204 uint8_t app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64)));
205 #else
206 uint8_t app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64))) __attribute__ ((section (".bss:emac_ddr_mem")));
207 #endif
208 #endif
210 int32_t gFail_count;
212 int32_t testPktClone = 0;
213 #ifndef EMAC_TEST_APP_WITHOUT_DDR
214 #define EMAC_TEST_MAX_CHANS_PER_PORT 4
215 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 9
216 #else
217 #define EMAC_TEST_MAX_CHANS_PER_PORT 1
218 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 3
219 #endif
220 /*
221 * UDMA driver objects
222 */
223 struct Udma_DrvObj gUdmaDrvObj;
224 struct Udma_ChObj gUdmaTxChObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT];
225 struct Udma_ChObj gUdmaRxChObj[EMAC_MAX_PORTS];
226 struct Udma_EventObj gUdmaRxCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
229 struct Udma_ChObj gUdmaRxMgmtPsiChObj[EMAC_MAX_PORTS];
230 struct Udma_EventObj gUdmaRxMgmtPsiCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
232 Udma_DrvHandle gDrvHandle = NULL;
234 /* Ring parameters*/
235 /*brief Number of ring entries - we can prime this much memcpy operations */
236 #ifdef EMAC_TEST_APP_WITHOUT_DDR
237 #define EMAC_TEST_APP_RING_ENTRIES (32)
238 #else
239 #define EMAC_TEST_APP_RING_ENTRIES (128)
240 #endif
241 /* Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
243 #define EMAC_TEST_APP_RING_ENTRY_SIZE (sizeof(uint64_t))
244 /* Total ring memory */
246 #define EMAC_TEST_APP_RING_MEM_SIZE (EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_RING_ENTRY_SIZE)
248 /* UDMA host mode buffer descriptor memory size. * Make it multiple of 128 byte alignment */
249 #define EMAC_TEST_APP_DESC_SIZE (sizeof(CSL_UdmapCppi5HMPD) + (128U - sizeof(CSL_UdmapCppi5HMPD)))
251 /*
252 * UDMA Memories
253 */
254 #ifdef EMAC_TEST_APP_WITHOUT_DDR
255 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
256 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
257 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
258 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
259 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
260 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
261 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
262 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
263 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
264 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
265 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
266 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
267 /* TX/RX ring CPPI descriptor memory */
268 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
269 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
270 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
271 #else
272 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
273 __attribute__ ((section (".bss:emac_ddr_mem")));
274 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
275 __attribute__ ((section (".bss:emac_ddr_mem")));
276 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
277 __attribute__ ((section (".bss:emac_ddr_mem")));
278 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
279 __attribute__ ((section (".bss:emac_ddr_mem")));
280 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
281 __attribute__ ((section (".bss:emac_ddr_mem")));
282 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
283 __attribute__ ((section (".bss:emac_ddr_mem")));
284 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
285 __attribute__ ((section (".bss:emac_ddr_mem")));
286 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
287 __attribute__ ((section (".bss:emac_ddr_mem")));
288 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
289 __attribute__ ((section (".bss:emac_ddr_mem")));
291 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
292 __attribute__ ((section (".bss:emac_ddr_mem")));
293 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
294 __attribute__ ((section (".bss:emac_ddr_mem")));
295 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
296 __attribute__ ((section (".bss:emac_ddr_mem")));
297 /* TX/RX ring CPPI descriptor memory */
298 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
299 __attribute__ ((section (".bss:emac_ddr_mem")));
300 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
301 __attribute__ ((section (".bss:emac_ddr_mem")));
302 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
303 __attribute__ ((section (".bss:emac_ddr_mem")));
305 #endif
309 #ifdef EMAC_TEST_APP_WITHOUT_DDR
310 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
311 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
312 APP_EMAC_MCB_T app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
313 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
314 #else
315 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
316 __attribute__ ((section (".bss:emac_ddr_mem")));
318 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
319 __attribute__ ((section (".bss:emac_ddr_mem")));
321 APP_EMAC_MCB_T app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
322 __attribute__ ((section (".bss:emac_ddr_mem")));
324 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
325 __attribute__ ((section (".bss:emac_ddr_mem")));
326 #endif
328 uint32_t pkt_rcv_count = 0;
329 static volatile uint32_t pkt_received = 0;
330 static volatile uint32_t timestamp_received = 1;
332 #ifdef UNITY_INCLUDE_CONFIG_H
333 /*
334 * ======== Unity set up and tear down ========
335 */
336 void setUp(void)
337 {
338 /* Do nothing */
339 }
341 void tearDown(void)
342 {
343 /* Do nothing */
344 }
345 #endif
347 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult);
349 /**********************************************************************
350 ****************** Test Configuration Variables **********************
351 **********************************************************************/
354 #define APP_TEST_PKT_SEND_COUNT 16
355 #define APP_TEST_MIN_PKT_SEND_SIZE 60
356 #define APP_TEST_MAX_PKT_SEND_SIZE 1500
358 /* DO NOT CHANGE app_test_uc_pkt UNLESS APP_TEST_PKT_SIZE IS UPDATED */
359 #define APP_TEST_PKT_SIZE 64
360 static uint8_t app_test_uc_pkt[APP_TEST_PKT_SIZE] = {
361 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
362 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
363 0x08, 0x06, 0x00, 0x01,
364 0x08, 0x00, 0x06, 0x04,
365 0x00,0x01,0x01, 0xbb,
366 0xcc, 0xdd, 0xee, 0xff,
367 0xc0, 0xa8, 0x01, 0x16,
368 0x00, 0x00, 0x00, 0x00,
369 0xc0, 0xa8,0x01, 0x02,
370 0x01,0x02,0x03,0x04,
371 0x01,0x02,0x03,0x04,
372 0x01,0x02,0x03,0x04,
373 0x01,0x02,0x03,0x04,
374 0x01,0x02,0x03,0x04,
375 0xfe,0xfe, 0x00, 0x00
376 };
377 static uint8_t app_test_bc_pkt[APP_TEST_PKT_SIZE] = {
378 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
379 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
380 0x08, 0x06, 0x00, 0x01,
381 0x08, 0x00, 0x06, 0x04,
382 0x00,0x01,0x01, 0xbb,
383 0xcc, 0xdd, 0xee, 0xff,
384 0xc0, 0xa8, 0x01, 0x16,
385 0x00, 0x00, 0x00, 0x00,
386 0xc0, 0xa8,0x01, 0x02,
387 0x01,0x02,0x03,0x04,
388 0x01,0x02,0x03,0x04,
389 0x01,0x02,0x03,0x04,
390 0x01,0x02,0x03,0x04,
391 0x01,0x02,0x03,0x04,
392 0xfe,0xfe, 0x00, 0x00
393 };
395 static uint8_t app_test_mc_pkt[APP_TEST_PKT_SIZE] = {
396 0x01, 0x93, 0x20, 0x21, 0x22, 0x2a,
397 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
398 0x08, 0x06, 0x00, 0x01,
399 0x08, 0x00, 0x06, 0x04,
400 0x00,0x01,0x01, 0xbb,
401 0xcc, 0xdd, 0xee, 0xff,
402 0xc0, 0xa8, 0x01, 0x16,
403 0x00, 0x00, 0x00, 0x00,
404 0xc0, 0xa8,0x01, 0x02,
405 0x01,0x02,0x03,0x04,
406 0x01,0x02,0x03,0x04,
407 0x01,0x02,0x03,0x04,
408 0x01,0x02,0x03,0x04,
409 0x01,0x02,0x03,0x04,
410 0xfe,0xfe, 0x00, 0x00
411 };
413 static uint8_t mac1_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x22};
414 static uint8_t app_test_mc1_pkt[APP_TEST_PKT_SIZE] = {
415 0x01, 0x93, 0x20, 0x21, 0x22, 0x22,
416 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
417 0x08, 0x06, 0x00, 0x01,
418 0x08, 0x00, 0x06, 0x04,
419 0x00,0x01,0x01, 0xbb,
420 0xcc, 0xdd, 0xee, 0xff,
421 0xc0, 0xa8, 0x01, 0x16,
422 0x00, 0x00, 0x00, 0x00,
423 0xc0, 0xa8,0x01, 0x02,
424 0x01,0x02,0x03,0x04,
425 0x01,0x02,0x03,0x04,
426 0x01,0x02,0x03,0x04,
427 0x01,0x02,0x03,0x04,
428 0x01,0x02,0x03,0x04,
429 0xfe,0xfe, 0x00, 0x00
430 };
433 static uint8_t mac2_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x24};
434 static uint8_t mac3_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x26};
435 static uint8_t mac4_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x28};
438 static uint8_t app_test_mc2_pkt[APP_TEST_PKT_SIZE] = {
439 0x01, 0x93, 0x20, 0x21, 0x22, 0x24,
440 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
441 0x08, 0x06, 0x00, 0x01,
442 0x08, 0x00, 0x06, 0x04,
443 0x00,0x01,0x01, 0xbb,
444 0xcc, 0xdd, 0xee, 0xff,
445 0xc0, 0xa8, 0x01, 0x16,
446 0x00, 0x00, 0x00, 0x00,
447 0xc0, 0xa8,0x01, 0x02,
448 0x01,0x02,0x03,0x04,
449 0x01,0x02,0x03,0x04,
450 0x01,0x02,0x03,0x04,
451 0x01,0x02,0x03,0x04,
452 0x01,0x02,0x03,0x04,
453 0xfe,0xfe, 0x00, 0x00
454 };
456 static uint8_t app_test_mc3_pkt[APP_TEST_PKT_SIZE] = {
457 0x01, 0x93, 0x20, 0x21, 0x22, 0x26,
458 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
459 0x08, 0x06, 0x00, 0x01,
460 0x08, 0x00, 0x06, 0x04,
461 0x00,0x01,0x01, 0xbb,
462 0xcc, 0xdd, 0xee, 0xff,
463 0xc0, 0xa8, 0x01, 0x16,
464 0x00, 0x00, 0x00, 0x00,
465 0xc0, 0xa8,0x01, 0x02,
466 0x01,0x02,0x03,0x04,
467 0x01,0x02,0x03,0x04,
468 0x01,0x02,0x03,0x04,
469 0x01,0x02,0x03,0x04,
470 0x01,0x02,0x03,0x04,
471 0xfe,0xfe, 0x00, 0x00
472 };
474 static uint8_t app_test_mc4_pkt[APP_TEST_PKT_SIZE] = {
475 0x01, 0x93, 0x20, 0x21, 0x22, 0x28,
476 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
477 0x08, 0x06, 0x00, 0x01,
478 0x08, 0x00, 0x06, 0x04,
479 0x00,0x01,0x01, 0xbb,
480 0xcc, 0xdd, 0xee, 0xff,
481 0xc0, 0xa8, 0x01, 0x16,
482 0x00, 0x00, 0x00, 0x00,
483 0xc0, 0xa8,0x01, 0x02,
484 0x01,0x02,0x03,0x04,
485 0x01,0x02,0x03,0x04,
486 0x01,0x02,0x03,0x04,
487 0x01,0x02,0x03,0x04,
488 0x01,0x02,0x03,0x04,
489 0xfe,0xfe, 0x00, 0x00
491 };
493 uint8_t app_test_128_pkt[128] = {
494 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
495 0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
496 0x08, 0x06, 0x00, 0x01,
497 0x08, 0x00, 0x06, 0x04,
498 0x00,0x01,0x01, 0xbb,
499 0xcc, 0xdd, 0xee, 0xff,
500 0xc0, 0xa8, 0x01, 0x16,
501 0x00, 0x00, 0x00, 0x00,
502 0xc0, 0xa8,0x01, 0x02,
503 0x01,0x02,0x03,0x04,
504 0x01,0x02,0x03,0x04,
505 0x01,0x02,0x03,0x04,
506 0x01,0x02,0x03,0x04,
507 0x01,0x02,0x03,0x04,
508 0xfe,0xfe, 0x00, 0x00,
509 0x48, 0x93, 0xfe, 0xfa,
510 0x18, 0x44, 0x18, 0x4a,
511 0x48, 0x93, 0xfe, 0xfa,
512 0x08, 0x06, 0x00, 0x01,
513 0x08, 0x00, 0x06, 0x04,
514 0x00,0x01,0x01, 0xbb,
515 0xcc, 0xdd, 0xee, 0xff,
516 0xc0, 0xa8, 0x01, 0x16,
517 0x00, 0x00, 0x00, 0x00,
518 0xc0, 0xa8,0x01, 0x02,
519 0x01,0x02,0x03,0x04,
520 0x01,0x02,0x03,0x04,
521 0x01,0x02,0x03,0x04,
522 0x01,0x02,0x03,0x04,
523 0x01,0x02,0x03,0x04,
524 0xfe,0xfe, 0x00, 0x00
525 };
527 static uint8_t *pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
529 /**********************************************************************
530 ************************ EMAC TEST FUNCTIONS *************************
531 **********************************************************************/
533 /*
534 * ======== app_detect_interposer_card ========
535 */
536 bool app_detect_interposer_card(void)
537 {
538 #ifdef am65xx_idk
539 EMAC_socGetInitCfg(0, &emac_cfg);
540 CSL_MdioRegs *pBaseAddr = (CSL_MdioRegs*) (uintptr_t)(emac_cfg.portCfg[2].mdioRegsBaseAddr);
541 #ifdef EMAC_TEST_APP_WITHOUT_DDR
542 Task_sleep(5000);
543 #endif
544 if ((CSL_MDIO_isPhyAlive(pBaseAddr,emac_cfg.portCfg[2].phyAddr)) ||(CSL_MDIO_isPhyAlive(pBaseAddr,emac_cfg.portCfg[3].phyAddr)))
545 {
546 UART_printf("PHYs for ICSSG1 are ALIVE, interposer card is NOT present\n");
547 return FALSE;
548 }
549 else
550 {
551 UART_printf("PHYs for ICSSG1 are not ALIVE, interposer card is present\n");
552 return TRUE;
553 }
554 #else
555 return FALSE;
556 #endif
557 }
559 /**
560 * @b app_queue_pop
561 * @n
562 * Dequeues a packet descriptor from an app queue.
563 *
564 * @param[in] pq
565 * Packet queue of type APP_PKT_QUEUE_T .
566 *
567 * @retval
568 * EMAC_Pkt popped from the queue.
569 */
570 EMAC_PKT_DESC_T*
571 app_queue_pop
572 (
573 uint32_t port_num,
574 APP_PKT_QUEUE_T* pq
575 )
576 {
577 EMAC_PKT_DESC_T* pPktHdr;
578 #ifndef EMAC_BENCHMARK
579 uintptr_t key;
580 #endif
581 if (!pq->Count)
582 {
583 return 0;
584 }
585 #ifndef EMAC_BENCHMARK
586 key = EMAC_osalHardwareIntDisable();
587 #endif
589 pPktHdr = pq->pHead;
590 if( pPktHdr )
591 {
592 pq->pHead = pPktHdr->pNext;
593 pq->Count--;
594 pPktHdr->pPrev = pPktHdr->pNext = 0;
595 }
596 #ifndef EMAC_BENCHMARK
597 EMAC_osalHardwareIntRestore(key);
598 #endif
600 return( pPktHdr );
601 }
603 /**
604 * @b app_queue_push
605 * @n
606 * Enqueues a packet in EMAC_Pkt queue.
607 *
608 * @param[in] pq
609 * Packet queue of type EMAC_PKT_QUEUE_T .
610 * @param[in] pPktHdr
611 * EMAC_PKT_DESC_T type packet to push.
612 *
613 * @retval
614 * void
615 */
616 void
617 app_queue_push
618 (
619 uint32_t port_num,
620 APP_PKT_QUEUE_T* pq,
621 EMAC_PKT_DESC_T* pPktHdr
622 )
623 {
624 #ifndef EMAC_BENCHMARK
625 uintptr_t key;
626 key = EMAC_osalHardwareIntDisable();
627 #endif
628 pPktHdr->pNext = 0;
630 if( !pq->pHead )
631 {
632 /* Queue is empty - Initialize it with this one packet */
633 pq->pHead = pPktHdr;
634 pq->pTail = pPktHdr;
635 }
636 else
637 {
638 /* Queue is not empty - Push onto end */
639 pq->pTail->pNext = pPktHdr;
640 pq->pTail = pPktHdr;
641 }
642 pq->Count++;
643 #ifndef EMAC_BENCHMARK
644 EMAC_osalHardwareIntRestore(key);
645 #endif
646 }
648 uint32_t allocCount = 0;
649 uint32_t allocFailed = 0;
650 uint32_t gAppAllocFailure = 0;
652 #ifndef EMAC_TEST_ALLOC_FAIL
653 /**
654 * @b Description
655 * @n
656 * Call back function provided by application for EMAC driver
657 * to allocate a packet descriptor.
658 *
659 * @retval
660 * pointer to the allocated packet descriptor.
661 */
662 EMAC_PKT_DESC_T*
663 app_alloc_pkt
664 (
665 uint32_t port_num,
666 uint32_t pkt_size
667 )
668 {
669 EMAC_PKT_DESC_T* p_pkt_desc = NULL;
670 if (pkt_size <= APP_EMAC_MAX_PKT_SIZE)
671 {
672 /* Get a packet descriptor from the free queue */
673 p_pkt_desc = app_queue_pop(port_num, &app_mcb.emac_pcb[port_num].freeQueue);
674 if(p_pkt_desc)
675 {
676 p_pkt_desc->AppPrivate = (uintptr_t)p_pkt_desc;
677 p_pkt_desc->BufferLen = APP_EMAC_MAX_PKT_SIZE;
678 p_pkt_desc->DataOffset = 0;
679 p_pkt_desc->pPrev = NULL;
680 p_pkt_desc->pNext = NULL;
681 }
682 else
683 gAppAllocFailure++;
684 }
685 else
686 {
687 UART_printf ("app_alloc_pkt on port %d failed, packet size %d is too big\n", port_num, pkt_size);
688 return NULL;
689 }
690 return p_pkt_desc;
691 }
692 #else
693 #endif
695 /**
696 * @b Description
697 * @n
698 * Call back function provided by application for EMAC driver
699 * to free a packet descriptor.
700 *
701 * @retval
702 * None.
703 */
704 void
705 app_free_pkt
706 (
707 uint32_t port_num,
708 EMAC_PKT_DESC_T* p_pkt_desc
709 )
710 {
711 /* Free a packet descriptor to the free queue */
712 app_queue_push(port_num, &app_mcb.emac_pcb[port_num].freeQueue,
713 (EMAC_PKT_DESC_T *)p_pkt_desc->AppPrivate);
714 }
718 /**
719 * @b Description
720 * @n
721 * Intialize the application control block, free/rx packet queue.
722 *
723 * @retval
724 * None.
725 */
726 void
727 app_init(void)
728 {
729 uint32_t i, j;
730 EMAC_PKT_DESC_T* p_pkt_desc;
731 uint8_t* pktbuf_ptr;
733 UART_printf ("EMAC loopback test application initialization\n");
735 /* Reset application control block */
736 memset(&app_mcb, 0, sizeof (APP_EMAC_MCB_T));
738 #ifdef _TMS320C6X
739 app_mcb.core_num = CSL_chipReadReg (CSL_CHIP_DNUM);
740 #else
741 app_mcb.core_num = 0;
742 #endif
743 pktbuf_ptr = (uint8_t *) ((uintptr_t) app_pkt_buffer);
744 /* Initialize the free packet queue */
745 for (i=portNum; i <=endPort; i++)
746 {
747 if (!port_en[i])
748 continue;
749 #ifndef EMAC_BENCHMARK
750 for (j=0; j<APP_MAX_PKTS/MAX_NUM_EMAC_PORTS; j++)
751 #else
752 for (j=0; j<(APP_MAX_PKTS); j++)
753 #endif
754 {
755 p_pkt_desc = &app_mcb.emac_pcb[i].pkt_desc[j];
756 p_pkt_desc->pDataBuffer = pktbuf_ptr;
757 p_pkt_desc->BufferLen = APP_EMAC_MAX_PKT_SIZE;
758 app_queue_push( i, &app_mcb.emac_pcb[i].freeQueue, p_pkt_desc );
759 pktbuf_ptr += APP_EMAC_MAX_PKT_SIZE;
760 }
761 }
762 }
764 #if defined (EMAC_BENCHMARK)
765 uint32_t app_test_send_fail = 0;
766 uint32_t app_test_alloc_fail = 0;
768 /******************************************************************************
769 * Function: EMAC test loopback packet
770 ******************************************************************************/
771 /**
772 * @brief This function is used to loopback the pkt received to sender
773 */
774 void app_test_loopback_pkt(uint32_t portNum, EMAC_PKT_DESC_T* pDesc)
775 {
776 EMAC_DRV_ERR_E sentRetVal;
777 uint8_t* temp;
778 EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(portNum, APP_EMAC_MAX_PKT_SIZE);
779 if (p_pkt_desc == NULL)
780 {
781 UART_printf("app_test_loopback_pkt: app alloc pkt failed\n");
782 app_test_alloc_fail++;
783 }
784 else
785 {
786 temp = p_pkt_desc->pDataBuffer; // temp is now buffer
788 p_pkt_desc->pDataBuffer = pDesc->pDataBuffer;
789 pDesc->pDataBuffer = temp;
791 p_pkt_desc->AppPrivate = (uint32_t)p_pkt_desc;
792 p_pkt_desc->ValidLen = pDesc->PktLength-4;
793 p_pkt_desc->DataOffset = 0;
794 p_pkt_desc->PktLength = pDesc->PktLength-4;
795 p_pkt_desc->PktFrags = 1;
796 p_pkt_desc->pNext = NULL;
797 p_pkt_desc->pPrev = NULL;
798 p_pkt_desc->PktChannel = 0;
799 p_pkt_desc->PktLength = pDesc->PktLength-4;
800 sentRetVal = emac_send(portNum, p_pkt_desc);
801 if(sentRetVal != EMAC_DRV_RESULT_OK)
802 {
803 app_test_send_fail++;
804 app_free_pkt(portNum,p_pkt_desc);
805 }
806 }
807 }
808 #endif
811 /******************************************************************************
812 * Function: EMAC RX packet call back function
813 ******************************************************************************/
814 /**
815 * @brief This function is used to call back the network application when a
816 * packet is received.
817 */
818 void app_test_rx_pkt_cb(uint32_t port_num, EMAC_PKT_DESC_T* p_desc)
819 {
820 #if !defined (EMAC_BENCHMARK)
821 if (memcmp(p_desc->pDataBuffer, pTestPkt, APP_TEST_PKT_SIZE) == 0)
822 {
823 pkt_rcv_count++;
824 if (port_num != EMAC_PORT_CPSW)
825 {
826 UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d, rx timestamp: 0x%x%08x\n",
827 port_num,
828 p_desc->PktChannel,
829 pkt_rcv_count,
830 (unsigned int)(p_desc->RxTimeStamp >> 32),
831 (unsigned int)(p_desc->RxTimeStamp & 0xFFFFFFFF));
832 }
833 else
834 {
835 UART_printf("app_test_rx_pkt_cb: port %d: ring num: %d, received packet %d\n",port_num, p_desc->PktChannel, pkt_rcv_count);
836 }
837 }
838 else
839 {
840 UART_printf("app_test_rx_pkt_cb: port %u: ring num %d: packet match failed\n", port_num, p_desc->PktChannel);
841 while(1);
842 }
843 if (p_desc->AppPrivate != 0U)
844 {
845 app_free_pkt(port_num, (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
846 }
847 pkt_received = 1;
848 #else
849 if (p_desc->AppPrivate != 0U)
850 {
851 if (port_num != EMAC_PORT_CPSW)
852 app_test_loopback_pkt(app_test_send_port,p_desc);
853 app_free_pkt(port_num, (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
854 pkt_received = 1;
855 }
856 pkt_rcv_count++;
857 #endif
858 }
862 /******************************************************************************
863 * Function: EMAC RX timestamp_response back function
864 ******************************************************************************/
865 /**
866 * @brief This function is used to call back the network application when a
867 * timestamp response packet is receive from ICSSG firmware.
868 */
869 void app_test_ts_response_cb(uint32_t port_num, uint32_t ts_id, uint64_t ts, bool is_valid)
870 {
871 UART_printf("app_test_ts_response_cb: port %d: tx timestamp id: 0x%x, tx timestamp: 0x%x%08x is_valid: %d\n",
872 port_num,
873 ts_id,
874 (unsigned int)(ts >> 32),
875 (unsigned int)(ts& 0xFFFFFFFF),
876 is_valid);
877 timestamp_received = 1;
879 }
880 void app_test_task_poll_pkt (UArg arg0, UArg arg1)
881 {
882 uint32_t port = (uint32_t) arg0;
883 linkStatus = 1;
884 while(initComplete == 0)
885 {
886 Task_sleep(1);
887 }
888 UART_printf("polling rx packets on port: %d\n", port);
889 while(1)
890 {
891 if (pollModeEnabled == 0)
892 {
893 emac_poll_pkt(port);
894 #ifndef EMAC_BENCHMARK
895 Task_sleep(5);
896 if (pkt_rcv_count == APP_TEST_PKT_SEND_COUNT)
897 break;
898 #endif
899 }
900 else
901 {
902 break;
903 }
904 }
905 }
907 void app_test_task_poll_ctrl (UArg arg0, UArg arg1)
908 {
909 uint32_t port = (uint32_t) arg0;
910 #ifdef EMAC_TEST_APP_ICSSG
911 uint32_t mgmtRings =0x7;
912 uint32_t pktRings =0x1ff;
913 uint32_t txRings = 0xf;
914 #else
915 uint32_t mgmtRings =0x0;
916 uint32_t pktRings =0x1;
917 uint32_t txRings = 0x0;
918 #endif
919 linkStatus = 1;
920 while(initComplete == 0)
921 {
922 Task_sleep(1);
923 }
925 UART_printf("polling all pkts on port: %d\n", port);
926 while(1)
927 {
928 if (pollModeEnabled == 1)
929 emac_poll_ctrl(port, pktRings,mgmtRings,txRings);
930 else
931 emac_poll_ctrl(port, 0,EMAC_POLL_RX_MGMT_RING2,txRings);
932 Task_sleep(2);
933 }
934 }
936 int32_t emac_send_fail = 0;
939 int32_t app_test_send(uint32_t pNum, uint8_t* pPkt, uint32_t pktChannel, uint32_t pktSize)
940 {
941 uint32_t i;
942 static uint32_t pkt_send_count =0;
943 EMAC_DRV_ERR_E sentRetVal;
945 gFail_count = 0;
946 for (i = 0; i < APP_TEST_PKT_SEND_COUNT/2; i++)
947 {
949 EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(pNum, pktSize);
950 if (p_pkt_desc == NULL)
951 {
952 UART_printf("app_test_send: app alloc pkt failed\n");
953 while(1);
954 }
955 memcpy (p_pkt_desc->pDataBuffer, pPkt, pktSize);
956 p_pkt_desc->AppPrivate = (uintptr_t)p_pkt_desc;
957 /* only enable TX timestamp when in poll mode of operation, currently not support for SWITCH use case */
958 if (pollModeEnabled)
959 {
960 /* PG2.0 test firmware does not currently support TX TS */
961 if ((pNum != EMAC_CPSW_PORT_NUM) && (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION))
962 {
963 p_pkt_desc->Flags = EMAC_PKT_FLAG_TX_TS_REQ;
964 p_pkt_desc->TxtimestampId = pNum + i;
965 timestamp_received = 0;
966 }
967 }
968 p_pkt_desc->TxPktTc = i % 8;
969 p_pkt_desc->ValidLen = pktSize;
970 p_pkt_desc->DataOffset = 0;
971 p_pkt_desc->PktLength = pktSize;
972 p_pkt_desc->PktFrags = 1;
973 p_pkt_desc->pNext = NULL;
974 p_pkt_desc->pPrev = NULL;
975 p_pkt_desc->PktChannel = pktChannel;
976 p_pkt_desc->PktLength = pktSize;
977 sentRetVal = emac_send(pNum, p_pkt_desc);
978 if(sentRetVal != EMAC_DRV_RESULT_OK)
979 {
980 UART_printf("app_test_send: emac send on port failed with status: : %d: retVal %d, pkt_count: %d\n", pNum, sentRetVal, i+1);
981 app_free_pkt(pNum,p_pkt_desc);
982 emac_send_fail++;
983 }
985 #if !defined(EMAC_BENCHMARK)
987 while((pkt_received == 0) || (timestamp_received == 0))
988 {
989 Task_sleep(100);
990 }
991 #endif
993 pkt_received = 0;
994 pkt_send_count++;
996 }
997 return gFail_count;
998 }
1000 void app_test_pkt_clone(void)
1001 {
1002 int32_t status;
1003 testPktClone = 1;
1004 app_test_id++;
1005 pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1006 UART_printf("EMAC_UT_%d begin: app_test_pkt_clone\n", app_test_id);
1007 status = app_test_send_receive(portNum, endPort,0);
1008 if(status == 0)
1009 UART_printf("EMAC_UT_%d begin: app_test_pkt_clone passed\n", app_test_id);
1010 testPktClone = 0;
1012 }
1013 void app_test_port_mac(void)
1014 {
1015 int32_t status;
1016 Task_sleep(500);
1017 app_test_id++;
1018 pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1019 UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC\n", app_test_id);
1020 status = app_test_send_receive(portNum, endPort,0);
1021 if(status == 0)
1022 UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC passed\n", app_test_id);
1024 app_test_id++;
1025 pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1026 UART_printf("EMAC_UT_%d begin: sending BC packet\n", app_test_id);
1027 status = app_test_send_receive(portNum, endPort,0);
1028 if(status == 0)
1029 UART_printf("EMAC_UT_%d begin: sending BC packet passed\n", app_test_id);
1030 }
1031 void app_test_interrrupt_mode(void)
1032 {
1033 app_test_id++;
1034 pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1035 UART_printf("EMAC_UT_%d begin test interrupt mode\n", app_test_id);
1036 app_test_send_receive(portNum, endPort,0);
1037 UART_printf("EMAC_UT_%d begin test interrupt mode passed\n", app_test_id);
1038 }
1040 void app_test_tx_chans(void)
1041 {
1042 app_test_id++;
1043 uint32_t pNum;
1044 uint32_t txChannel;
1045 UART_printf("EMAC_UT_%d begin test_multiple tx chans mode\n", app_test_id);
1046 for (pNum = portNum; pNum <= endPort; pNum++)
1047 {
1048 if (!port_en[pNum])
1049 continue;
1051 if (1 == interposerCardPresent)
1052 {
1053 if((pNum == 0) || (pNum == 2) || (pNum == 6))
1054 continue;
1055 }
1056 for (txChannel = 0; txChannel < 4;txChannel++)
1057 {
1058 app_test_send(pNum, pTestPkt, txChannel, APP_TEST_PKT_SIZE);
1059 }
1060 }
1062 UART_printf("EMAC_UT_%d end test_multiple tx chans mode\n", app_test_id);
1064 }
1066 void app_test_poll_mode(void)
1067 {
1068 pollModeEnabled = 1;
1069 app_test_id++;
1070 pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1071 UART_printf("EMAC_UT_%d begin test poll mode\n", app_test_id);
1072 app_test_send_receive(portNum, endPort,0);
1073 UART_printf("EMAC_UT_%d begin test poll mode passed\n", app_test_id);
1074 }
1076 void app_test_multi_flows(void)
1077 {
1078 uint32_t pNum;
1079 EMAC_IOCTL_PARAMS params;
1080 EMAC_MAC_ADDR_T macAddrs[4];
1082 memcpy (&macAddrs[0], &mac1_mc[0], sizeof(EMAC_MAC_ADDR_T));
1083 memcpy (&macAddrs[1], &mac2_mc[0], sizeof(EMAC_MAC_ADDR_T));
1084 memcpy (&macAddrs[2], &mac3_mc[0], sizeof(EMAC_MAC_ADDR_T));
1085 memcpy (&macAddrs[3], &mac4_mc[0], sizeof(EMAC_MAC_ADDR_T));
1087 params.ioctlVal = (void*)&macAddrs[0];
1089 for (pNum =portNum; pNum <= endPort; pNum++)
1090 {
1091 if ((!port_en[pNum]) || (pNum == 6))
1092 continue;
1093 emac_ioctl(pNum,EMAC_IOCTL_TEST_MULTI_FLOW,(void*)(¶ms));
1094 }
1095 for (pNum =portNum; pNum <= endPort; pNum++)
1096 {
1097 if (1 == interposerCardPresent)
1098 {
1099 if((pNum == 0) || (pNum == 2) || (pNum == 6))
1100 continue;
1101 }
1102 if (!port_en[pNum])
1103 continue;
1104 pTestPkt = (uint8_t*)(&app_test_mc1_pkt[0]);
1105 app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1107 pTestPkt = (uint8_t*)(&app_test_mc2_pkt[0]);
1108 app_test_send(pNum, pTestPkt, 0, APP_TEST_PKT_SIZE);
1110 pTestPkt = (uint8_t*)(&app_test_mc3_pkt[0]);
1111 app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1113 pTestPkt = (uint8_t*)(&app_test_mc4_pkt[0]);
1114 app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1115 }
1117 }
1119 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult)
1120 {
1121 uint32_t pNum;
1122 int32_t status = 0;
1123 for (pNum = startP; pNum <= endP; pNum++)
1124 {
1125 if (!port_en[pNum])
1126 continue;
1128 if (1 == interposerCardPresent)
1129 {
1130 if((pNum == 0) || (pNum == 2))
1131 continue;
1132 }
1133 UART_printf("app_test_send_receive: testing port: %d\n", pNum);
1134 status = app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1136 if ((pNum == endPort) && (displayResult == 1))
1137 {
1138 UART_printf("All tests have passed\n");
1139 }
1140 }
1141 return status;
1142 }
1144 #ifdef EMAC_TEST_APP_ICSSG
1145 #define TX_BUFF_POOL_SIZE 0X1800u
1146 #define TX_BUFF_POOL_TOTAL_DUAL_MAC (TX_BUFF_POOL_SIZE + 0x80) * 8U /* //50176 per PORT, total of 100352 */
1147 void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1148 {
1149 EMAC_FW_APP_CONFIG *pFwAppCfg;
1150 emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1151 if ((port_num % 2) == 0)
1152 {
1153 pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num >> 1][0]);
1154 }
1155 else
1156 {
1157 pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num >> 1][TX_BUFF_POOL_TOTAL_DUAL_MAC]);
1158 }
1160 pFwAppCfg->txPortQueueHighAddr = 0;
1162 emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1164 /* Need to update the emac configuraiton with function required by the driver to get the FW configuration to write to shared mem */
1165 pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1167 }
1168 #endif
1170 void app_test_trace_cb(uint8_t traceLevel, const char* traceString, ...)
1171 {
1172 if (traceLevel <= UTIL_TRACE_LEVEL_ERR)
1173 {
1174 System_flush();
1175 VaList arg_ptr;
1176 /* print the format string */
1177 va_start(arg_ptr, traceString);
1178 System_vprintf(traceString, arg_ptr);
1179 va_end(arg_ptr);
1180 /* append newline */
1181 System_printf("\n");
1182 System_flush();
1183 }
1184 }
1186 int32_t app_test_emac_open(uint32_t mode)
1187 {
1188 EMAC_socGetInitCfg(0, &emac_cfg);
1189 int32_t chanNum = 0;
1190 int32_t subChanNum = 0;
1191 uint32_t pNum;
1192 EMAC_MAC_ADDR_T macTest;
1193 app_test_id++;
1194 UART_printf("EMAC_UT_%d begin, test emac open\n", app_test_id);
1196 #ifdef EMAC_TEST_APP_ICSSG
1197 for (pNum = portNum; pNum <= endPort; pNum++)
1198 {
1199 if (!port_en[pNum])
1200 continue;
1201 app_test_task_disable_pruicss(pNum);
1202 }
1203 #endif
1205 for (pNum = portNum; pNum <= endPort; pNum++)
1206 {
1207 if (!port_en[pNum])
1208 continue;
1209 #if defined(EMAC_TEST_APP_WITHOUT_DDR) || defined(EMAC_BENCHMARK)
1210 emac_cfg.portCfg[pNum].nTxChans = 1U;
1211 emac_cfg.portCfg[pNum].rxChannel.nsubChan = 1U;
1212 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan = EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT;
1213 emac_cfg.portCfg[pNum].rxChannel2CfgOverPSI.nsubChan = 0;
1214 #endif
1215 for (chanNum = 0; chanNum < emac_cfg.portCfg[pNum].nTxChans; chanNum++)
1216 {
1217 emac_cfg.portCfg[pNum].txChannel[chanNum].chHandle = (void *)&gUdmaTxChObj[pNum][chanNum];
1218 emac_cfg.portCfg[pNum].txChannel[chanNum].freeRingMem= (void*)&gTxRingMem[pNum][chanNum][0];
1219 emac_cfg.portCfg[pNum].txChannel[chanNum].compRingMem= (void*)&gTxCompRingMem[pNum][chanNum][0];
1220 emac_cfg.portCfg[pNum].txChannel[chanNum].hPdMem = (void*)&gUdmapDescRamTx[pNum][chanNum][0];
1221 }
1222 emac_cfg.portCfg[pNum].rxChannel.chHandle = (void *)&gUdmaRxChObj[pNum];
1223 emac_cfg.portCfg[pNum].rxChannel.flowHandle= (void *)&gUdmaFlowHnd[pNum];
1224 /* each subChan is a flow which is required 1 ring pair, subChanNum 0 is used for default flow*/
1225 for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannel.nsubChan; subChanNum++)
1226 {
1227 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMem[pNum][subChanNum][0];
1228 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHnd[pNum][subChanNum];
1229 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMem[pNum][subChanNum][0];
1230 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHnd[pNum][subChanNum];
1231 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRx[pNum][subChanNum][0];
1232 emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].eventHandle = (void *)&gUdmaRxCqEventObj[pNum][subChanNum];
1233 }
1235 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.chHandle = (void *)&gUdmaRxMgmtPsiChObj[pNum];
1236 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.flowHandle= (void *)&gUdmaFlowHndCfgPsi[pNum];
1237 for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan; subChanNum++)
1238 {
1239 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMemCfgPsi[pNum][subChanNum][0];
1240 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHndCfgPsi[pNum][subChanNum];
1241 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMemCfgPsi[pNum][subChanNum][0];
1242 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHndCfgPsi[pNum][subChanNum];
1243 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRxMgmtPsi[pNum][subChanNum][0];
1244 emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].eventHandle = (void *)&gUdmaRxMgmtPsiCqEventObj[pNum][subChanNum];
1245 }
1246 }
1248 for (pNum = portNum; pNum <= endPort; pNum++)
1249 {
1250 if (!port_en[pNum])
1251 continue;
1252 if (pNum != EMAC_PORT_CPSW)
1253 {
1255 #ifdef EMAC_TEST_APP_ICSSG
1256 app_test_setup_fw_dualmac(pNum, &emac_cfg);
1257 #endif
1258 }
1259 EMAC_socSetInitCfg(0, &emac_cfg);
1260 EMAC_socGetInitCfg(0, &emac_cfg);
1262 open_cfg.hwAttrs = (void*)&emac_cfg;
1263 open_cfg.alloc_pkt_cb = app_alloc_pkt;
1264 open_cfg.free_pkt_cb = app_free_pkt;
1265 open_cfg.rx_pkt_cb = app_test_rx_pkt_cb;
1266 open_cfg.tx_ts_cb = app_test_ts_response_cb;
1267 open_cfg.loop_back = 0U;
1268 /* Only need to enbale loopback for CPSW test application and when not doing benchmark testing */
1269 #ifndef EMAC_BENCHMARK
1270 if (pNum == EMAC_PORT_CPSW)
1271 {
1272 open_cfg.loop_back = 1U;
1273 }
1274 open_cfg.num_of_rx_pkt_desc = 8U;
1275 open_cfg.num_of_tx_pkt_desc = 8U;
1276 #else
1277 open_cfg.num_of_rx_pkt_desc = 128U;
1278 open_cfg.num_of_tx_pkt_desc = 128U;
1279 #endif
1280 open_cfg.master_core_flag = 1;
1281 open_cfg.max_pkt_size = APP_EMAC_MAX_PKT_SIZE;
1282 open_cfg.mdio_flag = 1;
1283 open_cfg.num_of_chans = 1;
1284 open_cfg.udmaHandle = (void*)gDrvHandle;
1286 macTest.addr[0] = 0x48;
1287 macTest.addr[1] = 0x93;
1288 macTest.addr[2] = 0xfe;
1289 macTest.addr[3] = 0xfa;
1290 macTest.addr[4] = 0x18;
1291 macTest.addr[5] = 0x44;
1293 open_cfg.p_chan_mac_addr = &chan_cfg[0];
1294 /* Set the channel configuration */
1295 chan_cfg[0].chan_num = 0;
1296 chan_cfg[0].num_of_mac_addrs = 1;
1297 chan_cfg[0].p_mac_addr = & macTest;
1298 open_cfg.mode_of_operation = mode;
1300 if (emac_open(pNum, &open_cfg) == EMAC_DRV_RESULT_OK)
1301 {
1302 UART_printf("main: emac_open sucess for port %d\n", pNum);
1303 #ifdef EMAC_TEST_APP_ICSSG
1304 app_test_task_init_pruicss(pNum);
1305 #endif
1306 }
1307 else
1308 {
1309 UART_printf("main: emac_open failure for port: %d\n",pNum);
1310 return -1;
1311 }
1313 }
1314 UART_printf("EMAC_UT_%d end, test emac open passed\n", app_test_id);
1316 return 0;
1317 }
1319 int32_t app_test_emac_close(void)
1320 {
1321 app_test_id++;
1322 UART_printf("EMAC_UT_%d begin, test emac close\n", app_test_id);
1324 uint32_t pNum;
1325 for (pNum = portNum; pNum <= endPort; pNum++)
1326 {
1327 if (!port_en[pNum])
1328 continue;
1329 if (emac_close(pNum) == EMAC_DRV_RESULT_OK)
1330 {
1331 UART_printf("app_test_emac_close: emac close for port %d success\n", pNum);
1332 }
1333 else
1334 {
1335 UART_printf("app_test_emac_close: emac close for port %d failed\n", pNum);
1336 return -1;
1337 }
1338 }
1339 UART_printf("EMAC_UT_%d end, test emac close\n", app_test_id);
1340 return 0;
1342 }
1344 void app_test_config_promiscous_mode(uint32_t enable)
1345 {
1346 uint32_t pNum;
1347 uint32_t promisEnableFlag = 0;
1348 EMAC_IOCTL_PARAMS params;
1350 if (enable == 1)
1351 promisEnableFlag = 1;
1352 params.ioctlVal = (void*)(&promisEnableFlag);
1354 for (pNum =portNum; pNum <= endPort; pNum++)
1355 {
1356 if ((!port_en[pNum]) || (pNum == 6))
1357 continue;
1358 emac_ioctl(pNum,EMAC_IOCTL_PROMISCOUS_MODE_CTRL,(void*)(¶ms));
1359 }
1361 }
1363 void app_test_promiscous_mode(void)
1364 {
1365 app_test_id++;
1366 UART_printf("EMAC_UT_%d begin test promiscous mode\n", app_test_id);
1368 pTestPkt = (uint8_t*)(&app_test_mc_pkt[0]);
1369 app_test_send_receive(portNum, endPort, 0);
1370 UART_printf("app_test_promiscous_mode with MC pkt success\n");
1371 pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1372 app_test_send_receive(portNum, endPort, 0);
1373 UART_printf("app_test_promiscous_mode with BC pkt success\n");
1375 pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1376 app_test_send_receive(portNum, endPort, 0);
1377 UART_printf("app_test_promiscous_mode with UC pkt success\n");
1379 UART_printf("EMAC_UT_%d test poll promiscous passed\n", app_test_id);
1380 }
1382 void emac_test_get_icssg_stats(void)
1383 {
1384 uint32_t pNum;
1385 EMAC_STATISTICS_ICSSG_T stats;
1386 app_test_id++;
1388 UART_printf("EMAC_UT_%d begin collecting icssg stats\n", app_test_id);
1389 for (pNum = portNum; pNum <= endPort; pNum++)
1390 {
1391 if (!port_en[pNum])
1392 continue;
1393 memset(&stats, 0, sizeof(EMAC_STATISTICS_ICSSG_T));
1394 if (emac_get_statistics_icssg(pNum, &stats, 0) == EMAC_DRV_RESULT_OK)
1395 {
1396 UART_printf("port:%d: rx packets: %d, tx packets: %d\n", pNum, stats.RxGoodFrames, stats.TXGoodFrame);
1397 }
1398 else
1399 {
1400 UART_printf("emac_test_get_icssg_stats: emac_get_statistics_icssg for port %d failed\n", pNum);
1401 while(1);
1402 }
1403 }
1404 UART_printf("EMAC_UT_%d collecting icssg stats passed\n", app_test_id);
1405 }
1407 void emac_test_get_cpsw_stats(void)
1408 {
1409 EMAC_STATISTICS_T stats;
1410 memset(&stats, 0, sizeof(EMAC_STATISTICS_T));
1411 if (!port_en[EMAC_PORT_CPSW])
1412 return;
1413 app_test_id++;
1415 UART_printf("EMAC_UT_%d begin collecting cpsw stats\n", app_test_id);
1416 if (emac_get_statistics(endPort, &stats) == EMAC_DRV_RESULT_OK)
1417 {
1418 UART_printf("port: %d: rx packets: %d, tx packets: %d\n", endPort, stats.RxGoodFrames, stats.TxGoodFrames);
1419 }
1420 else
1421 {
1422 UART_printf("emac_test_get_cpsw_stats: emac_get_statistics for port %d failed\n", endPort);
1423 while(1);
1424 }
1425 UART_printf("EMAC_UT_%d collecting cpsw stats passed\n", app_test_id);
1426 }
1429 void app_test_udma_init(void)
1430 {
1431 int32_t retVal = UDMA_SOK;
1432 Udma_InitPrms initPrms;
1433 uint32_t instId;
1435 #if defined (SOC_AM65XX)
1436 #if defined (EMAC_TEST_APP_CPSW)
1437 /* if A53 and pg 1.0 use mcu navss due to hw errata*/
1438 #if defined (BUILD_MPU1_0)
1439 if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1440 {
1441 instId = UDMA_INST_ID_MCU_0;
1442 }
1443 else
1444 {
1445 instId = UDMA_INST_ID_MAIN_0;
1446 }
1447 #else
1448 instId = UDMA_INST_ID_MCU_0;
1449 #endif
1450 #else
1451 /* icssg use case */
1452 instId = UDMA_INST_ID_MAIN_0;
1453 #endif
1454 #endif
1456 #if defined (SOC_J721E)
1457 #if defined (EMAC_TEST_APP_CPSW)
1458 #if defined (BUILD_MPU1_0)
1459 instId = UDMA_INST_ID_MAIN_0;
1460 #else
1461 instId = UDMA_INST_ID_MCU_0;
1462 #endif
1463 #else
1464 /* icssg use case */
1465 instId = UDMA_INST_ID_MAIN_0;
1466 #endif
1467 #endif
1469 UdmaInitPrms_init(instId, &initPrms);
1471 initPrms.rmInitPrms.numIrIntr = EMAC_MAX_PORTS*8;
1472 initPrms.rmInitPrms.numRxCh = EMAC_MAX_PORTS*4;
1473 initPrms.rmInitPrms.numTxCh= EMAC_MAX_PORTS*4;
1475 initPrms.rmInitPrms.startFreeFlow = 0;
1476 initPrms.rmInitPrms.numFreeFlow = 120;
1478 initPrms.rmInitPrms.startFreeRing= 2;
1479 initPrms.rmInitPrms.numFreeRing = 300;
1481 /* UDMA driver init */
1482 retVal = Udma_init(&gUdmaDrvObj, &initPrms);
1483 if(UDMA_SOK == retVal)
1484 {
1485 gDrvHandle = &gUdmaDrvObj;
1486 }
1487 }
1489 void app_test_check_port_link(uint32_t startP, uint32_t endP)
1490 {
1491 uint32_t pNum;
1492 EMAC_LINK_INFO_T linkInfo;
1494 for (pNum = startP; pNum <= endP; pNum++)
1495 {
1496 if (!port_en[pNum])
1497 continue;
1498 if (1 == interposerCardPresent)
1499 {
1500 if((pNum == 2) || (pNum == 3))
1501 continue;
1502 }
1503 memset(&linkInfo, 0, sizeof(EMAC_LINK_INFO_T));
1504 do
1505 {
1506 emac_poll(pNum, &linkInfo);
1507 Osal_delay(100);
1508 UART_printf("Link for port %d is DOWN\n", pNum);
1509 } while(linkInfo.link_status == EMAC_LINKSTATUS_NOLINK);
1510 UART_printf("Link for port %d is now UP\n", pNum);
1511 }
1513 }
1515 #ifdef EMAC_BENCHMARK
1516 void app_test_task_benchmark(UArg arg0, UArg arg1)
1517 {
1518 Board_STATUS boardInitStatus =0;
1519 #ifdef EMAC_TEST_APP_ICSSG
1520 PRUICSS_Config *prussCfg;
1521 #endif
1523 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1524 Task_sleep(5000);
1525 #endif
1526 Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1528 boardInitStatus = Board_init(cfg);
1529 if (boardInitStatus !=BOARD_SOK)
1530 {
1531 UART_printf("Board_init failure\n");
1532 while(1);
1533 }
1534 UART_printf("Board_init success benchmark\n");
1535 #if defined(SOC_J721E)
1536 #else
1537 if (app_detect_interposer_card() == TRUE)
1538 {
1539 UART_printf("Interposer card is present\n");
1540 interposerCardPresent = 1;
1541 }
1542 #endif
1543 else
1544 {
1545 UART_printf("Interposer card is NOT present\n");
1546 }
1548 app_init();
1549 #ifdef EMAC_TEST_APP_ICSSG
1550 PRUICSS_socGetInitCfg(&prussCfg);
1551 prussHandle[0] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1552 prussHandle[1] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1553 #if defined(SOC_AM65XX)
1554 prussHandle[2] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1555 #endif
1556 #endif
1558 app_test_udma_init();
1560 if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1561 {
1562 while(1);
1563 }
1564 app_test_check_port_link(portNum, endPort);
1565 app_test_config_promiscous_mode(1);
1567 initComplete = 1;
1569 UART_printf("app_test_task_benchmark: getting stats\n");
1570 while (1)
1571 {
1572 Task_sleep(1000*60);
1573 emac_test_get_icssg_stats();
1574 }
1575 }
1576 #endif
1579 #ifdef EMAC_TEST_APP_ICSSG
1580 void test_EMAC_verify_ut_dual_mac_icssg(void)
1581 {
1582 /* @description:Unit test for ICSSG dual mac use case
1584 @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1585 PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029,
1586 PRSDK-7156
1588 @cores: mpu1_0, mcu1_0 */
1589 Board_STATUS boardInitStatus =0;
1590 #ifdef EMAC_TEST_APP_ICSSG
1591 PRUICSS_Config *prussCfg;
1592 #endif
1594 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1595 Task_sleep(2000);
1596 #endif
1597 Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1599 #if defined(SOC_J721E)
1600 /* PINMUX config of GESI for ICSSG */
1601 Board_PinmuxConfig_t gesiIcssgPinmux;
1602 Board_pinmuxGetCfg(&gesiIcssgPinmux);
1603 gesiIcssgPinmux.autoCfg = BOARD_PINMUX_CUSTOM;
1604 gesiIcssgPinmux.gesiExp = BOARD_PINMUX_GESI_ICSSG;
1605 Board_pinmuxSetCfg(&gesiIcssgPinmux);
1606 #endif
1607 boardInitStatus = Board_init(cfg);
1608 if (boardInitStatus !=BOARD_SOK)
1609 {
1610 UART_printf("Board_init failure\n");
1611 while(1);
1612 }
1613 UART_printf("Board_init success for UT\n");
1615 gPgVersion = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_JTAGID);
1617 #if defined(SOC_J721E)
1618 #else
1619 if (app_detect_interposer_card() == TRUE)
1620 {
1621 UART_printf("Interposer card is present\n");
1622 interposerCardPresent = 1;
1623 }
1624 else
1625 #endif
1626 {
1627 UART_printf("Interposer card is NOT present\n");
1628 }
1630 app_init();
1631 #ifdef EMAC_TEST_APP_ICSSG
1632 PRUICSS_socGetInitCfg(&prussCfg);
1633 prussHandle[0] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1634 prussHandle[1] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1635 #if defined(SOC_AM65XX)
1636 prussHandle[2] = PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1637 #endif
1638 #endif
1640 app_test_udma_init();
1642 if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1643 {
1644 while(1);
1645 }
1646 initComplete = 1;
1648 /* Need to poll for link for ICSSG ports as they are port 2 port tests */
1649 /* For standalone CPSW test, we use internal loopback at CPSW-SS */
1650 app_test_check_port_link(portNum, endPort);
1652 /* Test with PORT_MAC address */
1653 app_test_port_mac();
1655 #ifndef BUILD_MCU1_0
1656 app_test_tx_chans();
1657 #endif
1658 app_test_interrrupt_mode();
1660 if (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1661 {
1662 /* test close -re open sequence */
1663 if(app_test_emac_close() == -1)
1664 {
1665 UART_printf("emac unit test app_test_emac_close failed\n");
1666 while(1);
1667 }
1668 /* re-init the app */
1669 app_init();
1671 /* re-open in polling mode */
1672 if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1673 {
1674 while(1);
1675 }
1677 app_test_poll_mode();
1678 #ifndef BUILD_MCU1_0
1679 app_test_multi_flows();
1680 #endif
1681 app_test_config_promiscous_mode(1);
1682 app_test_promiscous_mode();
1683 emac_test_get_icssg_stats();
1684 }
1685 else
1686 {
1687 emac_test_get_icssg_stats();
1688 /* test close -re open sequence */
1689 if(app_test_emac_close() == -1)
1690 {
1691 UART_printf("emac unit test app_test_emac_close failed\n");
1692 while(1);
1693 }
1694 }
1695 UART_printf("All tests have passed\n");
1696 #ifdef UNITY_INCLUDE_CONFIG_H
1697 TEST_PASS();
1698 #endif
1699 }
1701 #else
1702 void test_EMAC_verify_ut_cpsw(void)
1703 {
1704 /* @description:Unit test for ICSSG dual mac and CPSW use cases
1706 @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1707 PRSDK-3726, PRSDK-3755, PRSDK-3765
1709 @cores: mpu1_0, mcu1_0 */
1711 Board_STATUS boardInitStatus =0;
1712 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1713 Task_sleep(2000);
1714 #endif
1715 Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ETH_PHY | BOARD_INIT_ENETCTRL_CPSW2G;
1717 boardInitStatus = Board_init(cfg);
1718 if (boardInitStatus !=BOARD_SOK)
1719 {
1720 UART_printf("Board_init failure\n");
1721 while(1);
1722 }
1723 UART_printf("Board_init success for UT\n");
1726 app_init();
1728 app_test_udma_init();
1730 if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1731 {
1732 while(1);
1733 }
1734 initComplete = 1;
1736 /* Test with PORT_MAC address */
1737 app_test_port_mac();
1739 app_test_interrrupt_mode();
1741 /* test close -re open sequence */
1742 if(app_test_emac_close() == -1)
1743 {
1744 UART_printf("emac unit test app_test_emac_close failed\n");
1745 while(1);
1746 }
1747 /* re-init the app */
1748 app_init();
1750 /* re-open in polling mode */
1751 if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1752 {
1753 while(1);
1754 }
1756 app_test_poll_mode();
1758 app_test_config_promiscous_mode(1);
1759 app_test_promiscous_mode();
1761 emac_test_get_cpsw_stats();
1763 UART_printf("All tests have passed\n");
1764 #ifdef UNITY_INCLUDE_CONFIG_H
1765 TEST_PASS();
1766 #endif
1767 }
1769 #endif
1771 #ifdef UNITY_INCLUDE_CONFIG_H
1772 #ifdef EMAC_TEST_APP_ICSSG
1773 void test_Emac_Icssg_TestApp_runner(void)
1774 {
1775 /* @description: Test runner for EMAC ICSSG tests
1777 @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776,
1778 PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029
1780 @cores: mpu1_0, mcu1_0 */
1782 UNITY_BEGIN();
1783 RUN_TEST(test_EMAC_verify_ut_dual_mac_icssg);
1784 UNITY_END();
1785 /* Function to print results defined in our unity_config.h file */
1786 print_unityOutputBuffer_usingUARTstdio();
1787 }
1789 #else
1790 void test_Emac_Cpsw_TestApp_runner(void)
1791 {
1792 /* @description: Test runner for EMAC CPSW tests
1794 @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509,
1795 PRSDK-3726, PRSDK-3755, PRSDK-3765
1797 @cores: mpu1_0, mcu1_0 */
1799 UNITY_BEGIN();
1800 RUN_TEST(test_EMAC_verify_ut_cpsw);
1801 UNITY_END();
1802 /* Function to print results defined in our unity_config.h file */
1803 print_unityOutputBuffer_usingUARTstdio();
1804 }
1805 #endif
1806 #endif
1808 void app_test_task_verify_ut_dual_mac_cpsw(UArg arg0, UArg arg1)
1809 {
1810 #ifdef UNITY_INCLUDE_CONFIG_H
1811 #ifdef EMAC_TEST_APP_ICSSG
1812 test_Emac_Icssg_TestApp_runner();
1813 #else
1814 test_Emac_Cpsw_TestApp_runner();
1815 #endif
1816 #endif
1817 }
1819 #ifdef EMAC_TEST_APP_ICSSG
1820 /*
1821 * ======== app_test_task_init_pruicss========
1822 */
1823 int32_t app_test_task_disable_pruicss(uint32_t portNum)
1824 {
1825 PRUICSS_Handle prussDrvHandle;
1826 uint8_t pru_n, rtu_n, txpru_n, slice_n;
1828 if (portNum > 5)
1829 return -1;
1831 prussDrvHandle =prussHandle[portNum >> 1];
1832 if (prussDrvHandle == NULL)
1833 return -1;
1835 slice_n = (portNum & 1);
1836 pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1837 rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1838 txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1840 if (PRUICSS_pruDisable(prussDrvHandle, pru_n) != 0)
1841 UART_printf("PRUICSS_pruDisable for PRUICCSS_PRU%d failed\n", slice_n);
1843 if (PRUICSS_pruDisable(prussDrvHandle, rtu_n) != 0)
1844 UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1846 /* pg version check: only disable txpru if NOT version PG1.0 */
1847 if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1848 {
1849 if (PRUICSS_pruDisable(prussDrvHandle, txpru_n) != 0)
1850 UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1851 }
1853 /* CLEAR SHARED MEM which is used for host/firmware handshake */
1854 PRUICSS_pruInitMemory(prussDrvHandle, PRU_ICSS_SHARED_RAM);
1857 return 0;
1858 }
1860 /*
1861 * ======== app_test_task_init_pruicss========
1862 */
1863 int32_t app_test_task_init_pruicss(uint32_t portNum)
1864 {
1865 PRUICSS_Handle prussDrvHandle;
1866 uint8_t pru_n, rtu_n, txpru_n, slice_n;
1867 app_test_pru_rtu_fw_t *firmware;
1869 if (portNum > 5)
1870 return -1;
1872 prussDrvHandle =prussHandle[portNum >> 1];
1873 if (prussDrvHandle == NULL)
1874 return -1;
1875 slice_n = (portNum & 1);
1876 pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1877 rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1878 txpru_n = (slice_n) ? PRUICCSS_TPRU1 : PRUICCSS_TPRU0;
1880 firmware = (gPgVersion == APP_TEST_AM65XX_PG1_0_VERSION)?firmware_pg1:firmware_pg2;
1882 if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_PRU(slice_n), 0,
1883 firmware[slice_n].pru, firmware[slice_n].pru_size) == 0)
1884 {
1885 UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_PRU%d failed\n", slice_n);
1886 return -1;
1887 }
1888 if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_RTU(slice_n), 0,
1889 firmware[slice_n].rtu, firmware[slice_n].rtu_size) == 0)
1890 {
1891 UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_RTU%d failed\n", slice_n);
1892 return -1;
1893 }
1894 if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1895 {
1896 if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM_TXPRU(slice_n), 0,
1897 firmware[slice_n].txpru, firmware[slice_n].txpru_size) == 0)
1898 {
1899 UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_TXPRU%d failed\n", slice_n);
1900 return -1;
1901 }
1902 }
1903 if (PRUICSS_pruEnable(prussDrvHandle, pru_n) != 0)
1904 {
1905 UART_printf("PRUICSS_pruEnable for PRUICCSS_PRU%d failed\n", slice_n);
1906 return -1;
1907 }
1908 if (PRUICSS_pruEnable(prussDrvHandle, rtu_n) != 0)
1909 {
1910 UART_printf("PRUICSS_pruEnable for PRUICCSS_RTU%d failed\n", slice_n);
1911 return -1;
1912 }
1913 if (gPgVersion != APP_TEST_AM65XX_PG1_0_VERSION)
1914 {
1915 if (PRUICSS_pruEnable(prussDrvHandle, txpru_n) != 0)
1916 {
1917 UART_printf("PRUICSS_pruEnable for PRUICCSS_TXPRU%d failed\n", slice_n);
1918 return -1;
1919 }
1920 }
1922 return 0;
1923 }
1924 #endif
1926 void app_output_log(Char* str, UInt numChar)
1927 {
1928 if (numChar > 0)
1929 {
1930 UART_printf(str);
1931 }
1932 }