packages/ti/drv/emac/test/EmacLoopbackTest/test_utils_k3.c

   1 /* =============================================================================
   2  *   Copyright (c) Texas Instruments Incorporated 2018-2019
   3  *
   4  *  Redistribution and use in source and binary forms, with or without
   5  *  modification, are permitted provided that the following conditions
   6  *  are met:
   7  *
   8  *    Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  *
  11  *    Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the
  14  *    distribution.
  15  *
  16  *    Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33
  34 /**
  35  *  \file     test_utils_k3.c
  36  *
  37  *  \brief    This file contains common utility functions used by the emac loopback unit
  38  *             test applications.
  39  *
  40  */
  41
  42 #include <string.h>
  43 #include <stdio.h>
  44 #include <stdint.h>
  45
  46 #include <xdc/std.h>
  47 #include <xdc/runtime/System.h>
  48 #include <xdc/runtime/Memory.h>
  49 #include <xdc/runtime/Error.h>
  50
  51 #include <ti/sysbios/BIOS.h>
  52 #include <ti/sysbios/knl/Task.h>
  53
  54 #include <ti/csl/csl_chip.h>
  55 #include <ti/csl/cslr_icss.h>
  56 /* EMAC Driver Header File. */
  57 #include <ti/drv/emac/emac_drv.h>
  58
  59 #include <ti/drv/emac/src/emac_osal.h>
  60 #include <ti/drv/emac/emac_ioctl.h>
  61 #include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
  62 #include <ti/drv/emac/firmware/icss_switch/config/emac_fw_config_switch.h>
  63 /* SOC Include Files. */
  64 #include <ti/drv/emac/soc/emac_soc_v5.h>
  65
  66 /* Test application local header file */
  67 #include "ti/drv/emac/test/EmacLoopbackTest/test_loc.h"
  68
  69 #include <ti/drv/uart/UART.h>
  70 #include <ti/drv/uart/UART_stdio.h>
  71 #include <ti/board/board.h>
  72
  73 #ifdef SOC_J721E
  74 #include <ti/board/src/j721e_evm/include/board_pinmux.h>
  75 #include <ti/board/src/j721e_evm/include/board_control.h>
  76 #endif
  77
  78 #ifdef EMAC_TEST_APP_ICSSG
  79 /* PRUSS Driver Header File. */
  80 #include <ti/drv/pruss/pruicss.h>
  81 #include <ti/drv/pruss/soc/pruicss_v1.h>
  82 #endif
  83
  84
  85 #ifdef UNITY_INCLUDE_CONFIG_H
  86 #include <ti/build/unit-test/Unity/src/unity.h>
  87 #include <ti/build/unit-test/config/unity_config.h>
  88 #endif
  89
  90
  91 extern uint32_t portNum;
  92 extern uint32_t endPort;
  93 extern int port_en[];
  94
  95 /**********************************************************************
  96  ************************** Global Variables **************************
  97  **********************************************************************/
  98
  99 #ifdef SOC_J721E
 100 uint8_t icss_tx_port_queue[2][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_ocmc_mem")));
 101 #else
 102 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 103 /* DDR less test, can only test with 2 ports due to msmc memory constraints */
 104 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
 105 #else
 106 #ifdef EMAC_BENCHMARK
 107 uint8_t icss_tx_port_queue[1][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
 108 #else /* test all port for DUAL MAC */
 109 uint8_t icss_tx_port_queue[3][100352] __attribute__ ((aligned (UDMA_CACHELINE_ALIGNMENT))) __attribute__ ((section (".bss:emac_msmc_mem")));
 110 #endif
 111 #endif
 112 #endif
 113
 114 uint8_t sequenceNumber = 0;
 115
 116 uint32_t interposerCardPresent = 0;
 117
 118 #ifdef EMAC_TEST_APP_ICSSG
 119 PRUICSS_Handle prussHandle[EMAC_MAX_ICSS] = {NULL, NULL, NULL};
 120 int hs_index[EMAC_MAX_ICSS * EMAC_MAC_PORTS_PER_ICSS];    //one per icss slice
 121 #endif
 122
 123
 124 /* Test will use network firmware to verify packet transmission
 125   * and reception between 2 physical ICSSG ports, each ICSSG port needs to be connected
 126   * to another ICSSG port via ethernet cable.
 127
 128   * NOTE that for CPSW port, test will always test loopback mode of operation
 129   * with CPSW sub-system.
 130   */
 131
 132 #ifdef EMAC_TEST_APP_ICSSG
 133 /* EMAC firmware header files */
 134 typedef struct {
 135     const uint32_t *pru;
 136     uint32_t pru_size;
 137     const uint32_t *rtu;
 138     uint32_t rtu_size;
 139 } app_test_pru_rtu_fw_t;
 140
 141
 142 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii0_bin.h>      /* PDSPcode */
 143 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test0_bin.h>             /* PDSP2code */
 144 #include <ti/drv/emac/firmware/icss_dualmac/bin/rxl2_txl2_rgmii1_bin.h>      /*PDSP3code */
 145 #include <ti/drv/emac/firmware/icss_dualmac/bin/rtu_test1_bin.h>             /* PDSP4code */
 146
 147 static app_test_pru_rtu_fw_t firmware[2] = {
 148     { PDSPcode_0, sizeof(PDSPcode_0), PDSP2code_0, sizeof(PDSP2code_0) },
 149     { PDSP3code_0, sizeof(PDSP3code_0), PDSP4code_0, sizeof(PDSP4code_0) },
 150 };
 151 #endif
 152
 153 int32_t app_test_task_init_pruicss(uint32_t portNum);
 154 int32_t app_test_task_disable_pruicss(uint32_t portNum);
 155
 156
 157
 158
 159 uint32_t pollModeEnabled = 0;
 160 uint32_t linkStatus = 0;
 161 uint32_t initComplete = 0;
 162 uint32_t app_test_id = 0;
 163 #if defined (EMAC_BENCHMARK)
 164 #if defined  (EMAC_TEST_APP_ICSSG)
 165 uint32_t app_test_send_port = 4U;
 166 uint32_t app_test_recv_port = 4U;
 167 #else
 168 uint32_t app_test_send_port = 6U;
 169 uint32_t app_test_recv_port = 6U;
 170 #endif
 171 #endif
 172 #ifdef _TMS320C6X
 173 /* Memory allocated for the packet buffer. This is 128 bytes aligned. */
 174 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE];
 175 #pragma DATA_ALIGN(app_pkt_buffer, 64)
 176
 177 /* Memory allocated for the application control block */
 178 #else
 179 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 180 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64)));
 181 #else
 182 uint8_t   app_pkt_buffer[APP_TOTAL_PKTBUF_SIZE] __attribute__ ((aligned(64))) __attribute__ ((section (".bss:emac_ddr_mem")));
 183 #endif
 184 #endif
 185
 186 int32_t gFail_count;
 187
 188 int32_t testPktClone = 0;
 189 #ifndef EMAC_TEST_APP_WITHOUT_DDR
 190 #define EMAC_TEST_MAX_CHANS_PER_PORT 4
 191 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 9
 192 #else
 193 #define EMAC_TEST_MAX_CHANS_PER_PORT 1
 194 #define EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT 3
 195 #endif
 196 /*
 197  * UDMA driver objects
 198  */
 199 struct Udma_DrvObj      gUdmaDrvObj;
 200 struct Udma_ChObj       gUdmaTxChObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT];
 201 struct Udma_ChObj       gUdmaRxChObj[EMAC_MAX_PORTS];
 202 struct Udma_EventObj    gUdmaRxCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
 203
 204
 205 struct Udma_ChObj       gUdmaRxMgmtPsiChObj[EMAC_MAX_PORTS];
 206 struct Udma_EventObj    gUdmaRxMgmtPsiCqEventObj[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT];
 207
 208 Udma_DrvHandle          gDrvHandle = NULL;
 209
 210 /* Ring parameters*/
 211 /*brief Number of ring entries - we can prime this much memcpy operations */
 212 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 213 #define EMAC_TEST_APP_RING_ENTRIES      (32)
 214 #else
 215 #define EMAC_TEST_APP_RING_ENTRIES      (128)
 216 #endif
 217 /* Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
 218
 219 #define EMAC_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
 220 /* Total ring memory */
 221
 222 #define EMAC_TEST_APP_RING_MEM_SIZE     (EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_RING_ENTRY_SIZE)
 223
 224 /* UDMA host mode buffer descriptor memory size.    *  Make it multiple of 128 byte alignment */
 225 #define EMAC_TEST_APP_DESC_SIZE         (sizeof(CSL_UdmapCppi5HMPD) + (128U - sizeof(CSL_UdmapCppi5HMPD)))
 226
 227 /*
 228  * UDMA Memories
 229  */
 230 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 231 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 232 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 233 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 234 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 235 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 236 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 237 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 238 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 239 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 240 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 241 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 242 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 243 /* TX/RX ring CPPI descriptor memory */
 244 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 245 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 246 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 247 #else
 248 static uint8_t gTxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 249                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 250 static uint8_t gTxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 251                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 252 struct Udma_RingObj gUdmaRxRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 253                                             __attribute__ ((section (".bss:emac_ddr_mem")));
 254 struct Udma_RingObj gUdmaRxCompRingHnd[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 255                                             __attribute__ ((section (".bss:emac_ddr_mem")));
 256 struct Udma_FlowObj gUdmaFlowHnd[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 257                                         __attribute__ ((section (".bss:emac_ddr_mem")));
 258 struct Udma_RingObj gUdmaRxRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 259                                         __attribute__ ((section (".bss:emac_ddr_mem")));
 260 struct Udma_RingObj gUdmaRxCompRingHndCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 261                                         __attribute__ ((section (".bss:emac_ddr_mem")));
 262 static uint8_t gRxRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 263                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 264 static uint8_t gRxCompRingMem[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 265                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 266
 267 static uint8_t gRxRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 268                                         __attribute__ ((section (".bss:emac_ddr_mem")));
 269 static uint8_t gRxCompRingMemCfgPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_MEM_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 270                                          __attribute__ ((section (".bss:emac_ddr_mem")));
 271 struct Udma_FlowObj gUdmaFlowHndCfgPsi[EMAC_MAX_PORTS] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 272                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 273 /* TX/RX ring CPPI descriptor memory */
 274 static uint8_t gUdmapDescRamTx[EMAC_MAX_PORTS][EMAC_TEST_MAX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 275                                     __attribute__ ((section (".bss:emac_ddr_mem")));
 276 static uint8_t gUdmapDescRamRx[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 277                                       __attribute__ ((section (".bss:emac_ddr_mem")));
 278 static uint8_t gUdmapDescRamRxMgmtPsi[EMAC_MAX_PORTS][EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT][EMAC_TEST_APP_RING_ENTRIES * EMAC_TEST_APP_DESC_SIZE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 279                                   __attribute__ ((section (".bss:emac_ddr_mem")));
 280
 281 #endif
 282
 283
 284
 285 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 286 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 287 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 288 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 289 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)));
 290 #else
 291 EMAC_CHAN_MAC_ADDR_T chan_cfg[APP_EMAC_NUM_CHANS_PER_CORE] __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 292                                   __attribute__ ((section (".bss:emac_ddr_mem")));
 293
 294 EMAC_HwAttrs_V5 emac_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 295                                   __attribute__ ((section (".bss:emac_ddr_mem")));
 296
 297 APP_EMAC_MCB_T   app_mcb __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 298                                   __attribute__ ((section (".bss:emac_ddr_mem")));
 299
 300 EMAC_OPEN_CONFIG_INFO_T open_cfg __attribute__ ((aligned(UDMA_CACHELINE_ALIGNMENT)))
 301                                   __attribute__ ((section (".bss:emac_ddr_mem")));
 302 #endif
 303
 304 uint32_t pkt_rcv_count = 0;
 305 static volatile uint32_t pkt_received = 0;
 306 static volatile uint32_t timestamp_received = 1;
 307
 308 #ifdef UNITY_INCLUDE_CONFIG_H
 309 /*
 310  *  ======== Unity set up and tear down ========
 311  */
 312 void setUp(void)
 313 {
 314     /* Do nothing */
 315 }
 316
 317 void tearDown(void)
 318 {
 319     /* Do nothing */
 320 }
 321 #endif
 322
 323 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult);
 324
 325 /**********************************************************************
 326  ****************** Test Configuration Variables **********************
 327  **********************************************************************/
 328
 329
 330 #define APP_TEST_PKT_SEND_COUNT  16
 331 #define APP_TEST_MIN_PKT_SEND_SIZE 60
 332 #define APP_TEST_MAX_PKT_SEND_SIZE 1500
 333
 334 /* DO NOT CHANGE app_test_uc_pkt UNLESS APP_TEST_PKT_SIZE IS UPDATED */
 335 #define APP_TEST_PKT_SIZE       64
 336 static uint8_t app_test_uc_pkt[APP_TEST_PKT_SIZE] = {
 337     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
 338     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 339     0x08, 0x06, 0x00, 0x01,
 340     0x08, 0x00, 0x06, 0x04,
 341     0x00,0x01,0x01, 0xbb,
 342     0xcc, 0xdd, 0xee, 0xff,
 343     0xc0, 0xa8, 0x01, 0x16,
 344     0x00, 0x00, 0x00, 0x00,
 345     0xc0, 0xa8,0x01, 0x02,
 346     0x01,0x02,0x03,0x04,
 347     0x01,0x02,0x03,0x04,
 348     0x01,0x02,0x03,0x04,
 349     0x01,0x02,0x03,0x04,
 350     0x01,0x02,0x03,0x04,
 351     0xfe,0xfe, 0x00, 0x00
 352 };
 353 static uint8_t app_test_bc_pkt[APP_TEST_PKT_SIZE] = {
 354     0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 355     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 356     0x08, 0x06, 0x00, 0x01,
 357     0x08, 0x00, 0x06, 0x04,
 358     0x00,0x01,0x01, 0xbb,
 359     0xcc, 0xdd, 0xee, 0xff,
 360     0xc0, 0xa8, 0x01, 0x16,
 361     0x00, 0x00, 0x00, 0x00,
 362     0xc0, 0xa8,0x01, 0x02,
 363     0x01,0x02,0x03,0x04,
 364     0x01,0x02,0x03,0x04,
 365     0x01,0x02,0x03,0x04,
 366     0x01,0x02,0x03,0x04,
 367     0x01,0x02,0x03,0x04,
 368     0xfe,0xfe, 0x00, 0x00
 369 };
 370
 371 static uint8_t app_test_mc_pkt[APP_TEST_PKT_SIZE] = {
 372     0x01, 0x93, 0x20, 0x21, 0x22, 0x2a,
 373     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 374     0x08, 0x06, 0x00, 0x01,
 375     0x08, 0x00, 0x06, 0x04,
 376     0x00,0x01,0x01, 0xbb,
 377     0xcc, 0xdd, 0xee, 0xff,
 378     0xc0, 0xa8, 0x01, 0x16,
 379     0x00, 0x00, 0x00, 0x00,
 380     0xc0, 0xa8,0x01, 0x02,
 381     0x01,0x02,0x03,0x04,
 382     0x01,0x02,0x03,0x04,
 383     0x01,0x02,0x03,0x04,
 384     0x01,0x02,0x03,0x04,
 385     0x01,0x02,0x03,0x04,
 386     0xfe,0xfe, 0x00, 0x00
 387 };
 388
 389 static uint8_t mac1_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x22};
 390 static uint8_t app_test_mc1_pkt[APP_TEST_PKT_SIZE] = {
 391     0x01, 0x93, 0x20, 0x21, 0x22, 0x22,
 392     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 393     0x08, 0x06, 0x00, 0x01,
 394     0x08, 0x00, 0x06, 0x04,
 395     0x00,0x01,0x01, 0xbb,
 396     0xcc, 0xdd, 0xee, 0xff,
 397     0xc0, 0xa8, 0x01, 0x16,
 398     0x00, 0x00, 0x00, 0x00,
 399     0xc0, 0xa8,0x01, 0x02,
 400     0x01,0x02,0x03,0x04,
 401     0x01,0x02,0x03,0x04,
 402     0x01,0x02,0x03,0x04,
 403     0x01,0x02,0x03,0x04,
 404     0x01,0x02,0x03,0x04,
 405     0xfe,0xfe, 0x00, 0x00
 406 };
 407
 408
 409 static uint8_t mac2_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x24};
 410 static uint8_t mac3_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x26};
 411 static uint8_t mac4_mc[6] = {0x01, 0x93, 0x20, 0x21, 0x22, 0x28};
 412
 413
 414 static uint8_t app_test_mc2_pkt[APP_TEST_PKT_SIZE] = {
 415     0x01, 0x93, 0x20, 0x21, 0x22, 0x24,
 416     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 417     0x08, 0x06, 0x00, 0x01,
 418     0x08, 0x00, 0x06, 0x04,
 419     0x00,0x01,0x01, 0xbb,
 420     0xcc, 0xdd, 0xee, 0xff,
 421     0xc0, 0xa8, 0x01, 0x16,
 422     0x00, 0x00, 0x00, 0x00,
 423     0xc0, 0xa8,0x01, 0x02,
 424     0x01,0x02,0x03,0x04,
 425     0x01,0x02,0x03,0x04,
 426     0x01,0x02,0x03,0x04,
 427     0x01,0x02,0x03,0x04,
 428     0x01,0x02,0x03,0x04,
 429     0xfe,0xfe, 0x00, 0x00
 430 };
 431
 432 static uint8_t app_test_mc3_pkt[APP_TEST_PKT_SIZE] = {
 433     0x01, 0x93, 0x20, 0x21, 0x22, 0x26,
 434     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 435     0x08, 0x06, 0x00, 0x01,
 436     0x08, 0x00, 0x06, 0x04,
 437     0x00,0x01,0x01, 0xbb,
 438     0xcc, 0xdd, 0xee, 0xff,
 439     0xc0, 0xa8, 0x01, 0x16,
 440     0x00, 0x00, 0x00, 0x00,
 441     0xc0, 0xa8,0x01, 0x02,
 442     0x01,0x02,0x03,0x04,
 443     0x01,0x02,0x03,0x04,
 444     0x01,0x02,0x03,0x04,
 445     0x01,0x02,0x03,0x04,
 446     0x01,0x02,0x03,0x04,
 447     0xfe,0xfe, 0x00, 0x00
 448 };
 449
 450 static uint8_t app_test_mc4_pkt[APP_TEST_PKT_SIZE] = {
 451     0x01, 0x93, 0x20, 0x21, 0x22, 0x28,
 452     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 453     0x08, 0x06, 0x00, 0x01,
 454     0x08, 0x00, 0x06, 0x04,
 455     0x00,0x01,0x01, 0xbb,
 456     0xcc, 0xdd, 0xee, 0xff,
 457     0xc0, 0xa8, 0x01, 0x16,
 458     0x00, 0x00, 0x00, 0x00,
 459     0xc0, 0xa8,0x01, 0x02,
 460     0x01,0x02,0x03,0x04,
 461     0x01,0x02,0x03,0x04,
 462     0x01,0x02,0x03,0x04,
 463     0x01,0x02,0x03,0x04,
 464     0x01,0x02,0x03,0x04,
 465     0xfe,0xfe, 0x00, 0x00
 466
 467 };
 468
 469 uint8_t app_test_128_pkt[128] = {
 470         0x48, 0x93, 0xfe, 0xfa, 0x18, 0x44,
 471         0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 472         0x08, 0x06, 0x00, 0x01,
 473         0x08, 0x00, 0x06, 0x04,
 474         0x00,0x01,0x01, 0xbb,
 475         0xcc, 0xdd, 0xee, 0xff,
 476         0xc0, 0xa8, 0x01, 0x16,
 477         0x00, 0x00, 0x00, 0x00,
 478         0xc0, 0xa8,0x01, 0x02,
 479         0x01,0x02,0x03,0x04,
 480         0x01,0x02,0x03,0x04,
 481         0x01,0x02,0x03,0x04,
 482         0x01,0x02,0x03,0x04,
 483         0x01,0x02,0x03,0x04,
 484         0xfe,0xfe, 0x00, 0x00,
 485         0x48, 0x93, 0xfe, 0xfa,
 486         0x18, 0x44, 0x18, 0x4a,
 487         0x48, 0x93, 0xfe, 0xfa,
 488         0x08, 0x06, 0x00, 0x01,
 489         0x08, 0x00, 0x06, 0x04,
 490         0x00,0x01,0x01, 0xbb,
 491         0xcc, 0xdd, 0xee, 0xff,
 492         0xc0, 0xa8, 0x01, 0x16,
 493         0x00, 0x00, 0x00, 0x00,
 494         0xc0, 0xa8,0x01, 0x02,
 495         0x01,0x02,0x03,0x04,
 496         0x01,0x02,0x03,0x04,
 497         0x01,0x02,0x03,0x04,
 498         0x01,0x02,0x03,0x04,
 499         0x01,0x02,0x03,0x04,
 500         0xfe,0xfe, 0x00, 0x00
 501 };
 502
 503 static uint8_t app_test_vlan_pkt[APP_TEST_PKT_SIZE+4] = {
 504     0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 505     0x48, 0x93, 0xfe, 0xfa, 0x18, 0x4a,
 506     0x81, 0x00, 0x00,0x02,                      /* 00 is priority 0, 02 is vlanId */
 507     0x08, 0x06, 0x00, 0x01,
 508     0x08, 0x00, 0x06, 0x04,
 509     0x00,0x01,0x01, 0xbb,
 510     0xcc, 0xdd, 0xee, 0xff,
 511     0xc0, 0xa8, 0x01, 0x16,
 512     0x00, 0x00, 0x00, 0x00,
 513     0xc0, 0xa8,0x01, 0x02,
 514     0x01,0x02,0x03,0x04,
 515     0x01,0x02,0x03,0x04,
 516     0x01,0x02,0x03,0x04,
 517     0x01,0x02,0x03,0x04,
 518     0x01,0x02,0x03,0x04,
 519     0xfe,0xfe, 0x00, 0x00
 520 };
 521
 522 static uint8_t *pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
 523
 524 /**********************************************************************
 525  ************************ EMAC TEST FUNCTIONS *************************
 526  **********************************************************************/
 527
 528 /*
 529  *  ======== app_detect_interposer_card ========
 530  */
 531 bool app_detect_interposer_card(void)
 532 {
 533     EMAC_socGetInitCfg(0, &emac_cfg);
 534     CSL_MdioRegs *pBaseAddr = (CSL_MdioRegs*) (uintptr_t)(emac_cfg.portCfg[2].mdioRegsBaseAddr);
 535 #ifdef EMAC_TEST_APP_WITHOUT_DDR
 536     Task_sleep(5000);
 537 #endif
 538     if ((CSL_MDIO_isPhyAlive(pBaseAddr,emac_cfg.portCfg[2].phyAddr)) ||(CSL_MDIO_isPhyAlive(pBaseAddr,emac_cfg.portCfg[3].phyAddr)))
 539     {
 540         UART_printf("PHYs for ICSSG1 are ALIVE, interposer card is NOT present\n");
 541         return FALSE;
 542     }
 543     else
 544     {
 545         UART_printf("PHYs for ICSSG1 are not ALIVE, interposer card is present\n");
 546         return TRUE;
 547     }
 548 }
 549
 550 /**
 551  *  @b app_queue_pop
 552  *  @n
 553  *      Dequeues a packet descriptor from an app queue.
 554  *
 555  *  @param[in]  pq
 556  *      Packet queue of type APP_PKT_QUEUE_T .
 557  *
 558  *  @retval
 559  *      EMAC_Pkt popped from the queue.
 560  */
 561 EMAC_PKT_DESC_T*
 562 app_queue_pop
 563 (
 564     uint32_t              port_num,
 565     APP_PKT_QUEUE_T*    pq
 566 )
 567 {
 568     EMAC_PKT_DESC_T*    pPktHdr;
 569 #ifndef EMAC_BENCHMARK
 570     uintptr_t key;
 571 #endif
 572     if (!pq->Count)
 573     {
 574         return 0;
 575     }
 576 #ifndef EMAC_BENCHMARK
 577     key = EMAC_osalHardwareIntDisable();
 578 #endif
 579
 580     pPktHdr = pq->pHead;
 581     if( pPktHdr )
 582     {
 583         pq->pHead = pPktHdr->pNext;
 584         pq->Count--;
 585         pPktHdr->pPrev = pPktHdr->pNext = 0;
 586     }
 587 #ifndef EMAC_BENCHMARK
 588     EMAC_osalHardwareIntRestore(key);
 589 #endif
 590
 591     return( pPktHdr );
 592 }
 593
 594 /**
 595  *  @b app_queue_push
 596  *  @n
 597  *      Enqueues a packet in EMAC_Pkt queue.
 598  *
 599  *  @param[in]  pq
 600  *      Packet queue of type EMAC_PKT_QUEUE_T .
 601  *  @param[in]  pPktHdr
 602  *      EMAC_PKT_DESC_T type packet to push.
 603  *
 604  *  @retval
 605  *      void
 606  */
 607 void
 608 app_queue_push
 609 (
 610     uint32_t              port_num,
 611     APP_PKT_QUEUE_T*    pq,
 612     EMAC_PKT_DESC_T*    pPktHdr
 613 )
 614 {
 615 #ifndef EMAC_BENCHMARK
 616     uintptr_t key;
 617     key = EMAC_osalHardwareIntDisable();
 618 #endif
 619     pPktHdr->pNext = 0;
 620
 621     if( !pq->pHead )
 622     {
 623         /* Queue is empty - Initialize it with this one packet */
 624         pq->pHead = pPktHdr;
 625         pq->pTail = pPktHdr;
 626     }
 627     else
 628     {
 629         /* Queue is not empty - Push onto end */
 630         pq->pTail->pNext = pPktHdr;
 631         pq->pTail        = pPktHdr;
 632     }
 633     pq->Count++;
 634 #ifndef EMAC_BENCHMARK
 635     EMAC_osalHardwareIntRestore(key);
 636 #endif
 637 }
 638
 639 uint32_t allocCount = 0;
 640 uint32_t allocFailed = 0;
 641 uint32_t gAppAllocFailure = 0;
 642
 643 #ifndef EMAC_TEST_ALLOC_FAIL
 644 /**
 645  *  @b Description
 646  *  @n
 647  *      Call back function provided by application for EMAC driver
 648  *      to allocate a packet descriptor.
 649  *
 650  *  @retval
 651  *      pointer to the allocated packet descriptor.
 652  */
 653  EMAC_PKT_DESC_T*
 654 app_alloc_pkt
 655 (
 656     uint32_t              port_num,
 657     uint32_t              pkt_size
 658 )
 659 {
 660     EMAC_PKT_DESC_T*    p_pkt_desc = NULL;
 661     if (pkt_size <= APP_EMAC_MAX_PKT_SIZE)
 662     {
 663         /* Get a packet descriptor from the free queue */
 664         p_pkt_desc              = app_queue_pop(port_num, &app_mcb.emac_pcb[port_num].freeQueue);
 665         if(p_pkt_desc)
 666         {
 667             p_pkt_desc->AppPrivate  = (uintptr_t)p_pkt_desc;
 668             p_pkt_desc->BufferLen   = APP_EMAC_MAX_PKT_SIZE;
 669             p_pkt_desc->DataOffset  = 0;
 670             p_pkt_desc->pPrev = NULL;
 671             p_pkt_desc->pNext = NULL;
 672         }
 673         else
 674             gAppAllocFailure++;
 675     }
 676     else
 677     {
 678         UART_printf ("app_alloc_pkt on port %d failed, packet size %d is too big\n", port_num, pkt_size);
 679         return NULL;
 680     }
 681     return p_pkt_desc;
 682 }
 683 #else
 684 #endif
 685
 686 /**
 687  *  @b Description
 688  *  @n
 689  *      Call back function provided by application for EMAC driver
 690  *      to free a packet descriptor.
 691  *
 692  *  @retval
 693  *      None.
 694  */
 695 void
 696 app_free_pkt
 697 (
 698     uint32_t              port_num,
 699     EMAC_PKT_DESC_T*    p_pkt_desc
 700 )
 701 {
 702     /* Free a packet descriptor to the free queue */
 703     app_queue_push(port_num, &app_mcb.emac_pcb[port_num].freeQueue,
 704                    (EMAC_PKT_DESC_T *)p_pkt_desc->AppPrivate);
 705 }
 706
 707
 708
 709 /**
 710 *  @b Description
 711 *  @n
 712 *      Intialize the application control block, free/rx packet queue.
 713 *
 714 *  @retval
 715 *      None.
 716 */
 717 void
 718 app_init(void)
 719 {
 720     uint32_t            i, j;
 721     EMAC_PKT_DESC_T*    p_pkt_desc;
 722     uint8_t*            pktbuf_ptr;
 723
 724     UART_printf ("EMAC loopback test application initialization\n");
 725
 726     /* Reset application control block */
 727     memset(&app_mcb, 0, sizeof (APP_EMAC_MCB_T));
 728
 729 #ifdef _TMS320C6X
 730     app_mcb.core_num = CSL_chipReadReg (CSL_CHIP_DNUM);
 731 #else
 732     app_mcb.core_num = 0;
 733 #endif
 734     pktbuf_ptr = (uint8_t *) ((uintptr_t) app_pkt_buffer);
 735     /* Initialize the free packet queue */
 736     for (i=portNum; i <=endPort; i++)
 737     {
 738         if (!port_en[i])
 739             continue;
 740 #ifndef EMAC_BENCHMARK
 741         for (j=0; j<APP_MAX_PKTS/MAX_NUM_EMAC_PORTS; j++)
 742 #else
 743         for (j=0; j<(APP_MAX_PKTS); j++)
 744 #endif
 745         {
 746             p_pkt_desc               = &app_mcb.emac_pcb[i].pkt_desc[j];
 747             p_pkt_desc->pDataBuffer  = pktbuf_ptr;
 748             p_pkt_desc->BufferLen    = APP_EMAC_MAX_PKT_SIZE;
 749             app_queue_push( i, &app_mcb.emac_pcb[i].freeQueue, p_pkt_desc );
 750             pktbuf_ptr += APP_EMAC_MAX_PKT_SIZE;
 751         }
 752     }
 753 }
 754
 755 /******************************************************************************
 756  * Function: Test EMAC_IOCTL_VLAN_CTRL command
 757  ******************************************************************************/
 758 /**
 759  *  @brief  send IOCTL command to create default table
 760  */
 761 void app_test_vlan_ctrl_set_default_tbl(void)
 762 {
 763     EMAC_IOCTL_PARAMS params;
 764     /* send packet only to the host */
 765     EMAC_IOCTL_VLAN_FID_PARAMS vlanParams = {/*.fid = */0, /*.host_member =*/ 1, /*.p1_member =*/ 1,  /*.p2_member =*/ 0, \
 766                           /*.host_tagged = */0, /*.p1_tagged = */0, /*.p2_tagged = */0, /*.stream_vid =*/ 0, /*.flood_to_host = */0};
 767     params.subCommand = EMAC_IOCTL_VLAN_SET_DEFAULT_TBL;
 768     params.ioctlVal = (void*)&vlanParams;
 769
 770     app_test_id++;
 771     emac_ioctl(EMAC_SWITCH_PORT,EMAC_IOCTL_VLAN_CTRL,(void*)(&params));
 772 }
 773
 774 /******************************************************************************
 775  * Function: Test EMAC_IOCTL_VLAN_CTRL command
 776  ******************************************************************************/
 777 /**
 778  *  @brief  send IOCTL command set tble entry
 779  */
 780 int32_t app_test_vlan_ctrl_set_tbl_entry(uint32_t portNum, uint8_t fid, uint16_t tblIndex, EMAC_IOCTL_VLAN_FID_PARAMS *pVlanParams)
 781 {
 782     int32_t retVal;
 783     EMAC_IOCTL_PARAMS params;
 784     EMAC_IOCTL_VLAN_FID_ENTRY vlanEntry = {0};
 785     /* send packet only to the host */
 786
 787     params.subCommand = EMAC_IOCTL_VLAN_SET_ENTRY;
 788     params.ioctlVal = (void*)&vlanEntry;
 789     memcpy(&vlanEntry.vlanFidPrams, pVlanParams, sizeof(EMAC_IOCTL_VLAN_FID_PARAMS));
 790
 791     vlanEntry.vlanFidPrams.fid = fid;
 792     vlanEntry.vlanId = tblIndex;
 793     retVal = emac_ioctl(portNum,EMAC_IOCTL_VLAN_CTRL,(void*)(&params));
 794     return retVal;
 795 }
 796
 797 #if defined (EMAC_BENCHMARK)
 798 uint32_t app_test_send_fail = 0;
 799 uint32_t app_test_alloc_fail = 0;
 800
 801 /******************************************************************************
 802  * Function: EMAC test loopback packet
 803  ******************************************************************************/
 804 /**
 805  *  @brief  This function is used to loopback the pkt received to sender
 806  */
 807 void app_test_loopback_pkt(uint32_t portNum, EMAC_PKT_DESC_T* pDesc)
 808 {
 809     EMAC_DRV_ERR_E sentRetVal;
 810     uint8_t* temp;
 811     EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(portNum, APP_EMAC_MAX_PKT_SIZE);
 812     if (p_pkt_desc == NULL)
 813     {
 814         UART_printf("app_test_loopback_pkt: app alloc pkt failed\n");
 815         app_test_alloc_fail++;
 816     }
 817     else
 818     {
 819         temp = p_pkt_desc->pDataBuffer; // temp is now buffer
 820
 821         p_pkt_desc->pDataBuffer = pDesc->pDataBuffer;
 822         pDesc->pDataBuffer = temp;
 823
 824         p_pkt_desc->AppPrivate = (uint32_t)p_pkt_desc;
 825         p_pkt_desc->ValidLen     = pDesc->PktLength-4;
 826         p_pkt_desc->DataOffset   = 0;
 827         p_pkt_desc->PktLength    = pDesc->PktLength-4;
 828         p_pkt_desc->PktFrags     = 1;
 829         p_pkt_desc->pNext = NULL;
 830         p_pkt_desc->pPrev = NULL;
 831         p_pkt_desc->PktChannel     = 0;
 832         p_pkt_desc->PktLength      = pDesc->PktLength-4;
 833         sentRetVal = emac_send(portNum, p_pkt_desc);
 834         if(sentRetVal != EMAC_DRV_RESULT_OK)
 835         {
 836             app_test_send_fail++;
 837             app_free_pkt(portNum,p_pkt_desc);
 838         }
 839     }
 840 }
 841 #endif
 842
 843
 844 /******************************************************************************
 845  * Function: EMAC RX packet call back function
 846  ******************************************************************************/
 847 /**
 848  *  @brief  This function is used to call back the network application when a
 849  *          packet is received.
 850  */
 851 void app_test_rx_pkt_cb(uint32_t port_num, EMAC_PKT_DESC_T* p_desc)
 852 {
 853 #if !defined (EMAC_BENCHMARK)
 854     uint32_t i;uint32_t *pCfgPkt;
 855         if(p_desc->BufferLen == 16)
 856         {
 857             UART_printf("app_test_rx_pkt_cb:port: %d: received the following response begin\n", port_num);
 858             pCfgPkt = (uint32_t*)&p_desc->pDataBuffer[0];
 859             for (i = 0; i < 4; i++)
 860                 UART_printf("0x%08x ", pCfgPkt[i]);
 861
 862             UART_printf("\napp_test_rx_pkt_cb:port: %d: received the following response end\n", port_num);
 863
 864             if (p_desc->AppPrivate != 0U)
 865             {
 866                 app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
 867             }
 868         }
 869         else
 870         {
 871             if (memcmp(p_desc->pDataBuffer, pTestPkt, APP_TEST_PKT_SIZE) == 0)
 872             {
 873                 pkt_rcv_count++;
 874                 if (port_num != 6)
 875                     UART_printf("app_test_rx_pkt_cb: port %d: received packet %d, rx timestamp:  0x%x%08x\n",
 876                                             port_num,
 877                                             pkt_rcv_count,
 878                                             (unsigned int)(p_desc->RxTimeStamp >> 32),
 879                                             (unsigned int)(p_desc->RxTimeStamp & 0xFFFFFFFF));
 880                 else
 881                     UART_printf("app_test_rx_pkt_cb: port %d: received packet %d\n",port_num, pkt_rcv_count);
 882             }
 883             else
 884             {
 885                 UART_printf("app_test_rx_pkt_cb: port %u: packet match failed\n", port_num);
 886                 while(1);
 887             }
 888             if (p_desc->AppPrivate != 0U)
 889             {
 890                 app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
 891             }
 892             pkt_received = 1;
 893         }
 894 #else
 895         if (p_desc->AppPrivate != 0U)
 896         {
 897             if (port_num != 6)
 898
 899             app_test_loopback_pkt(app_test_send_port,p_desc);
 900             app_free_pkt(port_num,  (EMAC_PKT_DESC_T*) p_desc->AppPrivate);
 901             pkt_received = 1;
 902         }
 903         pkt_rcv_count++;
 904 #endif
 905 }
 906
 907
 908
 909 /******************************************************************************
 910 * Function: EMAC RX timestamp_response back function
 911 ******************************************************************************/
 912 /**
 913 *  @brief  This function is used to call back the network application when a
 914 *          timestamp response packet is receive from ICSSG firmware.
 915 */
 916 void app_test_ts_response_cb(uint32_t port_num, uint32_t ts_id, uint64_t ts, bool is_valid)
 917 {
 918     UART_printf("app_test_ts_response_cb: port %d: tx timestamp id: 0x%x, tx timestamp: 0x%x%08x is_valid: %d\n",
 919                             port_num,
 920                             ts_id,
 921                             (unsigned int)(ts >> 32),
 922                             (unsigned int)(ts& 0xFFFFFFFF),
 923                             is_valid);
 924     timestamp_received = 1;
 925
 926 }
 927 void app_test_task_poll_pkt (UArg arg0, UArg arg1)
 928 {
 929     uint32_t port = (uint32_t) arg0;
 930     linkStatus = 1;
 931     while(initComplete == 0)
 932     {
 933         Task_sleep(1);
 934     }
 935     UART_printf("polling rx packets on port: %d\n", port);
 936     while(1)
 937     {
 938         if (pollModeEnabled == 0)
 939         {
 940             emac_poll_pkt(port);
 941 #ifndef EMAC_BENCHMARK
 942             Task_sleep(5);
 943             if (pkt_rcv_count == APP_TEST_PKT_SEND_COUNT)
 944                 break;
 945 #endif
 946         }
 947         else
 948         {
 949             break;
 950         }
 951     }
 952 }
 953
 954 void app_test_task_poll_ctrl (UArg arg0, UArg arg1)
 955 {
 956     uint32_t port = (uint32_t) arg0;
 957 #ifdef EMAC_TEST_APP_ICSSG
 958     uint32_t mgmtRings =0x7;
 959     uint32_t pktRings =0x1ff;
 960     uint32_t txRings = 0xf;
 961 #else
 962     uint32_t mgmtRings =0x0;
 963     uint32_t pktRings =0x1;
 964     uint32_t txRings = 0x0;
 965 #endif
 966     linkStatus = 1;
 967     while(initComplete == 0)
 968     {
 969         Task_sleep(1);
 970     }
 971
 972     UART_printf("polling all pkts on port: %d\n", port);
 973     while(1)
 974     {
 975         if (pollModeEnabled == 1)
 976             emac_poll_ctrl(port, pktRings,mgmtRings,txRings);
 977         else
 978             emac_poll_ctrl(port, 0,0,txRings);
 979         Task_sleep(2);
 980     }
 981 }
 982
 983 int32_t emac_send_fail = 0;
 984
 985
 986 int32_t app_test_send(uint32_t pNum, uint8_t* pPkt, uint32_t pktChannel, uint32_t pktSize)
 987 {
 988     uint32_t i;
 989     static uint32_t pkt_send_count =0;
 990     EMAC_DRV_ERR_E sentRetVal;
 991
 992     gFail_count = 0;
 993     for (i = 0; i < APP_TEST_PKT_SEND_COUNT/2; i++)
 994     {
 995
 996         EMAC_PKT_DESC_T *p_pkt_desc = app_alloc_pkt(pNum, pktSize);
 997         if (p_pkt_desc == NULL)
 998         {
 999             UART_printf("app_test_send: app alloc pkt failed\n");
1000             while(1);
1001         }
1002         memcpy (p_pkt_desc->pDataBuffer, pPkt, pktSize);
1003         p_pkt_desc->AppPrivate = (uintptr_t)p_pkt_desc;
1004         /* only enable TX timestamp when in poll mode of operation, currently not support for SWITCH use case */
1005         if (pollModeEnabled)
1006         {
1007             if (pNum != EMAC_CPSW_PORT_NUM)
1008             {
1009                 p_pkt_desc->Flags = EMAC_PKT_FLAG_TX_TS_REQ;
1010                 p_pkt_desc->TxtimestampId = pNum + i;
1011                 timestamp_received = 0;
1012             }
1013         }
1014         p_pkt_desc->TxPktTc = i % 8;
1015         p_pkt_desc->ValidLen     = pktSize;
1016         p_pkt_desc->DataOffset   = 0;
1017         p_pkt_desc->PktLength    = pktSize;
1018         p_pkt_desc->PktFrags     = 1;
1019         p_pkt_desc->pNext = NULL;
1020         p_pkt_desc->pPrev = NULL;
1021         p_pkt_desc->PktChannel     = pktChannel;
1022         p_pkt_desc->PktLength      = pktSize;
1023         sentRetVal = emac_send(pNum, p_pkt_desc);
1024         if(sentRetVal != EMAC_DRV_RESULT_OK)
1025         {
1026             UART_printf("app_test_send: emac send on port failed with status: : %d: retVal %d, pkt_count: %d\n", pNum, sentRetVal, i+1);
1027             app_free_pkt(pNum,p_pkt_desc);
1028             emac_send_fail++;
1029         }
1030
1031 #if !defined(EMAC_BENCHMARK)
1032
1033     while((pkt_received == 0) || (timestamp_received == 0))
1034     {
1035         Task_sleep(100);
1036     }
1037 #endif
1038
1039         pkt_received = 0;
1040         pkt_send_count++;
1041
1042     }
1043     return gFail_count;
1044 }
1045
1046 void app_test_pkt_clone(void)
1047 {
1048     int32_t status;
1049     testPktClone = 1;
1050     app_test_id++;
1051     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1052     UART_printf("EMAC_UT_%d begin: app_test_pkt_clone\n", app_test_id);
1053     status = app_test_send_receive(portNum, endPort,0);
1054     if(status == 0)
1055         UART_printf("EMAC_UT_%d begin: app_test_pkt_clone passed\n", app_test_id);
1056     testPktClone = 0;
1057
1058 }
1059 void app_test_port_mac(void)
1060 {
1061     int32_t status;
1062     app_test_id++;
1063     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1064     UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC\n", app_test_id);
1065     status = app_test_send_receive(portNum, endPort,0);
1066     if(status == 0)
1067         UART_printf("EMAC_UT_%d begin: sending UC packet with PORT_MAC passed\n", app_test_id);
1068
1069     app_test_id++;
1070     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1071     UART_printf("EMAC_UT_%d begin: sending BC packet\n", app_test_id);
1072     status = app_test_send_receive(portNum, endPort,0);
1073     if(status == 0)
1074         UART_printf("EMAC_UT_%d begin: sending BC packet passed\n", app_test_id);
1075 }
1076 void app_test_interrrupt_mode(void)
1077 {
1078     app_test_id++;
1079     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1080     UART_printf("EMAC_UT_%d begin test interrupt mode\n", app_test_id);
1081     app_test_send_receive(portNum, endPort,0);
1082     UART_printf("EMAC_UT_%d begin test interrupt mode passed\n", app_test_id);
1083 }
1084
1085 void app_test_tx_chans(void)
1086 {
1087     app_test_id++;
1088     uint32_t pNum;
1089     uint32_t txChannel;
1090     UART_printf("EMAC_UT_%d begin test_multiple tx chans mode\n", app_test_id);
1091     for (pNum = portNum; pNum  <= endPort; pNum++)
1092     {
1093         if (!port_en[pNum])
1094             continue;
1095
1096         if (1 == interposerCardPresent)
1097         {
1098             if((pNum == 0) || (pNum == 2) ||  (pNum == 6))
1099                  continue;
1100         }
1101         for (txChannel = 0; txChannel < 4;txChannel++)
1102         {
1103             app_test_send(pNum, pTestPkt, txChannel, APP_TEST_PKT_SIZE);
1104         }
1105     }
1106
1107     UART_printf("EMAC_UT_%d end test_multiple tx chans mode\n", app_test_id);
1108
1109 }
1110
1111 void app_test_poll_mode(void)
1112 {
1113     pollModeEnabled = 1;
1114     app_test_id++;
1115     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1116     UART_printf("EMAC_UT_%d begin test poll mode\n", app_test_id);
1117     app_test_send_receive(portNum, endPort,0);
1118     UART_printf("EMAC_UT_%d begin test poll mode passed\n", app_test_id);
1119 }
1120
1121 void app_test_multi_flows(void)
1122 {
1123     uint32_t pNum;
1124     EMAC_IOCTL_PARAMS params;
1125     EMAC_MAC_ADDR_T macAddrs[4];
1126
1127     memcpy (&macAddrs[0], &mac1_mc[0], sizeof(EMAC_MAC_ADDR_T));
1128     memcpy (&macAddrs[1], &mac2_mc[0], sizeof(EMAC_MAC_ADDR_T));
1129     memcpy (&macAddrs[2], &mac3_mc[0], sizeof(EMAC_MAC_ADDR_T));
1130     memcpy (&macAddrs[3], &mac4_mc[0], sizeof(EMAC_MAC_ADDR_T));
1131
1132     params.ioctlVal = (void*)&macAddrs[0];
1133
1134     for (pNum =portNum; pNum  <= endPort; pNum++)
1135     {
1136         if ((!port_en[pNum]) || (pNum == 6))
1137             continue;
1138         emac_ioctl(pNum,EMAC_IOCTL_TEST_MULTI_FLOW,(void*)(&params));
1139     }
1140     for (pNum =portNum; pNum  <= endPort; pNum++)
1141     {
1142         if (1 == interposerCardPresent)
1143         {
1144             if((pNum == 0) || (pNum == 2) ||  (pNum == 6))
1145                 continue;
1146         }
1147         if (!port_en[pNum])
1148             continue;
1149         pTestPkt = (uint8_t*)(&app_test_mc1_pkt[0]);
1150         app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1151
1152         pTestPkt = (uint8_t*)(&app_test_mc2_pkt[0]);
1153         app_test_send(pNum, pTestPkt, 0, APP_TEST_PKT_SIZE);
1154
1155         pTestPkt = (uint8_t*)(&app_test_mc3_pkt[0]);
1156         app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1157
1158         pTestPkt = (uint8_t*)(&app_test_mc4_pkt[0]);
1159         app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1160     }
1161
1162 }
1163
1164 void app_test_multiple_rx_flows(void)
1165 {
1166     uint32_t pktSize;
1167     uint8_t pcp;
1168     EMAC_IOCTL_VLAN_FID_PARAMS vlanParams = {/*.fid = */0, /*.host_member =*/ 1, /*.p1_member =*/ 1,  /*.p2_member =*/ 0, \
1169                               /*.host_tagged = */0, /*.p1_tagged = */0, /*.p2_tagged = */0, /*.stream_vid =*/ 0, /*.flood_to_host = */0};
1170
1171     app_test_vlan_ctrl_set_tbl_entry(0, 0, 2, &vlanParams);
1172     app_test_vlan_ctrl_set_tbl_entry(2, 0, 2, &vlanParams);
1173     /* Start sending packet to verify local injection and host egress */
1174     //pTestPkt = (uint8_t*)(&app_test_vlan_pkt[0]);
1175     pktSize = APP_TEST_PKT_SIZE+4;
1176     for (pcp = 0;pcp < 8; pcp++)
1177     {
1178         app_test_vlan_pkt[14] = pcp << 5;
1179         pTestPkt = (uint8_t*)(&app_test_vlan_pkt[0]);
1180         /* want to go out on ICSSG0 port 1, need to use emac port  0*/
1181         app_test_send(0, pTestPkt, 0, pktSize);
1182     }
1183
1184 }
1185
1186 int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayResult)
1187 {
1188     uint32_t pNum;
1189     int32_t status = 0;
1190     for (pNum = startP; pNum  <= endP; pNum++)
1191     {
1192         if (!port_en[pNum])
1193             continue;
1194
1195         if (1 == interposerCardPresent)
1196         {
1197             if((pNum == 0) || (pNum == 2))
1198                  continue;
1199         }
1200         UART_printf("app_test_send_receive: testing port: %d\n", pNum);
1201         status = app_test_send(pNum, pTestPkt, 0,APP_TEST_PKT_SIZE);
1202
1203         if ((pNum == endPort) && (displayResult == 1))
1204         {
1205             UART_printf("All tests have passed\n");
1206         }
1207     }
1208     return status;
1209 }
1210
1211 #define TX_BUFF_POOL_SIZE 0X1800u
1212 #define TX_BUFF_POOL_TOTAL_DUAL_MAC (TX_BUFF_POOL_SIZE + 0x80) * 8U /* //50176 per PORT, total of 100352 */
1213 void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
1214 {
1215     EMAC_FW_APP_CONFIG *pFwAppCfg;
1216     emacGetDualMacFwAppInitCfg(port_num, &pFwAppCfg);
1217     if ((port_num % 2) == 0)
1218     {
1219         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num >> 1][0]);
1220     }
1221     else
1222     {
1223         pFwAppCfg->txPortQueueLowAddr = 0xFFFFFFFF & ((uintptr_t) &icss_tx_port_queue[port_num >> 1][TX_BUFF_POOL_TOTAL_DUAL_MAC]);
1224     }
1225
1226     pFwAppCfg->txPortQueueHighAddr = 0;
1227
1228     emacSetDualMacFwAppInitCfg(port_num, pFwAppCfg);
1229
1230     /* Need to update the emac configuraiton with  function required by the driver to get the FW configuration to write to shared mem */
1231     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
1232
1233 }
1234
1235 int32_t app_test_emac_open(uint32_t mode)
1236 {
1237     EMAC_socGetInitCfg(0, &emac_cfg);
1238     int32_t chanNum = 0;
1239     int32_t subChanNum = 0;
1240     uint32_t pNum;
1241     EMAC_MAC_ADDR_T macTest;
1242     app_test_id++;
1243     UART_printf("EMAC_UT_%d begin, test emac open\n", app_test_id);
1244
1245 #ifdef EMAC_TEST_APP_ICSSG
1246     for (pNum = portNum; pNum <= endPort; pNum++)
1247     {
1248         if (!port_en[pNum])
1249             continue;
1250         app_test_task_disable_pruicss(pNum);
1251     }
1252 #endif
1253
1254     for (pNum = portNum; pNum <= endPort; pNum++)
1255     {
1256         if (!port_en[pNum])
1257             continue;
1258 #if defined(EMAC_TEST_APP_WITHOUT_DDR) || defined(EMAC_BENCHMARK)
1259     emac_cfg.portCfg[pNum].nTxChans = 1U;
1260     emac_cfg.portCfg[pNum].rxChannel.nsubChan = 1U;
1261     emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan = EMAC_TEST_MAX_SUB_RX_CHANS_PER_PORT;
1262     emac_cfg.portCfg[pNum].rxChannel2CfgOverPSI.nsubChan = 0;
1263 #endif
1264         for (chanNum = 0; chanNum < emac_cfg.portCfg[pNum].nTxChans; chanNum++)
1265         {
1266             emac_cfg.portCfg[pNum].txChannel[chanNum].chHandle = (void *)&gUdmaTxChObj[pNum][chanNum];
1267             emac_cfg.portCfg[pNum].txChannel[chanNum].freeRingMem= (void*)&gTxRingMem[pNum][chanNum][0];
1268             emac_cfg.portCfg[pNum].txChannel[chanNum].compRingMem= (void*)&gTxCompRingMem[pNum][chanNum][0];
1269             emac_cfg.portCfg[pNum].txChannel[chanNum].hPdMem = (void*)&gUdmapDescRamTx[pNum][chanNum][0];
1270         }
1271         emac_cfg.portCfg[pNum].rxChannel.chHandle = (void *)&gUdmaRxChObj[pNum];
1272         emac_cfg.portCfg[pNum].rxChannel.flowHandle= (void *)&gUdmaFlowHnd[pNum];
1273         /* each subChan is a flow which is required 1 ring pair, subChanNum 0 is used for default flow*/
1274         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannel.nsubChan; subChanNum++)
1275         {
1276             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMem[pNum][subChanNum][0];
1277             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHnd[pNum][subChanNum];
1278             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMem[pNum][subChanNum][0];
1279             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHnd[pNum][subChanNum];
1280             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRx[pNum][subChanNum][0];
1281             emac_cfg.portCfg[pNum].rxChannel.subChan[subChanNum].eventHandle = (void *)&gUdmaRxCqEventObj[pNum][subChanNum];
1282         }
1283
1284         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.chHandle = (void *)&gUdmaRxMgmtPsiChObj[pNum];
1285         emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.flowHandle= (void *)&gUdmaFlowHndCfgPsi[pNum];
1286         for (subChanNum = 0; subChanNum < emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.nsubChan; subChanNum++)
1287         {
1288             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingMem[0] = (void*)&gRxRingMemCfgPsi[pNum][subChanNum][0];
1289             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].freeRingHandle[0] = (void*)&gUdmaRxRingHndCfgPsi[pNum][subChanNum];
1290             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingMem= (void*)&gRxCompRingMemCfgPsi[pNum][subChanNum][0];
1291             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].compRingHandle= (void*)&gUdmaRxCompRingHndCfgPsi[pNum][subChanNum];
1292             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].hPdMem[0] = (void*)&gUdmapDescRamRxMgmtPsi[pNum][subChanNum][0];
1293             emac_cfg.portCfg[pNum].rxChannelCfgOverPSI.subChan[subChanNum].eventHandle = (void *)&gUdmaRxMgmtPsiCqEventObj[pNum][subChanNum];
1294         }
1295     }
1296
1297     for (pNum = portNum; pNum <= endPort; pNum++)
1298     {
1299         if (!port_en[pNum])
1300             continue;
1301         if (pNum != EMAC_PORT_CPSW)
1302         {
1303
1304 #ifdef EMAC_TEST_APP_ICSSG
1305             app_test_setup_fw_dualmac(pNum, &emac_cfg);
1306 #endif
1307         }
1308         EMAC_socSetInitCfg(0, &emac_cfg);
1309         EMAC_socGetInitCfg(0, &emac_cfg);
1310
1311         open_cfg.hwAttrs = (void*)&emac_cfg;
1312         open_cfg.alloc_pkt_cb = app_alloc_pkt;
1313         open_cfg.free_pkt_cb = app_free_pkt;
1314         open_cfg.rx_pkt_cb = app_test_rx_pkt_cb;
1315         open_cfg.tx_ts_cb = app_test_ts_response_cb;
1316         open_cfg.loop_back = 0U;
1317         /* Only need to enbale loopback for CPSW test application and when not doing benchmark testing */
1318 #ifndef EMAC_BENCHMARK
1319         if (pNum == EMAC_PORT_CPSW)
1320         {
1321             open_cfg.loop_back = 1U;
1322         }
1323         open_cfg.num_of_rx_pkt_desc = 8U;
1324         open_cfg.num_of_tx_pkt_desc = 8U;
1325 #else
1326         open_cfg.num_of_rx_pkt_desc = 128U;
1327         open_cfg.num_of_tx_pkt_desc = 128U;
1328 #endif
1329         open_cfg.master_core_flag = 1;
1330         open_cfg.max_pkt_size = APP_EMAC_MAX_PKT_SIZE;
1331         open_cfg.mdio_flag = 1;
1332         open_cfg.num_of_chans = 1;
1333         open_cfg.udmaHandle = (void*)gDrvHandle;
1334
1335         macTest.addr[0] = 0x48;
1336         macTest.addr[1] = 0x93;
1337         macTest.addr[2] = 0xfe;
1338         macTest.addr[3] = 0xfa;
1339         macTest.addr[4] = 0x18;
1340         macTest.addr[5] = 0x44;
1341
1342         open_cfg.p_chan_mac_addr = &chan_cfg[0];
1343         /* Set the channel configuration */
1344         chan_cfg[0].chan_num = 0;
1345         chan_cfg[0].num_of_mac_addrs = 1;
1346         chan_cfg[0].p_mac_addr = & macTest;
1347         open_cfg.mode_of_operation = mode;
1348
1349         if (emac_open(pNum, &open_cfg) == EMAC_DRV_RESULT_OK)
1350         {
1351             UART_printf("main: emac_open sucess for port %d\n", pNum);
1352 #ifdef EMAC_TEST_APP_ICSSG
1353             app_test_task_init_pruicss(pNum);
1354 #endif
1355         }
1356         else
1357         {
1358             UART_printf("main: emac_open failure for port: %d\n",pNum);
1359             return -1;
1360         }
1361
1362     }
1363     UART_printf("EMAC_UT_%d end, test emac open passed\n", app_test_id);
1364
1365     return 0;
1366 }
1367
1368 int32_t  app_test_emac_close(void)
1369 {
1370     app_test_id++;
1371     UART_printf("EMAC_UT_%d begin, test emac close\n", app_test_id);
1372
1373     uint32_t pNum;
1374     for (pNum = portNum; pNum  <= endPort; pNum++)
1375     {
1376         if (!port_en[pNum])
1377             continue;
1378         if (emac_close(pNum) == EMAC_DRV_RESULT_OK)
1379         {
1380             UART_printf("app_test_emac_close: emac close for port %d success\n", pNum);
1381         }
1382         else
1383         {
1384             UART_printf("app_test_emac_close: emac close for port %d failed\n", pNum);
1385             return -1;
1386         }
1387     }
1388     UART_printf("EMAC_UT_%d end, test emac close\n", app_test_id);
1389     return 0;
1390
1391 }
1392
1393 void app_test_config_promiscous_mode(uint32_t enable)
1394 {
1395     uint32_t pNum;
1396     uint32_t promisEnableFlag = 0;
1397     EMAC_IOCTL_PARAMS params;
1398
1399     if (enable == 1)
1400         promisEnableFlag = 1;
1401     params.ioctlVal = (void*)(&promisEnableFlag);
1402
1403     for (pNum =portNum; pNum  <= endPort; pNum++)
1404     {
1405         if ((!port_en[pNum]) || (pNum == 6))
1406             continue;
1407         emac_ioctl(pNum,EMAC_IOCTL_PROMISCOUS_MODE_CTRL,(void*)(&params));
1408     }
1409
1410 }
1411
1412 void  app_test_promiscous_mode(void)
1413 {
1414     app_test_id++;
1415     UART_printf("EMAC_UT_%d begin test promiscous mode\n", app_test_id);
1416
1417     pTestPkt = (uint8_t*)(&app_test_mc_pkt[0]);
1418     app_test_send_receive(portNum, endPort, 0);
1419     UART_printf("app_test_promiscous_mode with MC pkt success\n");
1420     pTestPkt = (uint8_t*)(&app_test_bc_pkt[0]);
1421     app_test_send_receive(portNum, endPort, 0);
1422     UART_printf("app_test_promiscous_mode with BC pkt success\n");
1423
1424     pTestPkt = (uint8_t*)(&app_test_uc_pkt[0]);
1425     app_test_send_receive(portNum, endPort, 0);
1426     UART_printf("app_test_promiscous_mode with UC  pkt success\n");
1427
1428     UART_printf("EMAC_UT_%d test poll promiscous passed\n", app_test_id);
1429 }
1430
1431 void emac_test_get_icssg_stats(void)
1432 {
1433     uint32_t pNum;
1434     EMAC_STATISTICS_ICSSG_T stats;
1435     app_test_id++;
1436
1437     UART_printf("EMAC_UT_%d begin collecting icssg stats\n", app_test_id);
1438     for (pNum = portNum; pNum  <= endPort; pNum++)
1439     {
1440         if (!port_en[pNum])
1441             continue;
1442         memset(&stats, 0, sizeof(EMAC_STATISTICS_ICSSG_T));
1443         if (emac_get_statistics_icssg(pNum, &stats, 0) == EMAC_DRV_RESULT_OK)
1444         {
1445             UART_printf("port:%d: rx packets:          %d, tx packets:        %d\n", pNum, stats.RxGoodFrames, stats.TXGoodFrame);
1446         }
1447         else
1448         {
1449             UART_printf("emac_test_get_icssg_stats: emac_get_statistics_icssg for port %d failed\n", pNum);
1450             while(1);
1451         }
1452     }
1453     UART_printf("EMAC_UT_%d  collecting icssg stats passed\n", app_test_id);
1454 }
1455
1456 void emac_test_get_cpsw_stats(void)
1457 {
1458     EMAC_STATISTICS_T stats;
1459     memset(&stats, 0, sizeof(EMAC_STATISTICS_T));
1460     if (!port_en[EMAC_PORT_CPSW])
1461         return;
1462     app_test_id++;
1463
1464     UART_printf("EMAC_UT_%d begin collecting cpsw stats\n", app_test_id);
1465     if (emac_get_statistics(endPort, &stats) == EMAC_DRV_RESULT_OK)
1466     {
1467         UART_printf("port: %d: rx packets: %d, tx packets: %d\n", endPort, stats.RxGoodFrames, stats.TxGoodFrames);
1468     }
1469     else
1470     {
1471         UART_printf("emac_test_get_cpsw_stats: emac_get_statistics for port %d failed\n", endPort);
1472         while(1);
1473     }
1474     UART_printf("EMAC_UT_%d  collecting cpsw stats passed\n", app_test_id);
1475 }
1476
1477 #define APP_TEST_AM65XX_PG1_0_VERSION (0x0BB5A02FU)
1478
1479 void app_test_udma_init(void)
1480 {
1481     int32_t         retVal = UDMA_SOK;
1482     Udma_InitPrms   initPrms;
1483     uint32_t        instId;
1484
1485 #if defined (SOC_AM65XX)
1486 #if defined (EMAC_TEST_APP_CPSW)
1487     /* if A53 and pg 1.0 use mcu navss due to hw errata*/
1488     uint32_t pgVersion = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_JTAGID);
1489 #if defined (BUILD_MPU1_0)
1490     if (pgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
1491     {
1492         instId = UDMA_INST_ID_MCU_0;
1493     }
1494     else
1495     {
1496         instId = UDMA_INST_ID_MAIN_0;
1497     }
1498 #else
1499     instId = UDMA_INST_ID_MCU_0;
1500 #endif
1501 #else
1502     /* icssg use case */
1503     instId = UDMA_INST_ID_MAIN_0;
1504 #endif
1505 #endif
1506
1507 #if defined (SOC_J721E)
1508 #if defined (EMAC_TEST_APP_CPSW)
1509 #if defined (BUILD_MPU1_0)
1510     instId = UDMA_INST_ID_MAIN_0;
1511 #elif defined (BUILD_MCU1_0)
1512     instId = UDMA_INST_ID_MCU_0;
1513 #else
1514     instId = UDMA_INST_ID_MAIN_0;
1515 #endif
1516 #else
1517     /* icssg use case */
1518     instId = UDMA_INST_ID_MAIN_0;
1519 #endif
1520 #endif
1521
1522     UdmaInitPrms_init(instId, &initPrms);
1523
1524     initPrms.rmInitPrms.numIrIntr = EMAC_MAX_PORTS*8;
1525     initPrms.rmInitPrms.numRxCh = EMAC_MAX_PORTS*4;
1526     initPrms.rmInitPrms.numTxCh= EMAC_MAX_PORTS*4;
1527
1528     initPrms.rmInitPrms.startFreeFlow = 0;
1529     initPrms.rmInitPrms.numFreeFlow = 120;
1530
1531     initPrms.rmInitPrms.startFreeRing= 2;
1532     initPrms.rmInitPrms.numFreeRing = 300;
1533
1534     /* UDMA driver init */
1535     retVal = Udma_init(&gUdmaDrvObj, &initPrms);
1536     if(UDMA_SOK == retVal)
1537     {
1538         gDrvHandle = &gUdmaDrvObj;
1539     }
1540 }
1541
1542 void app_test_check_port_link(uint32_t startP, uint32_t endP)
1543 {
1544     uint32_t pNum;
1545     EMAC_LINK_INFO_T linkInfo;
1546
1547     for (pNum = startP; pNum  <= endP; pNum++)
1548     {
1549         if (!port_en[pNum])
1550             continue;
1551         if (1 == interposerCardPresent)
1552         {
1553             if((pNum == 2) || (pNum == 3))
1554                 continue;
1555         }
1556         memset(&linkInfo, 0, sizeof(EMAC_LINK_INFO_T));
1557         do
1558         {
1559             emac_poll(pNum, &linkInfo);
1560             Osal_delay(100);
1561             UART_printf("Link for port %d is DOWN\n", pNum);
1562         } while(linkInfo.link_status == EMAC_LINKSTATUS_NOLINK);
1563         UART_printf("Link for port %d is now UP\n", pNum);
1564     }
1565
1566 }
1567
1568 #ifdef EMAC_BENCHMARK
1569 void app_test_task_benchmark(UArg arg0, UArg arg1)
1570 {
1571     Board_STATUS boardInitStatus =0;
1572 #ifdef EMAC_TEST_APP_ICSSG
1573     PRUICSS_Config *prussCfg;
1574 #endif
1575
1576 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1577     Task_sleep(5000);
1578 #endif
1579     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK  | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1580
1581     boardInitStatus = Board_init(cfg);
1582     if (boardInitStatus !=BOARD_SOK)
1583     {
1584         UART_printf("Board_init failure\n");
1585         while(1);
1586     }
1587     UART_printf("Board_init success benchmark\n");
1588 #if defined(SOC_J721E)
1589 #else
1590     if (app_detect_interposer_card() == TRUE)
1591     {
1592         UART_printf("Interposer card is  present\n");
1593         interposerCardPresent = 1;
1594     }
1595 #endif
1596     else
1597     {
1598         UART_printf("Interposer card is NOT present\n");
1599     }
1600
1601     app_init();
1602 #ifdef EMAC_TEST_APP_ICSSG
1603     PRUICSS_socGetInitCfg(&prussCfg);
1604     prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1605     prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1606 #if defined(SOC_AM65XX)
1607     prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1608 #endif
1609 #endif
1610
1611     app_test_udma_init();
1612
1613     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1614     {
1615         while(1);
1616     }
1617     app_test_check_port_link(portNum, endPort);
1618     app_test_config_promiscous_mode(1);
1619
1620     initComplete = 1;
1621
1622     UART_printf("app_test_task_benchmark: getting stats\n");
1623     while (1)
1624     {
1625         Task_sleep(1000*60);
1626         emac_test_get_icssg_stats();
1627     }
1628 }
1629 #endif
1630
1631
1632 #ifdef EMAC_TEST_APP_ICSSG
1633 void test_EMAC_verify_ut_dual_mac_icssg(void)
1634 {
1635     /* @description:Unit test for ICSSG dual mac use case
1636
1637        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776
1638                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029
1639
1640        @cores: mpu1_0, mcu1_0 */
1641     Board_STATUS boardInitStatus =0;
1642 #ifdef EMAC_TEST_APP_ICSSG
1643     PRUICSS_Config *prussCfg;
1644 #endif
1645
1646 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1647         Task_sleep(2000);
1648 #endif
1649     Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ETH_PHY;
1650
1651 #if defined(SOC_J721E)
1652     /* PINMUX config of GESI for ICSSG */
1653     Board_PinmuxConfig_t gesiIcssgPinmux;
1654     Board_pinmuxGetCfg(&gesiIcssgPinmux);
1655     gesiIcssgPinmux.autoCfg = BOARD_PINMUX_CUSTOM;
1656     gesiIcssgPinmux.gesiExp = BOARD_PINMUX_GESI_ICSSG;
1657     Board_pinmuxSetCfg(&gesiIcssgPinmux);
1658 #endif
1659         boardInitStatus = Board_init(cfg);
1660         if (boardInitStatus !=BOARD_SOK)
1661         {
1662             UART_printf("Board_init failure\n");
1663             while(1);
1664         }
1665         UART_printf("Board_init success for UT\n");
1666
1667 #if defined(SOC_J721E)
1668 #else
1669         if (app_detect_interposer_card() == TRUE)
1670         {
1671             UART_printf("Interposer card is  present\n");
1672             interposerCardPresent = 1;
1673         }
1674         else
1675 #endif
1676         {
1677             UART_printf("Interposer card is NOT present\n");
1678         }
1679
1680         app_init();
1681 #ifdef EMAC_TEST_APP_ICSSG
1682         PRUICSS_socGetInitCfg(&prussCfg);
1683         prussHandle[0] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_ONE);
1684         prussHandle[1] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_TWO);
1685 #if defined(SOC_AM65XX)
1686         prussHandle[2] =  PRUICSS_create((PRUICSS_Config*)prussCfg,PRUICCSS_INSTANCE_THREE);
1687 #endif
1688 #endif
1689
1690     app_test_udma_init();
1691
1692     if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1693     {
1694         while(1);
1695     }
1696     initComplete = 1;
1697     /* Need to poll for link for ICSSG ports as they are port 2 port tests */
1698     /* For standalone CPSW test, we use internal loopback at CPSW-SS */
1699     app_test_check_port_link(portNum, endPort);
1700
1701     /* Test with PORT_MAC address */
1702     app_test_port_mac();
1703
1704 #ifndef BUILD_MCU1_0
1705     app_test_tx_chans();
1706 #endif
1707     app_test_interrrupt_mode();
1708
1709     /* test close -re open sequence */
1710     if(app_test_emac_close() == -1)
1711     {
1712         UART_printf("emac unit test app_test_emac_close failed\n");
1713         while(1);
1714     }
1715     /* re-init the app */
1716     app_init();
1717
1718     /* re-open in polling mode */
1719     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1720     {
1721         while(1);
1722     }
1723
1724     app_test_poll_mode();
1725
1726
1727 #ifndef BUILD_MCU1_0
1728         app_test_multi_flows();
1729 #endif
1730
1731     app_test_config_promiscous_mode(1);
1732     app_test_promiscous_mode();
1733
1734     emac_test_get_icssg_stats();
1735
1736     UART_printf("All tests have passed\n");
1737 #ifdef UNITY_INCLUDE_CONFIG_H
1738     TEST_PASS();
1739 #endif
1740 }
1741
1742 #else
1743 void test_EMAC_verify_ut_cpsw(void)
1744 {
1745     /* @description:Unit test for ICSSG dual mac and CPSW use cases
1746
1747        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509
1748                       PRSDK-3726, PRSDK-3755, PRSDK-3765
1749
1750        @cores: mpu1_0, mcu1_0 */
1751
1752     Board_STATUS boardInitStatus =0;
1753 #ifdef EMAC_TEST_APP_WITHOUT_DDR
1754         Task_sleep(2000);
1755 #endif
1756         Board_initCfg cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ETH_PHY;
1757
1758     boardInitStatus = Board_init(cfg);
1759     if (boardInitStatus !=BOARD_SOK)
1760     {
1761         UART_printf("Board_init failure\n");
1762         while(1);
1763     }
1764     UART_printf("Board_init success for UT\n");
1765
1766
1767     app_init();
1768
1769     app_test_udma_init();
1770
1771     if (app_test_emac_open(EMAC_MODE_INTERRUPT) != 0)
1772     {
1773         while(1);
1774     }
1775     initComplete = 1;
1776
1777     /* Test with PORT_MAC address */
1778     app_test_port_mac();
1779
1780     app_test_interrrupt_mode();
1781
1782     /* test close -re open sequence */
1783     if(app_test_emac_close() == -1)
1784     {
1785         UART_printf("emac unit test app_test_emac_close failed\n");
1786         while(1);
1787     }
1788     /* re-init the app */
1789     app_init();
1790
1791     /* re-open in polling mode */
1792     if (app_test_emac_open(EMAC_MODE_POLL) != 0)
1793     {
1794         while(1);
1795     }
1796
1797     app_test_poll_mode();
1798
1799     app_test_config_promiscous_mode(1);
1800     app_test_promiscous_mode();
1801
1802     emac_test_get_cpsw_stats();
1803
1804     UART_printf("All tests have passed\n");
1805 #ifdef UNITY_INCLUDE_CONFIG_H
1806     TEST_PASS();
1807 #endif
1808 }
1809
1810 #endif
1811
1812 #ifdef UNITY_INCLUDE_CONFIG_H
1813 #ifdef EMAC_TEST_APP_ICSSG
1814 void test_Emac_Icssg_TestApp_runner(void)
1815 {
1816     /* @description: Test runner for EMAC ICSSG tests
1817
1818        @requirements: PRSDK-3771, PRSDK-3767, PRSDK-3768, PRSDK-3774, PRSDK-3776
1819                       PRSDK-3780, PRSDK-3782, PRSDK-3813, PRSDK-3815, PRSDK-4029
1820
1821        @cores: mpu1_0, mcu1_0 */
1822
1823     UNITY_BEGIN();
1824     RUN_TEST(test_EMAC_verify_ut_dual_mac_icssg);
1825     UNITY_END();
1826     /* Function to print results defined in our unity_config.h file */
1827     print_unityOutputBuffer_usingUARTstdio();
1828 }
1829
1830 #else
1831 void test_Emac_Cpsw_TestApp_runner(void)
1832 {
1833     /* @description: Test runner for EMAC CPSW tests
1834
1835        @requirements: PRSDK-3485, PRSDK-3486, PRSDK-3487, PRSDK-3509
1836                       PRSDK-3726, PRSDK-3755, PRSDK-3765
1837
1838        @cores: mpu1_0, mcu1_0 */
1839
1840     UNITY_BEGIN();
1841     RUN_TEST(test_EMAC_verify_ut_cpsw);
1842     UNITY_END();
1843     /* Function to print results defined in our unity_config.h file */
1844     print_unityOutputBuffer_usingUARTstdio();
1845 }
1846 #endif
1847 #endif
1848
1849 void app_test_task_verify_ut_dual_mac_cpsw(UArg arg0, UArg arg1)
1850 {
1851 #ifdef UNITY_INCLUDE_CONFIG_H
1852 #ifdef EMAC_TEST_APP_ICSSG
1853     test_Emac_Icssg_TestApp_runner();
1854 #else
1855     test_Emac_Cpsw_TestApp_runner();
1856 #endif
1857 #endif
1858 }
1859
1860 #ifdef EMAC_TEST_APP_ICSSG
1861 /*
1862  *  ======== app_test_task_init_pruicss========
1863  */
1864 int32_t  app_test_task_disable_pruicss(uint32_t portNum)
1865 {
1866     PRUICSS_Handle prussDrvHandle;
1867     uint8_t pru_n, rtu_n, slice_n ;
1868
1869     if (portNum > 5)
1870         return -1;
1871
1872     prussDrvHandle =prussHandle[portNum >> 1];
1873     if (prussDrvHandle == NULL)
1874         return -1;
1875
1876     slice_n = (portNum & 1);
1877     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1878     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1879
1880     if (PRUICSS_pruDisable(prussDrvHandle, pru_n) != 0)
1881         UART_printf("PRUICSS_pruDisable for PRUICCSS_PRU%d failed\n", slice_n);
1882
1883     if (PRUICSS_pruDisable(prussDrvHandle, rtu_n) != 0)
1884         UART_printf("PRUICSS_pruDisable for PRUICCSS_RTU%d failed\n", slice_n);
1885
1886     /* CLEAR SHARED MEM which is used for host/firmware handshake */
1887     PRUICSS_pruInitMemory(prussDrvHandle, PRU_ICSS_SHARED_RAM);
1888
1889
1890     return 0;
1891 }
1892
1893 /*
1894  *  ======== app_test_task_init_pruicss========
1895  */
1896 int32_t  app_test_task_init_pruicss(uint32_t portNum)
1897 {
1898     PRUICSS_Handle prussDrvHandle;
1899     uint8_t firmwareLoad_done = FALSE;
1900     uint8_t pru_n, rtu_n, slice_n ;
1901
1902     if (portNum > 5)
1903         return -1;
1904
1905     prussDrvHandle =prussHandle[portNum >> 1];
1906     if (prussDrvHandle == NULL)
1907         return -1;
1908     slice_n = (portNum & 1);
1909     pru_n = (slice_n) ? PRUICCSS_PRU1 : PRUICCSS_PRU0;
1910     rtu_n = (slice_n) ? PRUICCSS_RTU1 : PRUICCSS_RTU0;
1911
1912
1913     if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM(slice_n), 0,
1914                                firmware[slice_n].pru, firmware[slice_n].pru_size)) {
1915         if (PRUICSS_pruWriteMemory(prussDrvHandle,PRU_ICSS_IRAM(slice_n + 2), 0,
1916                                    firmware[slice_n].rtu, firmware[slice_n].rtu_size))
1917             firmwareLoad_done = TRUE;
1918         else
1919             UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_PRU%d failed\n", slice_n);
1920     }
1921     else
1922         UART_printf("PRUICSS_pruWriteMemory for PRUICCSS_RTU%d failed\n", slice_n);
1923     if( firmwareLoad_done)
1924     {
1925         if (PRUICSS_pruEnable(prussDrvHandle, pru_n) != 0)
1926             UART_printf("PRUICSS_pruEnable for PRUICCSS_PRU%d failed\n", slice_n);
1927         if (PRUICSS_pruEnable(prussDrvHandle, rtu_n) != 0)
1928             UART_printf("PRUICSS_pruEnable for PRUICCSS_RTU%d failed\n", slice_n);
1929     }
1930
1931     return 0;
1932 }
1933 #endif
1934