1 /**
2 * \file k2l/GPIO_soc.c
3 *
4 * \brief K2L SOC specific GPIO hardware attributes.
5 *
6 * This file contains the GPIO hardware attributes like base address and
7 * interrupt ids.
8 */
10 /*
11 * Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the
23 * distribution.
24 *
25 * Neither the name of Texas Instruments Incorporated nor the names of
26 * its contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 */
43 #include <ti/csl/csl_utils.h>
44 #include <ti/csl/soc.h>
45 #include <ti/csl/csl_types.h>
46 #include <ti/csl/csl_device_interrupt.h>
47 #include <ti/drv/gpio/GPIO.h>
48 #include <ti/drv/gpio/soc/GPIO_soc.h>
50 /** \brief Number of gpio pins for each port */
51 #define GPIO_NUM_PINS_PER_PORT (64U)
53 /** \brief Number of gpio ports present in the soc */
54 #define GPIO_NUM_PORTS (CSL_GPIO_PER_CNT)
56 /* GPIO Pin interrupt configurations */
57 GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PORTS][GPIO_NUM_PINS_PER_PORT] =
58 {
59 {
60 /* GPIO port 0 pin 0 */
61 {
62 #ifdef _TMS320C6X
63 OSAL_REGINT_INTVEC_EVENT_COMBINER, /* default DSP Interrupt vector number, can be set in GPIO_socSetInitCfg() API */
64 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 0 */
65 #else
66 CSL_ARM_GIC_GPIO_INT0 + 32, /* GPIO pin interrupt event for ARM GIC */
67 0,
68 #endif
69 INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
70 0,
71 0
72 },
73 /* GPIO port 0 pin 1 */
74 {
75 #ifdef _TMS320C6X
76 OSAL_REGINT_INTVEC_EVENT_COMBINER,
77 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 1 */
78 #else
79 CSL_ARM_GIC_GPIO_INT1 + 32,
80 0,
81 #endif
82 INVALID_INTC_MUX_NUM,
83 0,
84 0
85 },
86 /* GPIO port 0 pin 2 */
87 {
88 #ifdef _TMS320C6X
89 OSAL_REGINT_INTVEC_EVENT_COMBINER,
90 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 2 */
91 #else
92 CSL_ARM_GIC_GPIO_INT2 + 32,
93 0,
94 #endif
95 INVALID_INTC_MUX_NUM,
96 0,
97 0
98 },
99 /* GPIO port 0 pin 3 */
100 {
101 #ifdef _TMS320C6X
102 OSAL_REGINT_INTVEC_EVENT_COMBINER,
103 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 3 */
104 #else
105 CSL_ARM_GIC_GPIO_INT3 + 32,
106 0,
107 #endif
108 INVALID_INTC_MUX_NUM,
109 0,
110 0
111 },
112 /* GPIO port 0 pin 4 */
113 {
114 #ifdef _TMS320C6X
115 OSAL_REGINT_INTVEC_EVENT_COMBINER,
116 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 4 */
117 #else
118 CSL_ARM_GIC_GPIO_INT4 + 32,
119 0,
120 #endif
121 INVALID_INTC_MUX_NUM,
122 0,
123 0
124 },
125 /* GPIO port 0 pin 5 */
126 {
127 #ifdef _TMS320C6X
128 OSAL_REGINT_INTVEC_EVENT_COMBINER,
129 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 5 */
130 #else
131 CSL_ARM_GIC_GPIO_INT5 + 32,
132 0,
133 #endif
134 INVALID_INTC_MUX_NUM,
135 0,
136 0
137 },
138 /* GPIO port 0 pin 6 */
139 {
140 #ifdef _TMS320C6X
141 OSAL_REGINT_INTVEC_EVENT_COMBINER,
142 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 6 */
143 #else
144 CSL_ARM_GIC_GPIO_INT6 + 32,
145 0,
146 #endif
147 INVALID_INTC_MUX_NUM,
148 0,
149 0
150 },
151 /* GPIO port 0 pin 7 */
152 {
153 #ifdef _TMS320C6X
154 OSAL_REGINT_INTVEC_EVENT_COMBINER,
155 CSL_C66X_COREPAC_GPIO_INTN, /* GPIO pin interrupt event for DSP corePac 7 */
156 #else
157 CSL_ARM_GIC_GPIO_INT7 + 32,
158 0,
159 #endif
160 INVALID_INTC_MUX_NUM,
161 0,
162 0
163 },
164 /* GPIO port 0 pin 8 */
165 {
166 #ifdef _TMS320C6X
167 OSAL_REGINT_INTVEC_EVENT_COMBINER,
168 CSL_C66X_COREPAC_GPIO_INT8,
169 #else
170 CSL_ARM_GIC_GPIO_INT8 + 32,
171 0,
172 #endif
173 INVALID_INTC_MUX_NUM,
174 0,
175 0
176 },
177 /* GPIO port 0 pin 9 */
178 {
179 #ifdef _TMS320C6X
180 OSAL_REGINT_INTVEC_EVENT_COMBINER,
181 CSL_C66X_COREPAC_GPIO_INT9,
182 #else
183 CSL_ARM_GIC_GPIO_INT9 + 32,
184 0,
185 #endif
186 INVALID_INTC_MUX_NUM,
187 0,
188 0
189 },
190 /* GPIO port 0 pin 10 */
191 {
192 #ifdef _TMS320C6X
193 OSAL_REGINT_INTVEC_EVENT_COMBINER,
194 CSL_C66X_COREPAC_GPIO_INT10,
195 #else
196 CSL_ARM_GIC_GPIO_INT10 + 32,
197 0,
198 #endif
199 INVALID_INTC_MUX_NUM,
200 0,
201 0
202 },
203 /* GPIO port 0 pin 11 */
204 {
205 #ifdef _TMS320C6X
206 OSAL_REGINT_INTVEC_EVENT_COMBINER,
207 CSL_C66X_COREPAC_GPIO_INT11,
208 #else
209 CSL_ARM_GIC_GPIO_INT11 + 32,
210 0,
211 #endif
212 INVALID_INTC_MUX_NUM,
213 0,
214 0
215 },
216 /* GPIO port 0 pin 12 */
217 {
218 #ifdef _TMS320C6X
219 OSAL_REGINT_INTVEC_EVENT_COMBINER,
220 CSL_C66X_COREPAC_GPIO_INT12,
221 #else
222 CSL_ARM_GIC_GPIO_INT12 + 32,
223 0,
224 #endif
225 INVALID_INTC_MUX_NUM,
226 0,
227 0
228 },
229 /* GPIO port 0 pin 13 */
230 {
231 #ifdef _TMS320C6X
232 OSAL_REGINT_INTVEC_EVENT_COMBINER,
233 CSL_C66X_COREPAC_GPIO_INT13,
234 #else
235 CSL_ARM_GIC_GPIO_INT13 + 32,
236 0,
237 #endif
238 INVALID_INTC_MUX_NUM,
239 0,
240 0
241 },
242 /* GPIO port 0 pin 14 */
243 {
244 #ifdef _TMS320C6X
245 OSAL_REGINT_INTVEC_EVENT_COMBINER,
246 CSL_C66X_COREPAC_GPIO_INT14,
247 #else
248 CSL_ARM_GIC_GPIO_INT14 + 32,
249 0,
250 #endif
251 INVALID_INTC_MUX_NUM,
252 0,
253 0
254 },
255 /* GPIO port 0 pin 15 */
256 {
257 #ifdef _TMS320C6X
258 OSAL_REGINT_INTVEC_EVENT_COMBINER,
259 CSL_C66X_COREPAC_GPIO_INT15,
260 #else
261 CSL_ARM_GIC_GPIO_INT15 + 32,
262 0,
263 #endif
264 INVALID_INTC_MUX_NUM,
265 0,
266 0
267 },
268 /* GPIO port 0 pin 16 */
269 {
270 #ifdef _TMS320C6X
271 OSAL_REGINT_INTVEC_EVENT_COMBINER,
272 62,
273 0,
274 CSL_CIC0_GPIO_INT16,
275 6
276 #else
277 CSL_ARM_GIC_GPIO_INT16 + 32,
278 0,
279 INVALID_INTC_MUX_NUM,
280 0,
281 0
282 #endif
283 },
284 /* GPIO port 0 pin 17 */
285 {
286 #ifdef _TMS320C6X
287 OSAL_REGINT_INTVEC_EVENT_COMBINER,
288 62,
289 0,
290 CSL_CIC0_GPIO_INT17,
291 6
292 #else
293 CSL_ARM_GIC_GPIO_INT17 + 32,
294 0,
295 INVALID_INTC_MUX_NUM,
296 0,
297 0
298 #endif
299 },
300 /* GPIO port 0 pin 18 */
301 {
302 #ifdef _TMS320C6X
303 OSAL_REGINT_INTVEC_EVENT_COMBINER,
304 62,
305 0,
306 CSL_CIC0_GPIO_INT18,
307 6
308 #else
309 CSL_ARM_GIC_GPIO_INT18 + 32,
310 0,
311 INVALID_INTC_MUX_NUM,
312 0,
313 0
314 #endif
315 },
316 /* GPIO port 0 pin 19 */
317 {
318 #ifdef _TMS320C6X
319 OSAL_REGINT_INTVEC_EVENT_COMBINER,
320 62,
321 0,
322 CSL_CIC0_GPIO_INT19,
323 6
324 #else
325 CSL_ARM_GIC_GPIO_INT19 + 32,
326 0,
327 INVALID_INTC_MUX_NUM,
328 0,
329 0
330 #endif
331 },
332 /* GPIO port 0 pin 20 */
333 {
334 #ifdef _TMS320C6X
335 OSAL_REGINT_INTVEC_EVENT_COMBINER,
336 62,
337 0,
338 CSL_CIC0_GPIO_INT20,
339 6
340 #else
341 CSL_ARM_GIC_GPIO_INT20 + 32,
342 0,
343 INVALID_INTC_MUX_NUM,
344 0,
345 0
346 #endif
347 },
348 /* GPIO port 0 pin 21 */
349 {
350 #ifdef _TMS320C6X
351 OSAL_REGINT_INTVEC_EVENT_COMBINER,
352 62,
353 0,
354 CSL_CIC0_GPIO_INT21,
355 6
356 #else
357 CSL_ARM_GIC_GPIO_INT21 + 32,
358 0,
359 INVALID_INTC_MUX_NUM,
360 0,
361 0
362 #endif
363 },
364 /* GPIO port 0 pin 22 */
365 {
366 #ifdef _TMS320C6X
367 OSAL_REGINT_INTVEC_EVENT_COMBINER,
368 62,
369 0,
370 CSL_CIC0_GPIO_INT22,
371 6
372 #else
373 CSL_ARM_GIC_GPIO_INT22 + 32,
374 0,
375 INVALID_INTC_MUX_NUM,
376 0,
377 0
378 #endif
379 },
380 /* GPIO port 0 pin 23 */
381 {
382 #ifdef _TMS320C6X
383 OSAL_REGINT_INTVEC_EVENT_COMBINER,
384 62,
385 0,
386 CSL_CIC0_GPIO_INT23,
387 6
388 #else
389 CSL_ARM_GIC_GPIO_INT23 + 32,
390 0,
391 INVALID_INTC_MUX_NUM,
392 0,
393 0
394 #endif
395 },
396 /* GPIO port 0 pin 24 */
397 {
398 #ifdef _TMS320C6X
399 OSAL_REGINT_INTVEC_EVENT_COMBINER,
400 62,
401 0,
402 CSL_CIC0_GPIO_INT24,
403 6
404 #else
405 CSL_ARM_GIC_GPIO_INT24 + 32,
406 0,
407 INVALID_INTC_MUX_NUM,
408 0,
409 0
410 #endif
411 },
412 /* GPIO port 0 pin 25 */
413 {
414 #ifdef _TMS320C6X
415 OSAL_REGINT_INTVEC_EVENT_COMBINER,
416 62,
417 0,
418 CSL_CIC0_GPIO_INT25,
419 6
420 #else
421 CSL_ARM_GIC_GPIO_INT25 + 32,
422 0,
423 INVALID_INTC_MUX_NUM,
424 0,
425 0
426 #endif
427 },
428 /* GPIO port 0 pin 26 */
429 {
430 #ifdef _TMS320C6X
431 OSAL_REGINT_INTVEC_EVENT_COMBINER,
432 62,
433 0,
434 CSL_CIC0_GPIO_INT26,
435 6
436 #else
437 CSL_ARM_GIC_GPIO_INT26 + 32,
438 0,
439 INVALID_INTC_MUX_NUM,
440 0,
441 0
442 #endif
443 },
444 /* GPIO port 0 pin 27 */
445 {
446 #ifdef _TMS320C6X
447 OSAL_REGINT_INTVEC_EVENT_COMBINER,
448 62,
449 0,
450 CSL_CIC0_GPIO_INT27,
451 6
452 #else
453 CSL_ARM_GIC_GPIO_INT27 + 32,
454 0,
455 INVALID_INTC_MUX_NUM,
456 0,
457 0
458 #endif
459 },
460 /* GPIO port 0 pin 28 */
461 {
462 #ifdef _TMS320C6X
463 OSAL_REGINT_INTVEC_EVENT_COMBINER,
464 62,
465 0,
466 CSL_CIC0_GPIO_INT28,
467 6
468 #else
469 CSL_ARM_GIC_GPIO_INT28 + 32,
470 0,
471 INVALID_INTC_MUX_NUM,
472 0,
473 0
474 #endif
475 },
476 /* GPIO port 0 pin 29 */
477 {
478 #ifdef _TMS320C6X
479 OSAL_REGINT_INTVEC_EVENT_COMBINER,
480 62,
481 0,
482 CSL_CIC0_GPIO_INT29,
483 6
484 #else
485 CSL_ARM_GIC_GPIO_INT29 + 32,
486 0,
487 INVALID_INTC_MUX_NUM,
488 0,
489 0
490 #endif
491 },
492 /* GPIO port 0 pin 30 */
493 {
494 #ifdef _TMS320C6X
495 OSAL_REGINT_INTVEC_EVENT_COMBINER,
496 62,
497 0,
498 CSL_CIC0_GPIO_INT30,
499 6
500 #else
501 CSL_ARM_GIC_GPIO_INT30 + 32,
502 0,
503 INVALID_INTC_MUX_NUM,
504 0,
505 0
506 #endif
507 },
508 /* GPIO port 0 pin 31 */
509 {
510 #ifdef _TMS320C6X
511 OSAL_REGINT_INTVEC_EVENT_COMBINER,
512 62,
513 0,
514 CSL_CIC0_GPIO_INT31,
515 6
516 #else
517 CSL_ARM_GIC_GPIO_INT31 + 32,
518 0,
519 INVALID_INTC_MUX_NUM,
520 0,
521 0
522 #endif
523 },
524 /* GPIO port 0 pin 32 */
525 {
526 #ifdef _TMS320C6X
527 OSAL_REGINT_INTVEC_EVENT_COMBINER,
528 62,
529 0,
530 CSL_CIC0_GPIO_INT32,
531 6
532 #else
533 CSL_ARM_GIC_GPIO_INT32 + 32,
534 0,
535 INVALID_INTC_MUX_NUM,
536 0,
537 0
538 #endif
539 },
540 /* GPIO port 0 pin 33 */
541 {
542 #ifdef _TMS320C6X
543 OSAL_REGINT_INTVEC_EVENT_COMBINER,
544 62,
545 0,
546 CSL_CIC0_GPIO_INT33,
547 6
548 #else
549 CSL_ARM_GIC_GPIO_INT33 + 32,
550 0,
551 INVALID_INTC_MUX_NUM,
552 0,
553 0
554 #endif
555 },
556 /* GPIO port 0 pin 34 */
557 {
558 #ifdef _TMS320C6X
559 OSAL_REGINT_INTVEC_EVENT_COMBINER,
560 62,
561 0,
562 CSL_CIC0_GPIO_INT34,
563 6
564 #else
565 CSL_ARM_GIC_GPIO_INT34 + 32,
566 0,
567 INVALID_INTC_MUX_NUM,
568 0,
569 0
570 #endif
571 },
572 /* GPIO port 0 pin 35 */
573 {
574 #ifdef _TMS320C6X
575 OSAL_REGINT_INTVEC_EVENT_COMBINER,
576 62,
577 0,
578 CSL_CIC0_GPIO_INT35,
579 6
580 #else
581 CSL_ARM_GIC_GPIO_INT35 + 32,
582 0,
583 INVALID_INTC_MUX_NUM,
584 0,
585 0
586 #endif
587 },
588 /* GPIO port 0 pin 36 */
589 {
590 #ifdef _TMS320C6X
591 OSAL_REGINT_INTVEC_EVENT_COMBINER,
592 62,
593 0,
594 CSL_CIC0_GPIO_INT36,
595 6
596 #else
597 CSL_ARM_GIC_GPIO_INT36 + 32,
598 0,
599 INVALID_INTC_MUX_NUM,
600 0,
601 0
602 #endif
603 },
604 /* GPIO port 0 pin 37 */
605 {
606 #ifdef _TMS320C6X
607 OSAL_REGINT_INTVEC_EVENT_COMBINER,
608 62,
609 0,
610 CSL_CIC0_GPIO_INT37,
611 6
612 #else
613 CSL_ARM_GIC_GPIO_INT37 + 32,
614 0,
615 INVALID_INTC_MUX_NUM,
616 0,
617 0
618 #endif
619 },
620 /* GPIO port 0 pin 38 */
621 {
622 #ifdef _TMS320C6X
623 OSAL_REGINT_INTVEC_EVENT_COMBINER,
624 62,
625 0,
626 CSL_CIC0_GPIO_INT38,
627 6
628 #else
629 CSL_ARM_GIC_GPIO_INT38 + 32,
630 0,
631 INVALID_INTC_MUX_NUM,
632 0,
633 0
634 #endif
635 },
636 /* GPIO port 0 pin 39 */
637 {
638 #ifdef _TMS320C6X
639 OSAL_REGINT_INTVEC_EVENT_COMBINER,
640 62,
641 0,
642 CSL_CIC0_GPIO_INT39,
643 6
644 #else
645 CSL_ARM_GIC_GPIO_INT39 + 32,
646 0,
647 INVALID_INTC_MUX_NUM,
648 0,
649 0
650 #endif
651 },
652 /* GPIO port 0 pin 40 */
653 {
654 #ifdef _TMS320C6X
655 OSAL_REGINT_INTVEC_EVENT_COMBINER,
656 62,
657 0,
658 CSL_CIC0_GPIO_INT40,
659 6
660 #else
661 CSL_ARM_GIC_GPIO_INT40 + 32,
662 0,
663 INVALID_INTC_MUX_NUM,
664 0,
665 0
666 #endif
667 },
668 /* GPIO port 0 pin 41 */
669 {
670 #ifdef _TMS320C6X
671 OSAL_REGINT_INTVEC_EVENT_COMBINER,
672 62,
673 0,
674 CSL_CIC0_GPIO_INT41,
675 6
676 #else
677 CSL_ARM_GIC_GPIO_INT41 + 32,
678 0,
679 INVALID_INTC_MUX_NUM,
680 0,
681 0
682 #endif
683 },
684 /* GPIO port 0 pin 42 */
685 {
686 #ifdef _TMS320C6X
687 OSAL_REGINT_INTVEC_EVENT_COMBINER,
688 62,
689 0,
690 CSL_CIC0_GPIO_INT42,
691 6
692 #else
693 CSL_ARM_GIC_GPIO_INT42 + 32,
694 0,
695 INVALID_INTC_MUX_NUM,
696 0,
697 0
698 #endif
699 },
700 /* GPIO port 0 pin 43 */
701 {
702 #ifdef _TMS320C6X
703 OSAL_REGINT_INTVEC_EVENT_COMBINER,
704 62,
705 0,
706 CSL_CIC0_GPIO_INT43,
707 6
708 #else
709 CSL_ARM_GIC_GPIO_INT43 + 32,
710 0,
711 INVALID_INTC_MUX_NUM,
712 0,
713 0
714 #endif
715 },
716 /* GPIO port 0 pin 44 */
717 {
718 #ifdef _TMS320C6X
719 OSAL_REGINT_INTVEC_EVENT_COMBINER,
720 62,
721 0,
722 CSL_CIC0_GPIO_INT44,
723 6
724 #else
725 CSL_ARM_GIC_GPIO_INT44 + 32,
726 0,
727 INVALID_INTC_MUX_NUM,
728 0,
729 0
730 #endif
731 },
732 /* GPIO port 0 pin 45 */
733 {
734 #ifdef _TMS320C6X
735 OSAL_REGINT_INTVEC_EVENT_COMBINER,
736 62,
737 0,
738 CSL_CIC0_GPIO_INT45,
739 6
740 #else
741 CSL_ARM_GIC_GPIO_INT45 + 32,
742 0,
743 INVALID_INTC_MUX_NUM,
744 0,
745 0
746 #endif
747 },
748 /* GPIO port 0 pin 46 */
749 {
750 #ifdef _TMS320C6X
751 OSAL_REGINT_INTVEC_EVENT_COMBINER,
752 62,
753 0,
754 CSL_CIC0_GPIO_INT46,
755 6
756 #else
757 CSL_ARM_GIC_GPIO_INT46 + 32,
758 0,
759 INVALID_INTC_MUX_NUM,
760 0,
761 0
762 #endif
763 },
764 /* GPIO port 0 pin 47 */
765 {
766 #ifdef _TMS320C6X
767 OSAL_REGINT_INTVEC_EVENT_COMBINER,
768 62,
769 0,
770 CSL_CIC0_GPIO_INT47,
771 6
772 #else
773 CSL_ARM_GIC_GPIO_INT47 + 32,
774 0,
775 INVALID_INTC_MUX_NUM,
776 0,
777 0
778 #endif
779 },
780 /* GPIO port 0 pin 48 */
781 {
782 #ifdef _TMS320C6X
783 OSAL_REGINT_INTVEC_EVENT_COMBINER,
784 62,
785 0,
786 CSL_CIC0_GPIO_INT48,
787 6
788 #else
789 CSL_ARM_GIC_GPIO_INT48 + 32,
790 0,
791 INVALID_INTC_MUX_NUM,
792 0,
793 0
794 #endif
795 },
796 /* GPIO port 0 pin 49 */
797 {
798 #ifdef _TMS320C6X
799 OSAL_REGINT_INTVEC_EVENT_COMBINER,
800 62,
801 0,
802 CSL_CIC0_GPIO_INT49,
803 6
804 #else
805 CSL_ARM_GIC_GPIO_INT49 + 32,
806 0,
807 INVALID_INTC_MUX_NUM,
808 0,
809 0
810 #endif
811 },
812 /* GPIO port 0 pin 50 */
813 {
814 #ifdef _TMS320C6X
815 OSAL_REGINT_INTVEC_EVENT_COMBINER,
816 62,
817 0,
818 CSL_CIC0_GPIO_INT50,
819 6
820 #else
821 CSL_ARM_GIC_GPIO_INT50 + 32,
822 0,
823 INVALID_INTC_MUX_NUM,
824 0,
825 0
826 #endif
827 },
828 /* GPIO port 0 pin 51 */
829 {
830 #ifdef _TMS320C6X
831 OSAL_REGINT_INTVEC_EVENT_COMBINER,
832 62,
833 0,
834 CSL_CIC0_GPIO_INT51,
835 6
836 #else
837 CSL_ARM_GIC_GPIO_INT51 + 32,
838 0,
839 INVALID_INTC_MUX_NUM,
840 0,
841 0
842 #endif
843 },
844 /* GPIO port 0 pin 52 */
845 {
846 #ifdef _TMS320C6X
847 OSAL_REGINT_INTVEC_EVENT_COMBINER,
848 62,
849 0,
850 CSL_CIC0_GPIO_INT52,
851 6
852 #else
853 CSL_ARM_GIC_GPIO_INT52 + 32,
854 0,
855 INVALID_INTC_MUX_NUM,
856 0,
857 0
858 #endif
859 },
860 /* GPIO port 0 pin 53 */
861 {
862 #ifdef _TMS320C6X
863 OSAL_REGINT_INTVEC_EVENT_COMBINER,
864 62,
865 0,
866 CSL_CIC0_GPIO_INT53,
867 6
868 #else
869 CSL_ARM_GIC_GPIO_INT53 + 32,
870 0,
871 INVALID_INTC_MUX_NUM,
872 0,
873 0
874 #endif
875 },
876 /* GPIO port 0 pin 54 */
877 {
878 #ifdef _TMS320C6X
879 OSAL_REGINT_INTVEC_EVENT_COMBINER,
880 62,
881 0,
882 CSL_CIC0_GPIO_INT54,
883 6
884 #else
885 CSL_ARM_GIC_GPIO_INT54 + 32,
886 0,
887 INVALID_INTC_MUX_NUM,
888 0,
889 0
890 #endif
891 },
892 /* GPIO port 0 pin 55 */
893 {
894 #ifdef _TMS320C6X
895 OSAL_REGINT_INTVEC_EVENT_COMBINER,
896 62,
897 0,
898 CSL_CIC0_GPIO_INT55,
899 6
900 #else
901 CSL_ARM_GIC_GPIO_INT55 + 32,
902 0,
903 INVALID_INTC_MUX_NUM,
904 0,
905 0
906 #endif
907 },
908 /* GPIO port 0 pin 56 */
909 {
910 #ifdef _TMS320C6X
911 OSAL_REGINT_INTVEC_EVENT_COMBINER,
912 62,
913 0,
914 CSL_CIC0_GPIO_INT56,
915 6
916 #else
917 CSL_ARM_GIC_GPIO_INT56 + 32,
918 0,
919 INVALID_INTC_MUX_NUM,
920 0,
921 0
922 #endif
923 },
924 /* GPIO port 0 pin 57 */
925 {
926 #ifdef _TMS320C6X
927 OSAL_REGINT_INTVEC_EVENT_COMBINER,
928 62,
929 0,
930 CSL_CIC0_GPIO_INT57,
931 6
932 #else
933 CSL_ARM_GIC_GPIO_INT57 + 32,
934 0,
935 INVALID_INTC_MUX_NUM,
936 0,
937 0
938 #endif
939 },
940 /* GPIO port 0 pin 58 */
941 {
942 #ifdef _TMS320C6X
943 OSAL_REGINT_INTVEC_EVENT_COMBINER,
944 62,
945 0,
946 CSL_CIC0_GPIO_INT58,
947 6
948 #else
949 CSL_ARM_GIC_GPIO_INT58 + 32,
950 0,
951 INVALID_INTC_MUX_NUM,
952 0,
953 0
954 #endif
955 },
956 /* GPIO port 0 pin 59 */
957 {
958 #ifdef _TMS320C6X
959 OSAL_REGINT_INTVEC_EVENT_COMBINER,
960 62,
961 0,
962 CSL_CIC0_GPIO_INT59,
963 6
964 #else
965 CSL_ARM_GIC_GPIO_INT59 + 32,
966 0,
967 INVALID_INTC_MUX_NUM,
968 0,
969 0
970 #endif
971 },
972 /* GPIO port 0 pin 60 */
973 {
974 #ifdef _TMS320C6X
975 OSAL_REGINT_INTVEC_EVENT_COMBINER,
976 62,
977 0,
978 CSL_CIC0_GPIO_INT60,
979 6
980 #else
981 CSL_ARM_GIC_GPIO_INT60 + 32,
982 0,
983 INVALID_INTC_MUX_NUM,
984 0,
985 0
986 #endif
987 },
988 /* GPIO port 0 pin 61 */
989 {
990 #ifdef _TMS320C6X
991 OSAL_REGINT_INTVEC_EVENT_COMBINER,
992 62,
993 0,
994 CSL_CIC0_GPIO_INT61,
995 6
996 #else
997 CSL_ARM_GIC_GPIO_INT61 + 32,
998 0,
999 INVALID_INTC_MUX_NUM,
1000 0,
1001 0
1002 #endif
1003 },
1004 /* GPIO port 0 pin 62 */
1005 {
1006 #ifdef _TMS320C6X
1007 OSAL_REGINT_INTVEC_EVENT_COMBINER,
1008 62,
1009 0,
1010 CSL_CIC0_GPIO_INT62,
1011 6
1012 #else
1013 CSL_ARM_GIC_GPIO_INT62 + 32,
1014 0,
1015 INVALID_INTC_MUX_NUM,
1016 0,
1017 0
1018 #endif
1019 },
1020 /* GPIO port 0 pin 63 */
1021 {
1022 #ifdef _TMS320C6X
1023 OSAL_REGINT_INTVEC_EVENT_COMBINER,
1024 62,
1025 0,
1026 CSL_CIC0_GPIO_INT63,
1027 6
1028 #else
1029 CSL_ARM_GIC_GPIO_INT63 + 32,
1030 0,
1031 INVALID_INTC_MUX_NUM,
1032 0,
1033 0
1034 #endif
1035 }
1036 },
1037 {
1038 /* "pad to full predefined length of array" */
1039 {0,0,0,0,0},
1040 {0,0,0,0,0},
1041 {0,0,0,0,0},
1042 {0,0,0,0,0},
1044 {0,0,0,0,0},
1045 {0,0,0,0,0},
1046 {0,0,0,0,0},
1047 {0,0,0,0,0},
1049 {0,0,0,0,0},
1050 {0,0,0,0,0},
1051 {0,0,0,0,0},
1052 {0,0,0,0,0},
1054 {0,0,0,0,0},
1055 {0,0,0,0,0},
1056 {0,0,0,0,0},
1057 {0,0,0,0,0},
1059 {0,0,0,0,0},
1060 {0,0,0,0,0},
1061 {0,0,0,0,0},
1062 {0,0,0,0,0},
1064 {0,0,0,0,0},
1065 {0,0,0,0,0},
1066 {0,0,0,0,0},
1067 {0,0,0,0,0},
1069 {0,0,0,0,0},
1070 {0,0,0,0,0},
1071 {0,0,0,0,0},
1072 {0,0,0,0,0},
1074 {0,0,0,0,0},
1075 {0,0,0,0,0},
1076 {0,0,0,0,0},
1077 {0,0,0,0,0},
1079 {0,0,0,0,0},
1080 {0,0,0,0,0},
1081 {0,0,0,0,0},
1082 {0,0,0,0,0},
1084 {0,0,0,0,0},
1085 {0,0,0,0,0},
1086 {0,0,0,0,0},
1087 {0,0,0,0,0},
1089 {0,0,0,0,0},
1090 {0,0,0,0,0},
1091 {0,0,0,0,0},
1092 {0,0,0,0,0},
1094 {0,0,0,0,0},
1095 {0,0,0,0,0},
1096 {0,0,0,0,0},
1097 {0,0,0,0,0},
1099 {0,0,0,0,0},
1100 {0,0,0,0,0},
1101 {0,0,0,0,0},
1102 {0,0,0,0,0},
1104 {0,0,0,0,0},
1105 {0,0,0,0,0},
1106 {0,0,0,0,0},
1107 {0,0,0,0,0},
1109 {0,0,0,0,0},
1110 {0,0,0,0,0},
1111 {0,0,0,0,0},
1112 {0,0,0,0,0},
1114 {0,0,0,0,0},
1115 {0,0,0,0,0},
1116 {0,0,0,0,0},
1117 {0,0,0,0,0}
1118 }
1119 };
1121 /* GPIO Driver hardware attributes */
1122 GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
1123 {
1124 {
1125 CSL_GPIO_0_CFG_REGS,
1126 &GPIO_intCfgs[0][0],
1127 NULL
1128 },
1130 {
1131 CSL_GPIO_1_CFG_REGS,
1132 &GPIO_intCfgs[1][0],
1133 NULL
1134 }
1135 };
1137 /* GPIO configuration structure */
1138 CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
1139 {
1140 {
1141 &GPIO_FxnTable_v0,
1142 NULL,
1143 &GPIO_v0_hwAttrs[0]
1144 },
1146 {
1147 &GPIO_FxnTable_v0,
1148 NULL,
1149 &GPIO_v0_hwAttrs[1]
1150 },
1152 {
1153 NULL,
1154 NULL,
1155 NULL
1156 }
1157 };
1159 /**
1160 * \brief This API gets the SoC level of GPIO intial configuration
1161 *
1162 * \param index GPIO instance index.
1163 * \param cfg Pointer to GPIO SOC initial config.
1164 *
1165 * \return 0 success: -1: error
1166 *
1167 */
1168 int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
1169 {
1170 int32_t ret = 0;
1172 if (index < GPIO_NUM_PORTS)
1173 {
1174 *cfg = GPIO_v0_hwAttrs[index];
1175 }
1176 else
1177 {
1178 ret = -1;
1179 }
1181 return ret;
1182 }
1184 /**
1185 * \brief This API sets the SoC level of GPIO intial configuration
1186 *
1187 * \param index GPIO instance index.
1188 * \param cfg Pointer to GPIO SOC initial config.
1189 *
1190 * \return 0 success: -1: error
1191 *
1192 */
1193 int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
1194 {
1195 int32_t ret = 0;
1197 if (index < GPIO_NUM_PORTS)
1198 {
1199 GPIO_v0_hwAttrs[index] = *cfg;
1200 }
1201 else
1202 {
1203 ret = -1;
1204 }
1206 return ret;
1207 }
1209 /**
1210 * \brief This API gets the number of GPIO pins per port
1211 * and GPIO number of ports
1212 *
1213 * \param numPins pointer to numPins variable.
1214 * \param numPorts pointer to numPorts variable.
1215 *
1216 * \return none
1217 *
1218 */
1219 void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
1220 {
1221 *numPins = GPIO_NUM_PINS_PER_PORT;
1222 *numPorts = GPIO_NUM_PORTS;
1223 }