1 /*
2 *
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4 *
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36 #ifndef _HYPLNK_H
37 #define _HYPLNK_H
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
43 /* System level header files */
44 #include <stdint.h>
45 #include <stdlib.h>
46 #include "hyplnk_cfg.h"
47 #include "hyplnkver.h"
49 /* ============================================================= */
50 /**
51 * @file hyplnk.h
52 *
53 * path ti/drv/hyplnk/hyplnk.h
54 *
55 * @brief Hyperlink transport sub-system API and Data Definitions
56 *
57 */
59 /** @mainpage hyperlink Low Level Driver
60 *
61 * @section intro Introduction
62 *
63 * The Hyperlink peripheral has also been known as vUSR and MCM. Some chip-specific
64 * definitions in CSL and documentation may have references to the old names.
65 *
66 * The Hyperlink peripheral provides a high-speed, low-latency, and low-power
67 * point-to-point link between two KeyStone devices.
68 *
69 * There is a userguide <http://www.ti.com/lit/sprugw8>.
70 *
71 * The HyperLink provides three basic functionalities between two devices:
72 *
73 * -# There is a memory mapped window on the local device which can
74 * be mapped by the remote device. This is the top part of the
75 * diagram below.
76 * -# There is a mapping functionality in the receive direction
77 * which allows the incoming addresses to be mapped across the device's
78 * memory space. This is the bottom part of the diagram below\n
79 * @image html address_translation.jpg
80 * -# There is the ability to send events (which can trigger hardware
81 * such as the EDMA or produce interrupts).
82 * -# Finally there is an ability to bootload the secondary device.
83 * See <http://www.ti.com/lit/sprugy5>.
84 *
85 * The primary APIs are:\n
86 * -- @ref Hyplnk_open : Opens the driver (by pointing to the peripheral's base address)\n
87 * -- @ref Hyplnk_readRegs : Reads one or more registers or tables\n
88 * -- @ref Hyplnk_writeRegs : Writes one or more registers or tables\n
89 * -- @ref Hyplnk_close : Close the driver instance (NOP since no memory is used by the driver)\n
90 * -- @ref Hyplnk_getWindow : Get the base address of the memory window used to access remote device\n
91 *
92 * The normal sequence of events to enable peripheral are below. There is a C
93 * code example in ti/drv/hyplnk/example/memoryMappedExample.
94 *
95 * -# Set up the system PLL (in the example, this is done via
96 * ti/drv/hyplnk/example/board_setup.gel)
97 * -# Enable the power domain for the peripheral via the CSL_PSC_enablePowerDomain()
98 * CSL_PSC_setModuleNextState() and CSL_PSC_startStateTransition. This sequence
99 * is in the example in function hyplnkExampleSysSetup().
100 * -# Set up the SERDES configuration in CSL_BootCfgSetVUSRConfigPLL,
101 * CSL_BootCfgSetVUSRRxConfig, and CSL_BootCfgSetVUSRTxConfig.
102 * -# Confirm that the power is enabled by reading the revision register
103 * @ref hyplnkRevReg_s.
104 * -# Enable the peripherial via the control register @ref hyplnkControlReg_s
105 * -# The peripheral is ready when @ref hyplnkStatusReg_s::pllUnlock becomes 0,
106 * the @ref hyplnkStatusReg_s::link becomes 1. Since both endpoints of the
107 * HyperLink must perform the synchronization, busywaiting as in the example
108 * may not be applicable. Once the peripheral is up, one of the two endpoints
109 * can program the communication for both since both the local and remote
110 * registers are available to both sides.
111 * -# The errors in @ref hyplnkStatusReg_s::lError, @ref hyplnkStatusReg_s::rError,
112 * and in @ref hyplnkECCErrorsReg_s should not occur. These indicate
113 * problems with the link. Troubleshooting can involve reducing the link speed
114 * via the SERDES registers in the boot config peripheral.
115 *
116 * Once the link is up, both devices can see each other's peripheral registers.
117 * Thus, each device can program its own parameters, or one can act as a master
118 * and control both device's parameters.
119 *
120 * The following actions are generally taken to set up the logical connection
121 * once the link is established
122 *
123 * -# Use @ref hyplnkRegisters_s::TXAddrOvly and @ref hyplnkRegisters_s::RXAddrSel
124 * to specify the agreed address encoding between the two devices.
125 * -# Use @ref hyplnkRegisters_s::RXPrivIDTbl and @ref hyplnkRegisters_s::RXSegTbl
126 * to specify the address decoding.
127 * -# Use @ref hyplnkRegisters_s::intCtrlTbl and @ref hyplnkRegisters_s::intPtrTbl
128 * to specify event/interrupt configuration (consider @ref hyplnkControlReg_s::int2cfg).
129 *
130 * Once the local memory window is identified by @ref Hyplnk_getWindow, the remote
131 * device can be read/written via this memory window using any master (direct CPU
132 * access (memcpy), peripherals, or DMA (EDMA).
133 *
134 */
136 /* Define hyplnk LLD Module as a master group in Doxygen format and add all HYPLNK LLD API
137 definitions to this group. */
138 /** @defgroup hyplnklld_module HYPLNK LLD Module API
139 * @{
140 */
141 /** @} */
143 /** @defgroup hyplnklld_api_functions HYPLNK LLD Functions
144 * @ingroup hyplnklld_module
145 */
147 /** @defgroup hyplnklld_api_macros HYPLNK LLD Macros
148 * @ingroup hyplnklld_module
149 */
151 /** @defgroup hyplnklld_api_structures HYPLNK LLD API Data Structures
152 * @ingroup hyplnklld_module
153 */
155 /** @defgroup hyplnklld_reg_structures HYPLNK LLD Register Definitions
156 * @ingroup hyplnklld_module
157 */
159 /** @defgroup hyplnklld_api_constants HYPLNK LLD Constants (enum's and define's)
160 * @ingroup hyplnklld_module
161 */
163 /** These are the possible return values from all HYPLNK LLD functions */
164 typedef enum
165 {
166 #ifdef hyplnk_DEBUG
167 /**
168 * The call succeeded, but the application could have leaked memory
169 * since a non-NULL pointer was overwritten. This only
170 */
171 hyplnk_RET_DBG_NON_NULL = -100L,
172 hyplnk_RET_DBG_USELESS_WRITE, /**< register write to readonly register */
173 hyplnk_RET_DBG_WRITE_OVERFLOW, /**< write value too big for bitfield */
174 #endif
175 hyplnk_RET_OK = 0, /**< Call succeeded */
176 hyplnk_RET_INV_HANDLE, /**< Invalid handle */
177 hyplnk_RET_INV_DEVICENUM, /**< @ref Hyplnk_open deviceNum invalid */
178 hyplnk_RET_INV_INITCFG, /**< Invalid Hyplnk_InitCfg */
179 hyplnk_RET_NO_INIT /**< Forgot to call Hyplnk_init() ? */
180 } hyplnkRet_e;
181 /* @} */
183 /**
184 * @ingroup hyplnklld_api_constants
185 *
186 * @{
187 */
188 /** Selects whether to query or modify the local or remote HyperLink peripheral. */
189 typedef enum
190 {
191 hyplnk_LOCATION_LOCAL, /**< Access the local HyperLink peripheral */
192 hyplnk_LOCATION_REMOTE /**< Access the remote HyperLink peripheral */
193 } hyplnkLocation_e;
194 /* @} */
196 /**
197 * @ingroup hyplnklld_api_constants
198 *
199 * @{
200 */
201 /** Specifies what portion of the Hyperlink peripheral is changed */
202 typedef enum
203 {
204 hyplnk_CONFIG_TYPE_TX_ADDR, /**< Configures the TX address mapping */
205 hyplnk_CONFIG_TYPE_RX_ADDR, /**< Configures one or more RX address maps */
206 hyplnk_CONFIG_CONTROL /**< Configures the rest of the registers */
207 } hyplnkConfigType_e;
208 /* @} */
211 /**
212 * @ingroup hyplnklld_reg_structures
213 * @brief Specification of the HyperLink Revision Register
214 *
215 * The Revision Register contains the major and minor revisions
216 * for the HyperLink module.
217 *
218 * @{
219 */
220 typedef struct hyplnkRevReg_s {
221 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
222 /**
223 * @brief [ro] Scheme
224 *
225 * Field size: 2 bits
226 */
227 uint8_t scheme;
228 /**
229 * @brief [ro] Business Unit
230 *
231 * Field size: 2 bits
232 */
233 uint8_t bu;
234 /**
235 * @brief [ro] Function identifier
236 *
237 * 0xe90 is HyperLink
238 *
239 * Field size: 12 bits
240 */
241 uint16_t func;
242 /**
243 * @brief [ro] RTL Version
244 *
245 * Field size: 5 bits
246 */
247 uint8_t rtl;
248 /**
249 * @brief [ro] Customer special version
250 *
251 * Field size: 2 bits
252 */
253 uint8_t cust;
254 /**
255 * @brief [ro] Major revision
256 *
257 * Field size: 3 bits
258 */
259 uint8_t revMaj;
260 /**
261 * @brief [ro] Minor revision
262 *
263 * Field size: 6 bits
264 */
265 uint8_t revMin;
266 } hyplnkRevReg_t;
267 /* @} */
269 /**
270 * @ingroup hyplnklld_reg_structures
271 * @brief Specification of the HyperLink Control Register
272 *
273 * The Control Register determines operation of the HyperLink module.
274 *
275 * @{
276 */
277 typedef struct hyplnkControlReg_s {
278 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
279 /**
280 * @brief [rw] Interrupt Local: set to 1 to keep interrupts local
281 *
282 * Field size: 1 bit
283 *
284 * This bit determines whether interrupts are posted in the
285 * Interrupt Status/Clear Register or forwarded via the serial interface.
286 * When set, interrupts are posted in @ref hyplnkIntStatusClrReg_s.
287 * When clear, interrupts are forwarded out the serial interface to the
288 * remote device.
289 */
290 uint8_t intLocal;
291 /**
292 * @brief [rw] Module Status (Error) Interrupt Enable.
293 *
294 * Field size: 1 bit
295 *
296 * This bit causes HyperLink module status interrupts to be posted to
297 * @ref hyplnkIntPendSetReg_s.
298 *
299 * When this bit is enabled and one of the
300 * @ref hyplnkStatusReg_t::rError and @ref hyplnkStatusReg_t::lError fields
301 * become set, then this bit decides whether an interrupt is generated
302 */
303 uint8_t statusIntEnable;
304 /**
305 * @brief [rw] Vector (number) used by the Module Status (Error) Interrupt
306 *
307 * Field size: 5 bits
308 *
309 * When a Module Status interrupt allowed by @ref intLocal occurs,
310 * specifies which interrupt number in the Interrupt Pending/Set Register
311 * will be triggered.
312 */
313 uint8_t statusIntVec;
314 /**
315 * @brief [rw] Selects whether to use @ref hyplnkIntStatusClrReg_s.
316 *
317 * Field size: 1 bit
318 *
319 * When this bit is set, @ref hyplnkIntStatusClrReg_s is written
320 * directly with the status contained in interrupt packets. When this bit is
321 * set, the least significant 8 bits of the Interrupt Pointer Register are
322 * used to point to a local configuration register (typically the Interrupt
323 * Pending/Set Register). When clear, bits [31-2] of the Interrupt Pointer
324 * Register are used by the VBUSM Master interface as the address of interrupt
325 * set register.
326 */
327 uint8_t int2cfg;
328 /**
329 * @brief [rw] Stops/kills all pending transactions then stops serial tx/rx.
330 *
331 * Field size: 1 bit
332 *
333 * When set will disable all partial or remote register operation, and
334 * error them with an bad_address status. This bit should be set before
335 * @ref iLoop or @ref reset bits are changed.
336 */
337 uint8_t serialStop;
338 /**
339 * @brief [rw] Internal (serial level) loopback enable
340 *
341 * Field size: 1 bit
342 *
343 * This bit when set causes the serial transmit data to be wrapped back
344 * to the serial receive data. When changing this bit, it is recommended
345 * that the serial_stop bit be set and that all outstanding transactions have
346 * completed before the iloop bit is changes at which time the @ref serialStop
347 * bit can be cleared to resume normal operation.
348 */
349 uint8_t iLoop;
350 /**
351 * @brief [rw] Resets the peripheral
352 *
353 * Field size: 1 bit
354 *
355 * When this bit is set, all internal state machines are reset, the
356 * serial interface is disabled, and link is lost.
357 *
358 * Note: Any bus transaction in flight between the devices will be lost.
359 * When changing this bit, it is recommended that the
360 * @ref serialStop bit be set and that all outstanding
361 * transactions have completed @ref hyplnkStatusReg_t::rPend
362 * before the reset bit is set. After the @ref reset bit is cleared
363 * the @ref serialStop bit can be cleared to resume normal operation.
364 */
365 uint8_t reset;
366 } hyplnkControlReg_t;
367 /* @} */
369 /**
370 * @ingroup hyplnklld_reg_structures
371 * @brief Specification of the HyperLink Status Register
372 *
373 * The Status Register is used to detect conditions that may be of
374 * interest to the system designer
375 *
376 * @{
377 */
378 typedef struct hyplnkStatusReg_s {
379 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
380 /**
381 * @brief [ro] Size of the inbound serial data capability.
382 *
383 * Field size: 4 bits
384 */
385 uint8_t swidthin;
386 /**
387 * @brief [ro] Size of the outbound serial data capability.
388 *
389 * Field size: 4 bits
390 */
391 uint8_t swidthout;
392 /**
393 * @brief [ro] Serial logic in halted state
394 *
395 * Field size: 1 bit
396 *
397 * This could be because @ref hyplnkControlReg_t::reset,
398 * @ref hyplnkControlReg_t::serialStop, or @ref pllUnlock are active
399 */
400 uint8_t serialHalt;
401 /**
402 * @brief [ro] The SerDes PLL is not locked
403 *
404 * Field size: 1 bit
405 *
406 * This disables all serial operations
407 */
408 uint8_t pllUnlock;
409 /**
410 * @brief [ro] Remote Request Pending
411 *
412 * Field size: 1 bit
413 *
414 * The user should monitor this bit after setting
415 * @ref hyplnkControlReg_t::serialStop and before
416 * changing @ref hyplnkControlReg_t::iLoop or
417 * @ref hyplnkControlReg_t::reset bits
418 *
419 */
420 uint8_t rPend;
421 /**
422 * @brief [ro] Inbound flow control is blocking outbound data
423 *
424 * Field size: 1 bit
425 *
426 * Indicates that a flow control enable request has been received
427 * and has stalled transmit until a flow control disable request is received.
428 */
429 uint8_t iFlow;
430 /**
431 * @brief [ro] Outbound flow control has been requested
432 *
433 * Field size: 1 bit
434 *
435 * Indicates that a flow control enable request has been received
436 * and has stalled transmit until a flow control disable request is received.
437 */
438 uint8_t oFlow;
439 /**
440 * @brief [rw] Remote uncorrectable error
441 *
442 * Field size: 1 bit
443 *
444 * This bit indicates that a downstream HyperLink module
445 * has detected an uncorrectable ECC error. This bit is set when an ECC
446 * status is received from the management interface. This bit is cleared
447 * by writing a one to it and the remote serial interface has been reset.
448 *
449 * When this bit is set by the peripheral, an interrupt will occur if
450 * enabled in @ref hyplnkControlReg_t::statusIntEnable. The remote device
451 * will need to perform a serial reset @ref hyplnkControlReg_t::reset or
452 * device reset to recover from this catastrophic failure. Since this
453 * indicates that a transaction has been lost, if the @ref rPend bit is
454 * set along with this bit, it is possible that this device will also
455 * require a reset as a transaction from this device may have been lost.
456 */
457 uint8_t rError;
458 /**
459 * @brief [rw] Local uncorrectable error.
460 *
461 * Field size: 1 bit
462 *
463 * This bit indicates that an inbound packet contains an uncorrectable
464 * ECC error. This bit is cleared by writing a one to it after the error
465 * has been corrected. When set by the peripheral, this bit will cause an
466 * interrupt if enabled in @ref hyplnkControlReg_t::statusIntEnable.
467 *
468 * This error indicate a catastrophic failure and that the receive link
469 * is down. The @ref hyplnkControlReg_t::reset bit must be toggled to
470 * recover from this error. It is possible that returning transactions
471 * may have been lost in which case a device reset maybe necessary to recover.
472 */
473 uint8_t lError;
474 /**
475 * @brief [ro] FIFO 3 (Slave Commands) is not empty
476 *
477 * Field size: 1 bit
478 */
479 uint8_t nfEmpty3;
480 /**
481 * @brief [ro] FIFO 2 (Slave Data) is not empty
482 *
483 * Field size: 1 bit
484 */
485 uint8_t nfEmpty2;
486 /**
487 * @brief [ro] FIFO 1 (Master Commands) is not empty
488 *
489 * Field size: 1 bit
490 */
491 uint8_t nfEmpty1;
492 /**
493 * @brief [ro] FIFO 0 (Master Data) is not empty
494 *
495 * Field size: 1 bit
496 */
497 uint8_t nfEmpty0;
498 /**
499 * @brief [ro] There are pending slave requests
500 *
501 * Field size: 1 bit
502 */
503 uint8_t sPend;
504 /**
505 * @brief [ro] There are pending master requests
506 *
507 * Field size: 1 bit
508 */
509 uint8_t mPend;
510 /**
511 * @brief [ro] The serial interface is working
512 *
513 * Field size: 1 bit
514 */
515 uint8_t link;
516 } hyplnkStatusReg_t;
517 /* @} */
519 /**
520 * @ingroup hyplnklld_reg_structures
521 * @brief Specification of the Hyperlink Interrupt Priority Vector Status/Clear Register
522 *
523 * When read, the Interrupt Priority Vector Status/Clear register
524 * displays the highest priority vector with a pending interrupt.
525 * When writing, only @ref hyplnkIntPriVecReg_s::intStat "intStat" is valid,
526 * and the value represents the vector of the interrupt to be cleared.
527 *
528 * @{
529 */
530 typedef struct hyplnkIntPriVecReg_s {
531 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
532 /**
533 * @brief [ro] 1 indicates NO interrupts are in @ref hyplnkIntStatusClrReg_s
534 *
535 * Field size: 1 bit
536 */
537 uint8_t noIntPend; /**< @brief [ro] 1 indicates NO interrupts are in @ref hyplnkIntStatusClrReg_s */
538 /**
539 * @brief [rw] Interrupt Priority Vector Status
540 *
541 * Field size: 5 bits
542 *
543 * When read, this field displays the vector that is mapped to the highest
544 * priority interrupt bit that is pending from @ref hyplnkIntStatusClrReg_s,
545 * with Bit 0 as the highest priority, and Bit 31 as the lowest. Writing back
546 * the vector value into this field will clear the interrupt.
547 */
548 uint8_t intStat;
549 } hyplnkIntPriVecReg_t;
550 /* @} */
552 /**
553 * @ingroup hyplnklld_reg_structures
554 * @brief Specification of the Hyperlink Interrupt Status/Clear Register
555 *
556 * The Interrupt Status/Clear Register indicates the unmasked interrupt
557 * status. Writing 1 to any bit in this register will clear the
558 * corresponding interrupt.
559 *
560 * @{
561 */
562 typedef struct hyplnkIntStatusClrReg_s {
563 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
564 /**
565 * @brief [rw] Interrupt Status/Clear Bitfield
566 *
567 * Field size: 32 bits
568 *
569 * Each bit represents the unmasked status of its respective interrupt. Writing
570 * a 1 to a particular bit will clear it.
571 */
572 uint32_t intClr;
573 } hyplnkIntStatusClrReg_t;
574 /* @} */
576 /**
577 * @ingroup hyplnklld_reg_structures
578 * @brief Specification of the Hyperlink Interrupt Pending/Set Register
579 *
580 * The Interrupt Pending/Set Register indicates the pending interrupt
581 * status. This register can be written by the local host or by remote
582 * interrupt packets when the @ref hyplnkControlReg_s::int2cfg bit is
583 * set. When bits are set in this register, an interrupt output is signaled,
584 * if not already pending. Any write with a value of 0x0000 to this register
585 * will EOI the @ref hyplnkIntPendSetReg_s interrupt output pins so they
586 * retrigger the interrupt. That is, writing a zero to @ref hyplnkIntPendSetReg_s
587 * retriggers the output interrupt lines if any bits are still set in this
588 * register.
589 *
590 * @{
591 */
592 typedef struct hyplnkIntPendSetReg_s {
593 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
594 /**
595 * @brief [rw] Interrupt Pending/Set Bitfield
596 *
597 * Field size: 32 bits
598 *
599 * Each bit represents the unmasked status of its respective pending
600 * interrupt. Writing a 1 to a particular bit will activate it.
601 */
602 uint32_t intSet;
603 } hyplnkIntPendSetReg_t;
604 /* @} */
606 /**
607 * @ingroup hyplnklld_reg_structures
608 * @brief Specification of the Hyperlink Generate Soft Interrupt Value Register
609 *
610 * The Generate Soft Interrupt Register should be written with a vector
611 * of the hardware index of the interrupt that is enabled for software
612 * interrupts. If the @ref hyplnkIntCtrlValReg_s::iSec bit is also set,
613 * the csecure interface pin must be set to set the software interrupt.
614 * This register is also used to EOI Hyperlink_int_i hardware interrupts
615 * programmed in level mode.
616 *
617 * @{
618 */
619 typedef struct hyplnkGenSoftIntReg_s {
620 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
621 /**
622 * @brief [rw] Force end of interrupt
623 *
624 * Field size: 8 bits
625 *
626 * Reads as 0.
627 *
628 * Writing 0xff to @ref eoiFlag and @ref iVector will deassert (EOI) all
629 * level sensitive interrupts.
630 *
631 * Writing 0xfe to @ref eoiFlag and an interrupt number to @ref iVector
632 * will deassert (EOI) the specified interrupt.
633 *
634 * Writing 0 to the @ref eoiFlag will assert the interrupt specified
635 * by @ref iVector.
636 */
637 uint8_t eoiFlag;
638 /**
639 * @brief [rw] Interrupt number to assert or deassert (EOI)
640 *
641 * Field size: 8 bits
642 *
643 * Hardware index for the interrupt that will be asserted or deasserted.
644 * If the @ref hyplnkIntCtrlValReg_s::SIEN bit is set
645 * and the security level is met, the internal hardware pending bit will be set.
646 * This interrupt is forwarded based on @ref hyplnkControlReg_t::intLocal.
647 */
648 uint8_t iVector;
649 } hyplnkGenSoftIntReg_t;
650 /* @} */
652 /**
653 * @ingroup hyplnklld_reg_structures
654 * @brief Specification of the Tx Address Overlay Control Register
655 *
656 * The Tx Address Map Mask Register is used to trim the transmitted packet
657 * address to remote device VBUSM addresses.
658 *
659 * @{
660 */
661 typedef struct hyplnkTXAddrOvlyReg_s {
662 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
663 /**
664 * @brief [rw] Secure bit location in outgoing address
665 *
666 * Field size: 4 bits
667 *
668 * This is the inverse of @ref hyplnkRXAddrSelReg_s::rxSecSel
669 *
670 * <TABLE>
671 * <TR><TH>@ref txSecOvl</TH><TH>Secure bit position in outgoing addr</TH></TR>
672 * <TR><TD>0</TD> <TD>none</TD></TR>
673 * <TR><TD>1</TD> <TD>17</TD></TR>
674 * <TR><TD>2</TD> <TD>18</TD></TR>
675 * <TR><TD>3</TD> <TD>19</TD></TR>
676 * <TR><TD>4</TD> <TD>20</TD></TR>
677 * <TR><TD>5</TD> <TD>21</TD></TR>
678 * <TR><TD>6</TD> <TD>22</TD></TR>
679 * <TR><TD>7</TD> <TD>23</TD></TR>
680 * <TR><TD>8</TD> <TD>24</TD></TR>
681 * <TR><TD>9</TD> <TD>25</TD></TR>
682 * <TR><TD>10</TD> <TD>26</TD></TR>
683 * <TR><TD>11</TD> <TD>27</TD></TR>
684 * <TR><TD>12</TD> <TD>28</TD></TR>
685 * <TR><TD>13</TD> <TD>29</TD></TR>
686 * <TR><TD>14</TD> <TD>30</TD></TR>
687 * <TR><TD>15</TD> <TD>31</TD></TR>
688 * </TABLE>
689 */
690 uint8_t txSecOvl;
691 /**
692 * @brief [rw] PrivID bit location in outgoing address
693 *
694 * Field size: 4 bits
695 *
696 * This is the inverse of @ref hyplnkRXAddrSelReg_s::rxPrivIDSel
697 *
698 * <TABLE>
699 * <TR><TH>@ref txPrivIDOvl</TH><TH>Outgoing Address bits</TH><TH>PrivID bits</TH></TR>
700 * <TR><TD>0</TD> <TD>none</TD> <TD>none</TD></TR>
701 * <TR><TD>1</TD> <TD>[20-17]</TD> <TD>[3-0]</TD></TR>
702 * <TR><TD>2</TD> <TD>[21-18]</TD> <TD>[3-0]</TD></TR>
703 * <TR><TD>3</TD> <TD>[22-19]</TD> <TD>[3-0]</TD></TR>
704 * <TR><TD>4</TD> <TD>[23-20]</TD> <TD>[3-0]</TD></TR>
705 * <TR><TD>5</TD> <TD>[24-21]</TD> <TD>[3-0]</TD></TR>
706 * <TR><TD>6</TD> <TD>[25-22]</TD> <TD>[3-0]</TD></TR>
707 * <TR><TD>7</TD> <TD>[26-23]</TD> <TD>[3-0]</TD></TR>
708 * <TR><TD>8</TD> <TD>[27-24]</TD> <TD>[3-0]</TD></TR>
709 * <TR><TD>9</TD> <TD>[28-25]</TD> <TD>[3-0]</TD></TR>
710 * <TR><TD>10</TD> <TD>[29-26]</TD> <TD>[3-0]</TD></TR>
711 * <TR><TD>11</TD> <TD>[30-27]</TD> <TD>[3-0]</TD></TR>
712 * <TR><TD>12</TD> <TD>[31-28]</TD> <TD>[3-0]</TD></TR>
713 * <TR><TD>13</TD> <TD>[31-29]</TD> <TD>[2-0]</TD></TR>
714 * <TR><TD>14</TD> <TD>[31-30]</TD> <TD>[1-0]</TD></TR>
715 * <TR><TD>15</TD> <TD>[31]</TD> <TD>[0]</TD></TR>
716 * </TABLE>
717 */
718 uint8_t txPrivIDOvl;
719 /**
720 * @brief [rw] Mask applied to each address before transmitting
721 *
722 * Field size: 4 bits
723 *
724 * <TABLE>
725 * <TR><TH>@ref txIgnMask</TH><TH>AND-mask</TH></TR>
726 * <TR><TD>0</TD> <TD>0x0001FFFF</TD></TR>
727 * <TR><TD>1</TD> <TD>0x0003FFFF</TD></TR>
728 * <TR><TD>2</TD> <TD>0x0007FFFF</TD></TR>
729 * <TR><TD>3</TD> <TD>0x000FFFFF</TD></TR>
730 * <TR><TD>4</TD> <TD>0x001FFFFF</TD></TR>
731 * <TR><TD>5</TD> <TD>0x003FFFFF</TD></TR>
732 * <TR><TD>6</TD> <TD>0x007FFFFF</TD></TR>
733 * <TR><TD>7</TD> <TD>0x00FFFFFF</TD></TR>
734 * <TR><TD>8</TD> <TD>0x01FFFFFF</TD></TR>
735 * <TR><TD>9</TD> <TD>0x03FFFFFF</TD></TR>
736 * <TR><TD>10</TD> <TD>0x07FFFFFF</TD></TR>
737 * <TR><TD>11</TD> <TD>0x0FFFFFFF</TD></TR>
738 * <TR><TD>12</TD> <TD>0x1FFFFFFF</TD></TR>
739 * <TR><TD>13</TD> <TD>0x3FFFFFFF</TD></TR>
740 * <TR><TD>14</TD> <TD>0x7FFFFFFF</TD></TR>
741 * <TR><TD>15</TD> <TD>0xFFFFFFFF</TD></TR>
742 * </TABLE>
743 */
744 uint8_t txIgnMask;
745 } hyplnkTXAddrOvlyReg_t;
746 /* @} */
748 /**
749 * @ingroup hyplnklld_reg_structures
750 * @brief Specification of the Rx Address Selector Control Register
751 *
752 * The Rx Address Selector Control Register is used to configure
753 * which Rx Address bits select the Secure, PrivID and Segment/Length
754 * value arrays. This register also holds the secure value when the
755 * secure selection is one or zero.
756 *
757 * @image html address_translation_RX.jpg
758 *
759 * @{
760 */
761 typedef struct hyplnkRXAddrSelReg_s {
762 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
763 /**
764 * @brief Value of secure signal when bit referenced by @ref rxSecSel is 1
765 *
766 * Field size: 1 bit
767 */
768 uint8_t rxSecHi;
769 /**
770 * @brief Value of secure signal when bit referenced by @ref rxSecSel is 0
771 *
772 * Field size: 1 bit
773 */
774 uint8_t rxSecLo;
775 /**
776 * @brief Select RX address bit used as Secure bit.
777 *
778 * Field size: 4 bits
779 *
780 * This is the inverse of @ref hyplnkTXAddrOvlyReg_s::txSecOvl
781 *
782 * The secure signal is determined by selecting the bit specified by
783 * @ref rxSecSel from the incoming address, then deciding the signal value
784 * by apply @ref rxSecHi when that address bit is 1, or @ref rxSecLo when that
785 * address bit is 0.
786 *
787 * <TABLE>
788 * <TR><TH>@ref rxSecSel</TH><TH>Secure bit position in incoming addr</TH></TR>
789 * <TR><TD>0</TD> <TD>16</TD></TR>
790 * <TR><TD>1</TD> <TD>17</TD></TR>
791 * <TR><TD>2</TD> <TD>18</TD></TR>
792 * <TR><TD>3</TD> <TD>19</TD></TR>
793 * <TR><TD>4</TD> <TD>20</TD></TR>
794 * <TR><TD>5</TD> <TD>21</TD></TR>
795 * <TR><TD>6</TD> <TD>22</TD></TR>
796 * <TR><TD>7</TD> <TD>23</TD></TR>
797 * <TR><TD>8</TD> <TD>24</TD></TR>
798 * <TR><TD>9</TD> <TD>25</TD></TR>
799 * <TR><TD>10</TD> <TD>26</TD></TR>
800 * <TR><TD>11</TD> <TD>27</TD></TR>
801 * <TR><TD>12</TD> <TD>28</TD></TR>
802 * <TR><TD>13</TD> <TD>29</TD></TR>
803 * <TR><TD>14</TD> <TD>30</TD></TR>
804 * <TR><TD>15</TD> <TD>31</TD></TR>
805 * </TABLE>
806 */
807 uint8_t rxSecSel;
808 /**
809 * @brief [rw] The RX address bits to use as PrivID lookup
810 *
811 * Field size: 4 bits
812 *
813 * The PrivID index is extracted from the specified incoming address bits.
814 * The index is then looked up in the table defined through
815 * @ref hyplnkRXPrivIDIdxReg_s and @ref hyplnkRXPrivIDValReg_s
816 *
817 * This is the inverse of @ref hyplnkTXAddrOvlyReg_s::txPrivIDOvl
818 *
819 * <TABLE>
820 * <TR><TH>@ref rxPrivIDSel</TH><TH>PrivID index</TH></TR>
821 * <TR><TD>0</TD> <TD>0</TD></TR>
822 * <TR><TD>1</TD> <TD>RxAddress[20-17]</TD></TR>
823 * <TR><TD>2</TD> <TD>RxAddress[21-18]</TD></TR>
824 * <TR><TD>3</TD> <TD>RxAddress[22-19]</TD></TR>
825 * <TR><TD>4</TD> <TD>RxAddress[23-20]</TD></TR>
826 * <TR><TD>5</TD> <TD>RxAddress[24-21]</TD></TR>
827 * <TR><TD>6</TD> <TD>RxAddress[25-22]</TD></TR>
828 * <TR><TD>7</TD> <TD>RxAddress[26-23]</TD></TR>
829 * <TR><TD>8</TD> <TD>RxAddress[27-24]</TD></TR>
830 * <TR><TD>9</TD> <TD>RxAddress[28-25]</TD></TR>
831 * <TR><TD>10</TD> <TD>RxAddress[29-26]</TD></TR>
832 * <TR><TD>11</TD> <TD>RxAddress[30-27]</TD></TR>
833 * <TR><TD>12</TD> <TD>RxAddress[31-28]</TD></TR>
834 * <TR><TD>13</TD> <TD>RxAddress[31-29]</TD></TR>
835 * <TR><TD>14</TD> <TD>RxAddress[31-30]</TD></TR>
836 * <TR><TD>15</TD> <TD>RxAddress[31]</TD></TR>
837 * </TABLE>
838 */
839 uint8_t rxPrivIDSel;
840 /**
841 * @brief [rw] Segment and Offset Selector
842 *
843 * Field size: 4 bits
844 *
845 * The segment number and offset are extracted from the incoming
846 * address as specified in the following table.
847 *
848 * The segment number is then looked up in @ref hyplnkRXSegValReg_s
849 *
850 * This is the inverse of @ref hyplnkTXAddrOvlyReg_s::txIgnMask
851 *
852 * <TABLE>
853 * <TR><TH>@ref rxSegSel</TH><TH>Segment index</TH><TH>Offset mask</TH></TR>
854 * <TR><TD>0</TD> <TD>0</TD> <TD>0xFFFFFFFF</TD></TR>
855 * <TR><TD>1</TD> <TD>RxAddress[22-17]</TD> <TD>0x0001FFFF</TD></TR>
856 * <TR><TD>2</TD> <TD>RxAddress[23-18]</TD> <TD>0x0003FFFF</TD></TR>
857 * <TR><TD>3</TD> <TD>RxAddress[24-19]</TD> <TD>0x0007FFFF</TD></TR>
858 * <TR><TD>4</TD> <TD>RxAddress[25-20]</TD> <TD>0x000FFFFF</TD></TR>
859 * <TR><TD>5</TD> <TD>RxAddress[26-21]</TD> <TD>0x001FFFFF</TD></TR>
860 * <TR><TD>6</TD> <TD>RxAddress[27-22]</TD> <TD>0x003FFFFF</TD></TR>
861 * <TR><TD>7</TD> <TD>RxAddress[28-23]</TD> <TD>0x007FFFFF</TD></TR>
862 * <TR><TD>8</TD> <TD>RxAddress[29-24]</TD> <TD>0x00FFFFFF</TD></TR>
863 * <TR><TD>9</TD> <TD>RxAddress[30-25]</TD> <TD>0x01FFFFFF</TD></TR>
864 * <TR><TD>10</TD> <TD>RxAddress[31-26]</TD> <TD>0x03FFFFFF</TD></TR>
865 * <TR><TD>11</TD> <TD>RxAddress[31-17]</TD> <TD>0x07FFFFFF</TD></TR>
866 * <TR><TD>12</TD> <TD>RxAddress[31-28]</TD> <TD>0x0FFFFFFF</TD></TR>
867 * <TR><TD>13</TD> <TD>RxAddress[31-29]</TD> <TD>0x1FFFFFFF</TD></TR>
868 * <TR><TD>14</TD> <TD>RxAddress[31-30]</TD> <TD>0x3FFFFFFF</TD></TR>
869 * <TR><TD>15</TD> <TD>RxAddress[31]</TD> <TD>0x7FFFFFFF</TD></TR>
870 * </TABLE>
871 */
872 uint8_t rxSegSel;
873 } hyplnkRXAddrSelReg_t;
874 /* @} */
876 /**
877 * @ingroup hyplnklld_reg_structures
878 * @brief Specification of the Rx Address PrivID Index Register
879 *
880 * @{
881 */
882 typedef struct hyplnkRXPrivIDIdxReg_s {
883 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
884 /**
885 * @brief [rw] Selects PrivID array element number
886 *
887 * Field size: 4 bits
888 *
889 * The specified array element can be read or written via
890 * @ref hyplnkRXPrivIDValReg_s::rxPrivIDVal after the index is
891 * written.
892 */
893 uint8_t rxPrivIDIdx;
894 } hyplnkRXPrivIDIdxReg_t;
895 /* @} */
897 /**
898 * @ingroup hyplnklld_reg_structures
899 * @brief Specification of the Rx Address PrivID Value Register
900 *
901 * @{
902 */
903 typedef struct hyplnkRXPrivIDValReg_s {
904 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
905 /**
906 * @brief [rw] Selects PrivID value
907 *
908 * Field size: 4 bits
909 *
910 * Specifies the PrivID in the PrivID lookup table at the position
911 * specified by @ref hyplnkRXPrivIDIdxReg_s::rxPrivIDIdx. This
912 * is used to dereference the PrivID from the address bits selected
913 * by @ref hyplnkRXAddrSelReg_s::rxPrivIDSel.
914 */
915 uint8_t rxPrivIDVal;
916 } hyplnkRXPrivIDValReg_t;
917 /* @} */
919 /**
920 * @ingroup hyplnklld_reg_structures
921 * @brief Specification of the Rx Address Segment Index Register
922 *
923 * @{
924 */
925 typedef struct hyplnkRXSegIdxReg_s {
926 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
927 /**
928 * @brief [rw] Selects segment array element number
929 *
930 * Field size: 6 bits
931 *
932 * The specified array element can be read or written via
933 * @ref hyplnkRXSegValReg_s after the index is written.
934 */
935 uint8_t rxSegIdx;
936 } hyplnkRXSegIdxReg_t;
937 /* @} */
939 /**
940 * @ingroup hyplnklld_reg_structures
941 * @brief Specification of the Rx Address Segment Value Register
942 *
943 * There is an array of 64 segment value registers. The particular
944 * segment value register accessed via @ref hyplnkRXSegValReg_s
945 * is specified in @ref hyplnkRXSegIdxReg_s::rxSegIdx.
946 *
947 * After the segment index is extracted from the incoming address
948 * based on @ref hyplnkRXAddrSelReg_s::rxSegSel, the index
949 * is dereferenced through this table to get a base address and
950 * length.
951 *
952 * The local address (which will be presented through the SES
953 * or SMS MPAX) is constructed by:
954 *
955 * ((@ref hyplnkRXSegValReg_s::rxSegVal "rxSegVal" << 16) | RxAddress) &
956 * ((1 << (1 + @ref hyplnkRXSegValReg_s::rxLenVal "rxLenVal")) - 1)
957 * @{
958 */
959 typedef struct hyplnkRXSegValReg_s {
960 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
961 /**
962 * @brief [rw] Segment address value (base address)
963 *
964 * Field size: 16 bits
965 */
966 uint16_t rxSegVal;
967 /**
968 * @brief [rw] Selects segment size
969 *
970 * Field size: 5 bits
971 *
972 * <TABLE>
973 * <TR><TH>@ref rxLenVal</TH><TH>Segment Size</TH></TR>
974 * <TR><TD>0-7</TD> <TD>0</TD></TR>
975 * <TR><TD>8</TD> <TD>0x0 0000 0200</TD></TR>
976 * <TR><TD>9</TD> <TD>0x0 0000 0400</TD></TR>
977 * <TR><TD>10</TD> <TD>0x0 0000 0800</TD></TR>
978 * <TR><TD>11</TD> <TD>0x0 0000 1000</TD></TR>
979 * <TR><TD>12</TD> <TD>0x0 0000 2000</TD></TR>
980 * <TR><TD>13</TD> <TD>0x0 0000 4000</TD></TR>
981 * <TR><TD>14</TD> <TD>0x0 0000 8000</TD></TR>
982 * <TR><TD>15</TD> <TD>0x0 0001 0000</TD></TR>
983 * <TR><TD>16</TD> <TD>0x0 0002 0000</TD></TR>
984 * <TR><TD>17</TD> <TD>0x0 0004 0000</TD></TR>
985 * <TR><TD>18</TD> <TD>0x0 0008 0000</TD></TR>
986 * <TR><TD>19</TD> <TD>0x0 0010 0000</TD></TR>
987 * <TR><TD>20</TD> <TD>0x0 0020 0000</TD></TR>
988 * <TR><TD>21</TD> <TD>0x0 0040 0000</TD></TR>
989 * <TR><TD>22</TD> <TD>0x0 0080 0000</TD></TR>
990 * <TR><TD>23</TD> <TD>0x0 0100 0000</TD></TR>
991 * <TR><TD>24</TD> <TD>0x0 0200 0000</TD></TR>
992 * <TR><TD>25</TD> <TD>0x0 0400 0000</TD></TR>
993 * <TR><TD>26</TD> <TD>0x0 0800 0000</TD></TR>
994 * <TR><TD>27</TD> <TD>0x0 1000 0000</TD></TR>
995 * <TR><TD>28</TD> <TD>0x0 2000 0000</TD></TR>
996 * <TR><TD>29</TD> <TD>0x0 4000 0000</TD></TR>
997 * <TR><TD>30</TD> <TD>0x0 8000 0000</TD></TR>
998 * <TR><TD>31</TD> <TD>0x1 0000 0000</TD></TR>
999 * </TABLE>
1000 */
1001 uint8_t rxLenVal;
1002 } hyplnkRXSegValReg_t;
1003 /* @} */
1005 /**
1006 * @ingroup hyplnklld_reg_structures
1007 * @brief Specification of the Chip Version Register
1008 *
1009 * @{
1010 */
1011 typedef struct hyplnkChipVerReg_s {
1012 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1013 /**
1014 * @brief [ro] Device Revision
1015 *
1016 * Field size: 16 bits
1017 *
1018 * Reflects value of device_rev pins (not brought out to chip pins)
1019 */
1020 uint16_t devRev;
1021 /**
1022 * @brief [ro] Device ID
1023 *
1024 * Field size: 16 bits
1025 *
1026 * Reflects value of device_id pins (not brought out to chip pins)
1027 */
1028 uint16_t devID;
1029 } hyplnkChipVerReg_t;
1030 /* @} */
1032 /**
1033 * @ingroup hyplnklld_reg_structures
1034 * @brief Specification of the Lane Power Management Control Register
1035 *
1036 * The Power Management Control Register configures how the HyperLink
1037 * peripheral dynamically changes the number of lanes to save power.
1038 *
1039 * @{
1040 */
1041 typedef struct hyplnkLanePwrMgmtReg_s {
1042 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1043 /**
1044 * @brief [rw] High to Low clocks
1045 *
1046 * Field size: 3 bits
1047 *
1048 * Number of clocks [in peripheral domain] that the FIFO falls below 1/4
1049 * rate before a transition from high speed to low speed is taken.
1050 *
1051 * <TABLE>
1052 * <TR><TH>@ref H2L</TH><TH>Clocks</TH></TR>
1053 * <TR><TD>0</TD> <TD>64</TD></TR>
1054 * <TR><TD>1</TD> <TD>128</TD></TR>
1055 * <TR><TD>2</TD> <TD>256</TD></TR>
1056 * <TR><TD>3</TD> <TD>512</TD></TR>
1057 * <TR><TD>4</TD> <TD>1024</TD></TR>
1058 * <TR><TD>5</TD> <TD>2048</TD></TR>
1059 * <TR><TD>6</TD> <TD>4096</TD></TR>
1060 * <TR><TD>7</TD> <TD>8192</TD></TR>
1061 * </TABLE>
1062 *
1063 */
1064 uint8_t H2L;
1065 /**
1066 * @brief [rw] Low to High clocks
1067 *
1068 * Field size: 3 bits
1069 *
1070 * Number of clocks [in peripheral domain] that the FIFO is busy before
1071 * a transition to high speed is taken.
1072 *
1073 * <TABLE>
1074 * <TR><TH>@ref L2H</TH><TH>Clocks</TH></TR>
1075 * <TR><TD>0</TD> <TD>64</TD></TR>
1076 * <TR><TD>1</TD> <TD>128</TD></TR>
1077 * <TR><TD>2</TD> <TD>256</TD></TR>
1078 * <TR><TD>3</TD> <TD>512</TD></TR>
1079 * <TR><TD>4</TD> <TD>1024</TD></TR>
1080 * <TR><TD>5</TD> <TD>2048</TD></TR>
1081 * <TR><TD>6</TD> <TD>4096</TD></TR>
1082 * <TR><TD>7</TD> <TD>8192</TD></TR>
1083 * </TABLE>
1084 */
1085 uint8_t L2H;
1086 /**
1087 * @brief [rw] Periodic Wakeup Control
1088 *
1089 * Field size: 8 bits
1090 *
1091 * The wakeup period is (@ref PWC + 1) * 65536 SERDES clocks.
1092 *
1093 * The expected value is 94 (10ms).
1094 *
1095 * When the timer expires, the SerDes will be woken up at full speed.
1096 * If the SerDes is operated at full speed due to other reasons, the
1097 * timer will start over. That is this controls the maximum interval between
1098 * full speed events.
1099 *
1100 */
1101 uint8_t PWC;
1102 /**
1103 * @brief [rw] or [ro] High Speed operation is possible
1104 *
1105 * Field size: 1 bits
1106 *
1107 * It is only settable when using the 45nm SerDes. Otherwise it is
1108 * a [ro] bit with a value of zero.
1109 */
1110 uint8_t highSpeed;
1111 /**
1112 * @brief [rw] Quad lane enable
1113 *
1114 * Field size: 1 bits
1115 *
1116 * Setting this bit allows four lane capability. Clearing this bit
1117 * forces one lane operation.
1118 *
1119 * (Automatic shifting between 0, 1 and 4 lane mode happens based on
1120 * the configuration of @ref H2L and @ref L2H)
1121 */
1122 uint8_t quadLane;
1123 /**
1124 * @brief [rw] Single lane enable
1125 *
1126 * Field size: 1 bits
1127 *
1128 * Setting this bit allows one lane operation. Clearing this bit
1129 * forces four lane operation.
1130 *
1131 * (Automatic shifting between 0, 1 and 4 lane mode happens based on
1132 * the configuration of @ref H2L and @ref L2H)
1133 */
1134 uint8_t singleLane;
1135 /**
1136 * @brief [rw] Zero lane enable
1137 *
1138 * Field size: 1 bits
1139 *
1140 * Setting this bit allows zero lane operation. Zero lane operation
1141 * shuts down the SERDES.
1142 *
1143 * Clearing this bit prohibits zero lane operation.
1144 */
1145 uint8_t zeroLane;
1146 } hyplnkLanePwrMgmtReg_t;
1147 /* @} */
1149 /**
1150 * @ingroup hyplnklld_reg_structures
1151 * @brief Specification of the ECC Error Counters Register
1152 *
1153 * The ECC Error Counter register counts the number of correctable
1154 * single bit errors detected by the receive PLS as well as the number
1155 * of detectable double bit errors. This value can be used to determine
1156 * the integrity of the SerDes Rx signal. Writing to this register clears
1157 * the current counts to zero.
1158 *
1159 * @{
1160 */
1161 typedef struct hyplnkECCErrorsReg_s {
1162 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1163 /**
1164 * @brief [rw] Corrected Single Error Counter
1165 *
1166 * Field size: 16 bits
1167 *
1168 * Counter is incremented when a correctable error is detected by the
1169 * Rx PLS layer. Writing any value to this register will clear this counter.
1170 */
1171 uint16_t sglErrCor;
1172 /**
1173 * @brief [rw] Detected Double Error Counter
1174 *
1175 * Field size: 8 bits
1176 *
1177 * Counter is incremented when a detectable two bit error is detected
1178 * by the Rx PLS layer. This indicates that the receive channel signal is
1179 * marginal. Writing any value to this register will clear this counter.
1180 */
1181 uint8_t dblErrDet;
1182 } hyplnkECCErrorsReg_t;
1183 /* @} */
1185 /**
1186 * @ingroup hyplnklld_reg_structures
1187 * @brief Specification of the Link Status Register
1188 *
1189 * The Link status register is used to debug failed link conditions.
1190 * It contains valuable information aoout the start of the link-state machines.
1191 * It is used only to determine what might be causing the link failure. Because
1192 * the source of this register can change quickly, this register updates only
1193 * when a change has been detected and it is capable of transferring it to
1194 * the bus clock domain.
1195 *
1196 * @{
1197 */
1198 typedef struct hyplnkLinkStatusReg_s {
1199 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1200 /**
1201 * @brief [ro] Number of lanes requested by PLS layer
1202 *
1203 * Field size: 2 bits
1204 *
1205 * <TABLE>
1206 * <TR><TH>@ref txPlsReq</TH><TH># of lanes</TH></TR>
1207 * <TR><TD>00b</TD> <TD>0</TD></TR>
1208 * <TR><TD>01b</TD> <TD>1</TD></TR>
1209 * <TR><TD>10b</TD> <TD>4</TD></TR>
1210 * <TR><TD>11b</TD> <TD>4</TD></TR>
1211 * </TABLE>
1212 */
1213 uint8_t txPlsReq;
1214 /**
1215 * @brief [ro] Number of lanes active by PLS layer
1216 *
1217 * Field size: 2 bits
1218 *
1219 * <TABLE>
1220 * <TR><TH>@ref txPlsAck</TH><TH># of lanes</TH></TR>
1221 * <TR><TD>00b</TD> <TD>0</TD></TR>
1222 * <TR><TD>01b</TD> <TD>1</TD></TR>
1223 * <TR><TD>10b</TD> <TD>4</TD></TR>
1224 * <TR><TD>11b</TD> <TD>4</TD></TR>
1225 * </TABLE>
1226 */
1227 uint8_t txPlsAck;
1228 /**
1229 * @brief [ro] TX Power Management Sideband Control State
1230 *
1231 * Field size: 2 bits
1232 *
1233 * <TABLE>
1234 * <TR><TH>@ref txPmReq</TH><TH># of lanes</TH></TR>
1235 * <TR><TD>00b</TD> <TD>0</TD></TR>
1236 * <TR><TD>01b</TD> <TD>1</TD></TR>
1237 * <TR><TD>10b</TD> <TD>4, transitioning to/from 0 lanes</TD></TR>
1238 * <TR><TD>11b</TD> <TD>4</TD></TR>
1239 * </TABLE>
1240 */
1241 uint8_t txPmReq;
1242 /**
1243 * @brief [ro] Remote device has synced to the transmit traning sequence
1244 *
1245 * Field size: 1 bits
1246 *
1247 * This is a latched version of the station management sync bit.
1248 */
1249 uint8_t txRSync;
1250 /**
1251 * @brief [ro] TX PLS layer is linked to the remote device
1252 *
1253 * Field size: 1 bits
1254 */
1255 uint8_t txPlsOK;
1256 /**
1257 * @brief [ro] Indicates which SERDES lanes are enabled
1258 *
1259 * Field size: 4 bits
1260 */
1261 uint8_t txPhyEn;
1262 /**
1263 * @brief [ro] Indicates which flow bit are set from the remote receiver.
1264 *
1265 * Only bits 0 and 1 are used.
1266 *
1267 * Field size: 4 bits
1268 */
1269 uint8_t txFlowSts;
1270 /**
1271 * @brief [ro] Number of lanes requested by PLS for RX
1272 *
1273 * Field size: 2 bits
1274 *
1275 * <TABLE>
1276 * <TR><TH>@ref rxPlsReq</TH><TH># of lanes</TH></TR>
1277 * <TR><TD>00b</TD> <TD>0</TD></TR>
1278 * <TR><TD>01b</TD> <TD>1</TD></TR>
1279 * <TR><TD>10b</TD> <TD>4</TD></TR>
1280 * <TR><TD>11b</TD> <TD>NS</TD></TR>
1281 * </TABLE>
1282 */
1283 uint8_t rxPlsReq;
1284 /**
1285 * @brief [ro] Number of lanes active by PLS for RX
1286 *
1287 * Field size: 2 bits
1288 *
1289 * <TABLE>
1290 * <TR><TH>@ref rxPlsAck</TH><TH># of lanes</TH></TR>
1291 * <TR><TD>00b</TD> <TD>0</TD></TR>
1292 * <TR><TD>01b</TD> <TD>1</TD></TR>
1293 * <TR><TD>10b</TD> <TD>4</TD></TR>
1294 * <TR><TD>11b</TD> <TD>4</TD></TR>
1295 * </TABLE>
1296 */
1297 uint8_t rxPlsAck;
1298 /**
1299 * @brief [ro] RX Power Management Sideband Control State
1300 *
1301 * Field size: 2 bits
1302 *
1303 * <TABLE>
1304 * <TR><TH>@ref rxPmReq</TH><TH># of lanes</TH></TR>
1305 * <TR><TD>00b</TD> <TD>0</TD></TR>
1306 * <TR><TD>01b</TD> <TD>1</TD></TR>
1307 * <TR><TD>10b</TD> <TD>4, transitioning to/from 0 lanes</TD></TR>
1308 * <TR><TD>11b</TD> <TD>4</TD></TR>
1309 * </TABLE>
1310 */
1311 uint8_t rxPmReq;
1312 /**
1313 * @brief [ro] Receive has synced to training sequence
1314 *
1315 * Field size: 1 bits
1316 *
1317 * This is the source of the station management sync bit.
1318 */
1319 uint8_t rxLSync;
1320 /**
1321 * @brief [ro] Lane zero has been identified during training
1322 *
1323 * Field size: 1 bits
1324 */
1325 uint8_t rxOneID;
1326 /**
1327 * @brief [ro] Indicates which SERDES lanes are enabled
1328 *
1329 * Field size: 4 bits
1330 */
1331 uint8_t rxPhyEn;
1332 /*
1333 * @brief [ro] Indicates which SERDES lanes are reversed polarity
1334 *
1335 * Field size: 4 bits
1336 */
1337 uint8_t rxPhyPol;
1338 } hyplnkLinkStatusReg_t;
1339 /* @} */
1341 /**
1342 * @ingroup hyplnklld_reg_structures
1343 * @brief Specification of the Interupt Control Index Register
1344 *
1345 * The Interrupt Control Index Register is used to control which
1346 * hardware or software internal control register is read or written
1347 * via hyplnkIntCtrlValReg_s.
1348 *
1349 * @{
1350 */
1351 typedef struct hyplnkIntCtrlIdxReg_s {
1352 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1353 /**
1354 * @brief [rw] Selects interrupt control value register
1355 *
1356 * Field size: 8 bits
1357 *
1358 * The specified array element can be read or written via
1359 * @ref hyplnkIntCtrlValReg_s after the index is written.
1360 */
1361 uint8_t intCtrlIdx;
1362 } hyplnkIntCtrlIdxReg_t;
1363 /* @} */
1366 /**
1367 * @ingroup hyplnklld_reg_structures
1368 * @brief Specification of the Interrupt Control Value Register
1369 *
1370 * The Interrupt Control Register reads or writes the associated fields to the
1371 * @ref hyplnkIntCtrlIdxReg_s::intCtrlIdx "intCtrlIdx" interrupt channel. All channels not
1372 * supported will return zero and be unsettable.
1373 *
1374 * @{
1375 */
1376 typedef struct hyplnkIntCtrlValReg_s {
1377 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1378 /**
1379 * @brief [rw] Interrupt Enable
1380 *
1381 * Field size: 1 bit
1382 *
1383 * When set, this bit indicates that interrupts detected on the
1384 * Hyperlink_int_i[@ref hyplnkIntCtrlIdxReg_s::intCtrlIdx "intCtrlIdx"] pin
1385 * (not a physical device pin) should be should be forwarded to the
1386 * (@ref DNID, @ref mps, @ref vector) interrupt vector.
1387 */
1388 uint8_t intEn;
1389 /**
1390 * @brief [rw] Interrupt Type (level or pulse)
1391 *
1392 * Field size: 1 bit
1393 *
1394 * When set, this bit indicates that the
1395 * Hyperlink_int_i[@ref hyplnkIntCtrlIdxReg_s::intCtrlIdx "intCtrlIdx"]
1396 * interrupt is pulsed. When clear, this bit indicates that
1397 * Hyperlink_int_i[@ref hyplnkIntCtrlIdxReg_s::intCtrlIdx "intCtrlIdx"]
1398 * is level sensitive.
1399 */
1400 uint8_t intType;
1401 /**
1402 * @brief [rw] Interrupt Polarity (active high or active low)
1403 *
1404 * Field size: 1 bit
1405 *
1406 * Interrupt Polarity When set, this bit indicates that this
1407 * is active low. When clear, it is active high
1408 */
1409 uint8_t intPol;
1410 /**
1411 * @brief [rw] Interrupt security
1412 *
1413 * Field size: 1 bit
1414 *
1415 * Indicates the security level that the master must have to set a
1416 * software interrupt for this interrupt.
1417 */
1418 uint8_t iSec;
1419 /** @brief [rw] Software interrupt enable
1420 *
1421 * Field size: 1 bit
1422 *
1423 * Software Interrupt Enable indicate if this interrupt can be issued
1424 * via software writing to @ref hyplnkGenSoftIntReg_s.
1425 */
1426 uint8_t SIEN;
1427 /** @brief [rw] Destination Network Identifier
1428 *
1429 * Field size: 2 bits
1430 */
1431 uint8_t DNID;
1432 /** @brief [rw] Microprocessor Select
1433 *
1434 * Field size: 4 bits
1435 */
1436 uint8_t mps;
1437 /** @brief [rw] Selects which interrupt pending to set on interrupt assertion
1438 *
1439 * Field size: 5 bits
1440 *
1441 * When the local device has @ref hyplnkControlReg_s::intLocal set, this field indicates
1442 * which bit of interrupt pending register (@ref hyplnkIntPendSetReg_s) to
1443 * set. When the local device has (@ref hyplnkControlReg_s::intLocal "intLocal")
1444 * clear, this field is transferred to the remote device, which is used to
1445 * indicate which bit of the interrupt pending register to set in the
1446 * remote device.
1447 */
1448 uint8_t vector;
1449 } hyplnkIntCtrlValReg_t;
1450 /* @} */
1452 /**
1453 * @ingroup hyplnklld_reg_structures
1454 * @brief Specification of the Interupt Control Index Register
1455 *
1456 * The Interrupt Pointer Index Register is used to control which
1457 * Interrupt Pointer Register is read or written via @ref hyplnkIntPtrIdxReg_s.
1458 * The Interrupt Pointer Registers typically map to microprocessor interrupt
1459 * controller set registers which get set to a one to interrupt that processor.
1460 *
1461 * @{
1462 */
1463 typedef struct hyplnkIntPtrIdxReg_s {
1464 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1465 /**
1466 * @brief [rw] Selects which Interrupt Pointer is used
1467 *
1468 * Field size: 4 bits
1469 *
1470 * The interrupt pointer specified by @ref intPtrIdx can be read or written via
1471 * @ref hyplnkIntPtrValReg_s;
1472 */
1473 uint8_t intPtrIdx;
1474 } hyplnkIntPtrIdxReg_t;
1475 /* @} */
1477 /**
1478 * @ingroup hyplnklld_reg_structures
1479 * @brief Specification of the Interrupt Control Value Register
1480 *
1481 * The Interrupt Pointer Value is used to write or read to the interrupt
1482 * pointer number (@ref hyplnkIntPtrIdxReg_s::intPtrIdx "intPtrIdx")
1483 * This allows the remote interrupts to interrupt any
1484 * MicroProcessor. Values written are stored in the Interrupt Pointer for
1485 * that MicroProcessor.
1486 *
1487 * @{
1488 */
1489 typedef struct hyplnkIntPtrValReg_s {
1490 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1491 /**
1492 * @brief [rw] Specifies an interrupt pointer
1493 *
1494 * Field size: 30 bits
1495 *
1496 * This allows the remote interrupts to interrupt any MicroProcessor. Values written
1497 * are stored in the Interrupt Pointer for that MicroProcessor.
1498 */
1499 uint32_t intPtr;
1500 } hyplnkIntPtrValReg_t;
1501 /* @} */
1503 /**
1504 * @ingroup hyplnklld_reg_structures
1505 * @brief Specification of the SerDes Control And Status 1 Register
1506 *
1507 * The SerDes Control and Status 1 Register is used to define the mask time
1508 * that the receive lane data is ignored after enabling the lane(s) from either
1509 * a sleep or disabled state. The default numbers of these counters are not
1510 * yet determined. When these counters are zero, there are no delays in link
1511 * establishment. This register delays the start of link establishment or step
1512 * up link by a number of symbol times sixteen.
1513 *
1514 * @{
1515 */
1516 typedef struct hyplnkSERDESControl1Reg_s {
1517 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1518 /**
1519 * @brief [rw] Sleep mask count
1520 *
1521 * Field size: 8 bits
1522 *
1523 * This count times 16 SerDes symbol times are masked for SerDes
1524 * lanes that enter a sleep/enable state. This allows the internal
1525 * SerDes power supplies to stabilize before the link is established.
1526 *
1527 */
1528 uint8_t sleepCnt;
1529 /**
1530 * @brief [rw] Disable mask count
1531 *
1532 * Field size: 8 bits
1533 *
1534 * This count times 16 SerDes symbol times are masked for SerDes
1535 * lanes that enter a disabled state. This allows the SerDes CDR and
1536 * equalizer to stabilize before the link is established
1537 */
1538 uint8_t disableCnt;
1539 } hyplnkSERDESControl1Reg_t;
1540 /* @} */
1542 /**
1543 * @ingroup hyplnklld_reg_structures
1544 * @brief Specification of the SerDes Control And Status 2 Register
1545 *
1546 * This register is Reserved for SerDes control and status operations.
1547 * There is no defined functionality for this register.
1548 *
1549 * @{
1550 */
1551 typedef struct hyplnkSERDESControl2Reg_s {
1552 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1553 /**
1554 * @brief [rw] Unused
1555 *
1556 * Field size: 16 bits
1557 */
1558 uint16_t s2Ctl;
1559 } hyplnkSERDESControl2Reg_t;
1560 /* @} */
1562 /**
1563 * @ingroup hyplnklld_reg_structures
1564 * @brief Specification of the SerDes Control And Status 3 Register
1565 *
1566 * This register is Reserved for SerDes control and status operations.
1567 * There is no defined functionality for this register.
1568 *
1569 * @{
1570 */
1571 typedef struct hyplnkSERDESControl3Reg_s {
1572 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1573 /**
1574 * @brief [rw] Unused
1575 *
1576 * Field size: 16 bits
1577 */
1578 uint16_t s3Ctl;
1579 } hyplnkSERDESControl3Reg_t;
1580 /* @} */
1582 /**
1583 * @ingroup hyplnklld_reg_structures
1584 * @brief Specification of the SerDes Control And Status 4 Register
1585 *
1586 * The SerDes Control and Status Register is used to quicken DV
1587 * so that the periodic wake-up timer can be tested more easily and to
1588 * allow change to the SerDes non-runtime power levels. The power-level
1589 * controls were added to reduce SerDes sleep mode functionality risk.
1590 * It provides the ability to enable or disable sleep functionality
1591 * for both the transmit and receive SerDes lanes.
1592 *
1593 * @{
1594 */
1595 typedef struct hyplnkSERDESControl4Reg_s {
1596 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */
1597 /**
1598 * @brief [rw] Unused
1599 *
1600 * Field size: 11 bits
1601 */
1602 uint16_t s4Ctl;
1603 /**
1604 * @brief [rw] For testing purposes
1605 *
1606 * DVQUICK reduces the periodic wake up event prescaler to 256 clocks
1607 * instead of 65,536 clocks. It allow for more exhaustive testing of the PWC.
1608 */
1609 uint8_t dvQuick;
1610 /*
1611 * @brief Transmit SERDES power control
1612 *
1613 * The transmit SerDes power control is used to modify the SLEEP and enable
1614 * characteristics of the SerDes. 01=Full Sleep configuration,
1615 * 00=fast sleep configuration, 1X=No sleep configuration
1616 */
1617 uint8_t txSpc;
1618 /*
1619 * @brief Receive SERDES power control
1620 *
1621 * The receive SerDes power control is used to modify the SLEEP and enable
1622 * characteristics of the SerDes. 01=Full Sleep configuration,
1623 * 00=fast sleep configuration, 1X=No sleep configuration
1624 */
1625 uint8_t rxSpc;
1626 } hyplnkSERDESControl4Reg_t;
1627 /* @} */
1629 /* By repeating the define here, we don't require cslr_vusr.h */
1630 /* There is a compile time check in hyplnk.c to make sure it matches */
1631 #define hyplnk_RX_PRIVID_TBL_ENTS 16 /**< Number of RX PrivID table entries */
1632 /**
1633 * @ingroup hyplnklld_reg_structures
1634 * @brief Access to the entire RX PrivID table
1635 *
1636 * @{
1637 */
1638 typedef hyplnkRXPrivIDValReg_t hyplnkRXPrivIDTbl_t[hyplnk_RX_PRIVID_TBL_ENTS];
1639 /* @} */
1641 /* By repeating the define here, we don't require cslr_vusr.h */
1642 /* There is a compile time check in hyplnk.c to make sure it matches */
1643 #define hyplnk_RX_SEG_TBL_ENTS 64 /**< Number of RX segment table entries */
1644 /**
1645 * @ingroup hyplnklld_reg_structures
1646 * @brief Access to the entire RX segment table
1647 *
1648 * @{
1649 */
1650 typedef hyplnkRXSegValReg_t hyplnkRXSegTbl_t[hyplnk_RX_SEG_TBL_ENTS];
1651 /* @} */
1653 /* By repeating the define here, we don't require cslr_vusr.h */
1654 /* There is a compile time check in hyplnk.c to make sure it matches */
1655 #define hyplnk_INT_CTRL_TBL_ENTS 256 /**< size of the interupt control table */
1656 /**
1657 * @ingroup hyplnklld_reg_structures
1658 * @brief Access to the entire interrupt control table
1659 *
1660 * @{
1661 */
1662 typedef hyplnkIntCtrlValReg_t hyplnkIntCtrlTbl_t[hyplnk_INT_CTRL_TBL_ENTS];
1663 /* @} */
1665 /* By repeating the define here, we don't require cslr_vusr.h */
1666 /* There is a compile time check in hyplnk.c to make sure it matches */
1667 #define hyplnk_INT_PTR_TBL_ENTS 16 /**< Size of the interrupt pointer table */
1668 /**
1669 * @ingroup hyplnklld_reg_structures
1670 * @brief Access to the entire interrupt pointer table
1671 *
1672 * @{
1673 */
1674 typedef hyplnkIntPtrValReg_t hyplnkIntPtrTbl_t[hyplnk_INT_PTR_TBL_ENTS];
1675 /* @} */
1677 /**
1678 * @ingroup hyplnklld_api_structures
1679 * @brief Specification all registers
1680 *
1681 * This structure allows one or more registers to be read or written
1682 * through a single call. Also, all of the registers that operate on
1683 * tables can be programmed in one shot as well.
1684 *
1685 * The user populates one or more pointers to structures. All structures
1686 * that are non-NULL are read or written.
1687 *
1688 * Once the pointers are populated, use @ref Hyplnk_readRegs and/or
1689 * @ref Hyplnk_writeRegs to perform the actual register accesses
1690 *
1691 */
1692 typedef struct hyplnkRegisters_s {
1693 hyplnkRevReg_t *rev; /**< @brief Revision */
1694 hyplnkControlReg_t *control; /**< @brief Control */
1695 hyplnkStatusReg_t *status; /**< @brief Status */
1696 hyplnkIntPriVecReg_t *intPriVec; /**< @brief Interrupt Priority Vector Status/Clear */
1697 hyplnkIntStatusClrReg_t *intStatusClr; /**< @brief Interrupt Status/Clear */
1698 hyplnkIntPendSetReg_t *intPendSet; /**< @brief Interrupt Pending/Set */
1699 hyplnkGenSoftIntReg_t *genSoftInt; /**< @brief Generate Soft Interrupt Value */
1700 hyplnkTXAddrOvlyReg_t *TXAddrOvly; /**< @brief TX Address Overlay */
1701 hyplnkRXAddrSelReg_t *RXAddrSel; /**< @brief RX Address Selector */
1702 hyplnkRXPrivIDIdxReg_t *RXPrivIDIdx; /**< @brief RX Address PrivID Index. See also @ref RXPrivIDTbl */
1703 hyplnkRXPrivIDValReg_t *RXPrivIDVal; /**< @brief RX Address PrivID Value. See also @ref RXPrivIDTbl */
1704 hyplnkRXSegIdxReg_t *RXSegIdx; /**< @brief RX Address Segment Index. See also @ref RXSegTbl */
1705 hyplnkRXSegValReg_t *RXSegVal; /**< @brief RX Address Segment Value. See also @ref RXSegTbl */
1706 hyplnkChipVerReg_t *chipVer; /**< @brief Chip Version */
1707 hyplnkLanePwrMgmtReg_t *lanePwrMgmt; /**< @brief Lane Power Management Control Register */
1708 hyplnkECCErrorsReg_t *ECCErrors; /**< @brief ECC Error Counters Register */
1709 hyplnkLinkStatusReg_t *linkStatus; /**< @brief Link status */
1710 hyplnkIntCtrlIdxReg_t *intCtrlIdx; /**< @brief Interrupt Control Index. See also @ref intCtrlTbl */
1711 hyplnkIntCtrlValReg_t *intCtrlVal; /**< @brief Interrupt Control Value. See also @ref intCtrlTbl */
1712 hyplnkIntPtrIdxReg_t *intPtrIdx; /**< @brief Interrupt Pointer Index. See also @ref intPtrTbl */
1713 hyplnkIntPtrValReg_t *intPtrVal; /**< @brief Interrupt Pointer Value. See also @ref intPtrTbl */
1714 hyplnkSERDESControl1Reg_t *serdesControl1; /**< @brief SERDES Control and Status #1 */
1715 hyplnkSERDESControl2Reg_t *serdesControl2; /**< @brief SERDES Control and Status #2 */
1716 hyplnkSERDESControl3Reg_t *serdesControl3; /**< @brief SERDES Control and Status #3 */
1717 hyplnkSERDESControl4Reg_t *serdesControl4; /**< @brief SERDES Control and Status #4 */
1718 hyplnkRXPrivIDTbl_t *RXPrivIDTbl; /**< @brief Entire RX PrivID table in one shot */
1719 hyplnkRXSegTbl_t *RXSegTbl; /**< @brief Entire RX Segment table in one shot */
1720 hyplnkIntCtrlTbl_t *intCtrlTbl; /**< @brief Entire Interrupt Control table in one shot */
1721 hyplnkIntPtrTbl_t *intPtrTbl; /**< @brief Entire Interrupt Pointer table in one shot */
1722 } hyplnkRegisters_t;
1724 /**
1725 * @ingroup hyplnklld_api_structures
1726 * @brief Specification of Hyplnk_Handle
1727 *
1728 * The Hyplnk_Handle is used to identify a HYPLNK LLD instance
1729 */
1730 typedef void *Hyplnk_Handle;
1732 /**
1733 * @ingroup hyplnklld_api_structures
1734 * @brief Specification of Hyplnk_DeviceCfgBaseAddr
1735 *
1736 * The Hyplnk_DeviceCfg is used to specify device level configuration
1737 * to the LLD.
1738 */
1739 typedef struct
1740 {
1741 void *cfgBase;
1742 void *dataBase;
1743 } Hyplnk_DeviceCfgBaseAddr;
1745 /**
1746 * @ingroup hyplnklld_api_structures
1747 * @brief Specification of Hyplnk_DeviceCfg
1748 *
1749 * The Hyplnk_DeviceCfg is used to specify device level configuration
1750 * to the LLD.
1751 */
1752 #define hyplnk_MAX_PERIPHS 4 /**< Maximum peripherals (base addresses) supported by LLD */
1753 typedef struct
1754 {
1755 Hyplnk_DeviceCfgBaseAddr bases[hyplnk_MAX_PERIPHS]; /**< base addreses */
1756 } Hyplnk_DeviceCfg;
1758 /**
1759 * @ingroup hyplnklld_api_structures
1760 * @brief Specification of Hyplnk_InitCfg
1761 *
1762 * The Hyplnk_InitCfg is used to specify per-core
1763 * configuration to the LLD. It is used with @ref Hyplnk_init ()
1764 * once per core.
1765 */
1766 typedef struct
1767 {
1768 Hyplnk_DeviceCfg dev; /**< Device Configuration */
1769 } Hyplnk_InitCfg;
1771 /**
1772 * @ingroup hyplnklld_api_functions
1773 * @brief Hyplnk_init sets device configuration
1774 *
1775 * @details This function binds a device configuration to
1776 * the LLD. This must be done before calling
1777 * the other APIs.
1778 *
1779 * Calling init is nondestrictive, ie it can be
1780 * done more than once without side effects (assuming
1781 * same argument is passed each time).
1782 *
1783 * @pre No assumptions
1784 *
1785 * @retval hyplnkRet_e status
1786 *
1787 * @post hyplnkLObj.device gets set to argument
1788 */
1789 hyplnkRet_e Hyplnk_init
1790 (
1791 Hyplnk_InitCfg *cfg /**< [in] configuration */
1792 );
1794 /**
1795 * @ingroup hyplnklld_api_functions
1796 * @brief Hyplnk_open creates/opens a HyperLink instance
1797 *
1798 * @details This function creates a handle. The peripheral itself
1799 * is not modified. More than one handle to the same
1800 * hyperlink peripheral can exist at the same time.
1801 *
1802 * @pre pHandle != NULL
1803 * @pre *pHandle == NULL
1804 *
1805 * @retval hyplnkRet_e status
1806 *
1807 * @post *pHandle == valid handle
1808 */
1809 hyplnkRet_e Hyplnk_open
1810 (
1811 /** [in] HyperLink port number (0,1,...)
1812 *
1813 * Current KeyStone devices only have one HyperLink port (port 0).
1814 * The port number allows forwards compatibility if future devices
1815 * have multiple ports.
1816 */
1817 int portNum,
1818 Hyplnk_Handle *pHandle /**< [out] Resulting instance handle */
1819 );
1821 /**
1822 * @ingroup hyplnklld_api_functions
1823 * @brief Hyplnk_close Closes (frees) the driver handle.
1824 *
1825 * @details The handle is released. The peripheral itself is not
1826 * modified.
1827 *
1828 * @pre pHandle != NULL
1829 * @pre *pHandle == valid handle
1830 *
1831 * @retval hyplnkRet_e status
1832 *
1833 * @post *pHandle == NULL
1834 */
1835 hyplnkRet_e Hyplnk_close
1836 (
1837 Hyplnk_Handle *pHandle /**< [in] The HYPLNK LLD instance indentifier */
1838 );
1840 /**
1841 * @ingroup hyplnklld_api_functions
1842 * @brief Performs a configuration read
1843 *
1844 * @details Reads one or more of the device registers
1845 *
1846 * Each non-NULL register pointer in readRegs will be read and
1847 * broken into its fields.
1848 *
1849 * It is the users responsibility to ensure that no other tasks
1850 * or cores will modify the registers while they are read,
1851 * or betwen the time the registers are read and they are
1852 * later written back.
1853 *
1854 * When the table-at-once fields are used
1855 * (@ref hyplnkRegisters_s::RXPrivIDTbl
1856 * @ref hyplnkRegisters_s::RXSegTbl
1857 * @ref hyplnkRegisters_s::intCtrlTbl
1858 * @ref hyplnkRegisters_s::intPtrTbl), then this API will
1859 * generate <b>implicit register writes</b>, so it should not
1860 * be assumed that multiple simutaneous reads are safe.
1861 *
1862 * Since the peripheral is shared across the device, and even
1863 * between peripherals, it is not expected to be dynamically
1864 * reprogramed (such as between thread or task switches). It
1865 * should only be reprogrammed at startup or when changing
1866 * applications. Therefore, there is a single-entry API instead
1867 * of a set of inlines since it is not time-critical code.
1868 *
1869 * @retval hyplnkRet_e status
1870 */
1871 hyplnkRet_e Hyplnk_readRegs
1872 (
1873 Hyplnk_Handle handle, /**< [in] The HYPLNK LLD instance identifier */
1874 hyplnkLocation_e location, /**< [in] Local or remote peripheral */
1875 hyplnkRegisters_t *readRegs /**< [in/out] List of registers to read */
1876 );
1878 /**
1879 * @ingroup hyplnklld_api_functions
1880 * @brief Performs a configuration write
1881 *
1882 * @details Writes one or more of the device registers
1883 *
1884 * It is the users responsibility to ensure that no other tasks
1885 * or cores will modify the registers while they are read,
1886 * or betwen the time the registers are read and they are
1887 * later written back.
1888 *
1889 * The user will typically use @ref Hyplnk_readRegs to read the current
1890 * values in the registers, modify them in the local copies, then
1891 * write back using @ref Hyplnk_writeRegs.
1892 *
1893 * It is guaranteed that all registers can be written together. The
1894 * actual ordering will, for example, write index registers before
1895 * the associated value registers
1896 *
1897 * On exit, the actual written values are returned in each register's
1898 * reg->raw.
1899 *
1900 * Since the peripheral is shared across the device, and even
1901 * between peripherals, it is not expected to be dynamically
1902 * reprogramed (such as between thread or task switches). It
1903 * should only be reprogrammed at startup or when changing
1904 * applications. Therefore, there is a single-entry API instead
1905 * of a set of inlines since it is not time-critical code.
1906 *
1907 * @retval hyplnkRet_e status
1908 */
1909 hyplnkRet_e Hyplnk_writeRegs
1910 (
1911 Hyplnk_Handle handle, /**< [in] The HYPLNK LLD instance identifier */
1912 hyplnkLocation_e location, /**< [in] Local or remote peripheral */
1913 hyplnkRegisters_t *writeRegs /**< [in] List of registers to write */
1914 );
1916 /**
1917 * @ingroup hyplnklld_api_functions
1918 * @brief Hyplnk_getWindow returns the address and size of the local memory window
1919 *
1920 * @retval hyplnkRet_e status
1921 */
1922 hyplnkRet_e Hyplnk_getWindow
1923 (
1924 Hyplnk_Handle handle, /**< [in] The HYPLNK LLD instance identifier */
1925 void **base, /**< [out] The data base address */
1926 uint32_t *size /**< [out] Data window size [bytes] */
1927 );
1929 /**
1930 * @ingroup hyplnklld_api_functions
1931 * @brief Hyplnk_getVersion returns the HYPLNK LLD version information
1932 *
1933 * @details This function is used to get the version information of the HYPLNK LLD in 0xAABBCCDD format.
1934 * where Arch (AA); API Changes (BB); Major (CC); Minor (DD)
1935 *
1936 * @retval 32-bit version information
1937 */
1938 uint32_t Hyplnk_getVersion (void);
1941 /**
1942 * @ingroup hyplnklld_api_functions
1943 * @brief Hyplnk_getVersionStr returns the HYPLNK LLD version string
1944 *
1945 * @details This function is used to get the version string of the HYPLNK LLD.
1946 *
1947 * @retval Version string
1948 */
1949 const char* Hyplnk_getVersionStr (void);
1951 #ifdef __cplusplus
1952 }
1953 #endif
1955 #endif /* _HYPLNK_H */
1957 /* Nothing past this point */