1 /**
2 * \file k2k/I2C_soc.c
3 *
4 * \brief K2K SoC specific I2C hardware attributes.
5 *
6 * This file contains the hardware attributes of I2C peripheral like
7 * base address, interrupt number etc.
8 */
10 /*
11 * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the
23 * distribution.
24 *
25 * Neither the name of Texas Instruments Incorporated nor the names of
26 * its contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 */
43 #include <stdint.h>
44 #include <ti/csl/soc.h>
45 #include <ti/csl/csl_device_interrupt.h>
46 #include <ti/drv/i2c/I2C.h>
47 #include <ti/drv/i2c/soc/I2C_soc.h>
48 #include <ti/csl/src/ip/i2c/V0/i2c.h>
50 /* I2C configuration structure */
51 I2C_HwAttrs i2cInitCfg[CSL_I2C_PER_CNT] =
52 {
53 {
54 CSL_I2C_0_DATA_CFG_REGS,
55 #ifdef _TMS320C6X
56 OSAL_REGINT_INTVEC_EVENT_COMBINER, /* default DSP Interrupt vector number, can be set in I2C_socSetInitCfg() API */
57 30, /* default DSP INTC I2C Event ID, can be set in I2C_socSetInitCfg() API */
58 0, /* CIC number 0 */
59 CSL_CIC0_I2C_0_INT, /* CIC UART Event ID */
60 72, /* default CIC Host Interrupt, map to CIC_OUT72_PLUS_10_MUL_N event */
61 #else
62 CSL_ARM_GIC_I2C_0_INT + 32, /* I2C int0 number for ARM GIC INTC */
63 0, /* Event ID not used for ARM INTC */
64 INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
65 0, /* cicEventId not used for ARM */
66 0, /* HostIntNum not used for ARM */
67 #endif
68 (983000000U/6U), /* default I2C frequency, system clock/6 */
69 true, /* interrupt mode enabled */
70 I2C_OWN_ADDR, /* default I2C own slave addresse */
71 },
72 {
73 CSL_I2C_1_DATA_CFG_REGS,
74 #ifdef _TMS320C6X
75 OSAL_REGINT_INTVEC_EVENT_COMBINER,
76 31,
77 0,
78 CSL_CIC0_I2C_1_INT,
79 73,
80 #else
81 CSL_ARM_GIC_I2C_1_INT + 32,
82 0,
83 INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
84 0,
85 0,
86 #endif
87 (983000000U/6U), /* default I2C frequency, system clock/6 */
88 true,
89 I2C_OWN_ADDR,
90 },
91 {
92 CSL_I2C_2_DATA_CFG_REGS,
93 #ifdef _TMS320C6X
94 OSAL_REGINT_INTVEC_EVENT_COMBINER,
95 32,
96 0,
97 CSL_CIC0_I2C_2_INT,
98 74,
99 #else
100 CSL_ARM_GIC_I2C_2_INT + 32,
101 0,
102 INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
103 0,
104 0,
105 #endif
106 (983000000U/6U), /* default I2C frequency, system clock/6 */
107 true,
108 I2C_OWN_ADDR,
109 }
110 };
112 /* I2C objects */
113 I2C_v0_Object I2cObjects[CSL_I2C_PER_CNT];
116 /* I2C configuration structure */
117 CSL_PUBLIC_CONST I2C_config_list I2C_config = {
118 {
119 &I2C_v0_FxnTable,
120 &I2cObjects[0],
121 &i2cInitCfg[0]
122 },
124 {
125 &I2C_v0_FxnTable,
126 &I2cObjects[1],
127 &i2cInitCfg[1]
128 },
130 {
131 &I2C_v0_FxnTable,
132 &I2cObjects[2],
133 &i2cInitCfg[2]
134 },
136 /*"pad to full predefined length of array"*/
137 {NULL, NULL, NULL},
138 {NULL, NULL, NULL},
139 {NULL, NULL, NULL},
140 {NULL, NULL, NULL},
141 {NULL, NULL, NULL},
142 {NULL, NULL, NULL},
143 {NULL, NULL, NULL},
144 {NULL, NULL, NULL},
145 {NULL, NULL, NULL},
146 {NULL, NULL, NULL},
147 {NULL, NULL, NULL}
148 };
150 /**
151 * \brief This API gets the SoC level of I2C intial configuration
152 *
153 * \param index I2C instance index.
154 * \param cfg Pointer to I2C SOC initial config.
155 *
156 * \return 0 success: -1: error
157 *
158 */
159 int32_t I2C_socGetInitCfg(uint32_t index, I2C_HwAttrs *cfg)
160 {
161 int32_t ret = 0;
163 if (index < CSL_I2C_PER_CNT)
164 {
165 *cfg = i2cInitCfg[index];
166 }
167 else
168 {
169 ret = -1;
170 }
172 return ret;
173 }
175 /**
176 * \brief This API sets the SoC level of I2C intial configuration
177 *
178 * \param index I2C instance index.
179 * \param cfg Pointer to I2C SOC initial config.
180 *
181 * \return 0 success: -1: error
182 *
183 */
184 int32_t I2C_socSetInitCfg(uint32_t index, const I2C_HwAttrs *cfg)
185 {
186 int32_t ret = 0;
188 if (index < CSL_I2C_PER_CNT)
189 {
190 i2cInitCfg[index] = *cfg;
191 }
192 else
193 {
194 ret = -1;
195 }
197 return ret;
198 }