[processor-sdk/pdk.git] / packages / ti / drv / icss_emac / firmware / icss_switch / src / icss_switch.h
1 ;
2 ; TEXAS INSTRUMENTS TEXT FILE LICENSE
3 ;
4 ; Copyright (c) 2017-2019 Texas Instruments Incorporated
5 ;
6 ; All rights reserved not granted herein.
7 ;
8 ; Limited License.
9 ;
10 ; Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
11 ; license under copyrights and patents it now or hereafter owns or controls to
12 ; make, have made, use, import, offer to sell and sell ("Utilize") this software
13 ; subject to the terms herein. With respect to the foregoing patent license,
14 ; such license is granted solely to the extent that any such patent is necessary
15 ; to Utilize the software alone. The patent license shall not apply to any
16 ; combinations which include this software, other than combinations with devices
17 ; manufactured by or for TI (�TI Devices�). No hardware patent is licensed hereunder.
18 ;
19 ; Redistributions must preserve existing copyright notices and reproduce this license
20 ; (including the above copyright notice and the disclaimer and (if applicable) source
21 ; code license limitations below) in the documentation and/or other materials provided
22 ; with the distribution.
23 ;
24 ; Redistribution and use in binary form, without modification, are permitted provided
25 ; that the following conditions are met:
26 ; No reverse engineering, decompilation, or disassembly of this software is
27 ; permitted with respect to any software provided in binary form.
28 ; Any redistribution and use are licensed by TI for use only with TI Devices.
29 ; Nothing shall obligate TI to provide you with source code for the software
30 ; licensed and provided to you in object code.
31 ;
32 ; If software source code is provided to you, modification and redistribution of the
33 ; source code are permitted provided that the following conditions are met:
34 ; Any redistribution and use of the source code, including any resulting derivative
35 ; works, are licensed by TI for use only with TI Devices.
36 ; Any redistribution and use of any object code compiled from the source code
37 ; and any resulting derivative works, are licensed by TI for use only with TI Devices.
38 ;
39 ; Neither the name of Texas Instruments Incorporated nor the names of its suppliers
40 ; may be used to endorse or promote products derived from this software without
41 ; specific prior written permission.
42 ;
43 ; DISCLAIMER.
44 ;
45 ; THIS SOFTWARE IS PROVIDED BY TI AND TI�S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED
46 ; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
47 ; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TI�S
48 ; LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
50 ; GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51 ; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
53 ; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 ;
55 ; file: icss_switch.h
56 ;
57 ; brief: Definitions and mapping of Ethernet switch over PRU
58 ; Includes:
59 ; 1. Buffer pools, queus, descriptors
60 ; 2. Switch configutation parameter
61 ; 3. Statistics
62 ; 4. Events for switch interaction
63 ; 5. Memory Map and Control Register definition
64 ;
65 ;
67 .if !$defined("ICSS_SWITCH__H")
68 ICSS_SWITCH__H .set 1
70 ;****************************************************************************
71 ;* Basic Switch Parameters *
72 ;* Used to auto compute offset addresses on L3 OCMC RAM. Do not modify these*
73 ;* without changing firmware accordingly *
74 ;****************************************************************************
76 SWITCH_BUFFER_SIZE .set 64*1024 ; L3 buffer
77 BLOCK_SIZE .set 32 ; bytes derived from ICSS architecture
78 BD_SIZE .set 4 ; one buffer descriptor is 4 bytes
79 MAX_NUMBER_OF_QUEUES .set 4 ; up to 4 queues supported
80 MIN_NUMBER_OF_QUEUES .set 1 ;
81 NUMBER_OF_PORTS .set 3 ; two phy ports and one host port
82 ;****************************************************************************
83 ;* End of Section *
84 ;****************************************************************************
89 ;****************************************************************************
90 ;* LINK/DUPLEX MACROS & MASKS *
91 ;* Bits for Port Status and Duplexity. This is set by ARM and read by FW *
92 ;* Possible to add more info as bits 2-7 are free *
93 ;****************************************************************************
94 .asg t0, PORT_LINK_UP
95 .asg t1, PORT_IS_HD
97 PORT_LINK_MASK .set 0x1
98 PORT_IS_HD_MASK .set 0x2
100 NUM_EXCESS_COLLISIONS .set 15
102 ;****************************************************************************
103 ;* End of Section *
104 ;****************************************************************************
106 ;****************************************************************************
107 ; *
108 ; *
109 ; *
110 ; *
111 ; Shared RAM Offsets for Switch *
112 ; *
113 ; *
114 ; *
115 ; *
116 ; *
117 ;****************************************************************************
118 ; ICSS Shared RAM 12kB.
120 ; Queues on PHY PORT 1/2
121 NUMBER_OF_QUEUES .set 4 ; different number of queues will have significant impact to memory map
122 ; 48 blocks per max packet
123 ; 2 full sized ETH packets: 96 blocks, 3 packets = 144, 4 packets = 192
125 ; Physical Port queue size. Same for both ports
126 QUEUE_1_SIZE .set 97 ; Network Management high
127 QUEUE_2_SIZE .set 97 ; Network Management low
128 QUEUE_3_SIZE .set 97 ; Protocol specific
129 QUEUE_4_SIZE .set 97 ; NRT (IP,ARP, ICMP, �)
131 ; HOST PORT QUEUES can buffer up to 4 full sized frames per queue
132 HOST_QUEUE_1_SIZE .set 194 ; Protocol and/or VLAN priority 7 and 6
133 HOST_QUEUE_2_SIZE .set 194 ; Protocol mid
134 HOST_QUEUE_3_SIZE .set 194 ; Protocol low
135 HOST_QUEUE_4_SIZE .set 194 ; NRT (IP, ARP, ICMP �)
137 COLLISION_QUEUE_SIZE .set 48
138 P0_COL_TOP_MOST_BD_OFFSET .set (4*COLLISION_QUEUE_SIZE) + P0_COL_BD_OFFSET - 4
139 P1_COL_TOP_MOST_BD_OFFSET .set (4*COLLISION_QUEUE_SIZE) + P1_COL_BD_OFFSET - 4
140 P2_COL_TOP_MOST_BD_OFFSET .set (4*COLLISION_QUEUE_SIZE) + P2_COL_BD_OFFSET - 4
142 TOTAL_BUFFER_POOL .set 2*(QUEUE_1_SIZE + QUEUE_2_SIZE + QUEUE_3_SIZE + QUEUE_4_SIZE) + HOST_QUEUE_1_SIZE + HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + HOST_QUEUE_4_SIZE
144 ; NRT Buffer descriptor definition
145 ; Each buffer descriptor points to a max 32 byte block and has 32 bit in size to have atomic operation.
146 ; PRU can address bytewise into memory.
147 ; Definition of 32 bit desriptor is as follows
148 ;
149 ; Bits Name Meaning
150 ; ==================================================================================================
151 ; 0..7 Index points to index in buffer queue, max 256 x 32 byte blocks can be addressed
152 ; 8..12 Block_length number of valid bytes in this specific block. Will be <=32 bytes on last block of packet
153 ; 13 More "More" bit indicating that there are more blocks for the
154 ; 14 Shadow inidcates that "index" is pointing into shadow buffer
155 ; 15 TimeStamp indicates that this packet has time stamp in seperate buffer - only needed of PTCP runs on host
156 ; 16..17 Port different meaning for ingress and egress, ingress Port=0 inidcates phy port 1 and Port = 1
157 ; inidcates phy port 2. Egress: 0 sends on phy port 1 and 1 sends on phy port 2. Port = 2 goes
158 ; over MAC table look-up
159 ; 18..28 Length 11 bit of total packet length which is put into first BD only so that host access only one BD
160 ; 29 VlanTag indicates that packet has Length/Type field of 0x08100 with VLAN tag in following byte
161 ; 30 Broadcast inidcates that packet goes out on both physical ports, there will be two bd but only one buffer
162 ; 31 Error indicates there was an error in the packet
163 ;
164 .if $defined("PRU")
165 .asg b0, Index
166 .asg b1, Block_length
167 .asg t13, More
168 .asg t14, Shadow
169 .asg t16, TimeStamp
170 .asg b2, Port
171 .asg w2, Length
172 .asg t29, VlanTag
173 .asg t30, Broadcat
174 .asg t31, Error
175 .else
176 ; #defines for bd masks
177 .endif
179 ; NRT Queue Defintion
180 ; Each port has up to 4 queues with variable length. The queus is processed as ring buffer with read and write pointer.
181 ; Both pointer are address pointers and increment by 4 for each buffer descriptor/position.
182 ; Queue has a length defined in constants and a status. Status is defined as described below
183 ;
184 ; Bits Name Meaning
185 ; =====================================================================================================
186 ; 0 Busy_M This queue is busy by the master port which is the PRU receiving packets from the master
187 ; 1 Collision Slave is/has written into shadow queue, both descriptors and data.
188 ; 2 Overflow there was not enough space to write to queue and packet was discarded
189 ; 4..7 Reserved reserved
190 ;
191 ; There is busy slave flag in different byte address to grant access to queue to master in case
192 ; of simultaneous access. Host will alwasys be slave in this case. The PRU which is sending the
193 ; packet on phy port will be the master. When both PRUs wants to write to host queues PRU0
194 ; is master and PRU1 is slave.
195 ;
196 ; Bits Name Meaning
197 ; =====================================================================================================
198 ; 0 Busy_S This queue is busy by the master port which is the PRU receiving packets from the master
199 ; 1..7 Reserved
200 ;
201 ; Length is the number of 32 byte blocks per queue. max_fill_level tells the minimum distance between write and read pointer.
202 ; over_flow_cnt tells how many times the write pointer runs into the read_pointer.
204 .if $defined("PRU")
205 struct_queue .struct
206 rd_ptr .ushort
207 wr_ptr .ushort
208 busy_s .ubyte
209 status .ubyte
210 max_fill_level .ubyte
211 overflow_cnt .ubyte
212 ;struct_queue_len
213 .endstruct
215 .asg t0, busy_m
216 ; .else
217 ;typedef struct _Queue
218 ;{
219 ; uint16_t rd_ptr;
220 ; uint16_t wr_ptr;
221 ; uint8_t busy_s;
222 ; uint8_t status;
223 ; uint8_t max_fill_level;
224 ; uint8_t overflow_cnt;
225 ;} Queue;
226 ;
227 .endif
229 .if $defined("PRU")
230 QUEUE_DESCRIPTOR_SIZE .set $sizeof(struct_queue) ; typically 8 bytes per register
231 ; .else
232 ; #define QUEUE_DESCRIPTOR_SIZE sizeof(Queue) ; typically 8 bytes per register
233 ; .endif
234 TOTAL_QUEUE_DESCRIPTOR_SIZE .set NUMBER_OF_PORTS * NUMBER_OF_QUEUES
236 Q_MAX_FILL_LEVEL_OFFSET .set 6
237 Q_OVERFLOW_CNT_OFFSET .set 7
238 ; Memory Map for buffer pool, buffer descriptor and queue descriptor
239 .asg t7, TX0_UNDERFLOW
240 .asg t8, TX0_OVERFLOW
241 .asg t19, TX1_UNDERFLOW
242 .asg t20, TX1_OVERFLOW
244 ;//**************************************************************************
245 ; *
246 ; *
247 ; Diagrams below show the memory usage for PRU DRAM *
248 ; and shared RAM for switch and EMAC *
249 ; *
250 ; *
251 ;****************************************************************************
253 ;//**************************************************************************
254 ; *
255 ; *
256 ; Usage for switch. Numbers indicate bytes *
257 ; *
258 ; *
259 ;****************************************************************************
261 ; DRAM0 DRAM1 Shared RAM
262 ;***********0x2000************** ************0x2000*************** *************0x3000**************
263 ;** Reserved * ** Reserved * ** Available for Protocol *
264 ;***********0x1FAC************** ***********0x1FAC**************** ** Usage *
265 ;** Used for statistics * ** Used for statistics * * *
266 ;** and misc * ** and misc * ** ***********0x2290*************
267 ;***********0x1F00************** ************0x1F00*************** ** Multicast Filtering Table *
268 ;** * ** Reserved * ** (Only used by Profinet) *
269 ;** * *************0x1EDC************** * Free for other protocols *
270 ;** * ** Switch Context + Misc * *************0X1E80**************
271 ;** Available for Protocol * ** Stored here * ** *
272 ;** Usage * ************0X1D00*************** ** BD Offsets for *
273 ;** * ** * ** 3 queues *
274 ;** * ** Available for Protocol * ** and collision queue *
275 ;** * ** Usage * ** *
276 ;** * ** * **************0x400**************
277 ;************0x200************** **************0x200************** ** Available for Protocols *
278 ;*** Reserved * ** Reserved * ** *
279 ;***********0x0000************** *************0x0000************** *************0x0000**************
281 ;***********************************************************************************************************
282 ; *
283 ; *
284 ; End of Section *
285 ; *
286 ; *
287 ;***********************************************************************************************************
290 ;//**************************************************************************
291 ; *
292 ; *
293 ; Usage for EMAC. Numbers indicate bytes *
294 ; *
295 ; *
296 ;****************************************************************************
298 ; DRAM0 DRAM1 Shared RAM
299 ;***********0x2000************** ************0x2000*************** *************0x3000**************
300 ;** Reserved * ** Reserved * ** *
301 ;***********0x1FA8************** *************0x1FA8************** ** *
302 ;** Used for statistics * ** Used for statistics * ** Available for Protocol *
303 ;** and misc * ** and misc * ** Usage *
304 ;***********0x1F00************** ************0x1F00*************** ** *
305 ;** Queue Context Offsets * ** Queue Context Offsets * ** *
306 ;************0x1EC0************* *************0x1EC0************** * *
307 ;** * ** * *************0X1D00**************
308 ;** Available for Protocol * ** Available for Protocol * ** *
309 ;** Usage * ** Usage * ** BD Offsets for *
310 ;** * ** * ** 3 queues *
311 ;** * ** * ** and host queue BD *
312 ;** * ** * ** + reserved *
313 ;** * ** * **************0x400**************
314 ;************0x200************** **************0x200************** ** Available for Protocols *
315 ;** Reserved * ** Reserved * ** *
316 ;***********0x0000************** *************0x0000************** *************0x0000**************
318 ;***********************************************************************************************************
319 ; *
320 ; *
321 ; End of Section *
322 ; *
323 ; *
324 ;***********************************************************************************************************
326 ;*******************************************************************************
327 ; The following offsets indicate which sections of the memory
328 ; are reserved/provided for other protocol
329 ;*******************************************************************************
330 ;NOTE:Some memory is reserved for future use
331 ;See map above for usage
332 SWITCH_PROTOCOL_SPECIFIC_DRAM0_MEMORY_SIZE .set 0x1F00
333 SWITCH_PROTOCOL_SPECIFIC_DRAM0_MEMORY_OFFSET .set 0x400
335 SWITCH_PROTOCOL_SPECIFIC_DRAM1_USAGE_SIZE .set 0x1D00
336 SWITCH_PROTOCOL_SPECIFIC_DRAM1_MEMORY_OFFSET .set 0x400
338 EMAC_PROTOCOL_SPECIFIC_DRAM_USAGE_SIZE .set 0x1D00
339 EMAC_PROTOCOL_SPECIFIC_DRAM_MEMORY_OFFSET .set 0x400
341 SWITCH_PROTOCOL_SPECIFIC_SRAM_USAGE_SIZE .set 0x3000
342 SWITCH_PROTOCOL_SPECIFIC_SRAM_MEMORY_OFFSET .set 0x2400
344 EMAC_PROTOCOL_SPECIFIC_SRAM_USAGE_SIZE .set 0x300
345 EMAC_PROTOCOL_SPECIFIC_SRAM_MEMORY_OFFSET .set 0x1C00
347 ;The following offsets indicate which sections of the memory are used for switch and EMAC internal tasks
348 SWITCH_SPECIFIC_DRAM0_START_SIZE .set 0x100
349 SWITCH_SPECIFIC_DRAM0_START_OFFSET .set 0x1F00
351 SWITCH_SPECIFIC_DRAM1_START_SIZE .set 0x300
352 SWITCH_SPECIFIC_DRAM1_START_OFFSET .set 0x1D00
354 EMAC_SPECIFIC_DRAM_USAGE_SIZE .set 0x140
355 EMAC_SPECIFIC_DRAM_START_OFFSET .set 0x1EC0
357 SWITCH_SPECIFIC_SRAM_USAGE_SIZE .set 0x2010
358 SWITCH_SPECIFIC_SRAM_START_OFFSET .set 0x400 ;same as EMAC. The BD offsets are common between EMAC and Switch. See diagram
360 EMAC_SPECIFIC_SRAM_USAGE_SIZE .set 0x1900
361 EMAC_SPECIFIC_SRAM_START_OFFSET .set 0x0
365 ;***********************************************************************************************************
366 ; *
367 ; *
368 ; End of Section *
369 ; *
370 ; *
371 ;***********************************************************************************************************
374 ;****************************************************************************
375 ;* General Purpose Statistics *
376 ;* These are present on both PRU0 and PRU1 DRAM *
377 ;****************************************************************************
378 ; base statistics offset
379 STATISTICS_OFFSET .set 0x1F00
381 ; MII port TX statistics flags
382 TX_BC_FRAMES_OFFSET .set 0x0
383 TX_MC_FRAMES_OFFSET .set 0x4
384 TX_UC_FRAMES_OFFSET .set 0x8
386 TX_BYTE_CNT_OFFSET .set 0xc
388 ; MII port RX statistics flags
389 RX_BC_FRAMES_OFFSET .set 0x10
390 RX_MC_FRAMES_OFFSET .set 0x14
391 RX_UC_FRAMES_OFFSET .set 0x18
393 ;Binning counters : disabled by default
394 RX_BYTE_CNT_OFFSET .set 0x1c
396 ;Binning counters : disabled by default
397 TX_64_BYTE_FRAME_OFFSET .set 0x20
398 TX_65_127_BYTE_FRAME_OFFSET .set 0x24
399 TX_128_255_BYTE_FRAME_OFFSET .set 0x28
400 TX_256_511_BYTE_FRAME_OFFSET .set 0x2c
401 TX_512_1023_BYTE_FRAME_OFFSET .set 0x30
402 TX_1024_MAX_BYTE_FRAME_OFFSET .set 0x34
404 RX_64_BYTE_FRAME_OFFSET .set 0x38
405 RX_65_127_BYTE_FRAME_OFFSET .set 0x3c
406 RX_128_255_BYTE_FRAME_OFFSET .set 0x40
407 RX_256_511_BYTE_FRAME_OFFSET .set 0x44
408 RX_512_1023_BYTE_FRAME_OFFSET .set 0x48
409 RX_1024_MAX_BYTE_FRAME_OFFSET .set 0x4c
411 ;**********************************Collision Counters*******************************/
412 LATE_COLLISION_OFFSET .set STATISTICS_OFFSET + 0x50 ;set for a frame where collision took place after 512 bytes were sent on wire
413 SINGLE_COLLISION_OFFSET .set STATISTICS_OFFSET + 0x54 ;frame was sent after a single collision was reported
414 MULTIPLE_COLLISION_OFFSET .set STATISTICS_OFFSET + 0x58 ;frame was sent after more than one collision
415 EXCESS_COLLISION_OFFSET .set STATISTICS_OFFSET + 0x5c ;more than 16 collisions
416 ;***********************************************************************************/
418 ;********************Error packets****************
419 ;Packed dropped on account of storm prevention
420 RX_MISALIGNMENT_COUNT_OFFSET .set EXCESS_COLLISION_OFFSET + 0x4 ;frame size in bits is not a multiple of 8
421 STORM_PREVENTION_COUNTER_BC .set RX_MISALIGNMENT_COUNT_OFFSET + 0x4
422 STORM_PREVENTION_COUNTER_MC .set STORM_PREVENTION_COUNTER_BC + 0x4
423 STORM_PREVENTION_COUNTER_UC .set STORM_PREVENTION_COUNTER_MC + 0x4
424 RX_ERROR_OFFSET .set STORM_PREVENTION_COUNTER_UC + 0x4
425 SFD_ERROR_OFFSET .set RX_ERROR_OFFSET + 0x4
426 TX_DEFERRED_OFFSET .set SFD_ERROR_OFFSET + 0x4
427 TX_ERROR_OFFSET .set TX_DEFERRED_OFFSET + 0x4
428 RX_OVERSIZED_FRAME_OFFSET .set TX_ERROR_OFFSET + 0x4 ;count of frames with size greater than 1518 bytes
429 RX_UNDERSIZED_FRAME_OFFSET .set RX_OVERSIZED_FRAME_OFFSET + 0x4 ;count of frames shorter than 64 bytes (including CRC)
430 RX_CRC_COUNT_OFFSET .set RX_UNDERSIZED_FRAME_OFFSET + 0x4 ;number of frames with CRC error
431 RX_DROPPED_FRAMES_OFFSET .set RX_CRC_COUNT_OFFSET + 0x4
433 ;****************Debug Statistics***************************************************/
434 TX_OVERFLOW_COUNTER .set RX_DROPPED_FRAMES_OFFSET + 0x4
435 TX_UNDERFLOW_COUNTER .set TX_OVERFLOW_COUNTER + 0x4
437 ;**********************************************************************************/
440 STAT_SIZE .set 0x98 ;always keep it's value same as the last stat offset
442 ;****************************************************************************
443 ; End of Statistics *
444 ;****************************************************************************
447 ;****************************************************************************
448 ;* Offset for storing *
449 ; 1. Storm Prevention Params *
450 ; 2. PHY Speed Offset *
451 ; 3. Port Status Offset *
452 ;* These are present on both PRU0 and PRU1 *
453 ;****************************************************************************
454 STORM_PREVENTION_OFFSET_BC_DRIVER .set STATISTICS_OFFSET + STAT_SIZE ;4 bytes
455 PHY_SPEED_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 4 ;4 bytes
456 PORT_STATUS_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 8 ;1 byte
457 COLLISION_COUNTER .set STATISTICS_OFFSET + STAT_SIZE + 9 ;1 byte
458 RX_PKT_SIZE_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 10 ;4 bytes
459 PORT_CONTROL_ADDR .set STATISTICS_OFFSET + STAT_SIZE + 14 ;4 bytes
460 PORT_MAC_ADDR .set STATISTICS_OFFSET + STAT_SIZE + 18 ;6 bytes
461 RX_INT_STATUS_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 24 ;1 byte
462 STORM_PREVENTION_OFFSET_MC_DRIVER .set STATISTICS_OFFSET + STAT_SIZE + 25 ;4 bytes
463 STORM_PREVENTION_OFFSET_UC_DRIVER .set STATISTICS_OFFSET + STAT_SIZE + 29 ;4 bytes
464 STORM_PREVENTION_OFFSET_BC .set STATISTICS_OFFSET + STAT_SIZE + 33 ;4 bytes
465 STORM_PREVENTION_OFFSET_MC .set STATISTICS_OFFSET + STAT_SIZE + 37 ;4 bytes
466 STORM_PREVENTION_OFFSET_UC .set STATISTICS_OFFSET + STAT_SIZE + 41 ;4 bytes
467 SP_UPDATE_TIMESTAMP_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 45 ;4 bytes
468 SP_INCREMENT_COUNT_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 49 ;4 bytes
469 SP_COUNTER_UPDATE_INTERVAL_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 53 ;4 bytes
470 DISABLE_STORM_PREV_FOR_HOST .set STATISTICS_OFFSET + STAT_SIZE + 57 ;1 byte
472 SP_COUNTER_UPDATE_INTERVAL_DEFAULT .set 100000000
475 ;****************************************************************************
476 ; Protocol-specific Stats *
477 ;****************************************************************************
478 ; Placing these AFTER cfg offsets so as to not interfere with icss_emac
479 STP_INVALID_STATE_OFFSET .set STATISTICS_OFFSET + STAT_SIZE + 58 ; number of invalid STP state errors
481 ;***********************************************************************************************************
482 ; *
483 ; *
484 ; End of Section *
485 ; *
486 ; *
487 ;***********************************************************************************************************
490 ;****************************************************************************
491 ; *
492 ; *
493 ; *
494 ; *
495 ; DRAM1 Offsets for Switch *
496 ; *
497 ; *
498 ; *
499 ; *
500 ; *
501 ;****************************************************************************
502 ;*****************Queue Descriptors********************
503 P2_QUEUE_DESC_OFFSET .set 0x1EBC ; 4 queue descriptors for port 2 (PRU0 xmt)
504 P1_QUEUE_DESC_OFFSET .set 0x1E9C ; 4 queue descriptors for port 1 (PRU1 xmt)
505 P0_QUEUE_DESC_OFFSET .set 0x1E7C ; 4 queue descriptors for port 0 (host receive)
506 P2_COL_QUEUE_DESC_OFFSET .set 0x1E74 ; collision descriptor of port 2
507 P1_COL_QUEUE_DESC_OFFSET .set 0x1E6C ; collision descriptor of port 1
508 P0_COL_QUEUE_DESC_OFFSET .set 0x1E64 ; collision descriptor of port 0
509 COLLISION_STATUS_ADDR .set 0x1E60 ; Collision Status Register, P0: bit 0 is pending flag, bit 1..2 inidicates which queue,
510 ; P1: bit 8 is pending flag, 9..10 is queue number
511 ; p2: bit 16 is pending flag, 17..18 is queue number, remaining bits are 0.
513 INTERFACE_MAC_ADDR .set 0x1E58 ; Interface MAC Address
514 P2_MAC_ADDR .set 0x1E50 ; Port 2 MAC Address
515 P1_MAC_ADDR .set 0x1E48 ; Port 1 MAC Address
516 ; With dynamic configuration of queue size the offsets are variablel. For PRU to find which queue and descriptor needs to be served there
517 ; is a look-up table with index of port and queue number.
518 ; table definition to access queue size, buffer descriptor and buffer
520 ; table offset for queue size: 3 ports * 4 Queues * 1 byte offset = 24 bytes
521 QUEUE_SIZE_ADDR .set 0x1E30
522 ; table offset for queue: 3 ports * 4 Queues * 2 byte offset = 24 bytes
523 QUEUE_OFFSET_ADDR .set 0x1E18
524 ; table offset for queue descriptors: 3 ports * 4 Queues * 2 byte offset = 24 bytes
525 QUEUE_DESCRIPTOR_OFFSET_ADDR .set 0x1E00
526 ; todo: remove this older definition
527 QUEUE_SIZE_TBL_ADDR .set 0x1E00 ; table is filled by host before operation and structured in
528 ; 0x1E08: P0Q0 0x1E09: P0Q1 0x1E0A: P0Q2 0x1E0B: P0Q3
529 ; 0x1E04: P1Q0 0x1E05: P1Q1 0x1E06: P1Q2 0x1E07: P0Q3
530 ; 0x1E00: P0Q0 0x1E01: P0Q1 0x1E02: P0Q2 0x1E03: P0Q3
532 CONFIGURATION_OFFSET .set 0x1E00 ; 256 bytes of Configuratuin which also includes queue descriptors
534 ; Port 1
535 TX_CONTEXT_P1_Q1_OFFSET_ADDR .set SWITCH_SPECIFIC_DRAM1_START_OFFSET
536 P1_Q1_TX_CONTEXT_OFFSET .set TX_CONTEXT_P1_Q1_OFFSET_ADDR
537 P1_Q2_TX_CONTEXT_OFFSET .set P1_Q1_TX_CONTEXT_OFFSET + 8
538 P1_Q3_TX_CONTEXT_OFFSET .set P1_Q2_TX_CONTEXT_OFFSET + 8
539 P1_Q4_TX_CONTEXT_OFFSET .set P1_Q3_TX_CONTEXT_OFFSET + 8
540 ; Port 2
541 TX_CONTEXT_P2_Q1_OFFSET_ADDR .set P1_Q4_TX_CONTEXT_OFFSET + 8
542 P2_Q1_TX_CONTEXT_OFFSET .set TX_CONTEXT_P2_Q1_OFFSET_ADDR
543 P2_Q2_TX_CONTEXT_OFFSET .set P2_Q1_TX_CONTEXT_OFFSET + 8
544 P2_Q3_TX_CONTEXT_OFFSET .set P2_Q2_TX_CONTEXT_OFFSET + 8
545 P2_Q4_TX_CONTEXT_OFFSET .set P2_Q3_TX_CONTEXT_OFFSET + 8
547 ; Port 1 Tx Collision Context
548 COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR .set P2_Q4_TX_CONTEXT_OFFSET + 8
549 ; Port 2 Tx Collision Context
550 COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR .set COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR + 8
552 ; Host Port Rx Context
553 RX_CONTEXT_P0_Q1_OFFSET_ADDR .set COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR + 8
554 P0_Q1_RX_CONTEXT_OFFSET .set RX_CONTEXT_P0_Q1_OFFSET_ADDR
555 P0_Q2_RX_CONTEXT_OFFSET .set P0_Q1_RX_CONTEXT_OFFSET + 8
556 P0_Q3_RX_CONTEXT_OFFSET .set P0_Q2_RX_CONTEXT_OFFSET + 8
557 P0_Q4_RX_CONTEXT_OFFSET .set P0_Q3_RX_CONTEXT_OFFSET + 8
559 ; Port 1 Rx Context
560 RX_CONTEXT_P1_Q1_OFFSET_ADDR .set P0_Q4_RX_CONTEXT_OFFSET + 8
561 P1_Q1_RX_CONTEXT_OFFSET .set RX_CONTEXT_P1_Q1_OFFSET_ADDR
562 P1_Q2_RX_CONTEXT_OFFSET .set P1_Q1_RX_CONTEXT_OFFSET + 8
563 P1_Q3_RX_CONTEXT_OFFSET .set P1_Q2_RX_CONTEXT_OFFSET + 8
564 P1_Q4_RX_CONTEXT_OFFSET .set P1_Q3_RX_CONTEXT_OFFSET + 8
566 ; Port 2 Rx Context
567 RX_CONTEXT_P2_Q1_OFFSET_ADDR .set P1_Q4_RX_CONTEXT_OFFSET + 8
568 P2_Q1_RX_CONTEXT_OFFSET .set RX_CONTEXT_P2_Q1_OFFSET_ADDR
569 P2_Q2_RX_CONTEXT_OFFSET .set P2_Q1_RX_CONTEXT_OFFSET + 8
570 P2_Q3_RX_CONTEXT_OFFSET .set P2_Q2_RX_CONTEXT_OFFSET + 8
571 P2_Q4_RX_CONTEXT_OFFSET .set P2_Q3_RX_CONTEXT_OFFSET + 8
573 ; Host Port Collision Context
574 COL_RX_CONTEXT_P0_OFFSET_ADDR .set P2_Q4_RX_CONTEXT_OFFSET + 8 ;10 bytes
575 ; Port 1 Rx Collision context
576 COL_RX_CONTEXT_P1_OFFSET_ADDR .set COL_RX_CONTEXT_P0_OFFSET_ADDR + 12 ;10 bytes
577 ; Port 2 Rx Collision context
578 COL_RX_CONTEXT_P2_OFFSET_ADDR .set COL_RX_CONTEXT_P1_OFFSET_ADDR + 12 ;10 bytes
581 ;***********************************************************************************************************
582 ; *
583 ; *
584 ; End of Section *
585 ; *
586 ; *
587 ;***********************************************************************************************************
590 PORT_QUEUE_DESC_OFFSET .set EMAC_SPECIFIC_DRAM_START_OFFSET ; 4 queue descriptors for port tx. 32 bytes
591 TX_CONTEXT_Q1_OFFSET_ADDR .set PORT_QUEUE_DESC_OFFSET + 32
592 ;***********************************************************************************************************
593 ; *
594 ; *
595 ; End of Section *
596 ; *
597 ; *
598 ;***********************************************************************************************************
600 ;****************************************************************************
601 ; *
602 ; *
603 ; *
604 ; *
605 ; DRAM Offsets for EMAC *
606 ; Present on Both DRAM0 and DRAM1 *
607 ; *
608 ; *
609 ; *
610 ; *
611 ;****************************************************************************
612 ; table offset for Port queue descriptors: 1 ports * 4 Queues * 2 byte offset = 8 bytes
613 Q1_TX_CONTEXT_OFFSET .set TX_CONTEXT_Q1_OFFSET_ADDR
614 Q2_TX_CONTEXT_OFFSET .set Q1_TX_CONTEXT_OFFSET + 8
615 Q3_TX_CONTEXT_OFFSET .set Q2_TX_CONTEXT_OFFSET + 8
616 Q4_TX_CONTEXT_OFFSET .set Q3_TX_CONTEXT_OFFSET + 8
618 HOST_BD_SIZE .set (HOST_QUEUE_1_SIZE + HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + HOST_QUEUE_4_SIZE) * BD_SIZE
619 PORT_BD_SIZE .set (QUEUE_1_SIZE + QUEUE_2_SIZE + QUEUE_3_SIZE + QUEUE_4_SIZE) * 2 * BD_SIZE
621 P0_BUFFER_DESC_OFFSET .set SWITCH_SPECIFIC_SRAM_START_OFFSET
622 EOF_48K_BUFFER_BD .set P0_BUFFER_DESC_OFFSET + HOST_BD_SIZE + PORT_BD_SIZE
623 P0_COL_BD_OFFSET .set EOF_48K_BUFFER_BD
624 EOF_COL_BUFFER_BD .set P0_COL_BD_OFFSET + 3* BD_SIZE * 48
626 ;***********************************************************************************************************
627 ; *
628 ; *
629 ; End of Section *
630 ; *
631 ; *
632 ;***********************************************************************************************************
634 ;****************************************************************************
635 ; *
636 ; *
637 ; *
638 ; *
639 ; Shared RAM offsets for EMAC *
640 ; *
641 ; *
642 ; *
643 ; *
644 ; *
645 ;****************************************************************************
647 P1_COL_BD_OFFSET .set P0_COL_BD_OFFSET + BD_SIZE * 48
648 P2_COL_BD_OFFSET .set P1_COL_BD_OFFSET + BD_SIZE * 48
650 ;EMAC Firmware Version Information
651 ICSS_EMAC_FIRMWARE_RELEASE_1_OFFSET .set 0
652 ICSS_EMAC_FIRMWARE_RELEASE_2_OFFSET .set ICSS_EMAC_FIRMWARE_RELEASE_1_OFFSET + 4
653 ICSS_EMAC_FIRMWARE_FEATURE_OFFSET .set ICSS_EMAC_FIRMWARE_RELEASE_2_OFFSET + 4
654 ICSS_EMAC_FIRMWARE_RESERVED_FEATURE_OFFSET .set ICSS_EMAC_FIRMWARE_FEATURE_OFFSET + 4
655 ; Host Port Rx Context
656 HOST_Q1_RX_CONTEXT_OFFSET .set EOF_48K_BUFFER_BD ;1; Prashant - TODO EOF_48K_BUFFER_BD
657 HOST_Q2_RX_CONTEXT_OFFSET .set HOST_Q1_RX_CONTEXT_OFFSET + 8
658 HOST_Q3_RX_CONTEXT_OFFSET .set HOST_Q2_RX_CONTEXT_OFFSET + 8
659 HOST_Q4_RX_CONTEXT_OFFSET .set HOST_Q3_RX_CONTEXT_OFFSET + 8
661 ;***********************************************************************************************************
662 ; *
663 ; *
664 ; End of Section *
665 ; *
666 ; *
667 ;***********************************************************************************************************
670 ;****************************************************************************
671 ; *
672 ; *
673 ; *
674 ; *
675 ; Shared RAM offsets for both Switch and EMAC *
676 ; *
677 ; *
678 ; *
679 ; *
680 ; *
681 ;****************************************************************************
683 ; allow for max 48k switch buffer which spans the descriptors up to 0x1800 6kB
685 ; table offset for Host queue descriptors: 1 ports * 4 Queues * 2 byte offset = 8 bytes
686 HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR .set HOST_Q4_RX_CONTEXT_OFFSET + 8 ;8 bytes
687 ; table offset for queue: 4 Queues * 2 byte offset = 8 bytes
688 HOST_QUEUE_OFFSET_ADDR .set HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR + 8
689 ; table offset for queue size: 3 ports * 4 Queues * 1 byte offset = 12 bytes
690 HOST_QUEUE_SIZE_ADDR .set HOST_QUEUE_OFFSET_ADDR + 8
692 ;------------------------------Queue Descriptors--------------------------------;
693 HOST_QUEUE_DESC_OFFSET .set HOST_QUEUE_SIZE_ADDR + 16 ; 4 queue descriptors for port 0 (host receive). 32 bytes
694 ;------------------------------End of queue descriptors---------------------------;
695 P0_Q1_BD_OFFSET .set P0_BUFFER_DESC_OFFSET
696 P0_Q2_BD_OFFSET .set P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE
697 P0_Q3_BD_OFFSET .set P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE
698 P0_Q4_BD_OFFSET .set P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE
700 P1_Q1_BD_OFFSET .set P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE
701 P1_Q2_BD_OFFSET .set P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE
702 P1_Q3_BD_OFFSET .set P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE
703 P1_Q4_BD_OFFSET .set P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE
705 P2_Q1_BD_OFFSET .set P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE
706 P2_Q2_BD_OFFSET .set P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE
707 P2_Q3_BD_OFFSET .set P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE
708 P2_Q4_BD_OFFSET .set P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE
710 ;***********************************************************************************************************
711 ; *
712 ; *
713 ; End of Section *
714 ; *
715 ; *
716 ;***********************************************************************************************************
719 ;****************************************************************************
720 ; *
721 ; *
722 ; *
723 ; *
724 ; Memory Usage of L3 OCMC RAM *
725 ; *
726 ; *
727 ; *
728 ; *
729 ; *
730 ;****************************************************************************
731 ; L3 64KB Memory - mainly buffer Pool
732 ; put collision buffer at end of L3 memory. Simplifies PRU coding to be on same memory as queue buffer
733 P2_COL_BUFFER_OFFSET .set 0xFA00 ; 1536 byte collision buffer for port 2 send queue
734 P1_COL_BUFFER_OFFSET .set 0xF400 ; 1536 byte collision buffer for port 1 send queue
735 P0_COL_BUFFER_OFFSET .set 0xEE00 ; 1536 byte collision buffer for port 0 send queue
737 P0_Q1_BUFFER_OFFSET .set 0x0000
738 P0_Q2_BUFFER_OFFSET .set P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * BLOCK_SIZE
739 P0_Q3_BUFFER_OFFSET .set P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * BLOCK_SIZE
740 P0_Q4_BUFFER_OFFSET .set P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * BLOCK_SIZE
741 P1_Q1_BUFFER_OFFSET .set P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * BLOCK_SIZE
742 P1_Q2_BUFFER_OFFSET .set P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * BLOCK_SIZE
743 P1_Q3_BUFFER_OFFSET .set P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * BLOCK_SIZE
744 P1_Q4_BUFFER_OFFSET .set P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * BLOCK_SIZE
745 P2_Q1_BUFFER_OFFSET .set P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * BLOCK_SIZE
746 P2_Q2_BUFFER_OFFSET .set P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * BLOCK_SIZE
747 P2_Q3_BUFFER_OFFSET .set P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * BLOCK_SIZE
748 P2_Q4_BUFFER_OFFSET .set P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * BLOCK_SIZE
749 END_OF_BUFFER_POOL .set P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * BLOCK_SIZE
751 ;***********************************************************************************************************
752 ; *
753 ; *
754 ; End of Section *
755 ; *
756 ; *
757 ;***********************************************************************************************************
759 .if $defined("PRU")
760 ; Collision Status Register
761 struct_collision_status .struct
762 port0 .ubyte ; port 0 pending and queue number
763 port1 .ubyte ; port 1 pending and queue number
764 port2 .ubyte ; port 2 pending and queue number
765 .endstruct
767 .asg t0, P0_COLLISION_PENDING
768 .asg t8, P1_COLLISION_PENDING
769 .asg t16, P2_COLLISION_PENDING
770 .asg t24, HOST_COLLISION_READ_PENDING ;Host yet to clear the collision buffer
773 .endif
775 ; switch configuration
776 ; enable ports : receive enable , transmit enable, block, learning, flush table, age out table (older are removed), tear
777 ; rate limiting setup
778 ; filter database setup for MC
779 ; learn multicast option one for both ports
780 ; learn broadcast option one for both ports
781 ; statistics clear
782 .endif ;ICSS_SWITCH__H