2 /*
3 * file: icss_emacLoc.h
4 *
5 * brief: Local function declarations
6 */
8 /* Copyright (C) {2016} Texas Instruments Incorporated - http://www.ti.com/
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the
20 * distribution.
21 *
22 * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 */
39 #ifndef ICSS_EMAC_LOC_H
40 #define ICSS_EMAC_LOC_H
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 #include <stdint.h>
46 #include <ti/drv/icss_emac/icss_emacDrv.h>
48 #include <ti/csl/src/ip/icss/V1/cslr_icss_intc.h>
49 #include <ti/csl/src/ip/icss/V1/cslr_icss_iep.h>
50 #include <ti/csl/src/ip/icss/V0/cslr_icssm_iep.h>
51 #if defined (SOC_AM335x) || defined (SOC_AM437x)
52 #include <ti/csl/src/ip/mdio/V2/cslr_mdio.h>
53 #include <ti/csl/src/ip/mdio/V2/csl_mdio.h>
54 #include <ti/csl/src/ip/mdio/V2/csl_mdioAux.h>
55 #else
56 #include <ti/csl/csl_mdioAux.h>
57 #endif
58 /***************************************************************************
59 * LINK/DUPLEX MACROS & MASKS *
60 * Bits for Port Status and Duplexity. This is set by ARM and read by FW *
61 * Possible to add more info as bits 2-7 are free *
62 ****************************************************************************
63 */
64 #define ICSS_EMAC_PORT_LINK_MASK (0x1U)
65 #define ICSS_EMAC_PORT_IS_HD_MASK (0x2U)
67 /* ICSS_EmacPollLink can be called from ISR or from actual poll, these defines depect those 2 cases, local to LLD*/
68 #define ICSS_EMAC_POLL_FROM_ISR 0x1U
69 #define ICSS_EMAC_POLL_FROM_POLL_LINK 0x2U
72 /* NRT Buffer descriptor definition
73 Each buffer descriptor points to a max 32 byte block and has 32 bit in size to have atomic operation.
74 PRU can address bytewise into memory.
75 Definition of 32 bit desriptor is as follows
77 Bits Name Meaning
78 ==================================================================================================
79 0..7 Index points to index in buffer queue, max 256 x 32 byte blocks can be addressed
80 8..12 Block_length number of valid bytes in this specific block. Will be <=32 bytes on last block of packet
81 13 More "More" bit indicating that there are more blocks for the
82 14 Shadow inidcates that "index" is pointing into shadow buffer
83 15 TimeStamp indicates that this packet has time stamp in seperate buffer - only needed of PTCP runs on host
84 16..17 Port different meaning for ingress and egress, ingress Port=0 inidcates phy port 1 and Port = 1
85 inidcates phy port 2. Egress: 0 sends on phy port 1 and 1 sends on phy port 2. Port = 2 goes
86 over MAC table look-up
87 18..28 Length 11 bit of total packet length which is put into first BD only so that host access only one BD
88 29 VlanTag indicates that packet has Length/Type field of 0x08100 with VLAN tag in following byte
89 30 Broadcast inidcates that packet goes out on both physical ports, there will be two bd but only one buffer
90 31 Error indicates there was an error in the packet
91 */
93 /* NRT Queue Defintion
94 Each port has up to 4 queues with variable length. The queus is processed as ring buffer with read and write pointer.
95 Both pointer are address pointers and increment by 4 for each buffer descriptor/position.
96 Queue has a length defined in constants and a status. Status is defined as described below
98 Bits Name Meaning
99 =====================================================================================================
100 0 Busy_M This queue is busy by the master port which is the PRU receiving packets from the master
101 1 Collision Slave is/has written into shadow queue, both descriptors and data.
102 2 Overflow there was not enough space to write to queue and packet was discarded
103 4..7 Reserved reserved
105 There is busy slave flag in different byte address to grant access to queue to master in case
106 of simultaneous access. Host will alwasys be slave in this case. The PRU which is sending the
107 packet on phy port will be the master. When both PRUs wants to write to host queues PRU0
108 is master and PRU1 is slave.
110 Bits Name Meaning
111 =====================================================================================================
112 0 Busy_S This queue is busy by the master port which is the PRU receiving packets from the master
113 1..7 Reserved
115 Length is the number of 32 byte blocks per queue. max_fill_level tells the minimum distance between write and read pointer.
116 over_flow_cnt tells how many times the write pointer runs into the read_pointer.
117 */
119 typedef struct ICSS_EmacQueue_s {
120 uint16_t rd_ptr;
121 uint16_t wr_ptr;
122 uint8_t busy_s;
123 uint8_t status;
124 uint8_t max_fill_level;
125 uint8_t overflow_cnt;
126 } ICSS_EmacQueue;
128 #define ICSS_EMAC_Q_MAX_FILL_LEVEL_OFFSET (6U)
129 #define ICSS_EMAC_Q_OVERFLOW_CNT_OFFSET (7U)
131 /* EMAC Time Triggered Send Status Bit Masks */
132 #define ICSS_EMAC_TTS_PRU_ENABLE_MASK ((uint32_t)0x1U)
133 #define ICSS_EMAC_TTS_MISSED_CYCLE_MASK ((ICSS_EMAC_TTS_PRU_ENABLE_MASK) << 1)
134 #define ICSS_EMAC_TTS_INSERT_CYC_FRAME_MASK ((ICSS_EMAC_TTS_MISSED_CYCLE_MASK) << 1)
135 #define ICSS_EMAC_TTS_CYC_TX_SOF_MASK ((ICSS_EMAC_TTS_INSERT_CYC_FRAME_MASK) << 1)
136 #define ICSS_EMAC_TTS_CYC_INTERRUPT_ENABLE_MASK ((ICSS_EMAC_TTS_CYC_TX_SOF_MASK) << 1)
138 /* With dynamic configuration of queue size the offsets are variablel. For PRU to find which queue and descriptor needs to be served there */
139 /* is a look-up table with index of port and queue number. */
140 /* table definition to access queue size, buffer descriptor and buffer */
142 /* table offset for queue size: 3 ports * 4 Queues * 1 byte offset = 24 bytes */
143 #define ICSS_EMAC_DEFAULT_FW_QUEUE_SIZE_ADDR (0x1E30U)
144 /* table offset for queue: 3 ports * 4 Queues * 2 byte offset = 24 bytes */
145 #define ICSS_EMAC_DEFAULT_FW_QUEUE_OFFSET_ADDR (0x1E18U)
146 /* table offset for queue descriptors: 3 ports * 4 Queues * 2 byte offset = 24 bytes */
147 #define ICSS_EMAC_DEFAULT_FW_QUEUE_DESCRIPTOR_OFFSET_ADDR (0x1E00U)
150 /**< Firmware MemoryMap Init DONE */
151 #define ICSS_EMAC_DEFAULT_FW_MMAP_INIT_DONE 0xABCD1234U
154 /* Keeping a copy of default firmware memory map configuration parameters for backward compatibility BEGIN */
155 #define ICSS_EMAC_DEFAULT_FW_BD_SIZE (4U) /* one buffer descriptor is 4 bytes */
156 #define ICSS_EMAC_DEFAULT_FW_BLOCK_SIZE (32U) /* bytes derived from ICSS architecture */
159 /*Memory Usage of DRAM0/DRAM1 and Shared RAM */
160 #define EMAC_SPECIFIC_DEFAULT_DRAM_START_OFFSET ((uint32_t)0x1E98U)
161 #define SWITCH_SPECIFIC_DEFAULT_SRAM_START_OFFSET ((uint32_t)0x400U)
162 #define SWITCH_SPECIFIC_DEFAULT_DRAM1_START_OFFSET ((uint32_t)0x1D00U)
165 /* Queues on PHY PORT 1/2, setting max to 16, number of queues requird will depend on protocol/firmware,
166 for dual emac, 4 queues per port will be used */
167 #define ICSS_EMAC_DEFAULT_MAX_NUMBER_OF_QUEUES ((uint32_t)16)
168 /* 48 blocks per max packet */
169 /* 2 full sized ETH packets: 96 blocks, 3 packets = 144, 4 packets = 192 */
171 /* Default number of queues per Port */
172 #define ICSS_EMAC_DEFAULT_NUMBER_OF_QUEUES ((uint32_t)4U)
174 /* Physical Port queue size. Same for both ports */
175 #define ICSS_EMAC_DEFAULT_FW_QUEUE_1_SIZE ((uint32_t)97U) /* Network Management high */
176 #define ICSS_EMAC_DEFAULT_FW_QUEUE_2_SIZE ((uint32_t)97U) /* Network Management low */
177 #define ICSS_EMAC_DEFAULT_FW_QUEUE_3_SIZE ((uint32_t)97U) /* Protocol specific */
178 #define ICSS_EMAC_DEFAULT_FW_QUEUE_4_SIZE ((uint32_t)97U) /* NRT (IP,ARP, ICMP, ?) */
179 #define ICSS_EMAC_DEFAULT_FW_QUEUE_5_SIZE ((uint32_t)0U)
180 #define ICSS_EMAC_DEFAULT_FW_QUEUE_6_SIZE ((uint32_t)0U)
181 #define ICSS_EMAC_DEFAULT_FW_QUEUE_7_SIZE ((uint32_t)0U)
182 #define ICSS_EMAC_DEFAULT_FW_QUEUE_8_SIZE ((uint32_t)0U)
183 #define ICSS_EMAC_DEFAULT_FW_QUEUE_9_SIZE ((uint32_t)0U)
184 #define ICSS_EMAC_DEFAULT_FW_QUEUE_10_SIZE ((uint32_t)0U)
185 #define ICSS_EMAC_DEFAULT_FW_QUEUE_11_SIZE ((uint32_t)0U)
186 #define ICSS_EMAC_DEFAULT_FW_QUEUE_12_SIZE ((uint32_t)0U)
187 #define ICSS_EMAC_DEFAULT_FW_QUEUE_13_SIZE ((uint32_t)0U)
188 #define ICSS_EMAC_DEFAULT_FW_QUEUE_14_SIZE ((uint32_t)0U)
189 #define ICSS_EMAC_DEFAULT_FW_QUEUE_15_SIZE ((uint32_t)0U)
190 #define ICSS_EMAC_DEFAULT_FW_QUEUE_16_SIZE ((uint32_t)0U)
192 /* HOST PORT QUEUES can buffer up to 4 full sized frames per queue */
193 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_1_SIZE ((uint32_t)194U) /* Protocol and/or VLAN priority 7 and 6 */
194 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_2_SIZE ((uint32_t)194U) /* Protocol mid */
195 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_3_SIZE ((uint32_t)194U) /* Protocol low */
196 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_4_SIZE ((uint32_t)194U) /* NRT (IP, ARP, ICMP ?) */
197 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_5_SIZE ((uint32_t)0U)
198 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_6_SIZE ((uint32_t)0U)
199 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_7_SIZE ((uint32_t)0U)
200 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_8_SIZE ((uint32_t)0U)
201 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_9_SIZE ((uint32_t)0U)
202 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_10_SIZE ((uint32_t)0U)
203 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_11_SIZE ((uint32_t)0U)
204 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_12_SIZE ((uint32_t)0U)
205 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_13_SIZE ((uint32_t)0U)
206 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_14_SIZE ((uint32_t)0U)
207 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_15_SIZE ((uint32_t)0U)
208 #define ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_16_SIZE ((uint32_t)0U)
211 #define ICSS_EMAC_DEFAULT_FW_COLLISION_QUEUE_SIZE (48U)
213 #define ICSS_EMAC_DEFAULT_FW_P0_BUFFER_DESC_OFFSET (SWITCH_SPECIFIC_DEFAULT_SRAM_START_OFFSET)
217 /* Shared RAM offsets for EMAC, Q2/Q3/Q4 derived from Q1 */
218 /* Host Port Rx Context OFFSET*/
220 #define ICSS_EMAC_DEFAULT_FW_PROMISCUOUS_MODE_OFFSET (ICSS_EMAC_DEFAULT_FW_EOF_BUFFER_BD + 4U)
221 #define ICSS_EMAC_DEFAULT_FW_HOST_Q1_RX_CONTEXT_OFFSET (ICSS_EMAC_DEFAULT_FW_PROMISCUOUS_MODE_OFFSET + 4U)
224 /* EMAC Firmware Version Information */
225 #define ICSS_EMAC_DEFAULT_FW_RELEASE_2_OFFSET (ICSS_EMAC_DEFAULT_FW_RELEASE_1_OFFSET + 4U)
226 #define ICSS_EMAC_DEFAULT_FW_RELEASE_1_OFFSET (0U)
228 /* ICSS_EMAC_FIRMWARE_FEATURE_OFFSET bitmap
229 Bit 0 1: TTS support
230 Bit 1 0 : MAC mode 1 : Switch Mode
231 Bit 2 1: VLAN
232 Bit 3 : 1 : Storm prevention
233 Bit 4-Bit 7 : 0: No redundancy 1 : MRP 2 : DLR 3 : HSR 4 : PRP 5 : MRPD
234 Bit 8-Bit 10 : PTP (0: None 1: IEEE1588 2: PTCP 3: gPTP)
235 Bit 11 : Reserved
236 Bit 12-Bit 14 : Number of queues -1
237 Bit 15: Reserved
238 Bit 16: 1: PROFINET( CPM/PPM)
239 Bit 17: 1: DCP filer (PROFINET)
240 Bit 18: 1: ARP filter (PROFINET)
241 Bit 19-25: RSVD for other features
242 Bit 26: Multicast filter
243 Bit 27: VLAN filtering
244 */
245 #define ICSS_EMAC_DEFAULT_FW_FEATURE_OFFSET (ICSS_EMAC_DEFAULT_FW_RELEASE_2_OFFSET + 4U)
246 #define ICSS_EMAC_DEFAULT_FW_RESERVED_FEATURE_OFFSET (ICSS_EMAC_DEFAULT_FW_FEATURE_OFFSET + 4U)
250 /***************************************************************************
251 * General Purpose Statistics, these are present on both PRU0 and PRU1 DRAM
252 ****************************************************************************/
253 /* Base statistics offset */
254 #define ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET (0x1F00U)
255 /* Needs to be updated anytime a new statistic is added or existing statistics is no longer supported (removed).*/
256 #define ICSS_EMAC_DEFAULT_FW_STAT_SIZE (0x90U)
258 /* Offsets from ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET */
259 #define ICSS_EMAC_DEFAULT_FW_STORM_PREVENTION_OFFSET (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE) /*4 bytes */
260 #define ICSS_EMAC_DEFAULT_FW_PHY_SPEED_OFFSET (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 4U) /*4 bytes*/
261 #define ICSS_EMAC_DEFAULT_FW_PORT_STATUS_OFFSET (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 8U) /*1 byte */
262 #define ICSS_EMAC_DEFAULT_FW_COLLISION_COUNTER (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 9U) /*1 byte */
263 #define ICSS_EMAC_DEFAULT_FW_RX_PKT_SIZE_OFFSET (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 10U) /*4 bytes */
264 #define ICSS_EMAC_DEFAULT_FW_PORT_CONTROL_ADDR (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 14U) /*4 bytes */
265 #define ICSS_EMAC_DEFAULT_FW_PORT_MAC_ADDR (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 18U) /*6 bytes */
266 #define ICSS_EMAC_DEFAULT_FW_RX_INT_STATUS_OFFSET (ICSS_EMAC_DEFAULT_FW_STATISTICS_OFFSET + ICSS_EMAC_DEFAULT_FW_STAT_SIZE + 24U) /*1 byte */
269 /* DRAM1 Offsets for Switch*/
270 #define ICSS_EMAC_DEFAULT_FW_P0_COL_QUEUE_DESC_OFFSET (0x1E64U) /* collision descriptor of port 0 */
271 #define ICSS_EMAC_DEFAULT_FW_P0_QUEUE_DESC_OFFSET (0x1E7CU) /* 4 queue descriptors for port 0 (host receive) */
273 #define ICSS_EMAC_DEFAULT_FW_INTERFACE_MAC_ADDR_OFFSET (0x1E58U) /* Interface MAC Address */
274 #define ICSS_EMAC_DEFAULT_FW_COLLISION_STATUS_ADDR (0x1E60U) /* Collision Status Register, P0: bit 0 is pending flag, bit 1..2 inidicates which queue, */
275 /* P1: bit 8 is pending flag, 9..10 is queue number */
276 /* p2: bit 16 is pending flag, 17..18 is queue number, remaining bits are 0. */
278 /* DRAM Offsets for EMAC. Present on Both DRAM0 and DRAM1 */
279 /* EMAC Time Triggered Send Base Offset Base, the following offsets are calcuated during init time by the driver, no changes expected in FW:
280 used by the driver, do not expect these offsets to change, same for all variants of Firmware
281 * ICSS_EMAC_TTS_CYCLE_START_OFFSET (ICSS_EMAC_DEFAULT_FW_TTS_BASE_OFFSET)
282 * ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET (ICSS_EMAC_TTS_CYCLE_START_OFFSET + 8U)
283 * ICSS_EMAC_TTS_CFG_TIME_OFFSET (ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET + 4U)
284 * ICSS_EMAC_TTS_STATUS_OFFSET (ICSS_EMAC_TTS_CFG_TIME_OFFSET + 4U)
285 * ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET (ICSS_EMAC_TTS_STATUS_OFFSET + 4U)
286 * ICSS_EMAC_TTS_PREV_TX_SOF (ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET + 4U)
287 * ICSS_EMAC_TTS_CYC_TX_SOF (ICSS_EMAC_TTS_PREV_TX_SOF + 8U)
288 */
289 #define ICSS_EMAC_DEFAULT_FW_TTS_BASE_OFFSET (EMAC_SPECIFIC_DEFAULT_DRAM_START_OFFSET)
293 /* Used to calculate end of buffer bd offset, not part of Mmap configuration, local usage only */
294 #define ICSS_EMAC_DEFAULT_FW_HOST_BD_SIZE ((ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_1_SIZE + ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_2_SIZE + ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_3_SIZE + ICSS_EMAC_DEFAULT_FW_HOST_QUEUE_4_SIZE) * ICSS_EMAC_DEFAULT_FW_BD_SIZE)
295 #define ICSS_EMAC_DEFAULT_FW_PORT_BD_SIZE ((ICSS_EMAC_DEFAULT_FW_QUEUE_1_SIZE + ICSS_EMAC_DEFAULT_FW_QUEUE_2_SIZE + ICSS_EMAC_DEFAULT_FW_QUEUE_3_SIZE + ICSS_EMAC_DEFAULT_FW_QUEUE_4_SIZE) * 2U * ICSS_EMAC_DEFAULT_FW_BD_SIZE)
298 #define ICSS_EMAC_DEFAULT_FW_EOF_BUFFER_BD (ICSS_EMAC_DEFAULT_FW_P0_BUFFER_DESC_OFFSET + ICSS_EMAC_DEFAULT_FW_HOST_BD_SIZE + ICSS_EMAC_DEFAULT_FW_PORT_BD_SIZE)
299 #define ICSS_EMAC_DEFAULT_FW_P0_COL_BD_OFFSET (ICSS_EMAC_DEFAULT_FW_EOF_BUFFER_BD)
303 /*DRAM1 Offsets for EMAC */
304 /*table offset for Port queue descriptors: 1 ports * 4 Queues * 2 byte offset = 8 bytes */
305 #define ICSS_EMAC_DEFAULT_FW_PORT_QUEUE_DESC_OFFSET (EMAC_SPECIFIC_DEFAULT_DRAM_START_OFFSET + 32U + 8U) /* 4 queue descriptors for port tx. 32 bytes */
306 #define ICSS_EMAC_DEFAULT_FW_EMAC_Q1_TX_CONTEXT_OFFSET (ICSS_EMAC_DEFAULT_FW_PORT_QUEUE_DESC_OFFSET + 32U)
308 /*DRAM1 Offsets for Switch */
309 /* TX/RX context offsets */
310 /* Port 1 */
311 #define ICSS_EMAC_DEFAULT_FW_SWITCH_P1_Q1_TX_CONTEXT_OFFSET (SWITCH_SPECIFIC_DEFAULT_DRAM1_START_OFFSET)
315 /* Memory Usage of L3 OCMC RAM */
316 /* L3 64KB Memory - mainly buffer Pool
317 * put collision buffer at end of L3 memory. Simplifies PRU coding to be on same memory as queue buffer
318 Note: Buffer queues for port 1 and port 2 are derived from base offset of Port 0*/
319 #define ICSS_EMAC_DEFAULT_FW_HOST_P0_Q1_BUFFER_OFFSET (0x0000U)
322 #define ICSS_EMAC_DEFAULT_FW_P0_COL_BUFFER_OFFSET (0xEE00U) /* 1536 byte collision buffer for port 0 send queue */
326 #define ICSS_EMAC_DEFAULT_FW_TX_QUEUES_BUFFER_OFFSET (0U)
329 /* Keeping a copy of firmware memory map configuration parameters for backward compatibility END */
331 /* Firmware feature set defines*/
332 #define ICSS_EMAC_FW_TTS_FEATURE_SHIFT ((uint32_t)0U)
333 #define ICSS_EMAC_FW_TTS_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_TTS_FEATURE_SHIFT)
336 /* MODE indicates firmware running configuration which can be either dual emac(0U) or switch (1U) MODE */
337 #define ICSS_EMAC_FW_MODE_FEATURE_SHIFT ((uint32_t)1U)
338 #define ICSS_EMAC_FW_MODE_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_MODE_FEATURE_SHIFT)
340 #define ICSS_EMAC_FW_VLAN_FEATURE_SHIFT ((uint32_t)2U)
341 #define ICSS_EMAC_FW_VLAN_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_VLAN_FEATURE_SHIFT)
343 #define ICSS_EMAC_FW_STORM_PREVENTIION_FEATURE_SHIFT ((uint32_t)3U)
344 #define ICSS_EMAC_FW_STORM_PREVENTIION_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_STORM_PREVENTIION_FEATURE_SHIFT)
346 #define ICSS_EMAC_FW_PROMISCOUS_MODE_FEATURE_SHIFT ((uint32_t)19U)
347 #define ICSS_EMAC_FW_PROMISCOUS_MODE_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_PROMISCOUS_MODE_FEATURE_SHIFT)
349 #define ICSS_EMAC_FW_PTP_FEATURE_SHIFT ((uint32_t)8U)
350 #define ICSS_EMAC_FW_PTP_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_PTP_FEATURE_SHIFT)
352 #define ICSS_EMAC_FW_MULTICAST_FILTER_FEATURE_SHIFT ((uint32_t)26U)
353 #define ICSS_EMAC_FW_MULTICAST_FILTER_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_MULTICAST_FILTER_FEATURE_SHIFT)
355 #define ICSS_EMAC_FW_VLAN_FILTER_FEATURE_SHIFT ((uint32_t)27U)
356 #define ICSS_EMAC_FW_VLAN_FILTER_FEATURE_CTRL (((uint32_t)1U) << ICSS_EMAC_FW_VLAN_FILTER_FEATURE_SHIFT)
358 /**This value in the MDIO Reg means 10 mbps mode is enabled*/
359 #define Ten_Mbps 0xa
360 /**This value in the MDIO Reg means 100 mbps mode is enabled*/
361 #define Hundread_Mbps 0x64
363 #define LINK0_PRU_EVT_MASK (0x200U)
364 #define LINK1_PRU_EVT_MASK (0x200000U)
365 #define TX_COMPLETION0_PRU_EVT_MASK (((uint32_t)1U) << 22)
366 #define TX_COMPLETION1_PRU_EVT_MASK (((uint32_t)1U) << 23)
367 #define TTS_CYC0_PRU_EVT_MASK (((uint32_t)1U) << 24)
368 #define TTS_CYC1_PRU_EVT_MASK (((uint32_t)1U) << 25)
369 /* Local Functions to LLD to Calculate Offsets and BD/Buffer sizes*/
370 void ICSS_EmacCalcPort0BufferOffset(ICSS_EmacHandle icssEmacHandle, uint32_t bufferOffsets[ICSS_EMAC_NUMQUEUES], uint32_t bdOffsets[ICSS_EMAC_NUMQUEUES]);
371 void ICSS_EmacCalcPort1BufferOffset(ICSS_EmacHandle icssEmacHandle, uint32_t bufferOffsets[ICSS_EMAC_NUMQUEUES], uint32_t bdOffsets[ICSS_EMAC_NUMQUEUES]);
372 void ICSS_EmacCalcPort2BufferOffset(ICSS_EmacHandle icssEmacHandle, uint32_t bufferOffsets[ICSS_EMAC_NUMQUEUES], uint32_t bdOffsets[ICSS_EMAC_NUMQUEUES]);
373 uint32_t ICSS_EmacCalcTotalPortBDSize(ICSS_EmacHandle icssEmacHandle);
374 uint32_t ICSS_EmacCalcTotalHostBDSize(ICSS_EmacHandle icssEmacHandle);
375 uint32_t ICSS_EmacCalcEndOfBufferBD(ICSS_EmacHandle icssEmacHandle);
376 uint32_t ICSS_EmacCalcEndOfColBufferBD(ICSS_EmacHandle icssEmacHandle);
377 uint32_t ICSS_EmacCalcTotalHostBDSize(ICSS_EmacHandle icssEmacHandle);
378 uint32_t ICSS_EmacCalcTotalPortBDSize(ICSS_EmacHandle icssEmacHandle);
379 uint32_t ICSS_EmacCalcTotalBufferPoolSize(ICSS_EmacHandle icssEmacHandle);
381 int32_t ICSS_EmacGetFwMMapInitConfigLocal(ICSS_EmacHandle icssEmacHandle, uint32_t instance);
382 int8_t ICSS_EmacValidateFeatureSet(ICSS_EmacHandle icssEmacHandle, uint8_t portNo, uint32_t featureCtrl);
383 void ICSS_EmacMemInit(uint32_t* addr, uint32_t size);
384 void ICSS_EmacInitLinkState(ICSS_EmacHandle icssEmacHandle, uint8_t interfaceId, uint8_t portNo);
386 #ifdef __cplusplus
387 }
388 #endif
390 #endif