[processor-sdk/pdk.git] / packages / ti / drv / ipc / examples / common / j721e / linker_r5f_mcu1_0_sbl_sysbios.lds
1 /*----------------------------------------------------------------------------*/
2 /* File: linker_r5f_mcu1_0_sysbios.lds */
3 /* Description: */
4 /* Link command file for J7ES MCU1_0 view */
5 /* TI ARM Compiler version 15.12.3 LTS or later */
6 /* */
7 /* (c) Texas Instruments 2018, All rights reserved. */
8 /*----------------------------------------------------------------------------*/
9 /* History: */
10 /* Aug 26th, 2016 Original version .......................... Loc Truong */
11 /* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
12 /* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
13 /* Sep 17th, 2018 Added DDR sections for IPC................. J. Bergsagel */
14 /* Sep 26th, 2018 Extra mem sections for IPC resource table.. J. Bergsagel */
15 /* Nov 06th, 2018 Correction to TCM addresses for MCU1_0..... J. Bergsagel */
16 /* Nov 07th, 2018 Split up OCMRAM_MCU for split-mode R5Fs.... J. Bergsagel */
17 /* Apr 23th, 2019 Changes for R5F startup Code............... Vivek Dhande */
18 /*----------------------------------------------------------------------------*/
19 /* Linker Settings */
20 /* Standard linker options */
21 --retain="*(.bootCode)"
22 --retain="*(.startupCode)"
23 --retain="*(.startupData)"
24 --fill_value=0
25 --stack_size=0x2000
26 --heap_size=0x1000
28 -stack 0x2000 /* SOFTWARE STACK SIZE */
29 -heap 0x2000 /* HEAP AREA SIZE */
31 #define DDR0_ALLOCATED_START 0xA0000000
33 #define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
34 #define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
35 #define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
36 #define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
38 #define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
39 #define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
40 #define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
41 #define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
42 #define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
44 #define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
45 #define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
46 #define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
47 #define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
48 #define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
50 #define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
51 #define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
52 #define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
53 #define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
54 #define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
56 #define OCMRAM_MCU1_0_START 0x41cfe000
57 #define OCMRAM_MCU1_1_START 0x41cff000
59 -e __VECS_ENTRY_POINT
60 --retain="*(.utilsCopyVecsToAtcm)"
62 /*----------------------------------------------------------------------------*/
63 /* Memory Map */
64 MEMORY
65 {
66 /* MCU1_R5F_0 local view */
67 /* MCU1_R5F0_TCMB0 (RWIX) : origin=0x41010000 length=0x8000 (documented only, to avoid conflict below) */
68 R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
69 RESET_VECTORS(X) : ORIGIN = 0x41C40000, LENGTH = 0x100
71 /* MCU1_R5F_0 SoC view */
72 MCU1_R5F0_ATCM (RWIX) : origin=0x41000000 length=0x8000
73 MCU1_R5F0_BTCM (RWIX) : origin=0x41010000 length=0x8000
75 /* MCUSS RAM - Start towards the end to avoid Bootloader usage of the SRAM */
76 OCMRAM_MCU1_0 (RWIX) : origin=OCMRAM_MCU1_0_START length=0x1000
77 OCMRAM_MCU1_1 (RWIX) : origin=OCMRAM_MCU1_1_START length=0x1000
79 DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
80 MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
81 MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
82 MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
83 MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
84 MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
85 MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
86 MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
87 MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
88 MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
89 MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
90 MCU2_0_IPC_DATA (RWIX) : origin=MCU2_0_ALLOCATED_START length=0x00100000 /* 1MB */
91 MCU2_0_EXT_DATA (RWIX) : origin=MCU2_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
92 MCU2_0_R5F_MEM_TEXT (RWIX) : origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
93 MCU2_0_R5F_MEM_DATA (RWIX) : origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
94 MCU2_0_DDR_SPACE (RWIX) : origin=MCU2_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
95 MCU2_1_IPC_DATA (RWIX) : origin=MCU2_1_ALLOCATED_START length=0x00100000 /* 1MB */
96 MCU2_1_EXT_DATA (RWIX) : origin=MCU2_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
97 MCU2_1_R5F_MEM_TEXT (RWIX) : origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
98 MCU2_1_R5F_MEM_DATA (RWIX) : origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
99 MCU2_1_DDR_SPACE (RWIX) : origin=MCU2_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
101 SHARED_DDR_SPACE (RWIX) : origin=0xAA000000 length=0x01C00000 /* 28MB */
103 } /* end of MEMORY */
105 /*----------------------------------------------------------------------------*/
106 /* Section Configuration */
108 SECTIONS
109 {
110 .vecs : {
111 *(.vecs)
112 } palign(8) > RESET_VECTORS
113 .vecs : {
114 __VECS_ENTRY_POINT = .;
115 } palign(8) > RESET_VECTORS
116 .init_text : {
117 boot.*(.text)
118 *(.text:ti_sysbios_family_arm_MPU_*)
119 *(.text:ti_sysbios_family_arm_v7r_Cache_*)
120 } > MCU1_R5F0_BTCM
121 .text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU1_R5F0_BTCM
122 .utilsCopyVecsToAtcm : {} palign(8) > MCU1_R5F0_BTCM
123 .bootCode : {} palign(8) > MCU1_R5F0_BTCM
124 .startupCode : {} palign(8) > MCU1_R5F0_BTCM
125 .startupData : {} palign(8) > MCU1_R5F0_BTCM, type = NOINIT
126 .text : {} palign(8) > MCU1_0_DDR_SPACE
127 .const : {} palign(8) > MCU1_0_DDR_SPACE
128 .cinit : {} palign(8) > MCU1_0_DDR_SPACE
129 .pinit : {} palign(8) > MCU1_0_DDR_SPACE
130 .bss : {} align(4) > MCU1_0_DDR_SPACE
131 .data : {} palign(128) > MCU1_0_DDR_SPACE
132 .data_buffer: {} palign(128) > MCU1_0_DDR_SPACE
133 .sysmem : {} > MCU1_0_DDR_SPACE
134 .stack : {} align(4) > MCU1_0_DDR_SPACE
135 ipc_data_buffer (NOINIT) : {} palign(128) > MCU1_0_DDR_SPACE
137 .const.devgroup.MCU_WAKEUP : {} align(4) > MCU1_0_DDR_SPACE
138 .const.devgroup.MAIN : {} align(4) > MCU1_0_DDR_SPACE
139 .const.devgroup.DMSC_INTERNAL : {} align(4) > MCU1_0_DDR_SPACE
140 .bss.devgroup.MAIN : {} align(4) > MCU1_0_DDR_SPACE
141 .bss.devgroup.MCU_WAKEUP : {} align(4) > MCU1_0_DDR_SPACE
142 .bss.devgroup.DMSC_INTERNAL : {} align(4) > MCU1_0_DDR_SPACE
143 .boardcfg_data : {} align(4) > MCU1_0_DDR_SPACE
144 .bss.devgroup* : {} align(4) > MCU1_0_DDR_SPACE
145 .const.devgroup* : {} align(4) > MCU1_0_DDR_SPACE
147 .resource_table : {
148 __RESOURCE_TABLE = .;
149 } > MCU1_0_EXT_DATA_BASE
151 .tracebuf : {} > MCU1_0_EXT_DATA
153 } /* end of SECTIONS */
155 /*----------------------------------------------------------------------------*/
156 /* Misc linker settings */
159 /*-------------------------------- END ---------------------------------------*/