[processor-sdk/pdk.git] / packages / ti / drv / ipc / examples / common / j721e / linker_r5f_mcu3_0_sysbios.lds
1 /*----------------------------------------------------------------------------*/
2 /* File: linker_r5f_mcu3_0_sysbios.lds */
3 /* Description: */
4 /* Linker command file for DRA8 MCU 3 view */
5 /* TI ARM Compiler version 16.9.6 LTS or later */
6 /* */
7 /* Platform: VLAB */
8 /* (c) Texas Instruments 2018, All rights reserved. */
9 /*----------------------------------------------------------------------------*/
10 /* History: */
11 /* Oct 12th, 2018 Original version .......................... Suman Anna */
12 /* Nov 06th, 2018 Corrections to TCM addresses for MCU3_0.... J. Bergsagel */
13 /* Nov 07th, 2018 Split up OCMRAM_MCU for split-mode R5Fs.... J. Bergsagel */
14 /* Apr 23th, 2019 Changes for R5F startup Code............... Vivek Dhande */
15 /*----------------------------------------------------------------------------*/
16 /* Linker Settings */
17 /* Standard linker options */
18 --retain="*(.bootCode)"
19 --retain="*(.startupCode)"
20 --retain="*(.startupData)"
21 --fill_value=0
22 --stack_size=0x2000
23 --heap_size=0x1000
25 -stack 0x2000 /* SOFTWARE STACK SIZE */
26 -heap 0x2000 /* HEAP AREA SIZE */
28 #define DDR0_ALLOCATED_START 0xA0000000
30 #define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
31 #define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
32 #define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
33 #define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
35 #define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
36 #define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
37 #define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
38 #define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
39 #define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
41 #define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
42 #define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
43 #define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
44 #define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
45 #define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
47 #define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
48 #define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
49 #define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
50 #define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
51 #define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
53 #define MCU3_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x04000000
54 #define MCU3_0_EXT_DATA_BASE (MCU3_0_ALLOCATED_START + 0x00100000)
55 #define MCU3_0_R5F_MEM_TEXT_BASE (MCU3_0_ALLOCATED_START + 0x00200000)
56 #define MCU3_0_R5F_MEM_DATA_BASE (MCU3_0_ALLOCATED_START + 0x00300000)
57 #define MCU3_0_DDR_SPACE_BASE (MCU3_0_ALLOCATED_START + 0x00400000)
59 #define MCU3_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x05000000
60 #define MCU3_1_EXT_DATA_BASE (MCU3_1_ALLOCATED_START + 0x00100000)
61 #define MCU3_1_R5F_MEM_TEXT_BASE (MCU3_1_ALLOCATED_START + 0x00200000)
62 #define MCU3_1_R5F_MEM_DATA_BASE (MCU3_1_ALLOCATED_START + 0x00300000)
63 #define MCU3_1_DDR_SPACE_BASE (MCU3_1_ALLOCATED_START + 0x00400000)
65 #define ATCM_START 0x00000000
67 -e __VECS_ENTRY_POINT
69 /*----------------------------------------------------------------------------*/
70 /* Memory Map */
71 MEMORY
72 {
73 /* MCU3_R5F_0 local view */
74 MCU_ATCM (RWX) : origin=ATCM_START length=0x8000
75 MCU3_R5F0_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
77 /* MCU3_R5F_0 SoC view */
78 MCU3_R5F0_ATCM (RWIX) : origin=0x05e00000 length=0x8000
79 MCU3_R5F0_BTCM (RWIX) : origin=0x05e10000 length=0x8000
81 /* MCUSS RAM */
82 OCMRAM_MCU1_0 (RWIX) : origin=0x41c29caa length=0x14cd5
83 OCMRAM_MCU1_1 (RWIX) : origin=0x41c3e97f length=0x14cd5
84 OCMRAM_MCU2_0 (RWIX) : origin=0x41c53654 length=0x14cd5
85 OCMRAM_MCU2_1 (RWIX) : origin=0x41c68329 length=0x14cd5
86 OCMRAM_MCU3_0 (RWIX) : origin=0x41c7cffe length=0x14cd5
87 OCMRAM_MCU3_1 (RWIX) : origin=0x41c91cd3 length=0x14cd5
89 DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
90 MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
91 MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
92 MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
93 MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
94 MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
95 MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
96 MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
97 MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
98 MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
99 MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
100 MCU2_0_IPC_DATA (RWIX) : origin=MCU2_0_ALLOCATED_START length=0x00100000 /* 1MB */
101 MCU2_0_EXT_DATA (RWIX) : origin=MCU2_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
102 MCU2_0_R5F_MEM_TEXT (RWIX) : origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
103 MCU2_0_R5F_MEM_DATA (RWIX) : origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
104 MCU2_0_DDR_SPACE (RWIX) : origin=MCU2_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
105 MCU2_1_IPC_DATA (RWIX) : origin=MCU2_1_ALLOCATED_START length=0x00100000 /* 1MB */
106 MCU2_1_EXT_DATA (RWIX) : origin=MCU2_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
107 MCU2_1_R5F_MEM_TEXT (RWIX) : origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
108 MCU2_1_R5F_MEM_DATA (RWIX) : origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
109 MCU2_1_DDR_SPACE (RWIX) : origin=MCU2_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
110 MCU3_0_IPC_DATA (RWIX) : origin=MCU3_0_ALLOCATED_START length=0x00100000 /* 1MB */
111 MCU3_0_EXT_DATA (RWIX) : origin=MCU3_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
112 MCU3_0_R5F_MEM_TEXT (RWIX) : origin=MCU3_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
113 MCU3_0_R5F_MEM_DATA (RWIX) : origin=MCU3_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
114 MCU3_0_DDR_SPACE (RWIX) : origin=MCU3_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
115 MCU3_1_IPC_DATA (RWIX) : origin=MCU3_1_ALLOCATED_START length=0x00100000 /* 1MB */
116 MCU3_1_EXT_DATA (RWIX) : origin=MCU3_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
117 MCU3_1_R5F_MEM_TEXT (RWIX) : origin=MCU3_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
118 MCU3_1_R5F_MEM_DATA (RWIX) : origin=MCU3_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
119 MCU3_1_DDR_SPACE (RWIX) : origin=MCU3_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
121 SHARED_DDR_SPACE (RWIX) : origin=0xAA000000 length=0x01C00000 /* 28MB */
123 } /* end of MEMORY */
125 /*----------------------------------------------------------------------------*/
126 /* Section Configuration */
128 SECTIONS
129 {
130 .vecs : {
131 *(.vecs)
132 } palign(8) > ATCM_START
133 .vecs : {
134 __VECS_ENTRY_POINT = .;
135 } palign(8) > MCU_ATCM
136 .init_text : {
137 boot.*(.text)
138 *(.text:ti_sysbios_family_arm_MPU_*)
139 *(.text:ti_sysbios_family_arm_v7r_Cache_*)
140 } > MCU_ATCM
141 .text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU_ATCM
142 .bootCode : {} palign(8) > MCU_ATCM
143 .utilsCopyVecsToAtcm : {} palign(8) > MCU_ATCM
144 .startupCode : {} palign(8) > MCU_ATCM
145 .startupData : {} palign(8) > MCU_ATCM, type = NOINIT
146 .text : {} palign(8) > MCU3_0_DDR_SPACE
147 .const : {} palign(8) > MCU3_0_DDR_SPACE
148 .cinit : {} palign(8) > MCU3_0_DDR_SPACE
149 .pinit : {} palign(8) > MCU3_0_DDR_SPACE
150 .bss : {} align(4) > MCU3_0_DDR_SPACE
151 .data : {} palign(128) > MCU3_0_DDR_SPACE
152 .data_buffer: {} palign(128) > MCU3_0_DDR_SPACE
153 .sysmem : {} > MCU3_0_DDR_SPACE
154 .stack : {} align(4) > MCU3_0_DDR_SPACE
155 ipc_data_buffer (NOINIT) : {} palign(128) > MCU3_0_DDR_SPACE
156 .resource_table : {
157 __RESOURCE_TABLE = .;
158 } > MCU3_0_EXT_DATA_BASE
160 .tracebuf : {} > MCU3_0_EXT_DATA
162 } /* end of SECTIONS */
164 /*----------------------------------------------------------------------------*/
165 /* Misc linker settings */
168 /*-------------------------------- END ---------------------------------------*/