[processor-sdk/pdk.git] / packages / ti / drv / ipc / examples / common / j784s4 / linker_r5f_mcu2_0.lds
1 /* Linker Settings */
2 --retain="*(.bootCode)"
3 --retain="*(.startupCode)"
4 --retain="*(.startupData)"
5 --retain="*(.intvecs)"
6 --retain="*(.intc_text)"
7 --retain="*(.rstvectors)"
8 --retain="*(.irqStack)"
9 --retain="*(.fiqStack)"
10 --retain="*(.abortStack)"
11 --retain="*(.undStack)"
12 --retain="*(.svcStack)"
13 --fill_value=0
14 --stack_size=0x2000
15 --heap_size=0x1000
16 --entry_point=_resetvectors /* Default C RTS boot.asm */
18 -stack 0x2000 /* SOFTWARE STACK SIZE */
19 -heap 0x2000 /* HEAP AREA SIZE */
21 /* Stack Sizes for various modes */
22 __IRQ_STACK_SIZE = 0x1000;
23 __FIQ_STACK_SIZE = 0x1000;
24 __ABORT_STACK_SIZE = 0x1000;
25 __UND_STACK_SIZE = 0x1000;
26 __SVC_STACK_SIZE = 0x1000;
28 #define DDR0_ALLOCATED_START 0xA0000000
30 #define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
31 #define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
32 #define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
33 #define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
35 #define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
36 #define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
37 #define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
38 #define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
39 #define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
41 #define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
42 #define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
43 #define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
44 #define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
45 #define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
47 #define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
48 #define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
49 #define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
50 #define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
51 #define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
53 #define MCU3_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x04000000
54 #define MCU3_0_EXT_DATA_BASE (MCU3_0_ALLOCATED_START + 0x00100000)
55 #define MCU3_0_R5F_MEM_TEXT_BASE (MCU3_0_ALLOCATED_START + 0x00200000)
56 #define MCU3_0_R5F_MEM_DATA_BASE (MCU3_0_ALLOCATED_START + 0x00300000)
57 #define MCU3_0_DDR_SPACE_BASE (MCU3_0_ALLOCATED_START + 0x00400000)
59 #define MCU3_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x05000000
60 #define MCU3_1_EXT_DATA_BASE (MCU3_1_ALLOCATED_START + 0x00100000)
61 #define MCU3_1_R5F_MEM_TEXT_BASE (MCU3_1_ALLOCATED_START + 0x00200000)
62 #define MCU3_1_R5F_MEM_DATA_BASE (MCU3_1_ALLOCATED_START + 0x00300000)
63 #define MCU3_1_DDR_SPACE_BASE (MCU3_1_ALLOCATED_START + 0x00400000)
65 #define MCU4_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x06000000
66 #define MCU4_0_EXT_DATA_BASE (MCU4_0_ALLOCATED_START + 0x00100000)
67 #define MCU4_0_R5F_MEM_TEXT_BASE (MCU4_0_ALLOCATED_START + 0x00200000)
68 #define MCU4_0_R5F_MEM_DATA_BASE (MCU4_0_ALLOCATED_START + 0x00300000)
69 #define MCU4_0_DDR_SPACE_BASE (MCU4_0_ALLOCATED_START + 0x00400000)
71 #define MCU4_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x07000000
72 #define MCU4_1_EXT_DATA_BASE (MCU4_1_ALLOCATED_START + 0x00100000)
73 #define MCU4_1_R5F_MEM_TEXT_BASE (MCU4_1_ALLOCATED_START + 0x00200000)
74 #define MCU4_1_R5F_MEM_DATA_BASE (MCU4_1_ALLOCATED_START + 0x00300000)
75 #define MCU4_1_DDR_SPACE_BASE (MCU4_1_ALLOCATED_START + 0x00400000)
77 #define ATCM_START 0x00000000
79 /* Memory Map */
80 MEMORY
81 {
82 /* VECTORS (X) : origin=0x41C7F000 length=0x1000 */
83 /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
84 RESET_VECTORS (X) : origin=0x0 length=0x100
85 /* MCU0_R5F_0 local view */
86 MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
87 MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
89 /* MCU0_R5F_1 SoC view */
90 MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
91 MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
93 /* MCU0 share locations */
94 OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
96 /* J784S4 MSMC3 locations */
97 /* J784S4 Reserved Memory for ARM Trusted Firmware */
98 MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
99 MSMC3 (RWIX) : origin=0x70040000 length=0x3B0000 /* 4MB - 320KB */
100 /* J784S4 Reserved Memory for DMSC Firmware */
101 MSMC3_DMSC_FW (RWIX) : origin=0x703F0000 length=0x10000 /* 64KB */
103 DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
104 MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
105 MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
106 MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
107 MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
108 MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
109 MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
110 MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
111 MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
112 MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
113 MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
114 MCU2_0_IPC_DATA (RWIX) : origin=MCU2_0_ALLOCATED_START length=0x00100000 /* 1MB */
115 MCU2_0_EXT_DATA (RWIX) : origin=MCU2_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
116 MCU2_0_R5F_MEM_TEXT (RWIX) : origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
117 MCU2_0_R5F_MEM_DATA (RWIX) : origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
118 MCU2_0_DDR_SPACE (RWIX) : origin=MCU2_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
119 MCU2_1_IPC_DATA (RWIX) : origin=MCU2_1_ALLOCATED_START length=0x00100000 /* 1MB */
120 MCU2_1_EXT_DATA (RWIX) : origin=MCU2_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
121 MCU2_1_R5F_MEM_TEXT (RWIX) : origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
122 MCU2_1_R5F_MEM_DATA (RWIX) : origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
123 MCU2_1_DDR_SPACE (RWIX) : origin=MCU2_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
124 MCU3_0_IPC_DATA (RWIX) : origin=MCU3_0_ALLOCATED_START length=0x00100000 /* 1MB */
125 MCU3_0_EXT_DATA (RWIX) : origin=MCU3_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
126 MCU3_0_R5F_MEM_TEXT (RWIX) : origin=MCU3_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
127 MCU3_0_R5F_MEM_DATA (RWIX) : origin=MCU3_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
128 MCU3_0_DDR_SPACE (RWIX) : origin=MCU3_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
129 MCU3_1_IPC_DATA (RWIX) : origin=MCU3_1_ALLOCATED_START length=0x00100000 /* 1MB */
130 MCU3_1_EXT_DATA (RWIX) : origin=MCU3_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
131 MCU3_1_R5F_MEM_TEXT (RWIX) : origin=MCU3_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
132 MCU3_1_R5F_MEM_DATA (RWIX) : origin=MCU3_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
133 MCU3_1_DDR_SPACE (RWIX) : origin=MCU3_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
134 MCU4_0_IPC_DATA (RWIX) : origin=MCU4_0_ALLOCATED_START length=0x00100000 /* 1MB */
135 MCU4_0_EXT_DATA (RWIX) : origin=MCU4_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
136 MCU4_0_R5F_MEM_TEXT (RWIX) : origin=MCU4_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
137 MCU4_0_R5F_MEM_DATA (RWIX) : origin=MCU4_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
138 MCU4_0_DDR_SPACE (RWIX) : origin=MCU4_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
139 MCU4_1_IPC_DATA (RWIX) : origin=MCU4_1_ALLOCATED_START length=0x00100000 /* 1MB */
140 MCU4_1_EXT_DATA (RWIX) : origin=MCU4_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
141 MCU4_1_R5F_MEM_TEXT (RWIX) : origin=MCU4_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
142 MCU4_1_R5F_MEM_DATA (RWIX) : origin=MCU4_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
143 MCU4_1_DDR_SPACE (RWIX) : origin=MCU4_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
144 }
146 /* Section Configuration */
147 SECTIONS
148 {
149 /* 'intvecs' and 'intc_text' sections shall be placed within */
150 /* a range of +\- 16 MB */
151 /* .intvecs : {} palign(8) > VECTORS
152 .intc_text : {} palign(8) > VECTORS */
153 .rstvectors : {} palign(8) > RESET_VECTORS
154 .bootCode : {} palign(8) > MCU0_R5F_TCMA
155 .startupCode : {} palign(8) > MCU0_R5F_TCMA
156 .startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
157 .text : {} palign(8) > MCU2_0_DDR_SPACE
158 .const : {} palign(8) > MCU2_0_DDR_SPACE
159 .rodata : {} palign(8) > MCU2_0_DDR_SPACE
160 .cinit : {} palign(8) > MCU2_0_DDR_SPACE
161 .pinit : {} palign(8) > MCU2_0_DDR_SPACE
162 .bss : {} align(4) > MCU2_0_DDR_SPACE
163 .far : {} align(4) > MCU2_0_DDR_SPACE
164 .data : {} palign(128) > MCU2_0_DDR_SPACE
165 .boardcfg_data : {} palign(128) > MCU2_0_DDR_SPACE
166 .sysmem : {} > MCU2_0_DDR_SPACE
167 .data_buffer : {} palign(128) > MCU2_0_DDR_SPACE
169 /* USB or any other LLD buffer for benchmarking */
170 .benchmark_buffer (NOLOAD) {} ALIGN (8) > MCU2_0_DDR_SPACE
171 ipc_data_buffer (NOINIT) : {} palign(128) > MCU2_0_DDR_SPACE
172 .resource_table : {
173 __RESOURCE_TABLE = .;
174 } > MCU2_0_EXT_DATA_BASE
176 .tracebuf : {} align(1024) > MCU2_0_EXT_DATA
178 .stack : {} align(4) > MCU2_0_DDR_SPACE (HIGH)
179 .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU2_0_DDR_SPACE (HIGH)
180 RUN_START(__IRQ_STACK_START)
181 RUN_END(__IRQ_STACK_END)
182 .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU2_0_DDR_SPACE (HIGH)
183 RUN_START(__FIQ_STACK_START)
184 RUN_END(__FIQ_STACK_END)
185 .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU2_0_DDR_SPACE (HIGH)
186 RUN_START(__ABORT_STACK_START)
187 RUN_END(__ABORT_STACK_END)
188 .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU2_0_DDR_SPACE (HIGH)
189 RUN_START(__UND_STACK_START)
190 RUN_END(__UND_STACK_END)
191 .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MCU2_0_DDR_SPACE (HIGH)
192 RUN_START(__SVC_STACK_START)
193 RUN_END(__SVC_STACK_END)
194 }