5315d6ee717f337808e8364a0260d342b7f470f9
1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
34 /**
35 * \file main_tirtos.c
36 *
37 * \brief Main file for TI-RTOS build
38 */
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 #include <stdio.h>
45 #include <stdint.h>
47 /* XDCtools Header files */
48 #include <xdc/std.h>
49 #include <xdc/runtime/Error.h>
50 #include <xdc/runtime/System.h>
51 /* BIOS Header files */
52 #include <ti/sysbios/BIOS.h>
53 #include <ti/sysbios/knl/Task.h>
55 #include "ipc_utils.h"
56 #if defined (__C7100__)
57 #include <ti/sysbios/family/c7x/Hwi.h>
58 #include <ti/sysbios/family/c7x/Mmu.h>
59 #include <ti/csl/soc.h>
60 #include <ti/csl/csl_clec.h>
61 #include <ti/csl/arch/csl_arch.h>
62 #include <ti/sysbios/family/c7x/Mmu.h>
63 #endif
65 #include <ti/drv/sciclient/sciclient.h>
66 #include <ti/board/board.h>
68 /* This needs to be enabled only for negative test cases */
69 #ifdef IPC_NEGATIVE_TEST
70 #include <ti/drv/ipc/examples/ex05_bios_multicore_echo_negative_test/ipc_neg_setup.h>
71 #endif
72 /* ========================================================================== */
73 /* Macros & Typedefs */
74 /* ========================================================================== */
76 /* Test application stack size */
77 #define APP_TSK_STACK_MAIN (32U * 1024U)
79 /* ========================================================================== */
80 /* Structure Declarations */
81 /* ========================================================================== */
83 /* None */
85 /* ========================================================================== */
86 /* Function Declarations */
87 /* ========================================================================== */
89 static Void taskFxn(UArg a0, UArg a1);
90 extern int32_t Ipc_echo_test(void);
92 /* ========================================================================== */
93 /* Global Variables */
94 /* ========================================================================== */
96 /* Test application stack */
97 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN]
98 __attribute__ ((aligned(8192)));
100 /* ========================================================================== */
101 /* Function Definitions */
102 /* ========================================================================== */
105 void ipc_initSciclient()
106 {
107 Sciclient_ConfigPrms_t config;
109 /* Now reinitialize it as default parameter */
110 Sciclient_configPrmsInit(&config);
112 Sciclient_init(&config);
114 }
116 #if !defined(A72_LINUX_OS)
117 void ipc_boardInit()
118 {
119 Board_initCfg boardCfg;
121 boardCfg = BOARD_INIT_PINMUX_CONFIG |
122 BOARD_INIT_UART_STDIO;
123 Board_init(boardCfg);
125 }
126 #endif
128 #if defined (__C7100__)
129 /* To set C71 timer interrupts */
130 void ipc_timerInterruptInit(void)
131 {
132 CSL_ClecEventConfig cfgClec;
133 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
135 uint32_t input = 1248; /* Used for Timer Interrupt */
136 uint32_t corepackEvent = 14;
138 /* Configure CLEC */
139 cfgClec.secureClaimEnable = FALSE;
140 cfgClec.evtSendEnable = TRUE;
141 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
142 cfgClec.extEvtNum = 0;
143 cfgClec.c7xEvtNum = corepackEvent;
144 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
145 CSL_clecConfigEventLevel(clecBaseAddr, input, 0); /* configure interrupt as pulse */
146 Hwi_setPriority(corepackEvent, 1);
147 }
148 #endif
150 #if defined (_TMS320C6X)
151 /* To set C66 timer interrupts */
152 void ipc_timerInterruptInit(void)
153 {
154 int32_t status = 0;
156 struct tisci_msg_rm_irq_set_req rmIrqReq;
157 struct tisci_msg_rm_irq_set_resp rmIrqResp;
159 /* On C66x builds we define OS timer tick in the configuration file to
160 * trigger event #21 for C66x_1 and #20 for C66x_2. Map
161 * DMTimer 0 interrupt to these events through DMSC RM API.
162 */
163 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
164 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
165 rmIrqReq.src_id = TISCI_DEV_TIMER0;
166 rmIrqReq.src_index = 0U;
167 #if defined(BUILD_C66X_1)
168 rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
169 rmIrqReq.dst_host_irq = 21U;
170 #elif defined(BUILD_C66X_2)
171 rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
172 rmIrqReq.dst_host_irq = 20U;
173 #endif
174 /* Unused params */
175 rmIrqReq.global_event = 0U;
176 rmIrqReq.ia_id = 0U;
177 rmIrqReq.vint = 0U;
178 rmIrqReq.vint_status_bit_index = 0U;
179 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
181 status = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
182 if(status != 0)
183 {
184 System_printf(" ERROR: failed to setup timer interrupt !!!\n" );
185 }
187 return;
188 }
189 #endif
191 int main(void)
192 {
193 Task_Handle task;
194 Error_Block eb;
195 Task_Params taskParams;
197 /* It must be called before board init */
198 ipc_initSciclient();
200 #if !defined(A72_LINUX_OS)
201 ipc_boardInit();
202 #endif
204 #if defined (__C7100__) || defined (_TMS320C6X)
205 ipc_timerInterruptInit();
206 #endif
208 Error_init(&eb);
210 /* Initialize the task params */
211 Task_Params_init(&taskParams);
212 /* Set the task priority higher than the default priority (1) */
213 taskParams.priority = 2;
214 taskParams.stack = gAppTskStackMain;
215 taskParams.stackSize = sizeof (gAppTskStackMain);
217 task = Task_create(taskFxn, &taskParams, &eb);
218 if(NULL == task)
219 {
220 BIOS_exit(0);
221 }
222 BIOS_start(); /* does not return */
224 return(0);
225 }
227 static Void taskFxn(UArg a0, UArg a1)
228 {
229 #ifdef IPC_NEGATIVE_TEST
230 Ipc_echo_neg_test();
231 #else
232 Ipc_echo_test();
233 #endif
234 }
236 #if defined(__C7100__)
237 /* The C7x CLEC should be programmed to allow config/re config either in secure
238 * OR non secure mode. This function configures all inputs to given level
239 *
240 * Instance is hard-coded for J721e only
241 *
242 */
243 void IpcCfgClecAccessCtrl (Bool onlyInSecure)
244 {
245 CSL_ClecEventConfig cfgClec;
246 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*) CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
247 uint32_t i, maxInputs = 2048U;
249 cfgClec.secureClaimEnable = onlyInSecure;
250 cfgClec.evtSendEnable = FALSE;
251 cfgClec.rtMap = CSL_CLEC_RTMAP_DISABLE;
252 cfgClec.extEvtNum = 0U;
253 cfgClec.c7xEvtNum = 0U;
254 for(i = 0U; i < maxInputs; i++)
255 {
256 CSL_clecConfigEvent(clecBaseAddr, i, &cfgClec);
257 }
258 }
260 static void IpcInitMmu(Bool isSecure)
261 {
262 Mmu_MapAttrs attrs;
264 Mmu_initMapAttrs(&attrs);
265 attrs.attrIndx = Mmu_AttrIndx_MAIR0;
267 if(TRUE == isSecure)
268 {
269 attrs.ns = 0;
270 }
271 else
272 {
273 attrs.ns = 1;
274 }
276 /* Register region */
277 (void)Mmu_map(0x00000000U, 0x00000000U, 0x20000000U, &attrs, isSecure);
278 (void)Mmu_map(0x20000000U, 0x20000000U, 0x20000000U, &attrs, isSecure);
279 (void)Mmu_map(0x40000000U, 0x40000000U, 0x20000000U, &attrs, isSecure);
280 (void)Mmu_map(0x60000000U, 0x60000000U, 0x10000000U, &attrs, isSecure);
281 (void)Mmu_map(0x78000000U, 0x78000000U, 0x08000000U, &attrs, isSecure); /* CLEC */
283 attrs.attrIndx = Mmu_AttrIndx_MAIR7;
284 (void)Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, isSecure); /* DDR */
285 (void)Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, isSecure); /* DDR */
286 (void)Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, isSecure); /* MSMC - 8MB */
287 (void)Mmu_map(0x41C00000U, 0x41C00000U, 0x00080000U, &attrs, isSecure); /* OCMC - 512KB */
289 /*
290 * DDR range 0xA0000000 - 0xAA000000 : Used as RAM by multiple
291 * remote cores, no need to mmp_map this range.
292 * IPC VRing Buffer - uncached
293 */
294 attrs.attrIndx = Mmu_AttrIndx_MAIR4;
295 (void)Mmu_map(0xAA000000U, 0xAA000000U, 0x02000000U, &attrs, isSecure);
296 (void)Mmu_map(0xA8000000U, 0xA8000000U, 0x00100000U, &attrs, isSecure);
298 return;
299 }
301 void InitMmu(void)
302 {
303 IpcInitMmu(FALSE);
304 IpcInitMmu(TRUE);
306 /* Setup CLEC access/configure in non-secure mode */
307 IpcCfgClecAccessCtrl(FALSE);
308 }
309 #endif
311 #if defined(BUILD_MPU)
312 extern void Osal_initMmuDefault(void);
313 void InitMmu(void)
314 {
315 Osal_initMmuDefault();
316 }
317 #endif