1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
34 /**
35 * \file ipc_soc.c
36 *
37 * \brief File containing the IPC driver - soc specific implementation.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
44 #include <ti/drv/ipc/ipc.h>
45 #include <ti/drv/ipc/soc/ipc_soc.h>
46 #include <ti/drv/ipc/src/ipc_priv.h>
47 #include <ti/drv/ipc/src/ipc_mailbox.h>
49 #include <ti/csl/csl_intr_router.h>
50 #include <ti/csl/csl_clec.h>
51 #include <ti/drv/sciclient/sciclient.h>
52 //#include <ti/drv/sciclient/soc/V1/sciclient_fmwMsgParams.h>
54 #define NAVSS_INTRTR_INPUT_MAILBOX0_USER0 (436U)
55 #define NAVSS_INTRTR_INPUT_MAILBOX1_USER0 (432U)
56 #define NAVSS_INTRTR_INPUT_MAILBOX2_USER0 (428U)
57 #define NAVSS_INTRTR_INPUT_MAILBOX3_USER0 (424U)
58 #define NAVSS_INTRTR_INPUT_MAILBOX4_USER0 (420U)
59 #define NAVSS_INTRTR_INPUT_MAILBOX5_USER0 (416U)
60 #define NAVSS_INTRTR_INPUT_MAILBOX6_USER0 (412U)
61 #define NAVSS_INTRTR_INPUT_MAILBOX7_USER0 (408U)
62 #define NAVSS_INTRTR_INPUT_MAILBOX8_USER0 (404U)
63 #define NAVSS_INTRTR_INPUT_MAILBOX9_USER0 (400U)
64 #define NAVSS_INTRTR_INPUT_MAILBOX10_USER0 (396U)
65 #define NAVSS_INTRTR_INPUT_MAILBOX11_USER0 (392U)
67 /**
68 * \brief Main NavSS512 - Mailbox input line
69 */
70 uint32_t g_Navss512MbInput[IPC_MAILBOX_CLUSTER_CNT] =
71 {
72 NAVSS_INTRTR_INPUT_MAILBOX0_USER0,
73 NAVSS_INTRTR_INPUT_MAILBOX1_USER0,
74 NAVSS_INTRTR_INPUT_MAILBOX2_USER0,
75 NAVSS_INTRTR_INPUT_MAILBOX3_USER0,
76 NAVSS_INTRTR_INPUT_MAILBOX4_USER0,
77 NAVSS_INTRTR_INPUT_MAILBOX5_USER0,
78 NAVSS_INTRTR_INPUT_MAILBOX6_USER0,
79 NAVSS_INTRTR_INPUT_MAILBOX7_USER0,
80 NAVSS_INTRTR_INPUT_MAILBOX8_USER0,
81 NAVSS_INTRTR_INPUT_MAILBOX9_USER0,
82 NAVSS_INTRTR_INPUT_MAILBOX10_USER0,
83 NAVSS_INTRTR_INPUT_MAILBOX11_USER0
84 };
86 /**
87 * \brief Processor IDs to name mapping for all processor in Jacinto7
88 */
89 static Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS] =
90 {
91 {IPC_MPU1_0, "mpu1_0"}, /**< ARM A72 - VM0 */
92 {IPC_MCU1_0, "mcu1_0"}, /**< ARM MCU R5F - core0 */
93 {IPC_MCU1_1, "mcu1_1"}, /**< ARM MCU R5F - core1 */
94 {IPC_MCU2_0, "mcu2_0"}, /**< ARM Main R5F - core0 */
95 {IPC_MCU2_1, "mcu2_1"}, /**< ARM Main R5F - core1 */
96 {IPC_MCU3_0, "mcu3_0"}, /**< ARM Main R5F - core2 */
97 {IPC_MCU3_1, "mcu3_1"}, /**< ARM Main R5F - core3 */
98 {IPC_C66X_1, "C66X_1"}, /**< DSP C66x - core0 */
99 {IPC_C66X_2, "C66X_2"}, /**< DSP C66x - core1 */
100 {IPC_C7X_1, "C7X_1"}, /**< DSP C7x - core0 */
101 {IPC_MPU1_1, "mpu1_1"} /**< ARM A72 - VM1 */
102 };
104 /* Mailbox Cluster Base Address */
105 static uint32_t g_IPC_Mailbox_BaseAddr[IPC_MAILBOX_CLUSTER_CNT] =
106 {
107 CSL_NAVSS_MAIN_MAILBOX_REGS_0_BASE, /* Mailbox - cluster0 */
108 CSL_NAVSS_MAIN_MAILBOX_REGS_1_BASE, /* Mailbox - cluster1 */
109 CSL_NAVSS_MAIN_MAILBOX_REGS_2_BASE, /* Mailbox - cluster2 */
110 CSL_NAVSS_MAIN_MAILBOX_REGS_3_BASE, /* Mailbox - cluster3 */
111 CSL_NAVSS_MAIN_MAILBOX_REGS_4_BASE, /* Mailbox - cluster4 */
112 CSL_NAVSS_MAIN_MAILBOX_REGS_5_BASE, /* Mailbox - cluster5 */
113 CSL_NAVSS_MAIN_MAILBOX_REGS_6_BASE, /* Mailbox - cluster6 */
114 CSL_NAVSS_MAIN_MAILBOX_REGS_7_BASE, /* Mailbox - cluster7 */
115 CSL_NAVSS_MAIN_MAILBOX_REGS_8_BASE, /* Mailbox - cluster8 */
116 CSL_NAVSS_MAIN_MAILBOX_REGS_9_BASE, /* Mailbox - cluster9 */
117 CSL_NAVSS_MAIN_MAILBOX_REGS_10_BASE, /* Mailbox - cluster10 */
118 CSL_NAVSS_MAIN_MAILBOX_REGS_11_BASE, /* Mailbox - cluster11 */
119 };
121 static Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS] =
122 {
123 /* Host Processor - A72-vm0 */
124 {
125 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0xFFU} }, /* Self - A72-vm0 */
126 { { 0U, 0U, 0U}, { 0U, 0U, 1U} }, /* mcu-r5f0 */
127 { { 0U, 0U, 2U}, { 0U, 0U, 3U} }, /* mcu-r5f1 */
128 { { 1U, 0U, 0U}, { 1U, 0U, 1U} }, /* main-r5f0 */
129 { { 1U, 0U, 2U}, { 1U, 0U, 3U} }, /* main-r5f1 */
130 { { 2U, 0U, 0U}, { 2U, 0U, 1U} }, /* main-r5f2 */
131 { { 2U, 0U, 2U}, { 2U, 0U, 3U} }, /* main-r5f3 */
132 { { 3U, 0U, 0U}, { 3U, 0U, 1U} }, /* C66x-0 */
133 { { 3U, 0U, 2U}, { 3U, 0U, 3U} }, /* C66x-1 */
134 { { 4U, 0U, 0U}, { 4U, 0U, 1U} }, /* C7x-1 */
135 { { 0U, 0U, 10U}, { 0U, 0U, 11U} } /* A72-vm1 */
136 },
137 /* Host Processor - mcu1_0 */
138 {
139 { { 0U, 1U, 1U }, { 0U, 1U, 0U} }, /* A72-vm0 */
140 { { 0xFFU, 0xFFU, 0U }, { 0xFFU, 0xFFU, 0U} }, /* Self - mcu-r5f0 */
141 { { 0U, 1U, 4U }, { 0U, 1U, 5U} }, /* mcu-r5f1 */
142 { { 7U, 0U, 0U }, { 5U, 0xFFU, 2U} }, /* main-r5f0 */
143 { { 7U, 0U, 1U }, { 5U, 0xFFU, 10U} }, /* main-r5f1 */
144 { { 7U, 0U, 2U }, { 6U, 0xFFU, 2U} }, /* main-r5f2 */
145 { { 7U, 0U, 3U }, { 6U, 0xFFU, 10U} }, /* main-r5f3 */
146 { { 7U, 1U, 4U }, { 8U, 0xFFU, 4U} }, /* C66x-0 */
147 { { 7U, 1U, 5U }, { 8U, 0xFFU, 12U} }, /* C66x-1 */
148 { { 7U, 1U, 6U }, { 9U, 0xFFU, 4U} }, /* C7x-1 */
149 { { 0U, 1U, 7U }, { 0U, 1U, 6U} } /* A72-vm1 */
150 },
151 /* Host Processor - mcu1_1 */
152 {
153 { { 0U, 2U, 3U }, { 0U, 2U, 2U} }, /* A72-vm0 */
154 { { 0U, 2U, 5U }, { 0U, 2U, 4U} }, /* mcu-r5f0 */
155 { { 0xFFU, 0xFFU, 0U }, { 0xFFU, 0xFFU, 0U} }, /* Self - mcu-r5f1 */
156 { { 7U, 2U, 8U }, { 5U, 0xFFU, 3U} }, /* main-r5f0 */
157 { { 7U, 2U, 9U }, { 5U, 0xFFU, 11U} }, /* main-r5f1 */
158 { { 7U, 2U, 10U }, { 6U, 0xFFU, 3U} }, /* main-r5f2 */
159 { { 7U, 2U, 11U }, { 6U, 0xFFU, 11U} }, /* main-r5f3 */
160 { { 7U, 3U, 12U }, { 8U, 0xFFU, 5U} }, /* C66x-0 */
161 { { 7U, 3U, 13U }, { 8U, 0xFFU, 13U} }, /* C66x-1 */
162 { { 7U, 3U, 14U }, { 9U, 0xFFU, 5U} }, /* C7x-1 */
163 { { 0U, 2U, 9U }, { 0U, 2U, 8U} } /* A72-vm1 */
164 },
165 /* Host Processor - mcu2_0 */
166 {
167 { { 1U, 1U, 1U}, { 1U, 1U, 0U} }, /* A72-vm0 */
168 { { 5U, 0U, 2U}, { 7U, 0xFFU, 0U} }, /* mcu-r5f0 */
169 { { 5U, 0U, 3U}, { 7U, 0xFFU, 8U} }, /* mcu-r5f1 */
170 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0U} }, /* Self - main-r5f0 */
171 { { 1U, 1U, 4U}, { 1U, 1U, 5U} }, /* main-r5f1 */
172 { { 5U, 0U, 0U}, { 6U, 0xFFU, 0U} }, /* main-r5f2 */
173 { { 5U, 0U, 1U}, { 6U, 0xFFU, 8U} }, /* main-r5f3 */
174 { { 5U, 1U, 4U}, { 8U, 0xFFU, 0U} }, /* C66x-0 */
175 { { 5U, 1U, 5U}, { 8U, 0xFFU, 8U} }, /* C66x-1 */
176 { { 5U, 1U, 6U}, { 9U, 0xFFU, 0U} }, /* C7x-1 */
177 { { 1U, 1U, 7U}, { 1U, 1U, 6U} } /* A72-vm1 */
178 },
179 /* Host Processor - mcu2_1 */
180 {
181 { { 1U, 2U, 3U }, { 1U, 2U, 2U} }, /* A72-vm0 */
182 { { 5U, 2U, 10U }, { 7U, 0xFFU, 1U} }, /* mcu-r5f0 */
183 { { 5U, 2U, 11U }, { 7U, 0xFFU, 9U} }, /* mcu-r5f1 */
184 { { 1U, 2U, 5U }, { 1U, 2U, 4U} }, /* main-r5f0 */
185 { { 0xFFU, 0xFFU, 0U }, { 0xFFU, 0xFFU, 0U} }, /* Self - main-r5f1 */
186 { { 5U, 2U, 8U }, { 6U, 0xFFU, 1U} }, /* main-r5f2 */
187 { { 5U, 2U, 9U }, { 6U, 0xFFU, 9U} }, /* main-r5f3 */
188 { { 5U, 3U, 12U }, { 8U, 0xFFU, 1U} }, /* C66x-0 */
189 { { 5U, 3U, 13U }, { 8U, 0xFFU, 9U} }, /* C66x-1 */
190 { { 5U, 3U, 14U }, { 9U, 0xFFU, 1U} }, /* C7x-1 */
191 { { 0U, 2U, 9U }, { 0U, 2U, 8U} } /* A72-vm1 */
192 },
193 /* Host Processor - mcu3_0 */
194 {
195 { { 2U, 1U, 1U }, { 2U, 1U, 0U} }, /* A72-vm0 */
196 { { 6U, 0U, 2U }, { 7U, 0xFFU, 2U} }, /* mcu-r5f0 */
197 { { 6U, 0U, 3U }, { 7U, 0xFFU, 10U} }, /* mcu-r5f1 */
198 { { 6U, 0U, 0U }, { 5U, 0xFFU, 0U} }, /* main-r5f0 */
199 { { 6U, 0U, 1U }, { 5U, 0xFFU, 8U} }, /* main-r5f1 */
200 { { 0xFFU, 0xFFU, 0U }, { 0xFFU, 0xFFU, 0U} }, /* Self - main-r5f2 */
201 { { 2U, 1U, 4U }, { 2U, 1U, 5U} }, /* main-r5f3 */
202 { { 6U, 1U, 4U }, { 8U, 0xFFU, 2U} }, /* C66x-0 */
203 { { 6U, 1U, 5U }, { 8U, 0xFFU, 10U} }, /* C66x-1 */
204 { { 6U, 1U, 6U }, { 9U, 0xFFU, 2U} }, /* C7x-1 */
205 { { 2U, 1U, 7U }, { 2U, 1U, 6U} } /* A72-vm1 */
206 },
207 /* Host Processor - mcu3_1 */
208 {
209 { { 2U, 2U, 3U }, { 2U, 2U, 2U} }, /* A72-vm0 */
210 { { 6U, 2U, 10U }, { 7U, 0xFFU, 3U} }, /* mcu-r5f0 */
211 { { 6U, 2U, 11U }, { 7U, 0xFFU, 11U} }, /* mcu-r5f1 */
212 { { 6U, 2U, 8U }, { 5U, 0xFFU, 1U} }, /* main-r5f0 */
213 { { 6U, 2U, 9U }, { 5U, 0xFFU, 9U} }, /* main-r5f1 */
214 { { 2U, 2U, 5U }, { 2U, 2U, 4U} }, /* main-r5f2 */
215 { { 0xFFU, 0xFFU, 0U }, { 0xFFU, 0xFFU, 0U} }, /* Self - main-r5f3 */
216 { { 6U, 3U, 12U }, { 8U, 0xFFU, 3U} }, /* C66x-0 */
217 { { 6U, 3U, 13U }, { 8U, 0xFFU, 11U} }, /* C66x-1 */
218 { { 6U, 3U, 14U }, { 9U, 0xFFU, 3U} }, /* C7x-1 */
219 { { 2U, 2U, 9U }, { 2U, 2U, 8U} } /* A72-vm1 */
220 },
221 /* Host Processor - c66xdsp_1 */
222 {
223 { { 3U, 1U, 1U}, { 3U, 1U, 0U} }, /* A72-vm0 */
224 { { 8U, 1U, 4U}, { 7U, 0xFFU, 4U} }, /* mcu-r5f0 */
225 { { 8U, 1U, 5U}, { 7U, 0xFFU, 12U} }, /* mcu-r5f1 */
226 { { 8U, 0U, 0U}, { 5U, 0xFFU, 4U} }, /* main-r5f0 */
227 { { 8U, 0U, 1U}, { 5U, 0xFFU, 12U} }, /* main-r5f1 */
228 { { 8U, 0U, 2U}, { 6U, 0xFFU, 4U} }, /* main-r5f2 */
229 { { 8U, 0U, 3U}, { 6U, 0xFFU, 12U} }, /* main-r5f3 */
230 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0U} }, /* Self - C66x-0 */
231 { { 3U, 1U, 4U}, { 3U, 1U, 5U} }, /* C66x-1 */
232 { { 8U, 1U, 6U}, { 9U, 0xFFU, 6U} }, /* C7x-1 */
233 { { 3U, 1U, 7U}, { 3U, 1U, 6U} } /* A72-vm1 */
234 },
235 /* Host Processor - c66xdsp_2 */
236 {
237 { { 3U, 2U, 3U}, { 3U, 2U, 2U} }, /* A72-vm0 */
238 { { 8U, 3U, 12U}, { 7U, 0xFFU, 5U} }, /* mcu-r5f0 */
239 { { 8U, 3U, 13U}, { 7U, 0xFFU, 13U} }, /* mcu-r5f1 */
240 { { 8U, 2U, 8U}, { 5U, 0xFFU, 5U} }, /* main-r5f0 */
241 { { 8U, 2U, 9U}, { 5U, 0xFFU, 13U} }, /* main-r5f1 */
242 { { 8U, 2U, 10U}, { 6U, 0xFFU, 5U} }, /* main-r5f2 */
243 { { 8U, 2U, 11U}, { 6U, 0xFFU, 13U} }, /* main-r5f3 */
244 { { 3U, 2U, 5U}, { 3U, 2U, 4U} }, /* C66x-0 */
245 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0U} }, /* Self - C66x-1 */
246 { { 8U, 3U, 14U}, { 9U, 0xFFU, 7U} }, /* C7x-1 */
247 { { 3U, 2U, 9U}, { 3U, 2U, 8U} } /* A72-vm1 */
248 },
249 /* Host Processor - c7x_1 */
250 {
251 { { 4U, 1U, 1U}, { 4U, 1U, 0U} }, /* A72-vm0 */
252 { { 9U, 1U, 4U}, { 7U, 0xFFU, 6U} }, /* mcu-r5f0 */
253 { { 9U, 1U, 5U}, { 7U, 0xFFU, 14U} }, /* mcu-r5f1 */
254 { { 9U, 0U, 0U}, { 5U, 0xFFU, 6U} }, /* main-r5f0 */
255 { { 9U, 0U, 1U}, { 5U, 0xFFU, 14U} }, /* main-r5f1 */
256 { { 9U, 0U, 2U}, { 6U, 0xFFU, 6U} }, /* main-r5f2 */
257 { { 9U, 0U, 3U}, { 6U, 0xFFU, 14U} }, /* main-r5f3 */
258 { { 9U, 1U, 6U}, { 8U, 0xFFU, 6U} }, /* C66x-0 */
259 { { 9U, 1U, 7U}, { 8U, 0xFFU, 14U} }, /* C66x-1 */
260 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0U} }, /* Self - C7x-1 */
261 { { 4U, 1U, 7U}, { 4U, 1U, 6U} } /* A72-vm1 */
262 },
263 /* Host Processor - A72-vm1 */
264 {
265 { { 0U, 3U, 11U}, { 0U, 3U, 10U} }, /* A72-vm0 */
266 { { 3U, 3U, 6U}, { 3U, 3U, 7U} }, /* C66x-0 */
267 { { 3U, 3U, 8U}, { 3U, 3U, 9U} }, /* C66x-1 */
268 { { 1U, 3U, 6U}, { 1U, 3U, 7U} }, /* main-r5f0 */
269 { { 1U, 3U, 8U}, { 1U, 3U, 9U} }, /* main-r5f1 */
270 { { 2U, 3U, 6U}, { 2U, 3U, 7U} }, /* main-r5f2 */
271 { { 2U, 3U, 8U}, { 2U, 3U, 9U} }, /* main-r5f3 */
272 { { 0U, 3U, 6U}, { 0U, 3U, 7U} }, /* mcu-r5f0 */
273 { { 0U, 3U, 8U}, { 0U, 3U, 9U} }, /* mcu-r5f1 */
274 { { 4U, 3U, 6U}, { 4U, 3U, 7U} }, /* C7x-1 */
275 { { 0xFFU, 0xFFU, 0U}, { 0xFFU, 0xFFU, 0U} } /* Self - A72-vm1 */
276 }
277 };
279 uint32_t Ipc_getNavss512MailboxInputIntr(uint32_t clusterId, uint32_t userId);
280 int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt);
283 int32_t Ipc_getMailboxInfoTx(uint32_t selfId, uint32_t remoteId,
284 uint32_t *clusterId, uint32_t *userId, uint32_t *queueId)
285 {
286 int32_t retVal = -1;
288 if( (selfId < IPC_MAX_PROCS) &&
289 (remoteId < IPC_MAX_PROCS))
290 {
291 Ipc_MailboxInfo *pMailboxInfo = &g_IPC_MailboxInfo[selfId][remoteId];
293 *clusterId = pMailboxInfo->tx.cluster;
294 *userId = pMailboxInfo->tx.user;
295 *queueId = pMailboxInfo->tx.fifo;
296 retVal = 0;
297 }
299 return retVal;
300 }
302 int32_t Ipc_getMailboxInfoRx(uint32_t selfId, uint32_t remoteId,
303 uint32_t *clusterId, uint32_t *userId, uint32_t *queueId)
304 {
305 int32_t retVal = -1;
307 if( (selfId < IPC_MAX_PROCS) &&
308 (remoteId < IPC_MAX_PROCS))
309 {
310 Ipc_MailboxInfo *pMailboxInfo = &g_IPC_MailboxInfo[selfId][remoteId];
312 *clusterId = pMailboxInfo->rx.cluster;
313 *userId = pMailboxInfo->rx.user;
314 *queueId = pMailboxInfo->rx.fifo;
315 retVal = 0;
316 }
318 return retVal;
320 }
322 uint32_t Ipc_getMailboxBaseAddr(uint32_t custerId)
323 {
324 uint32_t baseAddr = 0x00000000U;
326 if( custerId < IPC_MAX_PROCS)
327 {
328 baseAddr = g_IPC_Mailbox_BaseAddr[custerId];
329 }
331 return baseAddr;
332 }
334 uint32_t Ipc_getNavss512MailboxInputIntr(uint32_t clusterId, uint32_t userId)
335 {
336 uint32_t mailboxIntrNum = 0U;
338 if( (clusterId != MAILBOX_CLUSTER_INVALID) &&
339 (clusterId < IPC_MAILBOX_CLUSTER_CNT) &&
340 (userId != MAILBOX_USER_INVALID) &&
341 (userId < IPC_MAILBOX_USER_CNT))
342 {
343 mailboxIntrNum = g_Navss512MbInput[clusterId] + userId;
344 }
345 return mailboxIntrNum;
346 }
348 int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
349 {
350 int32_t retVal = IPC_SOK;
351 uint32_t outIntrBaseNum = 0;
352 uint32_t vimEventBaseNum = 0;
354 switch(selfId)
355 {
356 case IPC_MPU1_0:
357 outIntrBaseNum = NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET;
358 vimEventBaseNum = MPU1_0_MBINTR_OFFSET;
359 break;
360 case IPC_MCU1_0:
361 outIntrBaseNum = NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET;
362 vimEventBaseNum = MCU1R5F0_MBINTR_OFFSET;
363 break;
364 case IPC_MCU1_1:
365 outIntrBaseNum = NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET;
366 vimEventBaseNum = MCU1R5F1_MBINTR_OFFSET;
367 break;
368 case IPC_MCU2_0:
369 outIntrBaseNum = NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET;
370 vimEventBaseNum = MCU2R5F0_MBINTR_OFFSET;
371 break;
372 case IPC_MCU2_1:
373 outIntrBaseNum = NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET;
374 vimEventBaseNum = MCU2R5F1_MBINTR_OFFSET;
375 break;
376 case IPC_MCU3_0:
377 outIntrBaseNum = NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET;
378 vimEventBaseNum = MCU3R5F0_MBINTR_OFFSET;
379 break;
380 case IPC_MCU3_1:
381 outIntrBaseNum = NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET;
382 vimEventBaseNum = MCU3R5F1_MBINTR_OFFSET;
383 break;
384 case IPC_C66X_1:
385 outIntrBaseNum = NAVSS512_C66X1_INPUT_MAILBOX_OFFSET;
386 vimEventBaseNum = C66X1_MBINTR_OFFSET;
387 break;
388 case IPC_C66X_2:
389 outIntrBaseNum = NAVSS512_C66X2_INPUT_MAILBOX_OFFSET;
390 vimEventBaseNum = C66X2_MBINTR_OFFSET;
391 break;
392 case IPC_C7X_1:
393 outIntrBaseNum = NAVSS512_C7X1_INPUT_MAILBOX_OFFSET;
394 vimEventBaseNum = C7X1_MBINTR_OFFSET;
395 break;
396 default:
397 break;
398 }
399 cfg->outputIntrNum = outIntrBaseNum + intrCnt;
400 cfg->eventId = vimEventBaseNum + intrCnt;
402 return retVal;
403 }
406 int32_t Ipc_getMailboxIntrRouterCfg(uint32_t selfId, uint32_t clusterId,
407 uint32_t userId, Ipc_MbConfig* cfg, uint32_t cnt)
408 {
409 int32_t retVal = IPC_SOK;
410 uint32_t mailboxIntrNum = 0;
412 /* Get Navss512 input interrupt number for mailbox */
413 mailboxIntrNum = Ipc_getNavss512MailboxInputIntr(clusterId, userId);
415 cfg->inputIntrNum = mailboxIntrNum;
416 cfg->priority = 1U;
417 retVal = Ipc_setCoreEventId(selfId, cfg, cnt);
419 return retVal;
420 }
422 const char* Ipc_getCoreName(uint32_t procId)
423 {
424 char* p = (char*)0;
425 uint32_t id = procId;
427 if(id < IPC_MAX_PROCS)
428 {
429 p = g_Ipc_mp_procInfo[id].name;
430 }
431 return p;
432 }
434 #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
435 void Ipc_configC66xIntrRouter(uint32_t input)
436 {
437 volatile uint32_t *intr_router = (volatile uint32_t *)IPC_C66X_INTR_VA_BASE;
438 volatile uint32_t *RAT = (volatile uint32_t *)IPC_C66X_RAT_BASE;
439 uint32_t inputBase = 0U;
440 uint32_t outputBase = 0U;
441 uint32_t mbIntrBase = 0U;
442 uint32_t outputPin = 0U;
443 uint32_t inputPin = 0U;
445 /* program virtual address to REGION_BASE */
446 RAT[1] = (int)intr_router;
448 /* program C66_1/2 INTR_ROUTER physical addr to REGION_TRANS_L */
449 #ifdef BUILD_C66X_1
450 RAT[2] = IPC_C66X_1_INTR_PA_BASE;
451 #endif
452 #ifdef BUILD_C66X_2
453 RAT[2] = IPC_C66X_2_INTR_PA_BASE;
454 #endif
456 /* enable region and set size to 512 B */
457 RAT[0] = 0x80000009U;
459 #ifdef BUILD_C66X_1
460 inputBase = C66X1_MBINTR_INPUT_BASE;
461 outputBase = C66X1_MBINTR_OUTPUT_BASE;
462 mbIntrBase = C66X1_MBINTR_OFFSET;
463 #endif
465 #ifdef BUILD_C66X_2
466 inputBase = C66X2_MBINTR_INPUT_BASE;
467 outputBase = C66X2_MBINTR_OUTPUT_BASE;
468 mbIntrBase = C66X2_MBINTR_OFFSET;
469 #endif
471 inputPin = inputBase + (input - mbIntrBase);
472 outputPin = outputBase + (input - mbIntrBase);
474 #ifdef SUPPORT_C66X_BIT0
475 outputPin++;
476 #endif
478 /* Mailbox Interrupt Router */
479 intr_router[inputPin+1] = (0x1 << 16) + (outputPin & 0xFFFF);
480 }
481 #endif
483 #if defined(BUILD_C7X_1)
484 void Ipc_configClecRouter(uint32_t corePackEvent)
485 {
486 uint32_t input;
487 CSL_ClecEventConfig cfgClec;
488 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*)C7X_CLEC_BASE_ADDR;
490 input = C7X1_MBINTR_OUTPUT_BASE + (corePackEvent - C7X1_MBINTR_OFFSET);
492 /* Configure CLEC */
493 cfgClec.secureClaimEnable = FALSE;
494 cfgClec.evtSendEnable = TRUE;
495 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
496 cfgClec.extEvtNum = 0U;
497 cfgClec.c7xEvtNum = corePackEvent;
498 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
499 }
500 #endif
502 #ifdef IPC_SUPPORT_SCICLIENT
504 /* Indexed list of dst ids */
505 const uint8_t map_dst_id[] =
506 {
507 TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
508 TISCI_DEV_MCU_R5FSS0_CORE0,
509 TISCI_DEV_MCU_R5FSS0_CORE1,
510 TISCI_DEV_R5FSS0_CORE0,
511 TISCI_DEV_R5FSS0_CORE1,
512 TISCI_DEV_R5FSS1_CORE0,
513 TISCI_DEV_R5FSS1_CORE1,
514 TISCI_DEV_C66SS0_CORE0,
515 TISCI_DEV_C66SS1_CORE0,
516 TISCI_DEV_COMPUTE_CLUSTER0_CLEC
517 };
519 /* Indexed list of src ids */
520 const uint16_t map_src_id[] =
521 {
522 TISCI_DEV_NAVSS0_MAILBOX_0,
523 TISCI_DEV_NAVSS0_MAILBOX_1,
524 TISCI_DEV_NAVSS0_MAILBOX_2,
525 TISCI_DEV_NAVSS0_MAILBOX_3,
526 TISCI_DEV_NAVSS0_MAILBOX_4,
527 TISCI_DEV_NAVSS0_MAILBOX_5,
528 TISCI_DEV_NAVSS0_MAILBOX_6,
529 TISCI_DEV_NAVSS0_MAILBOX_7,
530 TISCI_DEV_NAVSS0_MAILBOX_8,
531 TISCI_DEV_NAVSS0_MAILBOX_9,
532 TISCI_DEV_NAVSS0_MAILBOX_10,
533 TISCI_DEV_NAVSS0_MAILBOX_11,
534 };
536 /* Indexed list of host ids */
537 const uint16_t map_host_id[] =
538 {
539 TISCI_HOST_ID_A72_0,
540 TISCI_HOST_ID_R5_0,
541 TISCI_HOST_ID_R5_2,
542 TISCI_HOST_ID_MAIN_0_R5_0,
543 TISCI_HOST_ID_MAIN_0_R5_2,
544 TISCI_HOST_ID_MAIN_1_R5_0,
545 TISCI_HOST_ID_MAIN_1_R5_2,
546 TISCI_HOST_ID_C6X_0_1,
547 TISCI_HOST_ID_C6X_1_1,
548 TISCI_HOST_ID_C7X_1
549 };
552 int32_t Ipc_sciclientIrqRelease(uint16_t coreId, uint32_t clusterId,
553 uint32_t userId, uint32_t intNumber)
554 {
555 int32_t retVal = IPC_SOK;
556 struct tisci_msg_rm_irq_release_req rmIrqRel;
558 rmIrqRel.ia_id = 0U;
559 rmIrqRel.vint = 0U;
560 rmIrqRel.global_event = 0U;
561 rmIrqRel.vint_status_bit_index = 0U;
563 rmIrqRel.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
564 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID |
565 TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID;
566 rmIrqRel.src_id = map_src_id[clusterId];
567 rmIrqRel.src_index = (uint16_t)userId;
568 rmIrqRel.dst_id = (uint16_t)map_dst_id[coreId];
569 #if defined(BUILD_C7X_1)
570 rmIrqRel.dst_host_irq = (uint16_t)(intNumber + IPC_C7X_COMPUTE_CLUSTER_OFFSET);
571 #else
572 rmIrqRel.dst_host_irq = (uint16_t)intNumber;
573 #endif
574 rmIrqRel.secondary_host = (uint8_t)map_host_id[coreId];
576 retVal = Sciclient_rmIrqRelease(&rmIrqRel, IPC_SCICLIENT_TIMEOUT);
578 return retVal;
579 }
581 int32_t Ipc_sciclientIrqSet(uint16_t coreId, uint32_t clusterId,
582 uint32_t userId, uint32_t intNumber)
583 {
584 int32_t retVal = IPC_SOK;
585 struct tisci_msg_rm_irq_set_req rmIrqReq;
586 struct tisci_msg_rm_irq_set_resp rmIrqResp;
588 rmIrqReq.ia_id = 0U;
589 rmIrqReq.vint = 0U;
590 rmIrqReq.global_event = 0U;
591 rmIrqReq.vint_status_bit_index = 0U;
593 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
594 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID |
595 TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID;
596 rmIrqReq.src_id = map_src_id[clusterId];
597 rmIrqReq.src_index = (uint16_t)userId;
598 rmIrqReq.dst_id = (uint16_t)map_dst_id[coreId];
599 #if defined(BUILD_C7X_1)
600 rmIrqReq.dst_host_irq = (uint16_t)(intNumber + IPC_C7X_COMPUTE_CLUSTER_OFFSET);
601 #else
602 rmIrqReq.dst_host_irq = (uint16_t)intNumber;
603 #endif
604 rmIrqReq.secondary_host = (uint8_t)map_host_id[coreId];
606 /* Config event */
607 retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, IPC_SCICLIENT_TIMEOUT);
609 return retVal;
610 }
612 #endif