1 /*
2 * Copyright (c) 2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== event_MPU.xs ========
34 * MPU Settings for SIMMAXWELL device's Cortex-R5F
35 */
37 /*
38 * -------------------------------------------------------------------------------------------------------------
39 * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
40 * |-------------------------------------------------------------------------------------------------------------|
41 * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
42 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
43 * | 1 | 0x00000000 | 1K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
44 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
45 * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
46 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
47 * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
48 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
49 * | 4 | 0x41C00000 | 512K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
50 * -------------------------------------------------------------------------------------------------------------
51 */
53 /*
54 * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
55 * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
56 * regions that are actually shared outside the R5 CPUSS must be marked as shared.
57 */
59 var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
60 MPU.enableMPU = true;
61 MPU.enableBackgroundRegion = true;
63 var attrs = new MPU.RegionAttrs();
64 MPU.initRegionAttrsMeta(attrs);
66 attrs.enable = true;
67 attrs.bufferable = false;
68 attrs.cacheable = false;
69 attrs.shareable = true;
70 attrs.noExecute = true;
71 attrs.accPerm = 1; /* RW at PL1 */
72 attrs.tex = 0;
73 attrs.subregionDisableMask = 0;
74 MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
76 attrs.enable = true;
77 attrs.bufferable = true;
78 attrs.cacheable = true;
79 attrs.shareable = false;
80 attrs.noExecute = false;
81 attrs.accPerm = 1; /* RW at PL1 */
82 attrs.tex = 1;
83 attrs.subregionDisableMask = 0;
84 MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
86 attrs.enable = true;
87 attrs.bufferable = true;
88 attrs.cacheable = true;
89 attrs.shareable = false;
90 attrs.noExecute = false;
91 attrs.accPerm = 1; /* RW at PL1 */
92 attrs.tex = 1;
93 attrs.subregionDisableMask = 0;
94 MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
96 attrs.enable = true;
97 attrs.bufferable = true;
98 attrs.cacheable = true;
99 attrs.shareable = false;
100 attrs.noExecute = false;
101 attrs.accPerm = 1; /* RW at PL1 */
102 attrs.tex = 1;
103 attrs.subregionDisableMask = 0x0;
104 MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
106 attrs.enable = true;
107 attrs.bufferable = true;
108 attrs.cacheable = true;
109 attrs.shareable = false;
110 attrs.noExecute = false;
111 attrs.accPerm = 1; /* RW at PL1 */
112 attrs.tex = 1;
113 attrs.subregionDisableMask = 0;
114 MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
116 /* MCASP */
117 attrs.enable = true;
118 attrs.bufferable = true;
119 attrs.cacheable = true;
120 attrs.shareable = false;
121 attrs.noExecute = false;
122 attrs.accPerm = 1; /* RW at PL1 */
123 attrs.tex = 1;
124 attrs.subregionDisableMask = 0;
125 MPU.setRegionMeta(5, 0x2B000000, MPU.RegionSize_256K, attrs);
128 attrs.enable = true;
129 attrs.bufferable = true;
130 attrs.cacheable = true;
131 attrs.shareable = false;
132 attrs.noExecute = false;
133 attrs.accPerm = 1; /* RW at PL1 */
134 attrs.tex = 1;
135 attrs.subregionDisableMask = 0;
136 MPU.setRegionMeta(6, 0x70000000, MPU.RegionSize_2M, attrs);
139 attrs.enable = true;
140 attrs.bufferable = true;
141 attrs.cacheable = true;
142 attrs.shareable = false;
143 attrs.noExecute = false;
144 attrs.accPerm = 1; /* RW at PL1 */
145 attrs.tex = 1;
146 attrs.subregionDisableMask = 0;
147 MPU.setRegionMeta(7, 0x04000000, MPU.RegionSize_2M, attrs);