packages/ti/drv/mcasp/example/idkAM574x/src/mcasp_cfg.c

   1 /*
   2  * mcasp_cfg.c
   3  *
   4  * This file contains the test / demo code to demonstrate the Audio component
   5  * driver functionality on SYS/BIOS 6.
   6  *
   7  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  *
  10  *  Redistribution and use in source and binary forms, with or without
  11  *  modification, are permitted provided that the following conditions
  12  *  are met:
  13  *
  14  *    Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  *
  17  *    Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  *    Neither the name of Texas Instruments Incorporated nor the names of
  23  *    its contributors may be used to endorse or promote products derived
  24  *    from this software without specific prior written permission.
  25  *
  26  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38 */
  39
  40 /** \file     mcasp_cfg.c
  41  *
  42  *  \brief    sample application for demostration of audio playing
  43  *
  44  *  This file contains the implementation of the sample appliation for the
  45  *  demonstration of audio playing through the audio interface layer.
  46  *
  47  *             (C) Copyright 2009, Texas Instruments, Inc
  48  */
  49
  50 /* ========================================================================== */
  51 /*                            INCLUDE FILES                                   */
  52 /* ========================================================================== */
  53
  54 #include <xdc/std.h>
  55 #include <ti/sysbios/io/IOM.h>
  56 #include <xdc/runtime/Memory.h>
  57 #include <ti/sysbios/heaps/HeapMem.h>
  58 #include <xdc/runtime/IHeap.h>
  59 #include <xdc/runtime/Error.h>
  60 #include <xdc/runtime/Log.h>
  61 #include <xdc/runtime/System.h>
  62 #include <ti/sysbios/BIOS.h>
  63 #include <ti/sysbios/knl/Semaphore.h>
  64 #include <mcasp_drv.h>
  65 #include <mcasp_cfg.h>
  66 #include <mcasp_tune.h>
  67 #include <ti/csl/csl_chip.h>
  68 #include <ti/sdo/edma3/drv/edma3_drv.h>
  69 #include <ti/sdo/edma3/rm/edma3_rm.h>
  70 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
  71 #include "ICodec.h"
  72 #include "stdio.h"
  73 #include "string.h"
  74
  75 void GblErrXmt(Mcasp_errCbStatus errCbStat);
  76 void GblErrRcv(Mcasp_errCbStatus errCbStat);
  77
  78 /* ========================================================================== */
  79 /*                          IMPORTED VARIABLES                                */
  80 /* ========================================================================== */
  81
  82
  83 extern EDMA3_DRV_Handle hEdma;
  84 extern HeapMem_Handle myHeap;
  85
  86 /* ========================================================================== */
  87 /*                          McASP Init config                                 */
  88 /* ========================================================================== */
  89
  90
  91
  92 Mcasp_HwSetupData mcaspRcvSetup = {
  93         /* .rmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */
  94 #if defined (DSP_MODE)
  95         /* .rfmt     = */ 0x000080f0,
  96 #else /* I2S MODE*/
  97     /* .rfmt     = */ 0x000180F0,
  98 #endif                                                            /* 0/1 bit delay from framsync
  99                                        * MSB first
 100                                        * No extra bit padding
 101                                        * Padding bit (ignore)
 102                                        * slot Size is 32
 103                                        * Reads from DMA port
 104                                        * NO rotation
 105                                        */
 106 #if defined (MCASP_MASTER)
 107         #if defined (DSP_MODE)
 108     /* .afsrctl  = */ 0x00000002,           /* burst mode,
 109                                              * Frame sync is one bit
 110                                              * internally generated frame sync
 111                                              * Rising edge is start of frame
 112                                              */
 113
 114         #else /* I2S MODE*/
 115           /* .afsrctl  = */ 0x00000113,     /* I2S mode,
 116                                              * Frame sync is one word
 117                                              * Internally generated frame sync
 118                                              * Falling edge is start of frame
 119                                              */
 120         #endif
 121 #else
 122         #if defined (DSP_MODE)
 123     /* .afsrctl  = */ 0x00000000,           /* burst mode,
 124                                              * Frame sync is one bit
 125                                              * Externally generated frame sync
 126                                              * Rising edge is start of frame
 127                                              */
 128
 129         #else /* I2S MODE*/
 130           /* .afsrctl  = */ 0x00000111,     /* I2S mode,
 131                                              * Frame sync is one word
 132                                              * Externally generated frame sync
 133                                              * Falling edge is start of frame
 134                                              */
 135         #endif
 136 #endif
 137
 138 #if defined (DSP_MODE)
 139 /* .rtdm     = */ 0x00000001,           /* slot 1 is active (DSP)
 140                                          *              */
 141
 142 #else /* I2S MODE*/
 143       /* .rtdm     = */ 0x00000003,     /* 2 slots are active (I2S)
 144                                          *            */
 145 #endif
 146         /* .rintctl  = */ 0x00000003, /* sync error and overrun error         */
 147         /* .rstat    = */ 0x000001FF, /* reset any existing status bits       */
 148         /* .revtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
 149         {
 150 #if defined (MCASP_MASTER)
 151                 #if defined (DSP_MODE)
 152                         /* .aclkrctl  = */ 0x00000027,
 153                         /* .ahclkrctl = */ 0x00008027,
 154                 #else /* I2S MODE*/
 155                         /* .aclkrctl  = */ 0x00000027,  /* Div (8), Internal Source, rising edge */
 156                         /* .ahclkrctl = */ 0x00008013,  /* Div (20), Internal AUX_CLK Source */
 157                 #endif
 158 #else
 159                 #if defined (DSP_MODE)
 160                         /* .aclkrctl  = */ 0x00000000,
 161                 #else /* I2S MODE*/
 162                         /* .aclkrctl  = */ 0x00000080,  /* External Source, rising edge */
 163                 #endif
 164                         /* .ahclkrctl = */ 0x00000000,  /* Don't Care */
 165 #endif
 166              /* .rclkchk   = */ 0x00000000
 167         }
 168 } ;
 169
 170 Mcasp_HwSetupData mcaspXmtSetup = {
 171         /* .xmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */
 172                 #if defined (DSP_MODE)
 173                         /* .xfmt     = */ 0x000080F0,
 174                 #else /* I2S MODE*/
 175                         /* .xfmt     = */ 0x000180F0,
 176                 #endif                                            /*
 177                                        * 0/1 bit delay from framsync
 178                                        * MSB first
 179                                        * No extra bit padding
 180                                        * Padding bit (ignore)
 181                                        * slot Size is 32
 182                                        * Reads from DMA port
 183                                        * 0-bit rotation
 184                                        */
 185 #if defined (MCASP_MASTER)
 186                 #if defined (DSP_MODE)
 187                 /* .afsxctl  = */ 0x00000002,       /* burst mode,
 188                                                                                          * Frame sync is one bit
 189                                                                                          * Internally generated frame sync
 190                                                                                          * Rising edge is start of frame
 191                                                                                          */
 192                 /* .xtdm     = */ 0x00000001,       /* slot 1 is active (DSP) */
 193                 #else /*I2S MODE*/
 194                           /* .afsxctl  = */ 0x00000113, /* I2S mode,
 195                                                                                          * Frame sync is one word
 196                                                                                          * internally generated frame sync
 197                                                                                          * Falling edge is start of frame
 198                                                                                          */
 199                           /* .xtdm     = */ 0x00000003, /* 2 slots are active (I2S) */
 200                 #endif
 201 #else
 202                 #if defined (DSP_MODE)
 203                 /* .afsxctl  = */ 0x00000000,       /* burst mode,
 204                                                                                          * Frame sync is one bit
 205                                                                                          * Rising edge is start of frame
 206                                                                                          * externally generated frame sync
 207                                                                                          */
 208                 /* .xtdm     = */ 0x00000001,       /* slot 1 is active (DSP) */
 209                 #else /*I2S MODE*/
 210                           /* .afsxctl  = */ 0x00000111, /* I2S mode,
 211                                                                                          * Frame sync is one word
 212                                                                                          * Externally generated frame sync
 213                                                                                          * Falling edge is start of frame
 214                                                                                          */
 215                           /* .xtdm     = */ 0x00000003, /* 2 slots are active (I2S) */
 216                 #endif
 217 #endif
 218         /* .xintctl  = */ 0x00000003, /* sync error,overrun error,clK error   */
 219         /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */
 220         /* .xevtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
 221         {
 222 #if defined (MCASP_MASTER)
 223         #if defined (DSP_MODE)
 224                         /* .aclkxctl  = */ 0x00000027,
 225                         /* .ahclkxctl = */ 0x00008027,
 226
 227                 #else /* I2S MODE*/
 228                         /* .aclkxctl  = */ 0x000000A7, /* Div (8), Internal Source, SYNC, Falling edge */
 229                         /* .ahclkxctl = */ 0x00008013, /* Div (20), Internal AUX_CLK Source */
 230                 #endif
 231 #else
 232                 #if defined (DSP_MODE)
 233                         /* .aclkxctl  = */ 0x00000000,  /* External Source, SYNC */
 234
 235                 #else /* I2S MODE*/
 236                         /* .aclkxctl  = */ 0x00000080, /* External Source, SYNC, Falling edge */
 237                 #endif
 238 #endif
 239              /* .xclkchk   = */ 0x00000000
 240         },
 241
 242 };
 243
 244 /* McAsp channel parameters                                  */
 245 Mcasp_ChanParams  mcasp_chanparam[2]=
 246 {
 247     {
 248         RX_NUM_SERIALIZER,         /* number of serialisers      */
 249         {Mcasp_SerializerNum_1, Mcasp_SerializerNum_3}, /* serialiser index           */
 250         &mcaspRcvSetup,
 251         TRUE,
 252         Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
 253         Mcasp_WordLength_32,
 254         NULL,
 255         0,
 256         NULL,
 257                 (Mcasp_GblCallback)&GblErrRcv,
 258 #if defined (DSP_MODE)
 259         1,
 260 #if RX_NUM_SERIALIZER == 1u
 261                 Mcasp_BufferFormat_1SER_1SLOT,
 262 #else
 263         Mcasp_BufferFormat_MULTISER_1SLOT_SER_INTERLEAVED,
 264 #endif
 265 #else      /* I2S MODE*/
 266         2, /* number of TDM channels      */
 267 #if RX_NUM_SERIALIZER == 1u
 268                 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
 269 #else
 270         Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
 271 #endif
 272 #endif
 273         TRUE,
 274                 RX_FIFO_EVENT_DMA_RATIO,
 275         TRUE,
 276         Mcasp_WordBitsSelect_LSB
 277     },
 278     {
 279         TX_NUM_SERIALIZER,        /* number of serialisers       */
 280         {Mcasp_SerializerNum_0, Mcasp_SerializerNum_2},
 281         &mcaspXmtSetup,
 282         TRUE,
 283         Mcasp_OpMode_TDM,
 284         Mcasp_WordLength_32,      /* word width                  */
 285         NULL,
 286         0,
 287         NULL,
 288                 (Mcasp_GblCallback)&GblErrXmt,
 289 #if defined (DSP_MODE)
 290         1,
 291 #if TX_NUM_SERIALIZER == 1u
 292                 Mcasp_BufferFormat_1SER_1SLOT,
 293 #else
 294         Mcasp_BufferFormat_MULTISER_1SLOT_SER_INTERLEAVED,
 295 #endif
 296 #else      /* I2S MODE*/
 297         2, /* number of TDM channels      */
 298 #if TX_NUM_SERIALIZER == 1u
 299                 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
 300 #else
 301         Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
 302 #endif
 303 #endif
 304         TRUE,
 305                 TX_FIFO_EVENT_DMA_RATIO,
 306         TRUE,
 307         Mcasp_WordBitsSelect_LSB
 308     }
 309 };
 310
 311 /*
 312  * ======== createStreams ========
 313  */
 314 ICodec_ChannelConfig AIC31_config =
 315 {
 316                 44100,  /* sampling rate for codec */
 317                 90,  /* gain (%) for codec      */
 318                 0x00,
 319                 0x00
 320 };