[processor-sdk/pdk.git] / packages / ti / drv / pa / example / emacExample / k2h / armv7 / bios / cpsw_example_k2h.cfg
1 /*
2 * Copyright 2015 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
10 /*
11 * ======== cpsw_example.cfg ========
12 *
13 */
15 /* Load all required BIOS/XDC runtime packages */
16 var Memory = xdc.useModule('xdc.runtime.Memory');
17 var BIOS = xdc.useModule('ti.sysbios.BIOS');
18 var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
19 var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
20 var Log = xdc.useModule('xdc.runtime.Log');
21 var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
22 var Task = xdc.useModule('ti.sysbios.knl.Task');
23 var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
24 var Main = xdc.useModule('xdc.runtime.Main');
25 var Defaults = xdc.useModule('xdc.runtime.Defaults');
26 var Diags = xdc.useModule('xdc.runtime.Diags');
27 var SysMin = xdc.useModule('xdc.runtime.SysMin');
28 var System = xdc.useModule('xdc.runtime.System');
29 var Text = xdc.useModule('xdc.runtime.Text');
31 Task.defaultStackSize = 0x4000;
33 /* Load the CPPI package */
34 var Cppi = xdc.loadPackage('ti.drv.cppi');
35 /* Load the QMSS package */
36 var Qmss = xdc.loadPackage('ti.drv.qmss');
38 /* Load the PA package */
39 var devType = "k2h"
40 var Pa = xdc.useModule('ti.drv.pa.Settings');
41 Pa.deviceType = devType;
43 /* Load the RM package */
44 var Rm = xdc.loadPackage('ti.drv.rm');
46 /*
47 * Program.argSize sets the size of the .args section.
48 * The examples don't use command line args so argSize is set to 0.
49 */
50 Program.argSize = 0x0;
52 /*
53 * The BIOS module will create the default heap for the system.
54 * Specify the size of this default heap.
55 */
56 BIOS.heapSize = 8192 * 30;
58 /*
59 * Build a custom SYS/BIOS library from sources.
60 */
61 BIOS.libType = BIOS.LibType_Custom;
63 /* System stack size (used by ISRs and Swis) */
64 Program.stack = 0x20000;
66 /* Circular buffer size for System_printf() */
67 SysMin.bufSize = 0x400;
69 /*
70 * Create and install logger for the whole system
71 */
72 var loggerBufParams = new LoggerBuf.Params();
73 loggerBufParams.numEntries = 32;
74 var logger0 = LoggerBuf.create(loggerBufParams);
75 Defaults.common$.logger = logger0;
76 Main.common$.diags_INFO = Diags.ALWAYS_ON;
78 System.SupportProxy = SysMin;
79 var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
81 var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
82 var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
84 /* Enable the cache */
85 Cache.enableCache = true;
87 // Enable the MMU (Required for L1/L2 data caching)
88 Mmu.enableMMU = true;
90 // descriptor attribute structure
91 var peripheralAttrs = new Mmu.DescriptorAttrs();
93 Mmu.initDescAttrsMeta(peripheralAttrs);
95 peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
96 peripheralAttrs.noExecute = true; // not executable
97 peripheralAttrs.accPerm = 0; // read/write at PL1
98 peripheralAttrs.attrIndx = 1; // MAIR0 Byte1 describes
99 // memory attributes for
100 // Define the base address of the 2 MB page
101 // the peripheral resides in.
102 var peripheralBaseAddrs = [
103 { base: 0x02620000, size: 0x00001000 }, // bootcfg
104 { base: 0x0bc00000, size: 0x00100000 }, // MSMC config
105 { base: 0x02000000, size: 0x00100000 }, // NETCP memory
106 { base: 0x02a00000, size: 0x00100000 }, // QMSS config memory
107 { base: 0x23A00000, size: 0x00100000 }, // QMSS Data memory
108 { base: 0x02901000, size: 0x00002000 }, // SRIO pkt dma config memory
109 { base: 0x01f14000, size: 0x00007000 }, // AIF pkt dma config memory
110 { base: 0x021F0200, size: 0x00000600 }, // FFTC 0 pkt dma config memory
111 { base: 0x021F0a00, size: 0x00000600 }, // FFTC 4 pkt dma config memory
112 { base: 0x021F1200, size: 0x00000600 }, // FFTC 5 pkt dma config memory
113 { base: 0x021F4200, size: 0x00000600 }, // FFTC 1 pkt dma config memory
114 { base: 0x021F8200, size: 0x00000600 }, // FFTC 2 pkt dma config memory
115 { base: 0x021FC200, size: 0x00000600 }, // FFTC 3 pkt dma config memory
116 { base: 0x02554000, size: 0x00009000 } // BCP pkt dma config memory
117 ];
119 // Configure the corresponding MMU page descriptor accordingly
120 for (var i =0; i < peripheralBaseAddrs.length; i++)
121 {
122 for (var j = 0; j < peripheralBaseAddrs[i].size; j += 0x200000)
123 {
124 var addr = peripheralBaseAddrs[i].base + j;
125 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
126 }
127 }
129 // Reconfigure DDR to use coherent address
130 Mmu.initDescAttrsMeta(peripheralAttrs);
132 peripheralAttrs.type = Mmu.DescriptorType_BLOCK;
133 peripheralAttrs.shareable = 2; // outer-shareable (3=inner, 0=none)
134 peripheralAttrs.accPerm = 1; // read/write at any privelege level
135 peripheralAttrs.attrIndx = 2; // normal cacheable (0=no cache, 1=strict order)
136 for (var vaddr = 0x80000000, paddr = 0x800000000; vaddr < 0x100000000; vaddr += 0x200000, paddr+= 0x200000)
137 {
138 Mmu.setSecondLevelDescMeta(vaddr, paddr, peripheralAttrs);
139 }
140 // Add MSMC as coherent
141 for (var addr = 0x0c000000; addr < 0x0c600000; addr += 0x200000)
142 {
143 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
144 }