[processor-sdk/pdk.git] / packages / ti / drv / pa / test / PAPktCapTest / src / armv7 / bios / fw_main.c
1 /* (C) Copyright 2012, Texas Instruments, Inc.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
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9 *
10 * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the
13 * distribution.
14 *
15 * Neither the name of Texas Instruments Incorporated nor the names of
16 * its contributors may be used to endorse or promote products derived
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18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 */
33 /** ============================================================================
34 * @n@b main
35 *
36 * @b Description
37 * @n Entry point for single core example application.
38 *
39 * @param[in]
40 * @n None
41 *
42 * @return
43 * @n None
44 * =============================================================================
45 */
46 #include <pcap_singlecore.h>
47 #include <stdio.h>
48 #include "ti/csl/csl_bootcfgAux.h"
50 #ifdef SIMULATOR_SUPPORT
51 uint32_t autodetectLogic = FALSE;
52 #else
53 uint32_t autodetectLogic = TRUE;
54 #endif
55 int32_t main (void)
56 {
57 Task_Params pCapTaskParams;
58 uint32_t bootMode;
60 #ifdef __ARM_ARCH_7A__
61 /* Add MMU entries for MMR's required for PCIE example */
62 Uint32 privid, index;
63 CSL_MsmcRegs *msmc = (CSL_MsmcRegs *)CSL_MSMC_CFG_REGS;
64 Mmu_DescriptorAttrs attrs;
65 extern char ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;
66 uint32_t addr = (uint32_t)&ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;
68 Mmu_initDescAttrs(&attrs);
70 attrs.type = Mmu_DescriptorType_TABLE;
71 attrs.shareable = 0; // non-shareable
72 attrs.accPerm = 1; // read/write at any privelege level
73 attrs.attrIndx = 0; // Use MAIR0 Register Byte 3 for
74 // determining the memory attributes
75 // for each MMU entry
78 // Update the first level table's MMU entry for 0x80000000 with the
79 // new attributes.
80 Mmu_setFirstLevelDesc((Ptr)0x40000000, (UInt64)addr, &attrs);
82 // Set up SES & SMS to make all masters coherent
83 for (privid = 0; privid < 16; privid++)
84 {
85 for (index = 0; index < 8; index++)
86 {
87 uint32_t ses_mpaxh = msmc->SES_MPAX_PER_PRIVID[privid].SES[index].MPAXH;
88 uint32_t sms_mpaxh = msmc->SMS_MPAX_PER_PRIVID[privid].SMS[index].MPAXH;
89 if (CSL_FEXT (ses_mpaxh, MSMC_SES_MPAXH_0_SEGSZ) != 0)
90 {
91 // Clear the "US" bit to make coherent. This is at 0x80.
92 ses_mpaxh &= ~0x80;
93 msmc->SES_MPAX_PER_PRIVID[privid].SES[index].MPAXH = ses_mpaxh;
94 }
95 if (CSL_FEXT (sms_mpaxh, MSMC_SMS_MPAXH_0_SEGSZ) != 0)
96 {
97 // Clear the "US" bit to make coherent. This is at 0x80.
98 sms_mpaxh &= ~0x80;
99 msmc->SMS_MPAX_PER_PRIVID[privid].SMS[index].MPAXH = sms_mpaxh;
100 }
101 }
102 }
103 #endif
105 #ifdef _TMS320C6X
106 /* Init internal cycle counter */
107 TSCL = 1;
108 #endif
109 if (autodetectLogic == TRUE)
110 {
111 bootMode = CSL_BootCfgGetBootMode() & 0x7;
113 if (bootMode == 0)
114 no_bootMode = TRUE;
115 else
116 no_bootMode = FALSE;
117 }
118 else {
119 no_bootMode = TRUE;
120 }
122 if (!cpswSimTest)
123 {
124 if (no_bootMode == TRUE)
125 {
126 passPowerUp();
127 }
128 }
130 /* Initialize the task params */
131 Task_Params_init(&pCapTaskParams);
132 pCapTaskParams.stackSize = 1024*8;
135 /* Create the CPSW single core example task */
136 Task_create((Task_FuncPtr)&pCap_SingleCoreApp, &pCapTaskParams, NULL);
138 /* Start the BIOS Task scheduler */
139 BIOS_start ();
141 return 0;
142 }