1 /**
2 * @file k2e/src/pcie_soc.c
3 *
4 * @brief
5 * This file contains the device specific configuration and initialization routines
6 * for pcie Low Level Driver.
7 *
8 * ============================================================================
9 * @n (C) Copyright 2013-2016, Texas Instruments, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 * \par
40 */
42 /**
43 * This file contains an example device configuration for the pcie LLD.
44 * It is not precompiled to facilitate user modification of the file.
45 */
47 #include <stdint.h>
48 #include <stdlib.h>
50 /* CSL RL includes */
51 #include <ti/csl/cslr_device.h>
52 #include <ti/csl/cslr_bootcfg.h>
54 #include <ti/csl/csl_bootcfg.h>
56 /* pcie LLD includes */
57 #include <ti/drv/pcie/soc/pcie_soc.h>
58 #include <ti/drv/pcie/pcie.h>
59 #include <ti/drv/pcie/src/v0/pcie.h>
61 /** @addtogroup PCIE_LLD_DATASTRUCT
62 @{
63 */
65 /** @brief PCIE v0 calltable */
66 Pcie_FxnTable fxnTablev0 =
67 {
68 /*! Function to set PCIE to EP or RC for one device */
69 &Pciev0_setInterfaceMode,
70 /*! Function to get the PCIE data area reserved size */
71 &Pciev0_getMemSpaceReserved,
72 /*! Function to get the PCIE data area base address & size */
73 &Pciev0_getMemSpaceRange,
74 /*! Function to read any PCIE register(s) */
75 &Pciev0_readRegs,
76 /*! Function to write any PCIE register(s) */
77 &Pciev0_writeRegs,
78 /*! Function to configure outbound translation registers */
79 &Pciev0_cfgObOffset,
80 /*! Function to configure inbound translation registers */
81 &Pciev0_cfgIbTrans,
82 /*! Function to configure a BAR register */
83 &Pciev0_cfgBar,
84 /*! Function to configure an ATU region */
85 NULL, /* unsupported on rev 0 */
86 /*! Function to read functional (MSI/INTX) pending bits with low overhead. */
87 NULL, /* unsupported on rev 0 */
88 /*! Function to clear functional (MSI/INTX) pending bits with low overhead. */
89 NULL /* unsupported on rev 0 */
90 };
92 Pciev0_DevParams modeSelDev0 =
93 {
94 (volatile uint32_t *)&hBootCfg->DEVCFG,
95 CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_MASK,
96 CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_SHIFT
97 };
99 Pcie_DeviceCfgBaseAddr baseAddrDev0 =
100 {
101 (void *)CSL_PCIE_0_SLV_CFG_REGS,
102 (void *)CSL_PCIE_0_SLV_DATA,
103 0U,
104 (void *)&modeSelDev0
105 };
107 Pciev0_DevParams modeSelDev1 =
108 {
109 (volatile uint32_t *)&hBootCfg->DEVCFG,
110 CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_MASK,
111 CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_SHIFT
112 };
114 Pcie_DeviceCfgBaseAddr baseAddrDev1 =
115 {
116 (void *)CSL_PCIE_1_SLV_CFG_REGS,
117 (void *)CSL_PCIE_1_SLV_DATA,
118 0U,
119 (void *)&modeSelDev1
120 };
122 /** @brief PCIE LLD initialization parameters */
123 const Pcie_InitCfg pcieInitCfg =
124 {
125 {
126 {
127 &baseAddrDev0,
128 &baseAddrDev1,
129 NULL,
130 NULL
131 },
132 {
133 &fxnTablev0,
134 &fxnTablev0,
135 NULL,
136 NULL
137 }
138 }
139 };
141 /**
142 @}
143 */