0ddcfd9f99e9e2775db6f6c2c81692db448b587c
1 /**
2 * @file pruicss_soc.c
3 *
4 * @brief This is device specific configuration file .
5 */
6 /*
7 * Copyright (c) 2019, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37 /** ============================================================================*/
39 #include <ti/csl/soc.h>
40 #include <ti/drv/pruss/pruicss.h>
41 #include <ti/drv/pruss/soc/pruicss_v1.h>
43 /* PRUICSS configuration structure */
44 PRUICSS_HwAttrs prussInitCfg[PRUICSS_INSTANCE_TWO] =
45 {
46 {
47 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
48 0, /* version */
49 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
50 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
51 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
52 CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
53 CSL_PRU_ICSSG0_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
54 CSL_PRU_ICSSG0_IEP0_BASE, /* prussIepRegBase */
55 CSL_PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
56 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
57 CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
58 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
59 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
60 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
61 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
62 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
63 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
64 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
65 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
66 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
67 CSL_PRU_ICSSG0_PR1_TX0_PR1_TX0_IRAM_BASE, /* prussTxPru0CtrlRegBase */
68 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_BASE, /* prussTxPru1CtrlRegBase */
69 CSL_PRU_ICSSG0_PR1_TX0_PR1_TX0_IRAM_RAM_BASE, /* prussTxPru0IramBase */
70 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
78 CSL_PRU_ICSSG0_PR1_TX0_PR1_TX0_IRAM_RAM_SIZE, /* prussTxPru0IramSize */
79 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_SIZE /* prussTxPru1IramSize */
80 },
81 {
82 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
83 0, /* version */
84 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
85 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
86 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
87 CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
88 CSL_PRU_ICSSG1_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
89 CSL_PRU_ICSSG1_IEP0_BASE, /* prussIepRegBase */
90 CSL_PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
91 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
92 CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
93 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
94 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
95 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
96 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
97 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
98 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
99 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
100 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
101 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
102 CSL_PRU_ICSSG1_PR1_TX0_PR1_TX0_IRAM_BASE, /* prussTxPru0CtrlRegBase */
103 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_BASE, /* prussTxPru1CtrlRegBase */
104 CSL_PRU_ICSSG1_PR1_TX0_PR1_TX0_IRAM_RAM_BASE, /* prussTxPru0IramBase */
105 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
113 CSL_PRU_ICSSG1_PR1_TX0_PR1_TX0_IRAM_RAM_SIZE, /* prussTxPru0IramSize */
114 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_SIZE /* prussTxPru1IramSize */
115 }
116 };
118 /* PRUICSS objects */
119 PRUICSS_V1_Object prussObjects[PRUICSS_INSTANCE_MAX-1];
121 /* PRUICSS configuration structure */
122 PRUICSS_Config pruss_config[PRUICSS_INSTANCE_MAX-1] = {
123 {
124 &prussObjects[0],
125 &prussInitCfg[0]
126 },
127 {
128 &prussObjects[1],
129 &prussInitCfg[1]
130 }
131 };