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112 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
113 <li class="toctree-l4"><a class="reference internal" href="#enumeration-of-device-ids">Enumeration of Device IDs</a></li>
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174 <div class="section" id="am6-devices-descriptions">
175 <h1>AM6 Devices Descriptions<a class="headerlink" href="#am6-devices-descriptions" title="Permalink to this headline">¶</a></h1>
176 <div class="section" id="introduction">
177 <span id="soc-doc-am6-public-devices-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
178 <p>This chapter provides information on Device IDs that are permitted in the am6
179 SoC. The device IDs represent SoC subsystems that can be modified via DMSC
180 TISCI message APIs. Some Secure, Power, and Resource Management DMSC subsystem
181 TISCI message APIs define a device ID as a parameter allowing a user to specify
182 management of a particular SoC subsystem.</p>
183 </div>
184 <div class="section" id="enumeration-of-device-ids">
185 <span id="soc-doc-am6-public-devices-desc-device-list"></span><h2>Enumeration of Device IDs<a class="headerlink" href="#enumeration-of-device-ids" title="Permalink to this headline">¶</a></h2>
186 <table border="1" class="docutils">
187 <colgroup>
188 <col width="21%" />
189 <col width="79%" />
190 </colgroup>
191 <thead valign="bottom">
192 <tr class="row-odd"><th class="head">Device ID</th>
193 <th class="head">Device Name</th>
194 </tr>
195 </thead>
196 <tbody valign="top">
197 <tr class="row-even"><td>0</td>
198 <td>AM6_DEV_MCU_ADC0</td>
199 </tr>
200 <tr class="row-odd"><td>1</td>
201 <td>AM6_DEV_MCU_ADC1</td>
202 </tr>
203 <tr class="row-even"><td>2</td>
204 <td>AM6_DEV_CAL0</td>
205 </tr>
206 <tr class="row-odd"><td>3</td>
207 <td>AM6_DEV_CMPEVENT_INTRTR0</td>
208 </tr>
209 <tr class="row-even"><td>5</td>
210 <td>AM6_DEV_MCU_CPSW0</td>
211 </tr>
212 <tr class="row-odd"><td>6</td>
213 <td>AM6_DEV_CPT2_AGGR0</td>
214 </tr>
215 <tr class="row-even"><td>7</td>
216 <td>AM6_DEV_MCU_CPT2_AGGR0</td>
217 </tr>
218 <tr class="row-odd"><td>8</td>
219 <td>AM6_DEV_STM0</td>
220 </tr>
221 <tr class="row-even"><td>9</td>
222 <td>AM6_DEV_DCC0</td>
223 </tr>
224 <tr class="row-odd"><td>10</td>
225 <td>AM6_DEV_DCC1</td>
226 </tr>
227 <tr class="row-even"><td>11</td>
228 <td>AM6_DEV_DCC2</td>
229 </tr>
230 <tr class="row-odd"><td>12</td>
231 <td>AM6_DEV_DCC3</td>
232 </tr>
233 <tr class="row-even"><td>13</td>
234 <td>AM6_DEV_DCC4</td>
235 </tr>
236 <tr class="row-odd"><td>14</td>
237 <td>AM6_DEV_DCC5</td>
238 </tr>
239 <tr class="row-even"><td>15</td>
240 <td>AM6_DEV_DCC6</td>
241 </tr>
242 <tr class="row-odd"><td>16</td>
243 <td>AM6_DEV_DCC7</td>
244 </tr>
245 <tr class="row-even"><td>17</td>
246 <td>AM6_DEV_MCU_DCC0</td>
247 </tr>
248 <tr class="row-odd"><td>18</td>
249 <td>AM6_DEV_MCU_DCC1</td>
250 </tr>
251 <tr class="row-even"><td>19</td>
252 <td>AM6_DEV_MCU_DCC2</td>
253 </tr>
254 <tr class="row-odd"><td>20</td>
255 <td>AM6_DEV_DDRSS0</td>
256 </tr>
257 <tr class="row-even"><td>21</td>
258 <td>AM6_DEV_DEBUGSS_WRAP0</td>
259 </tr>
260 <tr class="row-odd"><td>22</td>
261 <td>AM6_DEV_WKUP_DMSC0</td>
262 </tr>
263 <tr class="row-even"><td>23</td>
264 <td>AM6_DEV_TIMER0</td>
265 </tr>
266 <tr class="row-odd"><td>24</td>
267 <td>AM6_DEV_TIMER1</td>
268 </tr>
269 <tr class="row-even"><td>25</td>
270 <td>AM6_DEV_TIMER10</td>
271 </tr>
272 <tr class="row-odd"><td>26</td>
273 <td>AM6_DEV_TIMER11</td>
274 </tr>
275 <tr class="row-even"><td>27</td>
276 <td>AM6_DEV_TIMER2</td>
277 </tr>
278 <tr class="row-odd"><td>28</td>
279 <td>AM6_DEV_TIMER3</td>
280 </tr>
281 <tr class="row-even"><td>29</td>
282 <td>AM6_DEV_TIMER4</td>
283 </tr>
284 <tr class="row-odd"><td>30</td>
285 <td>AM6_DEV_TIMER5</td>
286 </tr>
287 <tr class="row-even"><td>31</td>
288 <td>AM6_DEV_TIMER6</td>
289 </tr>
290 <tr class="row-odd"><td>32</td>
291 <td>AM6_DEV_TIMER7</td>
292 </tr>
293 <tr class="row-even"><td>33</td>
294 <td>AM6_DEV_TIMER8</td>
295 </tr>
296 <tr class="row-odd"><td>34</td>
297 <td>AM6_DEV_TIMER9</td>
298 </tr>
299 <tr class="row-even"><td>35</td>
300 <td>AM6_DEV_MCU_TIMER0</td>
301 </tr>
302 <tr class="row-odd"><td>36</td>
303 <td>AM6_DEV_MCU_TIMER1</td>
304 </tr>
305 <tr class="row-even"><td>37</td>
306 <td>AM6_DEV_MCU_TIMER2</td>
307 </tr>
308 <tr class="row-odd"><td>38</td>
309 <td>AM6_DEV_MCU_TIMER3</td>
310 </tr>
311 <tr class="row-even"><td>39</td>
312 <td>AM6_DEV_ECAP0</td>
313 </tr>
314 <tr class="row-odd"><td>40</td>
315 <td>AM6_DEV_EHRPWM0</td>
316 </tr>
317 <tr class="row-even"><td>41</td>
318 <td>AM6_DEV_EHRPWM1</td>
319 </tr>
320 <tr class="row-odd"><td>42</td>
321 <td>AM6_DEV_EHRPWM2</td>
322 </tr>
323 <tr class="row-even"><td>43</td>
324 <td>AM6_DEV_EHRPWM3</td>
325 </tr>
326 <tr class="row-odd"><td>44</td>
327 <td>AM6_DEV_EHRPWM4</td>
328 </tr>
329 <tr class="row-even"><td>45</td>
330 <td>AM6_DEV_EHRPWM5</td>
331 </tr>
332 <tr class="row-odd"><td>46</td>
333 <td>AM6_DEV_ELM0</td>
334 </tr>
335 <tr class="row-even"><td>47</td>
336 <td>AM6_DEV_MMCSD0</td>
337 </tr>
338 <tr class="row-odd"><td>48</td>
339 <td>AM6_DEV_MMCSD1</td>
340 </tr>
341 <tr class="row-even"><td>49</td>
342 <td>AM6_DEV_EQEP0</td>
343 </tr>
344 <tr class="row-odd"><td>50</td>
345 <td>AM6_DEV_EQEP1</td>
346 </tr>
347 <tr class="row-even"><td>51</td>
348 <td>AM6_DEV_EQEP2</td>
349 </tr>
350 <tr class="row-odd"><td>52</td>
351 <td>AM6_DEV_ESM0</td>
352 </tr>
353 <tr class="row-even"><td>53</td>
354 <td>AM6_DEV_MCU_ESM0</td>
355 </tr>
356 <tr class="row-odd"><td>54</td>
357 <td>AM6_DEV_WKUP_ESM0</td>
358 </tr>
359 <tr class="row-even"><td>55</td>
360 <td>AM6_DEV_MCU_FSS0</td>
361 </tr>
362 <tr class="row-odd"><td>56</td>
363 <td>AM6_DEV_GIC0</td>
364 </tr>
365 <tr class="row-even"><td>57</td>
366 <td>AM6_DEV_GPIO0</td>
367 </tr>
368 <tr class="row-odd"><td>58</td>
369 <td>AM6_DEV_GPIO1</td>
370 </tr>
371 <tr class="row-even"><td>59</td>
372 <td>AM6_DEV_WKUP_GPIO0</td>
373 </tr>
374 <tr class="row-odd"><td>60</td>
375 <td>AM6_DEV_GPMC0</td>
376 </tr>
377 <tr class="row-even"><td>61</td>
378 <td>AM6_DEV_GTC0</td>
379 </tr>
380 <tr class="row-odd"><td>62</td>
381 <td>AM6_DEV_PRU_ICSSG0</td>
382 </tr>
383 <tr class="row-even"><td>63</td>
384 <td>AM6_DEV_PRU_ICSSG1</td>
385 </tr>
386 <tr class="row-odd"><td>64</td>
387 <td>AM6_DEV_PRU_ICSSG2</td>
388 </tr>
389 <tr class="row-even"><td>65</td>
390 <td>AM6_DEV_GPU0</td>
391 </tr>
392 <tr class="row-odd"><td>66</td>
393 <td>AM6_DEV_CCDEBUGSS0</td>
394 </tr>
395 <tr class="row-even"><td>67</td>
396 <td>AM6_DEV_DSS0</td>
397 </tr>
398 <tr class="row-odd"><td>68</td>
399 <td>AM6_DEV_DEBUGSS0</td>
400 </tr>
401 <tr class="row-even"><td>69</td>
402 <td>AM6_DEV_EFUSE0</td>
403 </tr>
404 <tr class="row-odd"><td>70</td>
405 <td>AM6_DEV_PSC0</td>
406 </tr>
407 <tr class="row-even"><td>71</td>
408 <td>AM6_DEV_MCU_DEBUGSS0</td>
409 </tr>
410 <tr class="row-odd"><td>72</td>
411 <td>AM6_DEV_MCU_EFUSE0</td>
412 </tr>
413 <tr class="row-even"><td>73</td>
414 <td>AM6_DEV_PBIST0</td>
415 </tr>
416 <tr class="row-odd"><td>74</td>
417 <td>AM6_DEV_PBIST1</td>
418 </tr>
419 <tr class="row-even"><td>75</td>
420 <td>AM6_DEV_MCU_PBIST0</td>
421 </tr>
422 <tr class="row-odd"><td>76</td>
423 <td>AM6_DEV_PLLCTRL0</td>
424 </tr>
425 <tr class="row-even"><td>77</td>
426 <td>AM6_DEV_WKUP_PLLCTRL0</td>
427 </tr>
428 <tr class="row-odd"><td>78</td>
429 <td>AM6_DEV_MCU_ROM0</td>
430 </tr>
431 <tr class="row-even"><td>79</td>
432 <td>AM6_DEV_WKUP_PSC0</td>
433 </tr>
434 <tr class="row-odd"><td>80</td>
435 <td>AM6_DEV_WKUP_VTM0</td>
436 </tr>
437 <tr class="row-even"><td>81</td>
438 <td>AM6_DEV_DEBUGSUSPENDRTR0</td>
439 </tr>
440 <tr class="row-odd"><td>82</td>
441 <td>AM6_DEV_CBASS0</td>
442 </tr>
443 <tr class="row-even"><td>83</td>
444 <td>AM6_DEV_CBASS_DEBUG0</td>
445 </tr>
446 <tr class="row-odd"><td>84</td>
447 <td>AM6_DEV_CBASS_FW0</td>
448 </tr>
449 <tr class="row-even"><td>85</td>
450 <td>AM6_DEV_CBASS_INFRA0</td>
451 </tr>
452 <tr class="row-odd"><td>86</td>
453 <td>AM6_DEV_ECC_AGGR0</td>
454 </tr>
455 <tr class="row-even"><td>87</td>
456 <td>AM6_DEV_ECC_AGGR1</td>
457 </tr>
458 <tr class="row-odd"><td>88</td>
459 <td>AM6_DEV_ECC_AGGR2</td>
460 </tr>
461 <tr class="row-even"><td>89</td>
462 <td>AM6_DEV_MCU_CBASS0</td>
463 </tr>
464 <tr class="row-odd"><td>90</td>
465 <td>AM6_DEV_MCU_CBASS_DEBUG0</td>
466 </tr>
467 <tr class="row-even"><td>91</td>
468 <td>AM6_DEV_MCU_CBASS_FW0</td>
469 </tr>
470 <tr class="row-odd"><td>92</td>
471 <td>AM6_DEV_MCU_ECC_AGGR0</td>
472 </tr>
473 <tr class="row-even"><td>93</td>
474 <td>AM6_DEV_MCU_ECC_AGGR1</td>
475 </tr>
476 <tr class="row-odd"><td>94</td>
477 <td>AM6_DEV_WKUP_CBASS0</td>
478 </tr>
479 <tr class="row-even"><td>95</td>
480 <td>AM6_DEV_WKUP_ECC_AGGR0</td>
481 </tr>
482 <tr class="row-odd"><td>96</td>
483 <td>AM6_DEV_WKUP_CBASS_FW0</td>
484 </tr>
485 <tr class="row-even"><td>97</td>
486 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
487 </tr>
488 <tr class="row-odd"><td>98</td>
489 <td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
490 </tr>
491 <tr class="row-even"><td>99</td>
492 <td>AM6_DEV_CTRL_MMR0</td>
493 </tr>
494 <tr class="row-odd"><td>100</td>
495 <td>AM6_DEV_GPIOMUX_INTRTR0</td>
496 </tr>
497 <tr class="row-even"><td>101</td>
498 <td>AM6_DEV_PLL_MMR0</td>
499 </tr>
500 <tr class="row-odd"><td>102</td>
501 <td>AM6_DEV_MCU_MCAN0</td>
502 </tr>
503 <tr class="row-even"><td>103</td>
504 <td>AM6_DEV_MCU_MCAN1</td>
505 </tr>
506 <tr class="row-odd"><td>104</td>
507 <td>AM6_DEV_MCASP0</td>
508 </tr>
509 <tr class="row-even"><td>105</td>
510 <td>AM6_DEV_MCASP1</td>
511 </tr>
512 <tr class="row-odd"><td>106</td>
513 <td>AM6_DEV_MCASP2</td>
514 </tr>
515 <tr class="row-even"><td>107</td>
516 <td>AM6_DEV_MCU_CTRL_MMR0</td>
517 </tr>
518 <tr class="row-odd"><td>108</td>
519 <td>AM6_DEV_MCU_PLL_MMR0</td>
520 </tr>
521 <tr class="row-even"><td>109</td>
522 <td>AM6_DEV_MCU_SEC_MMR0</td>
523 </tr>
524 <tr class="row-odd"><td>110</td>
525 <td>AM6_DEV_I2C0</td>
526 </tr>
527 <tr class="row-even"><td>111</td>
528 <td>AM6_DEV_I2C1</td>
529 </tr>
530 <tr class="row-odd"><td>112</td>
531 <td>AM6_DEV_I2C2</td>
532 </tr>
533 <tr class="row-even"><td>113</td>
534 <td>AM6_DEV_I2C3</td>
535 </tr>
536 <tr class="row-odd"><td>114</td>
537 <td>AM6_DEV_MCU_I2C0</td>
538 </tr>
539 <tr class="row-even"><td>115</td>
540 <td>AM6_DEV_WKUP_I2C0</td>
541 </tr>
542 <tr class="row-odd"><td>116</td>
543 <td>AM6_DEV_MCU_MSRAM0</td>
544 </tr>
545 <tr class="row-even"><td>117</td>
546 <td>AM6_DEV_DFTSS0</td>
547 </tr>
548 <tr class="row-odd"><td>118</td>
549 <td>AM6_DEV_NAVSS0</td>
550 </tr>
551 <tr class="row-even"><td>119</td>
552 <td>AM6_DEV_MCU_NAVSS0</td>
553 </tr>
554 <tr class="row-odd"><td>120</td>
555 <td>AM6_DEV_PCIE0</td>
556 </tr>
557 <tr class="row-even"><td>121</td>
558 <td>AM6_DEV_PCIE1</td>
559 </tr>
560 <tr class="row-odd"><td>122</td>
561 <td>AM6_DEV_PDMA_DEBUG0</td>
562 </tr>
563 <tr class="row-even"><td>123</td>
564 <td>AM6_DEV_PDMA0</td>
565 </tr>
566 <tr class="row-odd"><td>124</td>
567 <td>AM6_DEV_PDMA1</td>
568 </tr>
569 <tr class="row-even"><td>125</td>
570 <td>AM6_DEV_MCU_PDMA0</td>
571 </tr>
572 <tr class="row-odd"><td>126</td>
573 <td>AM6_DEV_MCU_PDMA1</td>
574 </tr>
575 <tr class="row-even"><td>127</td>
576 <td>AM6_DEV_MCU_PSRAM0</td>
577 </tr>
578 <tr class="row-odd"><td>128</td>
579 <td>AM6_DEV_PSRAMECC0</td>
580 </tr>
581 <tr class="row-even"><td>129</td>
582 <td>AM6_DEV_MCU_ARMSS0</td>
583 </tr>
584 <tr class="row-odd"><td>130</td>
585 <td>AM6_DEV_RTI0</td>
586 </tr>
587 <tr class="row-even"><td>131</td>
588 <td>AM6_DEV_RTI1</td>
589 </tr>
590 <tr class="row-odd"><td>132</td>
591 <td>AM6_DEV_RTI2</td>
592 </tr>
593 <tr class="row-even"><td>133</td>
594 <td>AM6_DEV_RTI3</td>
595 </tr>
596 <tr class="row-odd"><td>134</td>
597 <td>AM6_DEV_MCU_RTI0</td>
598 </tr>
599 <tr class="row-even"><td>135</td>
600 <td>AM6_DEV_MCU_RTI1</td>
601 </tr>
602 <tr class="row-odd"><td>136</td>
603 <td>AM6_DEV_SA2_UL0</td>
604 </tr>
605 <tr class="row-even"><td>137</td>
606 <td>AM6_DEV_MCSPI0</td>
607 </tr>
608 <tr class="row-odd"><td>138</td>
609 <td>AM6_DEV_MCSPI1</td>
610 </tr>
611 <tr class="row-even"><td>139</td>
612 <td>AM6_DEV_MCSPI2</td>
613 </tr>
614 <tr class="row-odd"><td>140</td>
615 <td>AM6_DEV_MCSPI3</td>
616 </tr>
617 <tr class="row-even"><td>141</td>
618 <td>AM6_DEV_MCSPI4</td>
619 </tr>
620 <tr class="row-odd"><td>142</td>
621 <td>AM6_DEV_MCU_MCSPI0</td>
622 </tr>
623 <tr class="row-even"><td>143</td>
624 <td>AM6_DEV_MCU_MCSPI1</td>
625 </tr>
626 <tr class="row-odd"><td>144</td>
627 <td>AM6_DEV_MCU_MCSPI2</td>
628 </tr>
629 <tr class="row-even"><td>145</td>
630 <td>AM6_DEV_TIMESYNC_INTRTR0</td>
631 </tr>
632 <tr class="row-odd"><td>146</td>
633 <td>AM6_DEV_UART0</td>
634 </tr>
635 <tr class="row-even"><td>147</td>
636 <td>AM6_DEV_UART1</td>
637 </tr>
638 <tr class="row-odd"><td>148</td>
639 <td>AM6_DEV_UART2</td>
640 </tr>
641 <tr class="row-even"><td>149</td>
642 <td>AM6_DEV_MCU_UART0</td>
643 </tr>
644 <tr class="row-odd"><td>150</td>
645 <td>AM6_DEV_WKUP_UART0</td>
646 </tr>
647 <tr class="row-even"><td>151</td>
648 <td>AM6_DEV_USB3SS0</td>
649 </tr>
650 <tr class="row-odd"><td>152</td>
651 <td>AM6_DEV_USB3SS1</td>
652 </tr>
653 <tr class="row-even"><td>153</td>
654 <td>AM6_DEV_SERDES0</td>
655 </tr>
656 <tr class="row-odd"><td>154</td>
657 <td>AM6_DEV_SERDES1</td>
658 </tr>
659 <tr class="row-even"><td>155</td>
660 <td>AM6_DEV_WKUP_CTRL_MMR0</td>
661 </tr>
662 <tr class="row-odd"><td>156</td>
663 <td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
664 </tr>
665 <tr class="row-even"><td>157</td>
666 <td>AM6_DEV_BOARD0</td>
667 </tr>
668 <tr class="row-odd"><td>159</td>
669 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
670 </tr>
671 <tr class="row-even"><td>161</td>
672 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
673 </tr>
674 <tr class="row-odd"><td>162</td>
675 <td>AM6_DEV_WKUP_DMSC0_INTR_AGGR_0</td>
676 </tr>
677 <tr class="row-even"><td>163</td>
678 <td>AM6_DEV_NAVSS0_CPTS0</td>
679 </tr>
680 <tr class="row-odd"><td>164</td>
681 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
682 </tr>
683 <tr class="row-even"><td>165</td>
684 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
685 </tr>
686 <tr class="row-odd"><td>166</td>
687 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
688 </tr>
689 <tr class="row-even"><td>167</td>
690 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
691 </tr>
692 <tr class="row-odd"><td>168</td>
693 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
694 </tr>
695 <tr class="row-even"><td>169</td>
696 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
697 </tr>
698 <tr class="row-odd"><td>170</td>
699 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
700 </tr>
701 <tr class="row-even"><td>171</td>
702 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
703 </tr>
704 <tr class="row-odd"><td>172</td>
705 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
706 </tr>
707 <tr class="row-even"><td>173</td>
708 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
709 </tr>
710 <tr class="row-odd"><td>174</td>
711 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
712 </tr>
713 <tr class="row-even"><td>175</td>
714 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
715 </tr>
716 <tr class="row-odd"><td>176</td>
717 <td>AM6_DEV_NAVSS0_MCRC0</td>
718 </tr>
719 <tr class="row-even"><td>177</td>
720 <td>AM6_DEV_NAVSS0_PVU0</td>
721 </tr>
722 <tr class="row-odd"><td>178</td>
723 <td>AM6_DEV_NAVSS0_PVU1</td>
724 </tr>
725 <tr class="row-even"><td>179</td>
726 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
727 </tr>
728 <tr class="row-odd"><td>180</td>
729 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
730 </tr>
731 <tr class="row-even"><td>181</td>
732 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
733 </tr>
734 <tr class="row-odd"><td>182</td>
735 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
736 </tr>
737 <tr class="row-even"><td>183</td>
738 <td>AM6_DEV_NAVSS0_TIMER_MGR0</td>
739 </tr>
740 <tr class="row-odd"><td>184</td>
741 <td>AM6_DEV_NAVSS0_TIMER_MGR1</td>
742 </tr>
743 <tr class="row-even"><td>185</td>
744 <td>AM6_DEV_NAVSS0_PROXY0</td>
745 </tr>
746 <tr class="row-odd"><td>186</td>
747 <td>AM6_DEV_NAVSS0_SEC_PROXY0</td>
748 </tr>
749 <tr class="row-even"><td>187</td>
750 <td>AM6_DEV_NAVSS0_RINGACC0</td>
751 </tr>
752 <tr class="row-odd"><td>188</td>
753 <td>AM6_DEV_NAVSS0_UDMAP0</td>
754 </tr>
755 <tr class="row-even"><td>189</td>
756 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
757 </tr>
758 <tr class="row-odd"><td>190</td>
759 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
760 </tr>
761 <tr class="row-even"><td>191</td>
762 <td>AM6_DEV_MCU_NAVSS0_PROXY0</td>
763 </tr>
764 <tr class="row-odd"><td>192</td>
765 <td>AM6_DEV_MCU_NAVSS0_SEC_PROXY0</td>
766 </tr>
767 <tr class="row-even"><td>193</td>
768 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
769 </tr>
770 <tr class="row-odd"><td>194</td>
771 <td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
772 </tr>
773 <tr class="row-even"><td>195</td>
774 <td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
775 </tr>
776 <tr class="row-odd"><td>196</td>
777 <td>AM6_DEV_COMPUTE_CLUSTER_MSMC0</td>
778 </tr>
779 <tr class="row-even"><td>197</td>
780 <td>AM6_DEV_COMPUTE_CLUSTER_PBIST0</td>
781 </tr>
782 <tr class="row-odd"><td>198</td>
783 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC0</td>
784 </tr>
785 <tr class="row-even"><td>199</td>
786 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0</td>
787 </tr>
788 <tr class="row-odd"><td>200</td>
789 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC1</td>
790 </tr>
791 <tr class="row-even"><td>201</td>
792 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1</td>
793 </tr>
794 <tr class="row-odd"><td>202</td>
795 <td>AM6_DEV_COMPUTE_CLUSTER_A53_0</td>
796 </tr>
797 <tr class="row-even"><td>203</td>
798 <td>AM6_DEV_COMPUTE_CLUSTER_A53_1</td>
799 </tr>
800 <tr class="row-odd"><td>204</td>
801 <td>AM6_DEV_COMPUTE_CLUSTER_A53_2</td>
802 </tr>
803 <tr class="row-even"><td>205</td>
804 <td>AM6_DEV_COMPUTE_CLUSTER_A53_3</td>
805 </tr>
806 <tr class="row-odd"><td>206</td>
807 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4</td>
808 </tr>
809 <tr class="row-even"><td>207</td>
810 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3</td>
811 </tr>
812 <tr class="row-odd"><td>208</td>
813 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0</td>
814 </tr>
815 <tr class="row-even"><td>209</td>
816 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3</td>
817 </tr>
818 <tr class="row-odd"><td>210</td>
819 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1</td>
820 </tr>
821 <tr class="row-even"><td>211</td>
822 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5</td>
823 </tr>
824 <tr class="row-odd"><td>212</td>
825 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6</td>
826 </tr>
827 <tr class="row-even"><td>213</td>
828 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0</td>
829 </tr>
830 <tr class="row-odd"><td>214</td>
831 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2</td>
832 </tr>
833 <tr class="row-even"><td>215</td>
834 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2</td>
835 </tr>
836 <tr class="row-odd"><td>216</td>
837 <td>AM6_DEV_OLDI_TX_CORE_MAIN_0</td>
838 </tr>
839 <tr class="row-even"><td>217</td>
840 <td>AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0</td>
841 </tr>
842 <tr class="row-odd"><td>218</td>
843 <td>AM6_DEV_ICEMELTER_WKUP_0</td>
844 </tr>
845 <tr class="row-even"><td>219</td>
846 <td>AM6_DEV_K3_LED_MAIN_0</td>
847 </tr>
848 <tr class="row-odd"><td>220</td>
849 <td>AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU</td>
850 </tr>
851 <tr class="row-even"><td>221</td>
852 <td>AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP</td>
853 </tr>
854 <tr class="row-odd"><td>222</td>
855 <td>AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU</td>
856 </tr>
857 <tr class="row-even"><td>223</td>
858 <td>AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN</td>
859 </tr>
860 <tr class="row-odd"><td>224</td>
861 <td>AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC</td>
862 </tr>
863 <tr class="row-even"><td>225</td>
864 <td>AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA</td>
865 </tr>
866 <tr class="row-odd"><td>226</td>
867 <td>AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA</td>
868 </tr>
869 <tr class="row-even"><td>227</td>
870 <td>AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU</td>
871 </tr>
872 <tr class="row-odd"><td>228</td>
873 <td>AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN</td>
874 </tr>
875 <tr class="row-even"><td>229</td>
876 <td>AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU</td>
877 </tr>
878 <tr class="row-odd"><td>230</td>
879 <td>AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU</td>
880 </tr>
881 <tr class="row-even"><td>231</td>
882 <td>AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0</td>
883 </tr>
884 <tr class="row-odd"><td>232</td>
885 <td>AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0</td>
886 </tr>
887 <tr class="row-even"><td>233</td>
888 <td>AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0</td>
889 </tr>
890 <tr class="row-odd"><td>234</td>
891 <td>AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0</td>
892 </tr>
893 <tr class="row-even"><td>235</td>
894 <td>AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0</td>
895 </tr>
896 <tr class="row-odd"><td>236</td>
897 <td>AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU</td>
898 </tr>
899 <tr class="row-even"><td>237</td>
900 <td>AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA</td>
901 </tr>
902 <tr class="row-odd"><td>238</td>
903 <td>AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC</td>
904 </tr>
905 <tr class="row-even"><td>239</td>
906 <td>AM6_DEV_DUMMY_IP_LPSC_DMSC</td>
907 </tr>
908 <tr class="row-odd"><td>240</td>
909 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA</td>
910 </tr>
911 <tr class="row-even"><td>241</td>
912 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN</td>
913 </tr>
914 <tr class="row-odd"><td>242</td>
915 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP</td>
916 </tr>
917 <tr class="row-even"><td>243</td>
918 <td>AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU</td>
919 </tr>
920 <tr class="row-odd"><td>244</td>
921 <td>AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA</td>
922 </tr>
923 <tr class="row-even"><td>245</td>
924 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
925 </tr>
926 </tbody>
927 </table>
928 </div>
929 </div>
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