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 167     <li>AM6 Navigator Subsystem Descriptions</li>
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 178
 179   <div class="section" id="am6-navigator-subsystem-descriptions">
 180 <h1>AM6 Navigator Subsystem Descriptions<a class="headerlink" href="#am6-navigator-subsystem-descriptions" title="Permalink to this headline">¶</a></h1>
 181 <div class="section" id="introduction">
 182 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 183 <p>This chapter provides information on the Navigator Subsystems in the am6
 184 SoC. Some System Firmware TISCI messages take Navigator Subsystem
 185 specific inputs. This chapter provides information on the valid values
 186 for applicable TISCI message parameters.</p>
 187 </div>
 188 <div class="section" id="navigator-subsystem-device-ids">
 189 <span id="pub-soc-am6x-navss-ids"></span><h2>Navigator Subsystem Device IDs<a class="headerlink" href="#navigator-subsystem-device-ids" title="Permalink to this headline">¶</a></h2>
 190 <p>Some System Firmware TISCI message APIs require the device ID of the
 191 Navigator Subsystem to be modified as part of the request. Based on the
 192 <a class="reference internal" href="devices.html"><span class="doc">AM6 Device IDs</span></a> these are the valid Navigator
 193 Subsystem device IDs.</p>
 194 <table border="1" class="docutils">
 195 <colgroup>
 196 <col width="48%" />
 197 <col width="52%" />
 198 </colgroup>
 199 <thead valign="bottom">
 200 <tr class="row-odd"><th class="head">Ring Accelerator Device ID</th>
 201 <th class="head">Ring Accelerator Device Name</th>
 202 </tr>
 203 </thead>
 204 <tbody valign="top">
 205 <tr class="row-even"><td>187</td>
 206 <td>AM6_DEV_NAVSS0_RINGACC0</td>
 207 </tr>
 208 <tr class="row-odd"><td>195</td>
 209 <td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
 210 </tr>
 211 </tbody>
 212 </table>
 213 <table border="1" class="docutils">
 214 <colgroup>
 215 <col width="39%" />
 216 <col width="61%" />
 217 </colgroup>
 218 <thead valign="bottom">
 219 <tr class="row-odd"><th class="head">UDMAP Device ID</th>
 220 <th class="head">UDMAP Device Name</th>
 221 </tr>
 222 </thead>
 223 <tbody valign="top">
 224 <tr class="row-even"><td>188</td>
 225 <td>AM6_DEV_NAVSS0_UDMAP0</td>
 226 </tr>
 227 <tr class="row-odd"><td>194</td>
 228 <td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
 229 </tr>
 230 </tbody>
 231 </table>
 232 <table border="1" class="docutils">
 233 <colgroup>
 234 <col width="46%" />
 235 <col width="54%" />
 236 </colgroup>
 237 <thead valign="bottom">
 238 <tr class="row-odd"><th class="head">PSI-L Device ID</th>
 239 <th class="head">PSI-L Device Name</th>
 240 </tr>
 241 </thead>
 242 <tbody valign="top">
 243 <tr class="row-even"><td>118</td>
 244 <td>AM6_DEV_NAVSS0</td>
 245 </tr>
 246 <tr class="row-odd"><td>119</td>
 247 <td>AM6_DEV_MCU_NAVSS0</td>
 248 </tr>
 249 </tbody>
 250 </table>
 251 <table border="1" class="docutils">
 252 <colgroup>
 253 <col width="48%" />
 254 <col width="52%" />
 255 </colgroup>
 256 <thead valign="bottom">
 257 <tr class="row-odd"><th class="head">Interrupt Aggregator Device ID</th>
 258 <th class="head">Interrupt Aggregator Device Name</th>
 259 </tr>
 260 </thead>
 261 <tbody valign="top">
 262 <tr class="row-even"><td>179</td>
 263 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
 264 </tr>
 265 <tr class="row-odd"><td>180</td>
 266 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
 267 </tr>
 268 <tr class="row-even"><td>181</td>
 269 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
 270 </tr>
 271 <tr class="row-odd"><td>189</td>
 272 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
 273 </tr>
 274 </tbody>
 275 </table>
 276 </div>
 277 <div class="section" id="navigator-subsystem-ring-indices">
 278 <span id="pub-soc-am6x-navss-rings"></span><h2>Navigator Subsystem Ring Indices<a class="headerlink" href="#navigator-subsystem-ring-indices" title="Permalink to this headline">¶</a></h2>
 279 <p>This section describes valid Navigator Subsystem Ring Accelerator ring
 280 indices for each Navigator ring type. The ring index and type ID are
 281 used in some Ring Accelerator based TISCI messages.</p>
 282 <div class="admonition warning">
 283 <p class="first admonition-title">Warning</p>
 284 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
 285 host within the RM Board Configuration resource assignment array.  The
 286 RM Board Configuration is rejected if an overlap with a reserved resouce
 287 is detected.</p>
 288 </div>
 289 <p><strong>Main Navigator Subsystem</strong></p>
 290 <table border="1" class="docutils">
 291 <colgroup>
 292 <col width="64%" />
 293 <col width="36%" />
 294 </colgroup>
 295 <thead valign="bottom">
 296 <tr class="row-odd"><th class="head">Ring Type</th>
 297 <th class="head">Ring Index Range</th>
 298 </tr>
 299 </thead>
 300 <tbody valign="top">
 301 <tr class="row-even"><td>UDMAP Tx
 302 (<strong>Reserved for use by DMSC</strong>)</td>
 303 <td>0</td>
 304 </tr>
 305 <tr class="row-odd"><td>UDMAP Tx</td>
 306 <td>1 to 151</td>
 307 </tr>
 308 <tr class="row-even"><td>UDMAP Rx
 309 (<strong>Reserved for use by DMSC</strong>)</td>
 310 <td>152</td>
 311 </tr>
 312 <tr class="row-odd"><td>UDMAP Rx</td>
 313 <td>153 to 301</td>
 314 </tr>
 315 <tr class="row-even"><td>General Purpose
 316 (<strong>Reserved for use by DMSC</strong>)</td>
 317 <td>302 to 303</td>
 318 </tr>
 319 <tr class="row-odd"><td>General Purpose</td>
 320 <td>304 to 767</td>
 321 </tr>
 322 </tbody>
 323 </table>
 324 <table border="1" class="docutils">
 325 <colgroup>
 326 <col width="60%" />
 327 <col width="40%" />
 328 </colgroup>
 329 <thead valign="bottom">
 330 <tr class="row-odd"><th class="head">&#160;</th>
 331 <th class="head">Monitor Index Range</th>
 332 </tr>
 333 </thead>
 334 <tbody valign="top">
 335 <tr class="row-even"><td>Ring Monitors</td>
 336 <td>0 to 31</td>
 337 </tr>
 338 </tbody>
 339 </table>
 340 <p><strong>MCU Navigator Subsystem</strong></p>
 341 <table border="1" class="docutils">
 342 <colgroup>
 343 <col width="49%" />
 344 <col width="51%" />
 345 </colgroup>
 346 <thead valign="bottom">
 347 <tr class="row-odd"><th class="head">Ring Type</th>
 348 <th class="head">Ring Index Range</th>
 349 </tr>
 350 </thead>
 351 <tbody valign="top">
 352 <tr class="row-even"><td>UDMAP Tx</td>
 353 <td>0 to 47</td>
 354 </tr>
 355 <tr class="row-odd"><td>UDMAP Rx</td>
 356 <td>48 to 95</td>
 357 </tr>
 358 <tr class="row-even"><td>General Purpose</td>
 359 <td>96 to 255</td>
 360 </tr>
 361 </tbody>
 362 </table>
 363 <table border="1" class="docutils">
 364 <colgroup>
 365 <col width="62%" />
 366 <col width="38%" />
 367 </colgroup>
 368 <thead valign="bottom">
 369 <tr class="row-odd"><th class="head">&#160;</th>
 370 <th class="head">Ring Monitor Range</th>
 371 </tr>
 372 </thead>
 373 <tbody valign="top">
 374 <tr class="row-even"><td>Ring Monitors</td>
 375 <td>0 to 31</td>
 376 </tr>
 377 </tbody>
 378 </table>
 379 </div>
 380 <div class="section" id="navigator-subsystem-channel-and-flow-indices">
 381 <span id="pub-soc-am6x-udmap-channel-and-flow-indices"></span><h2>Navigator Subsystem Channel and Flow Indices<a class="headerlink" href="#navigator-subsystem-channel-and-flow-indices" title="Permalink to this headline">¶</a></h2>
 382 <p>This section describes valid Navigator Subsystem UDMAP transmit channel
 383 and receive channel indices for each Navigator UDMAP channel type. The
 384 receive flow index range has no type information since it’s required for
 385 receive flows.</p>
 386 <div class="admonition warning">
 387 <p class="first admonition-title">Warning</p>
 388 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
 389 host within the RM Board Configuration resource assignment array.  The
 390 RM Board Configuration is rejected if an overlap with a reserved resouce
 391 is detected.</p>
 392 </div>
 393 <p><strong>Main Navigator Subsystem</strong></p>
 394 <table border="1" class="docutils">
 395 <colgroup>
 396 <col width="49%" />
 397 <col width="14%" />
 398 <col width="37%" />
 399 </colgroup>
 400 <thead valign="bottom">
 401 <tr class="row-odd"><th class="head">Tx Channel Type</th>
 402 <th class="head">Type ID</th>
 403 <th class="head">Tx Channel Index Range</th>
 404 </tr>
 405 </thead>
 406 <tbody valign="top">
 407 <tr class="row-even"><td>High Capacity
 408 (<strong>Reserved for use by DMSC</strong>)</td>
 409 <td>1</td>
 410 <td>0</td>
 411 </tr>
 412 <tr class="row-odd"><td>High Capacity</td>
 413 <td>1</td>
 414 <td>1 to 7</td>
 415 </tr>
 416 <tr class="row-even"><td>Standard</td>
 417 <td>0</td>
 418 <td>8 to 119</td>
 419 </tr>
 420 <tr class="row-odd"><td>External</td>
 421 <td>2</td>
 422 <td>120 to 151</td>
 423 </tr>
 424 </tbody>
 425 </table>
 426 <table border="1" class="docutils">
 427 <colgroup>
 428 <col width="49%" />
 429 <col width="14%" />
 430 <col width="37%" />
 431 </colgroup>
 432 <thead valign="bottom">
 433 <tr class="row-odd"><th class="head">Rx Channel Type</th>
 434 <th class="head">Type ID</th>
 435 <th class="head">Rx Channel Index Range</th>
 436 </tr>
 437 </thead>
 438 <tbody valign="top">
 439 <tr class="row-even"><td>High Capacity
 440 (<strong>Reserved for use by DMSC</strong>)</td>
 441 <td>1</td>
 442 <td>0 to 1</td>
 443 </tr>
 444 <tr class="row-odd"><td>High Capacity</td>
 445 <td>1</td>
 446 <td>2 to 7</td>
 447 </tr>
 448 <tr class="row-even"><td>Standard</td>
 449 <td>0</td>
 450 <td>8 to 149</td>
 451 </tr>
 452 </tbody>
 453 </table>
 454 <table border="1" class="docutils">
 455 <colgroup>
 456 <col width="42%" />
 457 <col width="28%" />
 458 <col width="30%" />
 459 </colgroup>
 460 <thead valign="bottom">
 461 <tr class="row-odd"><th class="head">Rx Flow Type</th>
 462 <th class="head">Rx Flow Index Range</th>
 463 <th class="head">Description</th>
 464 </tr>
 465 </thead>
 466 <tbody valign="top">
 467 <tr class="row-even"><td>Static
 468 (<strong>Reserved for use by DMSC</strong>)</td>
 469 <td>0 to 1</td>
 470 <td>Receive flows
 471 statically mapped to
 472 receive channels</td>
 473 </tr>
 474 <tr class="row-odd"><td>Static</td>
 475 <td>2 to 149</td>
 476 <td>Receive flows
 477 statically mapped to
 478 receive channels</td>
 479 </tr>
 480 <tr class="row-even"><td>Common flows</td>
 481 <td>150 to 299</td>
 482 <td>Receive flows usable
 483 in receive channel
 484 flow range register</td>
 485 </tr>
 486 </tbody>
 487 </table>
 488 <p><strong>MCU Navigator Subsystem</strong></p>
 489 <table border="1" class="docutils">
 490 <colgroup>
 491 <col width="34%" />
 492 <col width="18%" />
 493 <col width="48%" />
 494 </colgroup>
 495 <thead valign="bottom">
 496 <tr class="row-odd"><th class="head">Tx Channel Type</th>
 497 <th class="head">Type ID</th>
 498 <th class="head">Tx Channel Index Range</th>
 499 </tr>
 500 </thead>
 501 <tbody valign="top">
 502 <tr class="row-even"><td>High Capacity</td>
 503 <td>1</td>
 504 <td>0 to 1</td>
 505 </tr>
 506 <tr class="row-odd"><td>Standard</td>
 507 <td>0</td>
 508 <td>2 to 47</td>
 509 </tr>
 510 </tbody>
 511 </table>
 512 <table border="1" class="docutils">
 513 <colgroup>
 514 <col width="34%" />
 515 <col width="18%" />
 516 <col width="48%" />
 517 </colgroup>
 518 <thead valign="bottom">
 519 <tr class="row-odd"><th class="head">Rx Channel Type</th>
 520 <th class="head">Type ID</th>
 521 <th class="head">Rx Channel Index Range</th>
 522 </tr>
 523 </thead>
 524 <tbody valign="top">
 525 <tr class="row-even"><td>High Capacity</td>
 526 <td>1</td>
 527 <td>0 to 1</td>
 528 </tr>
 529 <tr class="row-odd"><td>Standard</td>
 530 <td>0</td>
 531 <td>2 to 47</td>
 532 </tr>
 533 </tbody>
 534 </table>
 535 <table border="1" class="docutils">
 536 <colgroup>
 537 <col width="100%" />
 538 </colgroup>
 539 <thead valign="bottom">
 540 <tr class="row-odd"><th class="head">Rx Flow Index Range</th>
 541 </tr>
 542 </thead>
 543 <tbody valign="top">
 544 <tr class="row-even"><td>0 to 95</td>
 545 </tr>
 546 </tbody>
 547 </table>
 548 </div>
 549 <div class="section" id="navigator-subsystem-virtual-interrupts">
 550 <span id="pub-soc-am6x-vints"></span><h2>Navigator Subsystem Virtual Interrupts<a class="headerlink" href="#navigator-subsystem-virtual-interrupts" title="Permalink to this headline">¶</a></h2>
 551 <p>This section describes Navigator Subsystem virtual interrupts.  The virtual
 552 interrupts are used in interrupt management based TISCI messages.</p>
 553 <div class="admonition warning">
 554 <p class="first admonition-title">Warning</p>
 555 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
 556 host within the RM Board Configuration resource assignment array.  The
 557 RM Board Configuration is rejected if an overlap with a reserved resouce
 558 is detected.</p>
 559 </div>
 560 <table border="1" class="docutils">
 561 <colgroup>
 562 <col width="55%" />
 563 <col width="24%" />
 564 <col width="21%" />
 565 </colgroup>
 566 <thead valign="bottom">
 567 <tr class="row-odd"><th class="head">IA Name</th>
 568 <th class="head">IA Device ID</th>
 569 <th class="head">VINT Range</th>
 570 </tr>
 571 </thead>
 572 <tbody valign="top">
 573 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
 574 (<strong>Reserved for use by DMSC</strong>)</td>
 575 <td>179</td>
 576 <td>0 - 15</td>
 577 </tr>
 578 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
 579 <td>179</td>
 580 <td>16 - 255</td>
 581 </tr>
 582 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
 583 <td>180</td>
 584 <td>0 - 63</td>
 585 </tr>
 586 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
 587 <td>181</td>
 588 <td>0 - 63</td>
 589 </tr>
 590 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
 591 (<strong>Reserved for use by DMSC</strong>)</td>
 592 <td>189</td>
 593 <td>0 - 7</td>
 594 </tr>
 595 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
 596 <td>189</td>
 597 <td>8 - 255</td>
 598 </tr>
 599 </tbody>
 600 </table>
 601 </div>
 602 <div class="section" id="navigator-subsystem-global-events">
 603 <span id="pub-soc-am6x-global-events"></span><h2>Navigator Subsystem Global Events<a class="headerlink" href="#navigator-subsystem-global-events" title="Permalink to this headline">¶</a></h2>
 604 <p>This section describes Navigator Subsystem global events.  The global
 605 events are used in Interrupt management based TISCI messages.</p>
 606 <div class="admonition warning">
 607 <p class="first admonition-title">Warning</p>
 608 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
 609 host within the RM Board Configuration resource assignment array.  The
 610 RM Board Configuration is rejected if an overlap with a reserved resouce
 611 is detected.</p>
 612 </div>
 613 <table border="1" class="docutils">
 614 <colgroup>
 615 <col width="44%" />
 616 <col width="29%" />
 617 <col width="27%" />
 618 </colgroup>
 619 <thead valign="bottom">
 620 <tr class="row-odd"><th class="head">Global Event Destination</th>
 621 <th class="head">Global Event Offset</th>
 622 <th class="head">Global Event Count</th>
 623 </tr>
 624 </thead>
 625 <tbody valign="top">
 626 <tr class="row-even"><td>Main NavSS UDMASS IA0 SEVI
 627 (<strong>Reserved for use by DMSC</strong>)</td>
 628 <td>0</td>
 629 <td>16</td>
 630 </tr>
 631 <tr class="row-odd"><td>Main NavSS UDMASS IA0 SEVI</td>
 632 <td>16</td>
 633 <td>4592</td>
 634 </tr>
 635 <tr class="row-even"><td>MCU NavSS UDMASS IA0 SEVI
 636 (<strong>Reserved for use by DMSC</strong>)</td>
 637 <td>16384</td>
 638 <td>8</td>
 639 </tr>
 640 <tr class="row-odd"><td>MCU NavSS UDMASS IA0 SEVI</td>
 641 <td>16392</td>
 642 <td>1528</td>
 643 </tr>
 644 <tr class="row-even"><td>Main NavSS MODSS IA0 SEVI</td>
 645 <td>20480</td>
 646 <td>1024</td>
 647 </tr>
 648 <tr class="row-odd"><td>Main NavSS MODSS IA1 SEVI</td>
 649 <td>22528</td>
 650 <td>1024</td>
 651 </tr>
 652 <tr class="row-even"><td>Main NavSS UDMASS IA0 MEVI</td>
 653 <td>32768</td>
 654 <td>512</td>
 655 </tr>
 656 <tr class="row-odd"><td>MCU NavSS UDMASS IA0 MEVI</td>
 657 <td>34816</td>
 658 <td>128</td>
 659 </tr>
 660 <tr class="row-even"><td>Main NavSS UDMASS IA0 GEVI</td>
 661 <td>36864</td>
 662 <td>512</td>
 663 </tr>
 664 <tr class="row-odd"><td>MCU NavSS UDMASS IA0 GEVI</td>
 665 <td>39936</td>
 666 <td>256</td>
 667 </tr>
 668 <tr class="row-even"><td>Main NavSS MCRC LEVI</td>
 669 <td>43008</td>
 670 <td>4</td>
 671 </tr>
 672 <tr class="row-odd"><td>MCU NavSS MCRC LEVI</td>
 673 <td>43136</td>
 674 <td>4</td>
 675 </tr>
 676 <tr class="row-even"><td>Main NavSS UDMAP Trigger</td>
 677 <td>49152</td>
 678 <td>1024</td>
 679 </tr>
 680 <tr class="row-odd"><td>MCU NavSS UDMAP Trigger</td>
 681 <td>56320</td>
 682 <td>256</td>
 683 </tr>
 684 <tr class="row-even"><td>MSMC DRU</td>
 685 <td>61440</td>
 686 <td>64</td>
 687 </tr>
 688 </tbody>
 689 </table>
 690 </div>
 691 <div class="section" id="navigator-subsystem-psi-l-source-and-destination-thread-ids">
 692 <span id="pub-soc-am6x-psil-thread-ids"></span><h2>Navigator Subsystem PSI-L Source and Destination Thread IDs<a class="headerlink" href="#navigator-subsystem-psi-l-source-and-destination-thread-ids" title="Permalink to this headline">¶</a></h2>
 693 <p>This section describes valid Navigator Subsystem PSI-L source and
 694 destination thread IDs for each thread type. The thread IDs are used in
 695 the PSI-L based TISCI messages.</p>
 696 <div class="admonition warning">
 697 <p class="first admonition-title">Warning</p>
 698 <p class="last">PSI-L threads marked as reserved for use by DMSC <strong>cannot</strong> be assigned
 699 be linked to another thread.</p>
 700 </div>
 701 <table border="1" class="docutils">
 702 <colgroup>
 703 <col width="63%" />
 704 <col width="37%" />
 705 </colgroup>
 706 <thead valign="bottom">
 707 <tr class="row-odd"><th class="head">Source Thread ID Type</th>
 708 <th class="head">Source Thread ID Range</th>
 709 </tr>
 710 </thead>
 711 <tbody valign="top">
 712 <tr class="row-even"><td>Main NavSS UDMAP0 Threads (Tx channels)
 713 (<strong>Reserved for use by DMSC</strong>)</td>
 714 <td>0x1000</td>
 715 </tr>
 716 <tr class="row-odd"><td>Main NavSS UDMAP0 Threads (Tx channels)</td>
 717 <td>0x1001 to 0x1077</td>
 718 </tr>
 719 <tr class="row-even"><td>Main NavSS SAUL0
 720 (<strong>Reserved for use by DMSC</strong>)</td>
 721 <td>0x4000</td>
 722 </tr>
 723 <tr class="row-odd"><td>Main NavSS SAUL0</td>
 724 <td>0x4001 to 0x4003</td>
 725 </tr>
 726 <tr class="row-even"><td>Main NavSS ICSSG0</td>
 727 <td>0x4100 to 0x4113</td>
 728 </tr>
 729 <tr class="row-odd"><td>Main NavSS ICSSG1</td>
 730 <td>0x4200 to 0x4213</td>
 731 </tr>
 732 <tr class="row-even"><td>Main NavSS ICSSG2</td>
 733 <td>0x4300 to 0x4313</td>
 734 </tr>
 735 <tr class="row-odd"><td>Main NavSS PDMA Main 0</td>
 736 <td>0x4400 to 0x443F</td>
 737 </tr>
 738 <tr class="row-even"><td>Main NavSS PDMA Main 1</td>
 739 <td>0x4500 to 0x453F</td>
 740 </tr>
 741 <tr class="row-odd"><td>Main NavSS PDMA Debug</td>
 742 <td>0x4600 to 0x463F</td>
 743 </tr>
 744 <tr class="row-even"><td>Main NavSS CAL0</td>
 745 <td>0x4700 to 0x4707</td>
 746 </tr>
 747 <tr class="row-odd"><td>Main NavSS MSMC0</td>
 748 <td>0x4800 to 0x483F</td>
 749 </tr>
 750 <tr class="row-even"><td>MCU NavSS UDMAP0 Threads (Tx channels)</td>
 751 <td>0x6000 to 0x602F</td>
 752 </tr>
 753 <tr class="row-odd"><td>MCU NavSS CPSW0</td>
 754 <td>0x7000 to 0x7000</td>
 755 </tr>
 756 <tr class="row-even"><td>MCU NavSS PDMA MCU 0</td>
 757 <td>0x7100 to 0x713F</td>
 758 </tr>
 759 <tr class="row-odd"><td>MCU NavSS PDMA MCU 1</td>
 760 <td>0x7200 to 0x723F</td>
 761 </tr>
 762 </tbody>
 763 </table>
 764 <table border="1" class="docutils">
 765 <colgroup>
 766 <col width="59%" />
 767 <col width="41%" />
 768 </colgroup>
 769 <thead valign="bottom">
 770 <tr class="row-odd"><th class="head">Destination Thread ID Type</th>
 771 <th class="head">Destination Thread ID Range</th>
 772 </tr>
 773 </thead>
 774 <tbody valign="top">
 775 <tr class="row-even"><td>Main NavSS UDMAP0 Threads (Rx channels)
 776 (<strong>Reserved for use by DMSC</strong>)</td>
 777 <td>0x9000 to 0x9001</td>
 778 </tr>
 779 <tr class="row-odd"><td>Main NavSS UDMAP0 Threads (Rx channels)</td>
 780 <td>0x9002 to 0x9095</td>
 781 </tr>
 782 <tr class="row-even"><td>Main NavSS SAUL0
 783 (<strong>Reserved for use by DMSC</strong>)</td>
 784 <td>0xC000</td>
 785 </tr>
 786 <tr class="row-odd"><td>Main NavSS SAUL0</td>
 787 <td>0xC001</td>
 788 </tr>
 789 <tr class="row-even"><td>Main NavSS ICSSG0</td>
 790 <td>0xC100 to 0xC10F</td>
 791 </tr>
 792 <tr class="row-odd"><td>Main NavSS ICSSG1</td>
 793 <td>0xC200 to 0xC20F</td>
 794 </tr>
 795 <tr class="row-even"><td>Main NavSS ICSSG2</td>
 796 <td>0xC300 to 0xC30F</td>
 797 </tr>
 798 <tr class="row-odd"><td>Main NavSS PDMA Main 0</td>
 799 <td>0xC400 to 0xC43F</td>
 800 </tr>
 801 <tr class="row-even"><td>Main NavSS PDMA Main 1</td>
 802 <td>0xC500 to 0xC53F</td>
 803 </tr>
 804 <tr class="row-odd"><td>Main NavSS PDMA Debug</td>
 805 <td>0xC600 to 0xC63F</td>
 806 </tr>
 807 <tr class="row-even"><td>Main NavSS MSMC0</td>
 808 <td>0xC800 to 0xC83F</td>
 809 </tr>
 810 <tr class="row-odd"><td>MCU NavSS UDMAP0 Threads (Rx channels)</td>
 811 <td>0xE000 to 0xE02F</td>
 812 </tr>
 813 <tr class="row-even"><td>MCU NavSS CPSW0</td>
 814 <td>0xF000 to 0xF007</td>
 815 </tr>
 816 <tr class="row-odd"><td>MCU NavSS PDMA MCU 0</td>
 817 <td>0xF100 to 0xF13F</td>
 818 </tr>
 819 <tr class="row-even"><td>MCU NavSS PDMA MCU 1</td>
 820 <td>0xF200 to 0xF23F</td>
 821 </tr>
 822 </tbody>
 823 </table>
 824 </div>
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