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 176 <h1>J721E Secure Proxy Descriptions<a class="headerlink" href="#j721e-secure-proxy-descriptions" title="Permalink to this headline">¶</a></h1>
 177 <div class="section" id="introduction">
 178 <span id="soc-doc-j721e-public-sproxy-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 179 <p>This chapter provides information of Secure Proxies and communication paths
 180 that are permitted in the J721E SoC. These host IDs represent processing entities
 181 (or PEs) which is mandatory identification of a Host in a processor. See
 182 PE/Host documentation for further information</p>
 183 </div>
 184 <div class="section" id="enumeration-of-secure-proxies">
 185 <span id="soc-doc-j721e-public-sproxy-desc-sproxy-list"></span><h2>Enumeration of Secure Proxies<a class="headerlink" href="#enumeration-of-secure-proxies" title="Permalink to this headline">¶</a></h2>
 186 <table border="1" class="docutils">
 187 <colgroup>
 188 <col width="35%" />
 189 <col width="65%" />
 190 </colgroup>
 191 <thead valign="bottom">
 192 <tr class="row-odd"><th class="head">Sproxy ID</th>
 193 <th class="head">Sproxy Name</th>
 194 </tr>
 195 </thead>
 196 <tbody valign="top">
 197 <tr class="row-even"><td>0</td>
 198 <td>NAVSS0_SEC_PROXY_0</td>
 199 </tr>
 200 <tr class="row-odd"><td>1</td>
 201 <td>MCU_NAVSS0_SEC_PROXY_0</td>
 202 </tr>
 203 </tbody>
 204 </table>
 205 </div>
 206 <div class="section" id="thread-allocation-per-secure-proxy">
 207 <span id="soc-doc-j721e-public-sproxy-desc-sproxy-per-list"></span><h2>Thread Allocation per Secure Proxy<a class="headerlink" href="#thread-allocation-per-secure-proxy" title="Permalink to this headline">¶</a></h2>
 208 <div class="section" id="secure-proxy-thread-allocation-for-navss0-sec-proxy-0">
 209 <span id="soc-doc-j721e-public-sproxy-desc-sproxy-per-list-navss0-sec-proxy-0"></span><h3>Secure Proxy thread allocation for NAVSS0_SEC_PROXY_0<a class="headerlink" href="#secure-proxy-thread-allocation-for-navss0-sec-proxy-0" title="Permalink to this headline">¶</a></h3>
 210 <table border="1" class="docutils">
 211 <colgroup>
 212 <col width="10%" />
 213 <col width="11%" />
 214 <col width="8%" />
 215 <col width="5%" />
 216 <col width="7%" />
 217 <col width="29%" />
 218 <col width="29%" />
 219 </colgroup>
 220 <thead valign="bottom">
 221 <tr class="row-odd"><th class="head">Secure Proxy Thread ID</th>
 222 <th class="head">Direction (write or read)</th>
 223 <th class="head">Number of Messages</th>
 224 <th class="head">Host</th>
 225 <th class="head">Host Function</th>
 226 <th class="head">IRQ (threshold)</th>
 227 <th class="head">IRQ (error)</th>
 228 </tr>
 229 </thead>
 230 <tbody valign="top">
 231 <tr class="row-even"><td>0</td>
 232 <td>read</td>
 233 <td>2</td>
 234 <td>A72_0</td>
 235 <td>notify</td>
 236 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_64, COMPUTE_CLUSTER0_GIC500SS/SPI_64</td>
 237 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_64, COMPUTE_CLUSTER0_GIC500SS/SPI_64</td>
 238 </tr>
 239 <tr class="row-odd"><td>1</td>
 240 <td>read</td>
 241 <td>30</td>
 242 <td>A72_0</td>
 243 <td>response</td>
 244 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_65, COMPUTE_CLUSTER0_GIC500SS/SPI_65</td>
 245 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_65, COMPUTE_CLUSTER0_GIC500SS/SPI_65</td>
 246 </tr>
 247 <tr class="row-even"><td>2</td>
 248 <td>write</td>
 249 <td>10</td>
 250 <td>A72_0</td>
 251 <td>high_priority</td>
 252 <td>N/A</td>
 253 <td>N/A</td>
 254 </tr>
 255 <tr class="row-odd"><td>3</td>
 256 <td>write</td>
 257 <td>20</td>
 258 <td>A72_0</td>
 259 <td>low_priority</td>
 260 <td>N/A</td>
 261 <td>N/A</td>
 262 </tr>
 263 <tr class="row-even"><td>4</td>
 264 <td>write</td>
 265 <td>2</td>
 266 <td>A72_0</td>
 267 <td>notify_resp</td>
 268 <td>N/A</td>
 269 <td>N/A</td>
 270 </tr>
 271 <tr class="row-odd"><td>5</td>
 272 <td>read</td>
 273 <td>2</td>
 274 <td>A72_1</td>
 275 <td>notify</td>
 276 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_66, COMPUTE_CLUSTER0_GIC500SS/SPI_66</td>
 277 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_66, COMPUTE_CLUSTER0_GIC500SS/SPI_66</td>
 278 </tr>
 279 <tr class="row-even"><td>6</td>
 280 <td>read</td>
 281 <td>30</td>
 282 <td>A72_1</td>
 283 <td>response</td>
 284 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_67, COMPUTE_CLUSTER0_GIC500SS/SPI_67</td>
 285 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_67, COMPUTE_CLUSTER0_GIC500SS/SPI_67</td>
 286 </tr>
 287 <tr class="row-odd"><td>7</td>
 288 <td>write</td>
 289 <td>10</td>
 290 <td>A72_1</td>
 291 <td>high_priority</td>
 292 <td>N/A</td>
 293 <td>N/A</td>
 294 </tr>
 295 <tr class="row-even"><td>8</td>
 296 <td>write</td>
 297 <td>20</td>
 298 <td>A72_1</td>
 299 <td>low_priority</td>
 300 <td>N/A</td>
 301 <td>N/A</td>
 302 </tr>
 303 <tr class="row-odd"><td>9</td>
 304 <td>write</td>
 305 <td>2</td>
 306 <td>A72_1</td>
 307 <td>notify_resp</td>
 308 <td>N/A</td>
 309 <td>N/A</td>
 310 </tr>
 311 <tr class="row-even"><td>10</td>
 312 <td>read</td>
 313 <td>2</td>
 314 <td>A72_2</td>
 315 <td>notify</td>
 316 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_68, COMPUTE_CLUSTER0_GIC500SS/SPI_68</td>
 317 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_68, COMPUTE_CLUSTER0_GIC500SS/SPI_68</td>
 318 </tr>
 319 <tr class="row-odd"><td>11</td>
 320 <td>read</td>
 321 <td>22</td>
 322 <td>A72_2</td>
 323 <td>response</td>
 324 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_69, COMPUTE_CLUSTER0_GIC500SS/SPI_69</td>
 325 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_69, COMPUTE_CLUSTER0_GIC500SS/SPI_69</td>
 326 </tr>
 327 <tr class="row-even"><td>12</td>
 328 <td>write</td>
 329 <td>2</td>
 330 <td>A72_2</td>
 331 <td>high_priority</td>
 332 <td>N/A</td>
 333 <td>N/A</td>
 334 </tr>
 335 <tr class="row-odd"><td>13</td>
 336 <td>write</td>
 337 <td>20</td>
 338 <td>A72_2</td>
 339 <td>low_priority</td>
 340 <td>N/A</td>
 341 <td>N/A</td>
 342 </tr>
 343 <tr class="row-even"><td>14</td>
 344 <td>write</td>
 345 <td>2</td>
 346 <td>A72_2</td>
 347 <td>notify_resp</td>
 348 <td>N/A</td>
 349 <td>N/A</td>
 350 </tr>
 351 <tr class="row-odd"><td>15</td>
 352 <td>read</td>
 353 <td>2</td>
 354 <td>A72_3</td>
 355 <td>notify</td>
 356 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_70, COMPUTE_CLUSTER0_GIC500SS/SPI_70</td>
 357 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_70, COMPUTE_CLUSTER0_GIC500SS/SPI_70</td>
 358 </tr>
 359 <tr class="row-even"><td>16</td>
 360 <td>read</td>
 361 <td>7</td>
 362 <td>A72_3</td>
 363 <td>response</td>
 364 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_71, COMPUTE_CLUSTER0_GIC500SS/SPI_71</td>
 365 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_71, COMPUTE_CLUSTER0_GIC500SS/SPI_71</td>
 366 </tr>
 367 <tr class="row-odd"><td>17</td>
 368 <td>write</td>
 369 <td>2</td>
 370 <td>A72_3</td>
 371 <td>high_priority</td>
 372 <td>N/A</td>
 373 <td>N/A</td>
 374 </tr>
 375 <tr class="row-even"><td>18</td>
 376 <td>write</td>
 377 <td>5</td>
 378 <td>A72_3</td>
 379 <td>low_priority</td>
 380 <td>N/A</td>
 381 <td>N/A</td>
 382 </tr>
 383 <tr class="row-odd"><td>19</td>
 384 <td>write</td>
 385 <td>2</td>
 386 <td>A72_3</td>
 387 <td>notify_resp</td>
 388 <td>N/A</td>
 389 <td>N/A</td>
 390 </tr>
 391 <tr class="row-even"><td>20</td>
 392 <td>read</td>
 393 <td>2</td>
 394 <td>A72_4</td>
 395 <td>notify</td>
 396 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_72, COMPUTE_CLUSTER0_GIC500SS/SPI_72</td>
 397 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_72, COMPUTE_CLUSTER0_GIC500SS/SPI_72</td>
 398 </tr>
 399 <tr class="row-odd"><td>21</td>
 400 <td>read</td>
 401 <td>7</td>
 402 <td>A72_4</td>
 403 <td>response</td>
 404 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_73, COMPUTE_CLUSTER0_GIC500SS/SPI_73</td>
 405 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_73, COMPUTE_CLUSTER0_GIC500SS/SPI_73</td>
 406 </tr>
 407 <tr class="row-even"><td>22</td>
 408 <td>write</td>
 409 <td>2</td>
 410 <td>A72_4</td>
 411 <td>high_priority</td>
 412 <td>N/A</td>
 413 <td>N/A</td>
 414 </tr>
 415 <tr class="row-odd"><td>23</td>
 416 <td>write</td>
 417 <td>5</td>
 418 <td>A72_4</td>
 419 <td>low_priority</td>
 420 <td>N/A</td>
 421 <td>N/A</td>
 422 </tr>
 423 <tr class="row-even"><td>24</td>
 424 <td>write</td>
 425 <td>2</td>
 426 <td>A72_4</td>
 427 <td>notify_resp</td>
 428 <td>N/A</td>
 429 <td>N/A</td>
 430 </tr>
 431 <tr class="row-odd"><td>25</td>
 432 <td>read</td>
 433 <td>2</td>
 434 <td>C7X_0</td>
 435 <td>notify</td>
 436 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_734, COMPUTE_CLUSTER0_GIC500SS/SPI_734</td>
 437 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_734, COMPUTE_CLUSTER0_GIC500SS/SPI_734</td>
 438 </tr>
 439 <tr class="row-even"><td>26</td>
 440 <td>read</td>
 441 <td>7</td>
 442 <td>C7X_0</td>
 443 <td>response</td>
 444 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_735, COMPUTE_CLUSTER0_GIC500SS/SPI_735</td>
 445 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_735, COMPUTE_CLUSTER0_GIC500SS/SPI_735</td>
 446 </tr>
 447 <tr class="row-odd"><td>27</td>
 448 <td>write</td>
 449 <td>2</td>
 450 <td>C7X_0</td>
 451 <td>high_priority</td>
 452 <td>N/A</td>
 453 <td>N/A</td>
 454 </tr>
 455 <tr class="row-even"><td>28</td>
 456 <td>write</td>
 457 <td>5</td>
 458 <td>C7X_0</td>
 459 <td>low_priority</td>
 460 <td>N/A</td>
 461 <td>N/A</td>
 462 </tr>
 463 <tr class="row-odd"><td>29</td>
 464 <td>write</td>
 465 <td>2</td>
 466 <td>C7X_0</td>
 467 <td>notify_resp</td>
 468 <td>N/A</td>
 469 <td>N/A</td>
 470 </tr>
 471 <tr class="row-even"><td>30</td>
 472 <td>read</td>
 473 <td>2</td>
 474 <td>C7X_1</td>
 475 <td>notify</td>
 476 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_732, COMPUTE_CLUSTER0_GIC500SS/SPI_732</td>
 477 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_732, COMPUTE_CLUSTER0_GIC500SS/SPI_732</td>
 478 </tr>
 479 <tr class="row-odd"><td>31</td>
 480 <td>read</td>
 481 <td>7</td>
 482 <td>C7X_1</td>
 483 <td>response</td>
 484 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_733, COMPUTE_CLUSTER0_GIC500SS/SPI_733</td>
 485 <td>COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_733, COMPUTE_CLUSTER0_GIC500SS/SPI_733</td>
 486 </tr>
 487 <tr class="row-even"><td>32</td>
 488 <td>write</td>
 489 <td>2</td>
 490 <td>C7X_1</td>
 491 <td>high_priority</td>
 492 <td>N/A</td>
 493 <td>N/A</td>
 494 </tr>
 495 <tr class="row-odd"><td>33</td>
 496 <td>write</td>
 497 <td>5</td>
 498 <td>C7X_1</td>
 499 <td>low_priority</td>
 500 <td>N/A</td>
 501 <td>N/A</td>
 502 </tr>
 503 <tr class="row-even"><td>34</td>
 504 <td>write</td>
 505 <td>2</td>
 506 <td>C7X_1</td>
 507 <td>notify_resp</td>
 508 <td>N/A</td>
 509 <td>N/A</td>
 510 </tr>
 511 <tr class="row-odd"><td>35</td>
 512 <td>read</td>
 513 <td>2</td>
 514 <td>C6X_0_0</td>
 515 <td>notify</td>
 516 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_4</td>
 517 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_4</td>
 518 </tr>
 519 <tr class="row-even"><td>36</td>
 520 <td>read</td>
 521 <td>7</td>
 522 <td>C6X_0_0</td>
 523 <td>response</td>
 524 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_5</td>
 525 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_5</td>
 526 </tr>
 527 <tr class="row-odd"><td>37</td>
 528 <td>write</td>
 529 <td>2</td>
 530 <td>C6X_0_0</td>
 531 <td>high_priority</td>
 532 <td>N/A</td>
 533 <td>N/A</td>
 534 </tr>
 535 <tr class="row-even"><td>38</td>
 536 <td>write</td>
 537 <td>5</td>
 538 <td>C6X_0_0</td>
 539 <td>low_priority</td>
 540 <td>N/A</td>
 541 <td>N/A</td>
 542 </tr>
 543 <tr class="row-odd"><td>39</td>
 544 <td>write</td>
 545 <td>2</td>
 546 <td>C6X_0_0</td>
 547 <td>notify_resp</td>
 548 <td>N/A</td>
 549 <td>N/A</td>
 550 </tr>
 551 <tr class="row-even"><td>40</td>
 552 <td>read</td>
 553 <td>2</td>
 554 <td>C6X_0_1</td>
 555 <td>notify</td>
 556 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_6</td>
 557 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_6</td>
 558 </tr>
 559 <tr class="row-odd"><td>41</td>
 560 <td>read</td>
 561 <td>7</td>
 562 <td>C6X_0_1</td>
 563 <td>response</td>
 564 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_7</td>
 565 <td>C66SS0_CORE0/C66_EVENT_IN_SYNC_7</td>
 566 </tr>
 567 <tr class="row-even"><td>42</td>
 568 <td>write</td>
 569 <td>2</td>
 570 <td>C6X_0_1</td>
 571 <td>high_priority</td>
 572 <td>N/A</td>
 573 <td>N/A</td>
 574 </tr>
 575 <tr class="row-odd"><td>43</td>
 576 <td>write</td>
 577 <td>5</td>
 578 <td>C6X_0_1</td>
 579 <td>low_priority</td>
 580 <td>N/A</td>
 581 <td>N/A</td>
 582 </tr>
 583 <tr class="row-even"><td>44</td>
 584 <td>write</td>
 585 <td>2</td>
 586 <td>C6X_0_1</td>
 587 <td>notify_resp</td>
 588 <td>N/A</td>
 589 <td>N/A</td>
 590 </tr>
 591 <tr class="row-odd"><td>45</td>
 592 <td>read</td>
 593 <td>2</td>
 594 <td>C6X_1_0</td>
 595 <td>notify</td>
 596 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_4</td>
 597 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_4</td>
 598 </tr>
 599 <tr class="row-even"><td>46</td>
 600 <td>read</td>
 601 <td>7</td>
 602 <td>C6X_1_0</td>
 603 <td>response</td>
 604 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_5</td>
 605 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_5</td>
 606 </tr>
 607 <tr class="row-odd"><td>47</td>
 608 <td>write</td>
 609 <td>2</td>
 610 <td>C6X_1_0</td>
 611 <td>high_priority</td>
 612 <td>N/A</td>
 613 <td>N/A</td>
 614 </tr>
 615 <tr class="row-even"><td>48</td>
 616 <td>write</td>
 617 <td>5</td>
 618 <td>C6X_1_0</td>
 619 <td>low_priority</td>
 620 <td>N/A</td>
 621 <td>N/A</td>
 622 </tr>
 623 <tr class="row-odd"><td>49</td>
 624 <td>write</td>
 625 <td>2</td>
 626 <td>C6X_1_0</td>
 627 <td>notify_resp</td>
 628 <td>N/A</td>
 629 <td>N/A</td>
 630 </tr>
 631 <tr class="row-even"><td>50</td>
 632 <td>read</td>
 633 <td>2</td>
 634 <td>C6X_1_1</td>
 635 <td>notify</td>
 636 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_6</td>
 637 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_6</td>
 638 </tr>
 639 <tr class="row-odd"><td>51</td>
 640 <td>read</td>
 641 <td>7</td>
 642 <td>C6X_1_1</td>
 643 <td>response</td>
 644 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_7</td>
 645 <td>C66SS1_CORE0/C66_EVENT_IN_SYNC_7</td>
 646 </tr>
 647 <tr class="row-even"><td>52</td>
 648 <td>write</td>
 649 <td>2</td>
 650 <td>C6X_1_1</td>
 651 <td>high_priority</td>
 652 <td>N/A</td>
 653 <td>N/A</td>
 654 </tr>
 655 <tr class="row-odd"><td>53</td>
 656 <td>write</td>
 657 <td>5</td>
 658 <td>C6X_1_1</td>
 659 <td>low_priority</td>
 660 <td>N/A</td>
 661 <td>N/A</td>
 662 </tr>
 663 <tr class="row-even"><td>54</td>
 664 <td>write</td>
 665 <td>2</td>
 666 <td>C6X_1_1</td>
 667 <td>notify_resp</td>
 668 <td>N/A</td>
 669 <td>N/A</td>
 670 </tr>
 671 <tr class="row-odd"><td>55</td>
 672 <td>read</td>
 673 <td>2</td>
 674 <td>GPU_0</td>
 675 <td>notify</td>
 676 <td>N/A</td>
 677 <td>N/A</td>
 678 </tr>
 679 <tr class="row-even"><td>56</td>
 680 <td>read</td>
 681 <td>7</td>
 682 <td>GPU_0</td>
 683 <td>response</td>
 684 <td>N/A</td>
 685 <td>N/A</td>
 686 </tr>
 687 <tr class="row-odd"><td>57</td>
 688 <td>write</td>
 689 <td>2</td>
 690 <td>GPU_0</td>
 691 <td>high_priority</td>
 692 <td>N/A</td>
 693 <td>N/A</td>
 694 </tr>
 695 <tr class="row-even"><td>58</td>
 696 <td>write</td>
 697 <td>5</td>
 698 <td>GPU_0</td>
 699 <td>low_priority</td>
 700 <td>N/A</td>
 701 <td>N/A</td>
 702 </tr>
 703 <tr class="row-odd"><td>59</td>
 704 <td>write</td>
 705 <td>2</td>
 706 <td>GPU_0</td>
 707 <td>notify_resp</td>
 708 <td>N/A</td>
 709 <td>N/A</td>
 710 </tr>
 711 <tr class="row-even"><td>60</td>
 712 <td>read</td>
 713 <td>2</td>
 714 <td>MAIN_0_R5_0</td>
 715 <td>notify</td>
 716 <td>R5FSS0_CORE0/INTR_224</td>
 717 <td>R5FSS0_CORE0/INTR_224</td>
 718 </tr>
 719 <tr class="row-odd"><td>61</td>
 720 <td>read</td>
 721 <td>7</td>
 722 <td>MAIN_0_R5_0</td>
 723 <td>response</td>
 724 <td>R5FSS0_CORE0/INTR_225</td>
 725 <td>R5FSS0_CORE0/INTR_225</td>
 726 </tr>
 727 <tr class="row-even"><td>62</td>
 728 <td>write</td>
 729 <td>2</td>
 730 <td>MAIN_0_R5_0</td>
 731 <td>high_priority</td>
 732 <td>N/A</td>
 733 <td>N/A</td>
 734 </tr>
 735 <tr class="row-odd"><td>63</td>
 736 <td>write</td>
 737 <td>5</td>
 738 <td>MAIN_0_R5_0</td>
 739 <td>low_priority</td>
 740 <td>N/A</td>
 741 <td>N/A</td>
 742 </tr>
 743 <tr class="row-even"><td>64</td>
 744 <td>write</td>
 745 <td>2</td>
 746 <td>MAIN_0_R5_0</td>
 747 <td>notify_resp</td>
 748 <td>N/A</td>
 749 <td>N/A</td>
 750 </tr>
 751 <tr class="row-odd"><td>65</td>
 752 <td>read</td>
 753 <td>2</td>
 754 <td>MAIN_0_R5_1</td>
 755 <td>notify</td>
 756 <td>R5FSS0_CORE0/INTR_226</td>
 757 <td>R5FSS0_CORE0/INTR_226</td>
 758 </tr>
 759 <tr class="row-even"><td>66</td>
 760 <td>read</td>
 761 <td>7</td>
 762 <td>MAIN_0_R5_1</td>
 763 <td>response</td>
 764 <td>R5FSS0_CORE0/INTR_227</td>
 765 <td>R5FSS0_CORE0/INTR_227</td>
 766 </tr>
 767 <tr class="row-odd"><td>67</td>
 768 <td>write</td>
 769 <td>2</td>
 770 <td>MAIN_0_R5_1</td>
 771 <td>high_priority</td>
 772 <td>N/A</td>
 773 <td>N/A</td>
 774 </tr>
 775 <tr class="row-even"><td>68</td>
 776 <td>write</td>
 777 <td>5</td>
 778 <td>MAIN_0_R5_1</td>
 779 <td>low_priority</td>
 780 <td>N/A</td>
 781 <td>N/A</td>
 782 </tr>
 783 <tr class="row-odd"><td>69</td>
 784 <td>write</td>
 785 <td>2</td>
 786 <td>MAIN_0_R5_1</td>
 787 <td>notify_resp</td>
 788 <td>N/A</td>
 789 <td>N/A</td>
 790 </tr>
 791 <tr class="row-even"><td>70</td>
 792 <td>read</td>
 793 <td>1</td>
 794 <td>MAIN_0_R5_2</td>
 795 <td>notify</td>
 796 <td>R5FSS0_CORE1/INTR_224</td>
 797 <td>R5FSS0_CORE1/INTR_224</td>
 798 </tr>
 799 <tr class="row-odd"><td>71</td>
 800 <td>read</td>
 801 <td>2</td>
 802 <td>MAIN_0_R5_2</td>
 803 <td>response</td>
 804 <td>R5FSS0_CORE1/INTR_225</td>
 805 <td>R5FSS0_CORE1/INTR_225</td>
 806 </tr>
 807 <tr class="row-even"><td>72</td>
 808 <td>write</td>
 809 <td>1</td>
 810 <td>MAIN_0_R5_2</td>
 811 <td>high_priority</td>
 812 <td>N/A</td>
 813 <td>N/A</td>
 814 </tr>
 815 <tr class="row-odd"><td>73</td>
 816 <td>write</td>
 817 <td>1</td>
 818 <td>MAIN_0_R5_2</td>
 819 <td>low_priority</td>
 820 <td>N/A</td>
 821 <td>N/A</td>
 822 </tr>
 823 <tr class="row-even"><td>74</td>
 824 <td>write</td>
 825 <td>1</td>
 826 <td>MAIN_0_R5_2</td>
 827 <td>notify_resp</td>
 828 <td>N/A</td>
 829 <td>N/A</td>
 830 </tr>
 831 <tr class="row-odd"><td>75</td>
 832 <td>read</td>
 833 <td>1</td>
 834 <td>MAIN_0_R5_3</td>
 835 <td>notify</td>
 836 <td>R5FSS0_CORE1/INTR_226</td>
 837 <td>R5FSS0_CORE1/INTR_226</td>
 838 </tr>
 839 <tr class="row-even"><td>76</td>
 840 <td>read</td>
 841 <td>2</td>
 842 <td>MAIN_0_R5_3</td>
 843 <td>response</td>
 844 <td>R5FSS0_CORE1/INTR_227</td>
 845 <td>R5FSS0_CORE1/INTR_227</td>
 846 </tr>
 847 <tr class="row-odd"><td>77</td>
 848 <td>write</td>
 849 <td>1</td>
 850 <td>MAIN_0_R5_3</td>
 851 <td>high_priority</td>
 852 <td>N/A</td>
 853 <td>N/A</td>
 854 </tr>
 855 <tr class="row-even"><td>78</td>
 856 <td>write</td>
 857 <td>1</td>
 858 <td>MAIN_0_R5_3</td>
 859 <td>low_priority</td>
 860 <td>N/A</td>
 861 <td>N/A</td>
 862 </tr>
 863 <tr class="row-odd"><td>79</td>
 864 <td>write</td>
 865 <td>1</td>
 866 <td>MAIN_0_R5_3</td>
 867 <td>notify_resp</td>
 868 <td>N/A</td>
 869 <td>N/A</td>
 870 </tr>
 871 <tr class="row-even"><td>80</td>
 872 <td>read</td>
 873 <td>2</td>
 874 <td>MAIN_1_R5_0</td>
 875 <td>notify</td>
 876 <td>R5FSS1_CORE0/INTR_224</td>
 877 <td>R5FSS1_CORE0/INTR_224</td>
 878 </tr>
 879 <tr class="row-odd"><td>81</td>
 880 <td>read</td>
 881 <td>7</td>
 882 <td>MAIN_1_R5_0</td>
 883 <td>response</td>
 884 <td>R5FSS1_CORE0/INTR_225</td>
 885 <td>R5FSS1_CORE0/INTR_225</td>
 886 </tr>
 887 <tr class="row-even"><td>82</td>
 888 <td>write</td>
 889 <td>2</td>
 890 <td>MAIN_1_R5_0</td>
 891 <td>high_priority</td>
 892 <td>N/A</td>
 893 <td>N/A</td>
 894 </tr>
 895 <tr class="row-odd"><td>83</td>
 896 <td>write</td>
 897 <td>5</td>
 898 <td>MAIN_1_R5_0</td>
 899 <td>low_priority</td>
 900 <td>N/A</td>
 901 <td>N/A</td>
 902 </tr>
 903 <tr class="row-even"><td>84</td>
 904 <td>write</td>
 905 <td>2</td>
 906 <td>MAIN_1_R5_0</td>
 907 <td>notify_resp</td>
 908 <td>N/A</td>
 909 <td>N/A</td>
 910 </tr>
 911 <tr class="row-odd"><td>85</td>
 912 <td>read</td>
 913 <td>2</td>
 914 <td>MAIN_1_R5_1</td>
 915 <td>notify</td>
 916 <td>R5FSS1_CORE0/INTR_226</td>
 917 <td>R5FSS1_CORE0/INTR_226</td>
 918 </tr>
 919 <tr class="row-even"><td>86</td>
 920 <td>read</td>
 921 <td>7</td>
 922 <td>MAIN_1_R5_1</td>
 923 <td>response</td>
 924 <td>R5FSS1_CORE0/INTR_227</td>
 925 <td>R5FSS1_CORE0/INTR_227</td>
 926 </tr>
 927 <tr class="row-odd"><td>87</td>
 928 <td>write</td>
 929 <td>2</td>
 930 <td>MAIN_1_R5_1</td>
 931 <td>high_priority</td>
 932 <td>N/A</td>
 933 <td>N/A</td>
 934 </tr>
 935 <tr class="row-even"><td>88</td>
 936 <td>write</td>
 937 <td>5</td>
 938 <td>MAIN_1_R5_1</td>
 939 <td>low_priority</td>
 940 <td>N/A</td>
 941 <td>N/A</td>
 942 </tr>
 943 <tr class="row-odd"><td>89</td>
 944 <td>write</td>
 945 <td>2</td>
 946 <td>MAIN_1_R5_1</td>
 947 <td>notify_resp</td>
 948 <td>N/A</td>
 949 <td>N/A</td>
 950 </tr>
 951 <tr class="row-even"><td>90</td>
 952 <td>read</td>
 953 <td>1</td>
 954 <td>MAIN_1_R5_2</td>
 955 <td>notify</td>
 956 <td>R5FSS1_CORE1/INTR_224</td>
 957 <td>R5FSS1_CORE1/INTR_224</td>
 958 </tr>
 959 <tr class="row-odd"><td>91</td>
 960 <td>read</td>
 961 <td>2</td>
 962 <td>MAIN_1_R5_2</td>
 963 <td>response</td>
 964 <td>R5FSS1_CORE1/INTR_225</td>
 965 <td>R5FSS1_CORE1/INTR_225</td>
 966 </tr>
 967 <tr class="row-even"><td>92</td>
 968 <td>write</td>
 969 <td>1</td>
 970 <td>MAIN_1_R5_2</td>
 971 <td>high_priority</td>
 972 <td>N/A</td>
 973 <td>N/A</td>
 974 </tr>
 975 <tr class="row-odd"><td>93</td>
 976 <td>write</td>
 977 <td>1</td>
 978 <td>MAIN_1_R5_2</td>
 979 <td>low_priority</td>
 980 <td>N/A</td>
 981 <td>N/A</td>
 982 </tr>
 983 <tr class="row-even"><td>94</td>
 984 <td>write</td>
 985 <td>1</td>
 986 <td>MAIN_1_R5_2</td>
 987 <td>notify_resp</td>
 988 <td>N/A</td>
 989 <td>N/A</td>
 990 </tr>
 991 <tr class="row-odd"><td>95</td>
 992 <td>read</td>
 993 <td>1</td>
 994 <td>MAIN_1_R5_3</td>
 995 <td>notify</td>
 996 <td>R5FSS1_CORE1/INTR_226</td>
 997 <td>R5FSS1_CORE1/INTR_226</td>
 998 </tr>
 999 <tr class="row-even"><td>96</td>
1000 <td>read</td>
1001 <td>2</td>
1002 <td>MAIN_1_R5_3</td>
1003 <td>response</td>
1004 <td>R5FSS1_CORE1/INTR_227</td>
1005 <td>R5FSS1_CORE1/INTR_227</td>
1006 </tr>
1007 <tr class="row-odd"><td>97</td>
1008 <td>write</td>
1009 <td>1</td>
1010 <td>MAIN_1_R5_3</td>
1011 <td>high_priority</td>
1012 <td>N/A</td>
1013 <td>N/A</td>
1014 </tr>
1015 <tr class="row-even"><td>98</td>
1016 <td>write</td>
1017 <td>1</td>
1018 <td>MAIN_1_R5_3</td>
1019 <td>low_priority</td>
1020 <td>N/A</td>
1021 <td>N/A</td>
1022 </tr>
1023 <tr class="row-odd"><td>99</td>
1024 <td>write</td>
1025 <td>1</td>
1026 <td>MAIN_1_R5_3</td>
1027 <td>notify_resp</td>
1028 <td>N/A</td>
1029 <td>N/A</td>
1030 </tr>
1031 <tr class="row-even"><td>100</td>
1032 <td>read</td>
1033 <td>2</td>
1034 <td>ICSSG_0</td>
1035 <td>notify</td>
1036 <td>N/A</td>
1037 <td>N/A</td>
1038 </tr>
1039 <tr class="row-odd"><td>101</td>
1040 <td>read</td>
1041 <td>7</td>
1042 <td>ICSSG_0</td>
1043 <td>response</td>
1044 <td>N/A</td>
1045 <td>N/A</td>
1046 </tr>
1047 <tr class="row-even"><td>102</td>
1048 <td>write</td>
1049 <td>2</td>
1050 <td>ICSSG_0</td>
1051 <td>high_priority</td>
1052 <td>N/A</td>
1053 <td>N/A</td>
1054 </tr>
1055 <tr class="row-odd"><td>103</td>
1056 <td>write</td>
1057 <td>5</td>
1058 <td>ICSSG_0</td>
1059 <td>low_priority</td>
1060 <td>N/A</td>
1061 <td>N/A</td>
1062 </tr>
1063 <tr class="row-even"><td>104</td>
1064 <td>write</td>
1065 <td>2</td>
1066 <td>ICSSG_0</td>
1067 <td>notify_resp</td>
1068 <td>N/A</td>
1069 <td>N/A</td>
1070 </tr>
1071 </tbody>
1072 </table>
1073 </div>
1074 <div class="section" id="secure-proxy-thread-allocation-for-mcu-navss0-sec-proxy-0">
1075 <span id="soc-doc-j721e-public-sproxy-desc-sproxy-per-list-mcu-navss0-sec-proxy-0"></span><h3>Secure Proxy thread allocation for MCU_NAVSS0_SEC_PROXY_0<a class="headerlink" href="#secure-proxy-thread-allocation-for-mcu-navss0-sec-proxy-0" title="Permalink to this headline">¶</a></h3>
1076 <table border="1" class="docutils">
1077 <colgroup>
1078 <col width="16%" />
1079 <col width="18%" />
1080 <col width="14%" />
1081 <col width="8%" />
1082 <col width="11%" />
1083 <col width="16%" />
1084 <col width="16%" />
1085 </colgroup>
1086 <thead valign="bottom">
1087 <tr class="row-odd"><th class="head">Secure Proxy Thread ID</th>
1088 <th class="head">Direction (write or read)</th>
1089 <th class="head">Number of Messages</th>
1090 <th class="head">Host</th>
1091 <th class="head">Host Function</th>
1092 <th class="head">IRQ (threshold)</th>
1093 <th class="head">IRQ (error)</th>
1094 </tr>
1095 </thead>
1096 <tbody valign="top">
1097 <tr class="row-even"><td>0</td>
1098 <td>read</td>
1099 <td>2</td>
1100 <td>MCU_0_R5_0</td>
1101 <td>notify</td>
1102 <td>MCU_R5FSS0_CORE0/INTR_64</td>
1103 <td>MCU_R5FSS0_CORE0/INTR_64</td>
1104 </tr>
1105 <tr class="row-odd"><td>1</td>
1106 <td>read</td>
1107 <td>7</td>
1108 <td>MCU_0_R5_0</td>
1109 <td>response</td>
1110 <td>MCU_R5FSS0_CORE0/INTR_65</td>
1111 <td>MCU_R5FSS0_CORE0/INTR_65</td>
1112 </tr>
1113 <tr class="row-even"><td>2</td>
1114 <td>write</td>
1115 <td>2</td>
1116 <td>MCU_0_R5_0</td>
1117 <td>high_priority</td>
1118 <td>N/A</td>
1119 <td>N/A</td>
1120 </tr>
1121 <tr class="row-odd"><td>3</td>
1122 <td>write</td>
1123 <td>5</td>
1124 <td>MCU_0_R5_0</td>
1125 <td>low_priority</td>
1126 <td>N/A</td>
1127 <td>N/A</td>
1128 </tr>
1129 <tr class="row-even"><td>4</td>
1130 <td>write</td>
1131 <td>2</td>
1132 <td>MCU_0_R5_0</td>
1133 <td>notify_resp</td>
1134 <td>N/A</td>
1135 <td>N/A</td>
1136 </tr>
1137 <tr class="row-odd"><td>5</td>
1138 <td>read</td>
1139 <td>2</td>
1140 <td>MCU_0_R5_1</td>
1141 <td>notify</td>
1142 <td>MCU_R5FSS0_CORE0/INTR_66</td>
1143 <td>MCU_R5FSS0_CORE0/INTR_66</td>
1144 </tr>
1145 <tr class="row-even"><td>6</td>
1146 <td>read</td>
1147 <td>7</td>
1148 <td>MCU_0_R5_1</td>
1149 <td>response</td>
1150 <td>MCU_R5FSS0_CORE0/INTR_67</td>
1151 <td>MCU_R5FSS0_CORE0/INTR_67</td>
1152 </tr>
1153 <tr class="row-odd"><td>7</td>
1154 <td>write</td>
1155 <td>2</td>
1156 <td>MCU_0_R5_1</td>
1157 <td>high_priority</td>
1158 <td>N/A</td>
1159 <td>N/A</td>
1160 </tr>
1161 <tr class="row-even"><td>8</td>
1162 <td>write</td>
1163 <td>5</td>
1164 <td>MCU_0_R5_1</td>
1165 <td>low_priority</td>
1166 <td>N/A</td>
1167 <td>N/A</td>
1168 </tr>
1169 <tr class="row-odd"><td>9</td>
1170 <td>write</td>
1171 <td>2</td>
1172 <td>MCU_0_R5_1</td>
1173 <td>notify_resp</td>
1174 <td>N/A</td>
1175 <td>N/A</td>
1176 </tr>
1177 <tr class="row-even"><td>10</td>
1178 <td>read</td>
1179 <td>1</td>
1180 <td>MCU_0_R5_2</td>
1181 <td>notify</td>
1182 <td>MCU_R5FSS0_CORE1/INTR_64</td>
1183 <td>MCU_R5FSS0_CORE1/INTR_64</td>
1184 </tr>
1185 <tr class="row-odd"><td>11</td>
1186 <td>read</td>
1187 <td>2</td>
1188 <td>MCU_0_R5_2</td>
1189 <td>response</td>
1190 <td>MCU_R5FSS0_CORE1/INTR_65</td>
1191 <td>MCU_R5FSS0_CORE1/INTR_65</td>
1192 </tr>
1193 <tr class="row-even"><td>12</td>
1194 <td>write</td>
1195 <td>1</td>
1196 <td>MCU_0_R5_2</td>
1197 <td>high_priority</td>
1198 <td>N/A</td>
1199 <td>N/A</td>
1200 </tr>
1201 <tr class="row-odd"><td>13</td>
1202 <td>write</td>
1203 <td>1</td>
1204 <td>MCU_0_R5_2</td>
1205 <td>low_priority</td>
1206 <td>N/A</td>
1207 <td>N/A</td>
1208 </tr>
1209 <tr class="row-even"><td>14</td>
1210 <td>write</td>
1211 <td>1</td>
1212 <td>MCU_0_R5_2</td>
1213 <td>notify_resp</td>
1214 <td>N/A</td>
1215 <td>N/A</td>
1216 </tr>
1217 <tr class="row-odd"><td>15</td>
1218 <td>read</td>
1219 <td>1</td>
1220 <td>MCU_0_R5_3</td>
1221 <td>notify</td>
1222 <td>MCU_R5FSS0_CORE1/INTR_66</td>
1223 <td>MCU_R5FSS0_CORE1/INTR_66</td>
1224 </tr>
1225 <tr class="row-even"><td>16</td>
1226 <td>read</td>
1227 <td>2</td>
1228 <td>MCU_0_R5_3</td>
1229 <td>response</td>
1230 <td>MCU_R5FSS0_CORE1/INTR_67</td>
1231 <td>MCU_R5FSS0_CORE1/INTR_67</td>
1232 </tr>
1233 <tr class="row-odd"><td>17</td>
1234 <td>write</td>
1235 <td>1</td>
1236 <td>MCU_0_R5_3</td>
1237 <td>high_priority</td>
1238 <td>N/A</td>
1239 <td>N/A</td>
1240 </tr>
1241 <tr class="row-even"><td>18</td>
1242 <td>write</td>
1243 <td>1</td>
1244 <td>MCU_0_R5_3</td>
1245 <td>low_priority</td>
1246 <td>N/A</td>
1247 <td>N/A</td>
1248 </tr>
1249 <tr class="row-odd"><td>19</td>
1250 <td>write</td>
1251 <td>1</td>
1252 <td>MCU_0_R5_3</td>
1253 <td>notify_resp</td>
1254 <td>N/A</td>
1255 <td>N/A</td>
1256 </tr>
1257 </tbody>
1258 </table>
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