1 /*
2 * Copyright (C) 2017-2019 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 /**
34 * \ingroup TISCI
35 * \defgroup tisci_hosts TISCI Hosts
36 *
37 * DMSC controls the power management, security and resource management
38 * of the device.
39 *
40 *
41 * @{
42 */
43 /**
44 *
45 * \brief This file contains:
46 *
47 * WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
48 * System Firmware Source File
49 *
50 * Host IDs for AM6 device
51 *
52 */
54 /**
55 *
56 * \brief Host IDs for AM6 device
57 */
59 #ifndef TISCI_HOSTS_H
60 #define TISCI_HOSTS_H
62 /* Host IDs for AM6 Device */
64 /** DMSC(Secure): Device Management and Security Control */
65 #define TISCI_HOST_ID_DMSC (0U)
66 /** r5_0(Non Secure): Cortex R5 Context 0 on MCU island */
67 #define TISCI_HOST_ID_R5_0 (3U)
68 /** r5_1(Secure): Cortex R5 Context 1 on MCU island(Boot) */
69 #define TISCI_HOST_ID_R5_1 (4U)
70 /** r5_2(Non Secure): Cortex R5 Context 2 on MCU island */
71 #define TISCI_HOST_ID_R5_2 (5U)
72 /** r5_3(Secure): Cortex R5 Context 3 on MCU island */
73 #define TISCI_HOST_ID_R5_3 (6U)
74 /** a53_0(Secure): Cortex A53 context 0 on Main island */
75 #define TISCI_HOST_ID_A53_0 (10U)
76 /** a53_1(Secure): Cortex A53 context 1 on Main island */
77 #define TISCI_HOST_ID_A53_1 (11U)
78 /** a53_2(Non Secure): Cortex A53 context 2 on Main island */
79 #define TISCI_HOST_ID_A53_2 (12U)
80 /** a53_3(Non Secure): Cortex A53 context 3 on Main island */
81 #define TISCI_HOST_ID_A53_3 (13U)
82 /** a53_4(Non Secure): Cortex A53 context 4 on Main island */
83 #define TISCI_HOST_ID_A53_4 (14U)
84 /** a53_5(Non Secure): Cortex A53 context 5 on Main island */
85 #define TISCI_HOST_ID_A53_5 (15U)
86 /** a53_6(Non Secure): Cortex A53 context 6 on Main island */
87 #define TISCI_HOST_ID_A53_6 (16U)
88 /** a53_7(Non Secure): Cortex A53 context 7 on Main island */
89 #define TISCI_HOST_ID_A53_7 (17U)
90 /** gpu_0(Non Secure): SGX544 Context 0 on Main island */
91 #define TISCI_HOST_ID_GPU_0 (30U)
92 /** gpu_1(Non Secure): SGX544 Context 1 on Main island */
93 #define TISCI_HOST_ID_GPU_1 (31U)
94 /** icssg_0(Non Secure): ICSS Context 0 on Main island */
95 #define TISCI_HOST_ID_ICSSG_0 (50U)
96 /** icssg_1(Non Secure): ICSS Context 1 on Main island */
97 #define TISCI_HOST_ID_ICSSG_1 (51U)
98 /** icssg_2(Non Secure): ICSS Context 2 on Main island */
99 #define TISCI_HOST_ID_ICSSG_2 (52U)
101 /**
102 * Host catch all. Used in board configuration resource assignments to
103 * define resource ranges useable by all hosts. Cannot be used
104 */
105 #define TISCI_HOST_ID_ALL (128U)
107 /** Number of unique hosts on the SoC */
108 #define TISCI_HOST_ID_CNT (19U)
110 #endif /* TISCI_HOSTS_H */
112 /* @} */