[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / V1 / sciclient_fmwSecureProxyMap.c
1 /*
2 * Copyright (C) 2018 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 /**
34 * \file sciclient_fmwSecureProxyMap.c
35 *
36 * \brief File containing the secure proxy map for all hosts.
37 *
38 */
39 /* ========================================================================== */
40 /* Include Files */
41 /* ========================================================================== */
43 #include <stdint.h>
44 #include <ti/drv/sciclient/sciclient.h>
45 #include <ti/drv/sciclient/src/sciclient_priv.h>
47 /* ========================================================================== */
48 /* Macros & Typedefs */
49 /* ========================================================================== */
51 /* None */
53 /* ========================================================================== */
54 /* Structure Declarations */
55 /* ========================================================================== */
57 /* None */
59 /* ========================================================================== */
60 /* Function Declarations */
61 /* ========================================================================== */
63 /* None */
65 /* ========================================================================== */
66 /* Global Variables */
67 /* ========================================================================== */
69 const Sciclient_MapStruct_t gSciclientMap[SCICLIENT_CONTEXT_MAX_NUM] =
70 {
71 {
72 /** Context **/
73 SCICLIENT_NON_SECURE_CONTEXT,
74 /** CPU ID of the A53/A72/R5F/DSP */
75 TISCI_HOST_ID_R5_0,
76 /** Thread ID of the high priority thread(write) allowed for the CPU */
77 TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_HIGH_PRIORITY_THREAD_ID,
78 /** Thread ID of the low priority thread(write) allowed for the CPU */
79 TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID,
80 /** Thread ID of the thread(write) for sending a notification to the firmware */
81 TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_NOTIFY_RESP_THREAD_ID,
82 /** Thread ID of the response thread(read) available for the CPU */
83 TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_THREAD_ID,
84 /** Thread ID of the notification thread(read) available for the CPU */
85 TISCI_SEC_PROXY_MCU_0_R5_0_READ_NOTIFY_THREAD_ID,
86 /** Notification Interrupt Number. */
87 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_1
88 },
89 {
90 /** Context **/
91 SCICLIENT_SECURE_CONTEXT,
92 /** CPU ID of the A53/A72/R5F/DSP */
93 TISCI_HOST_ID_R5_1,
94 /** Thread ID of the high priority thread(write) allowed for the CPU */
95 TISCI_SEC_PROXY_MCU_0_R5_1_WRITE_HIGH_PRIORITY_THREAD_ID,
96 /** Thread ID of the low priority thread(write) allowed for the CPU */
97 TISCI_SEC_PROXY_MCU_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID,
98 /** Thread ID of the thread(write) for sending a notification to the firmware */
99 TISCI_SEC_PROXY_MCU_0_R5_1_WRITE_NOTIFY_RESP_THREAD_ID,
100 /** Thread ID of the response thread(read) available for the CPU */
101 TISCI_SEC_PROXY_MCU_0_R5_1_READ_RESPONSE_THREAD_ID,
102 /** Thread ID of the notification thread(read) available for the CPU */
103 TISCI_SEC_PROXY_MCU_0_R5_1_READ_NOTIFY_THREAD_ID,
104 /** Notification Interrupt Number. */
105 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_3
106 },
107 {
108 /** Context **/
109 SCICLIENT_NON_SECURE_CONTEXT,
110 /** CPU ID of the A53/A72/R5F/DSP */
111 TISCI_HOST_ID_R5_2,
112 /** Thread ID of the high priority thread(write) allowed for the CPU */
113 TISCI_SEC_PROXY_MCU_0_R5_2_WRITE_HIGH_PRIORITY_THREAD_ID,
114 /** Thread ID of the low priority thread(write) allowed for the CPU */
115 TISCI_SEC_PROXY_MCU_0_R5_2_WRITE_LOW_PRIORITY_THREAD_ID,
116 /** Thread ID of the thread(write) for sending a notification to the firmware */
117 TISCI_SEC_PROXY_MCU_0_R5_2_WRITE_NOTIFY_RESP_THREAD_ID,
118 /** Thread ID of the response thread(read) available for the CPU */
119 TISCI_SEC_PROXY_MCU_0_R5_2_READ_RESPONSE_THREAD_ID,
120 /** Thread ID of the notification thread(read) available for the CPU */
121 TISCI_SEC_PROXY_MCU_0_R5_2_READ_NOTIFY_THREAD_ID,
122 /** Notification Interrupt Number. */
123 CSLR_MCU_R5FSS0_CORE1_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_33
124 },
125 {
126 /** Context **/
127 SCICLIENT_SECURE_CONTEXT,
128 /** CPU ID of the A53/A72/R5F/DSP */
129 TISCI_HOST_ID_R5_3,
130 /** Thread ID of the high priority thread(write) allowed for the CPU */
131 TISCI_SEC_PROXY_MCU_0_R5_3_WRITE_HIGH_PRIORITY_THREAD_ID,
132 /** Thread ID of the low priority thread(write) allowed for the CPU */
133 TISCI_SEC_PROXY_MCU_0_R5_3_WRITE_LOW_PRIORITY_THREAD_ID,
134 /** Thread ID of the thread(write) for sending a notification to the firmware */
135 TISCI_SEC_PROXY_MCU_0_R5_3_WRITE_NOTIFY_RESP_THREAD_ID,
136 /** Thread ID of the response thread(read) available for the CPU */
137 TISCI_SEC_PROXY_MCU_0_R5_3_READ_RESPONSE_THREAD_ID,
138 /** Thread ID of the notification thread(read) available for the CPU */
139 TISCI_SEC_PROXY_MCU_0_R5_3_READ_NOTIFY_THREAD_ID,
140 /** Notification Interrupt Number. */
141 CSLR_MCU_R5FSS0_CORE1_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_35
142 },
143 {
144 /** Context **/
145 SCICLIENT_SECURE_CONTEXT,
146 /** CPU ID of the A53/A72/R5F/DSP */
147 TISCI_HOST_ID_A72_0,
148 /** Thread ID of the high priority thread(write) allowed for the CPU */
149 TISCI_SEC_PROXY_A72_0_WRITE_HIGH_PRIORITY_THREAD_ID,
150 /** Thread ID of the low priority thread(write) allowed for the CPU */
151 TISCI_SEC_PROXY_A72_0_WRITE_LOW_PRIORITY_THREAD_ID,
152 /** Thread ID of the thread(write) for sending a notification to the firmware */
153 TISCI_SEC_PROXY_A72_0_WRITE_NOTIFY_RESP_THREAD_ID,
154 /** Thread ID of the response thread(read) available for the CPU */
155 TISCI_SEC_PROXY_A72_0_READ_RESPONSE_THREAD_ID,
156 /** Thread ID of the notification thread(read) available for the CPU */
157 TISCI_SEC_PROXY_A72_0_READ_NOTIFY_THREAD_ID,
158 /** Notification Interrupt Number. */
159 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_1
160 },
161 {
162 /** Context **/
163 SCICLIENT_SECURE_CONTEXT,
164 /** CPU ID of the A53/A72/R5F/DSP */
165 TISCI_HOST_ID_A72_1,
166 /** Thread ID of the high priority thread(write) allowed for the CPU */
167 TISCI_SEC_PROXY_A72_1_WRITE_HIGH_PRIORITY_THREAD_ID,
168 /** Thread ID of the low priority thread(write) allowed for the CPU */
169 TISCI_SEC_PROXY_A72_1_WRITE_LOW_PRIORITY_THREAD_ID,
170 /** Thread ID of the thread(write) for sending a notification to the firmware */
171 TISCI_SEC_PROXY_A72_1_WRITE_NOTIFY_RESP_THREAD_ID,
172 /** Thread ID of the response thread(read) available for the CPU */
173 TISCI_SEC_PROXY_A72_1_READ_RESPONSE_THREAD_ID,
174 /** Thread ID of the notification thread(read) available for the CPU */
175 TISCI_SEC_PROXY_A72_1_READ_NOTIFY_THREAD_ID,
176 /** Notification Interrupt Number. */
177 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_3
178 },
179 {
180 /** Context **/
181 SCICLIENT_NON_SECURE_CONTEXT,
182 /** CPU ID of the A53/A72/R5F/DSP */
183 TISCI_HOST_ID_A72_2,
184 /** Thread ID of the high priority thread(write) allowed for the CPU */
185 TISCI_SEC_PROXY_A72_2_WRITE_HIGH_PRIORITY_THREAD_ID,
186 /** Thread ID of the low priority thread(write) allowed for the CPU */
187 TISCI_SEC_PROXY_A72_2_WRITE_LOW_PRIORITY_THREAD_ID,
188 /** Thread ID of the thread(write) for sending a notification to the firmware */
189 TISCI_SEC_PROXY_A72_2_WRITE_NOTIFY_RESP_THREAD_ID,
190 /** Thread ID of the response thread(read) available for the CPU */
191 TISCI_SEC_PROXY_A72_2_READ_RESPONSE_THREAD_ID,
192 /** Thread ID of the notification thread(read) available for the CPU */
193 TISCI_SEC_PROXY_A72_2_READ_NOTIFY_THREAD_ID,
194 /** Notification Interrupt Number. */
195 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_5
196 },
197 {
198 /** Context **/
199 SCICLIENT_NON_SECURE_CONTEXT,
200 /** CPU ID of the A53/A72/R5F/DSP */
201 TISCI_HOST_ID_A72_3,
202 /** Thread ID of the high priority thread(write) allowed for the CPU */
203 TISCI_SEC_PROXY_A72_3_WRITE_HIGH_PRIORITY_THREAD_ID,
204 /** Thread ID of the low priority thread(write) allowed for the CPU */
205 TISCI_SEC_PROXY_A72_3_WRITE_LOW_PRIORITY_THREAD_ID,
206 /** Thread ID of the thread(write) for sending a notification to the firmware */
207 TISCI_SEC_PROXY_A72_3_WRITE_NOTIFY_RESP_THREAD_ID,
208 /** Thread ID of the response thread(read) available for the CPU */
209 TISCI_SEC_PROXY_A72_3_READ_RESPONSE_THREAD_ID,
210 /** Thread ID of the notification thread(read) available for the CPU */
211 TISCI_SEC_PROXY_A72_3_READ_NOTIFY_THREAD_ID,
212 /** Notification Interrupt Number. */
213 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_7
214 },
215 {
216 /** Context **/
217 SCICLIENT_NON_SECURE_CONTEXT,
218 /** CPU ID of the A53/A72/R5F/DSP */
219 TISCI_HOST_ID_A72_4,
220 /** Thread ID of the high priority thread(write) allowed for the CPU */
221 TISCI_SEC_PROXY_A72_4_WRITE_HIGH_PRIORITY_THREAD_ID,
222 /** Thread ID of the low priority thread(write) allowed for the CPU */
223 TISCI_SEC_PROXY_A72_4_WRITE_LOW_PRIORITY_THREAD_ID,
224 /** Thread ID of the thread(write) for sending a notification to the firmware */
225 TISCI_SEC_PROXY_A72_4_WRITE_NOTIFY_RESP_THREAD_ID,
226 /** Thread ID of the response thread(read) available for the CPU */
227 TISCI_SEC_PROXY_A72_4_READ_RESPONSE_THREAD_ID,
228 /** Thread ID of the notification thread(read) available for the CPU */
229 TISCI_SEC_PROXY_A72_4_READ_NOTIFY_THREAD_ID,
230 /** Notification Interrupt Number. */
231 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_9
232 },
233 {
234 /** Context **/
235 SCICLIENT_SECURE_CONTEXT,
236 /** CPU ID of the A53/A72/R5F/DSP */
237 TISCI_HOST_ID_C7X_0,
238 /** Thread ID of the high priority thread(write) allowed for the CPU */
239 TISCI_SEC_PROXY_C7X_0_WRITE_HIGH_PRIORITY_THREAD_ID,
240 /** Thread ID of the low priority thread(write) allowed for the CPU */
241 TISCI_SEC_PROXY_C7X_0_WRITE_LOW_PRIORITY_THREAD_ID,
242 /** Thread ID of the thread(write) for sending a notification to the firmware */
243 TISCI_SEC_PROXY_C7X_0_WRITE_NOTIFY_RESP_THREAD_ID,
244 /** Thread ID of the response thread(read) available for the CPU */
245 TISCI_SEC_PROXY_C7X_0_READ_RESPONSE_THREAD_ID,
246 /** Thread ID of the notification thread(read) available for the CPU */
247 TISCI_SEC_PROXY_C7X_0_READ_NOTIFY_THREAD_ID,
248 /** Notification Interrupt Number. */
249 SCICLIENT_C7X_SECURE_INTERRUPT_NUM
250 },
251 {
252 /** Context **/
253 SCICLIENT_NON_SECURE_CONTEXT,
254 /** CPU ID of the A53/A72/R5F/DSP */
255 TISCI_HOST_ID_C7X_1,
256 /** Thread ID of the high priority thread(write) allowed for the CPU */
257 TISCI_SEC_PROXY_C7X_1_WRITE_HIGH_PRIORITY_THREAD_ID,
258 /** Thread ID of the low priority thread(write) allowed for the CPU */
259 TISCI_SEC_PROXY_C7X_1_WRITE_LOW_PRIORITY_THREAD_ID,
260 /** Thread ID of the thread(write) for sending a notification to the firmware */
261 TISCI_SEC_PROXY_C7X_1_WRITE_NOTIFY_RESP_THREAD_ID,
262 /** Thread ID of the response thread(read) available for the CPU */
263 TISCI_SEC_PROXY_C7X_1_READ_RESPONSE_THREAD_ID,
264 /** Thread ID of the notification thread(read) available for the CPU */
265 TISCI_SEC_PROXY_C7X_1_READ_NOTIFY_THREAD_ID,
266 /** Notification Interrupt Number. */
267 SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM
268 },
269 {
270 /** Context **/
271 SCICLIENT_SECURE_CONTEXT,
272 /** CPU ID of the A53/A72/R5F/DSP */
273 TISCI_HOST_ID_C6X_0_0,
274 /** Thread ID of the high priority thread(write) allowed for the CPU */
275 TISCI_SEC_PROXY_C6X_0_0_WRITE_HIGH_PRIORITY_THREAD_ID,
276 /** Thread ID of the low priority thread(write) allowed for the CPU */
277 TISCI_SEC_PROXY_C6X_0_0_WRITE_LOW_PRIORITY_THREAD_ID,
278 /** Thread ID of the thread(write) for sending a notification to the firmware */
279 TISCI_SEC_PROXY_C6X_0_0_WRITE_NOTIFY_RESP_THREAD_ID,
280 /** Thread ID of the response thread(read) available for the CPU */
281 TISCI_SEC_PROXY_C6X_0_0_READ_RESPONSE_THREAD_ID,
282 /** Thread ID of the notification thread(read) available for the CPU */
283 TISCI_SEC_PROXY_C6X_0_0_READ_NOTIFY_THREAD_ID,
284 /** Notification Interrupt Number. */
285 5U
286 },
287 {
288 /** Context **/
289 SCICLIENT_NON_SECURE_CONTEXT,
290 /** CPU ID of the A53/A72/R5F/DSP */
291 TISCI_HOST_ID_C6X_0_1,
292 /** Thread ID of the high priority thread(write) allowed for the CPU */
293 TISCI_SEC_PROXY_C6X_0_1_WRITE_HIGH_PRIORITY_THREAD_ID,
294 /** Thread ID of the low priority thread(write) allowed for the CPU */
295 TISCI_SEC_PROXY_C6X_0_1_WRITE_LOW_PRIORITY_THREAD_ID,
296 /** Thread ID of the thread(write) for sending a notification to the firmware */
297 TISCI_SEC_PROXY_C6X_0_1_WRITE_NOTIFY_RESP_THREAD_ID,
298 /** Thread ID of the response thread(read) available for the CPU */
299 TISCI_SEC_PROXY_C6X_0_1_READ_RESPONSE_THREAD_ID,
300 /** Thread ID of the notification thread(read) available for the CPU */
301 TISCI_SEC_PROXY_C6X_0_1_READ_NOTIFY_THREAD_ID,
302 /** Notification Interrupt Number. */
303 7U
304 },
305 {
306 /** Context **/
307 SCICLIENT_SECURE_CONTEXT,
308 /** CPU ID of the A53/A72/R5F/DSP */
309 TISCI_HOST_ID_C6X_1_0,
310 /** Thread ID of the high priority thread(write) allowed for the CPU */
311 TISCI_SEC_PROXY_C6X_1_0_WRITE_HIGH_PRIORITY_THREAD_ID,
312 /** Thread ID of the low priority thread(write) allowed for the CPU */
313 TISCI_SEC_PROXY_C6X_1_0_WRITE_LOW_PRIORITY_THREAD_ID,
314 /** Thread ID of the thread(write) for sending a notification to the firmware */
315 TISCI_SEC_PROXY_C6X_1_0_WRITE_NOTIFY_RESP_THREAD_ID,
316 /** Thread ID of the response thread(read) available for the CPU */
317 TISCI_SEC_PROXY_C6X_1_0_READ_RESPONSE_THREAD_ID,
318 /** Thread ID of the notification thread(read) available for the CPU */
319 TISCI_SEC_PROXY_C6X_1_0_READ_NOTIFY_THREAD_ID,
320 /** Notification Interrupt Number. */
321 5U
322 },
323 {
324 /** Context **/
325 SCICLIENT_NON_SECURE_CONTEXT,
326 /** CPU ID of the A53/A72/R5F/DSP */
327 TISCI_HOST_ID_C6X_1_1,
328 /** Thread ID of the high priority thread(write) allowed for the CPU */
329 TISCI_SEC_PROXY_C6X_1_1_WRITE_HIGH_PRIORITY_THREAD_ID,
330 /** Thread ID of the low priority thread(write) allowed for the CPU */
331 TISCI_SEC_PROXY_C6X_1_1_WRITE_LOW_PRIORITY_THREAD_ID,
332 /** Thread ID of the thread(write) for sending a notification to the firmware */
333 TISCI_SEC_PROXY_C6X_1_1_WRITE_NOTIFY_RESP_THREAD_ID,
334 /** Thread ID of the response thread(read) available for the CPU */
335 TISCI_SEC_PROXY_C6X_1_1_READ_RESPONSE_THREAD_ID,
336 /** Thread ID of the notification thread(read) available for the CPU */
337 TISCI_SEC_PROXY_C6X_1_1_READ_NOTIFY_THREAD_ID,
338 /** Notification Interrupt Number. */
339 7U
340 },
341 {
342 /** Context **/
343 SCICLIENT_NON_SECURE_CONTEXT,
344 /** CPU ID of the A53/A72/R5F/DSP */
345 TISCI_HOST_ID_GPU_0,
346 /** Thread ID of the high priority thread(write) allowed for the CPU */
347 TISCI_SEC_PROXY_GPU_0_WRITE_HIGH_PRIORITY_THREAD_ID,
348 /** Thread ID of the low priority thread(write) allowed for the CPU */
349 TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_THREAD_ID,
350 /** Thread ID of the thread(write) for sending a notification to the firmware */
351 TISCI_SEC_PROXY_GPU_0_WRITE_NOTIFY_RESP_THREAD_ID,
352 /** Thread ID of the response thread(read) available for the CPU */
353 TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_THREAD_ID,
354 /** Thread ID of the notification thread(read) available for the CPU */
355 TISCI_SEC_PROXY_GPU_0_READ_NOTIFY_THREAD_ID,
356 /** Notification Interrupt Number. */
357 0
358 },
359 {
360 /** Context **/
361 SCICLIENT_NON_SECURE_CONTEXT,
362 /** CPU ID of the A53/A72/R5F/DSP */
363 TISCI_HOST_ID_MAIN_0_R5_0,
364 /** Thread ID of the high priority thread(write) allowed for the CPU */
365 TISCI_SEC_PROXY_MAIN_0_R5_0_WRITE_HIGH_PRIORITY_THREAD_ID,
366 /** Thread ID of the low priority thread(write) allowed for the CPU */
367 TISCI_SEC_PROXY_MAIN_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID,
368 /** Thread ID of the thread(write) for sending a notification to the firmware */
369 TISCI_SEC_PROXY_MAIN_0_R5_0_WRITE_NOTIFY_RESP_THREAD_ID,
370 /** Thread ID of the response thread(read) available for the CPU */
371 TISCI_SEC_PROXY_MAIN_0_R5_0_READ_RESPONSE_THREAD_ID,
372 /** Thread ID of the notification thread(read) available for the CPU */
373 TISCI_SEC_PROXY_MAIN_0_R5_0_READ_NOTIFY_THREAD_ID,
374 /** Notification Interrupt Number. */
375 CSLR_R5FSS0_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_193
376 },
377 {
378 /** Context **/
379 SCICLIENT_SECURE_CONTEXT,
380 /** CPU ID of the A53/A72/R5F/DSP */
381 TISCI_HOST_ID_MAIN_0_R5_1,
382 /** Thread ID of the high priority thread(write) allowed for the CPU */
383 TISCI_SEC_PROXY_MAIN_0_R5_1_WRITE_HIGH_PRIORITY_THREAD_ID,
384 /** Thread ID of the low priority thread(write) allowed for the CPU */
385 TISCI_SEC_PROXY_MAIN_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID,
386 /** Thread ID of the thread(write) for sending a notification to the firmware */
387 TISCI_SEC_PROXY_MAIN_0_R5_1_WRITE_NOTIFY_RESP_THREAD_ID,
388 /** Thread ID of the response thread(read) available for the CPU */
389 TISCI_SEC_PROXY_MAIN_0_R5_1_READ_RESPONSE_THREAD_ID,
390 /** Thread ID of the notification thread(read) available for the CPU */
391 TISCI_SEC_PROXY_MAIN_0_R5_1_READ_NOTIFY_THREAD_ID,
392 /** Notification Interrupt Number. */
393 CSLR_R5FSS0_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_195
394 },
395 {
396 /** Context **/
397 SCICLIENT_NON_SECURE_CONTEXT,
398 /** CPU ID of the A53/A72/R5F/DSP */
399 TISCI_HOST_ID_MAIN_0_R5_2,
400 /** Thread ID of the high priority thread(write) allowed for the CPU */
401 TISCI_SEC_PROXY_MAIN_0_R5_2_WRITE_HIGH_PRIORITY_THREAD_ID,
402 /** Thread ID of the low priority thread(write) allowed for the CPU */
403 TISCI_SEC_PROXY_MAIN_0_R5_2_WRITE_LOW_PRIORITY_THREAD_ID,
404 /** Thread ID of the thread(write) for sending a notification to the firmware */
405 TISCI_SEC_PROXY_MAIN_0_R5_2_WRITE_NOTIFY_RESP_THREAD_ID,
406 /** Thread ID of the response thread(read) available for the CPU */
407 TISCI_SEC_PROXY_MAIN_0_R5_2_READ_RESPONSE_THREAD_ID,
408 /** Thread ID of the notification thread(read) available for the CPU */
409 TISCI_SEC_PROXY_MAIN_0_R5_2_READ_NOTIFY_THREAD_ID,
410 /** Notification Interrupt Number. */
411 CSLR_R5FSS0_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_225
412 },
413 {
414 /** Context **/
415 SCICLIENT_SECURE_CONTEXT,
416 /** CPU ID of the A53/A72/R5F/DSP */
417 TISCI_HOST_ID_MAIN_0_R5_3,
418 /** Thread ID of the high priority thread(write) allowed for the CPU */
419 TISCI_SEC_PROXY_MAIN_0_R5_3_WRITE_HIGH_PRIORITY_THREAD_ID,
420 /** Thread ID of the low priority thread(write) allowed for the CPU */
421 TISCI_SEC_PROXY_MAIN_0_R5_3_WRITE_LOW_PRIORITY_THREAD_ID,
422 /** Thread ID of the thread(write) for sending a notification to the firmware */
423 TISCI_SEC_PROXY_MAIN_0_R5_3_WRITE_NOTIFY_RESP_THREAD_ID,
424 /** Thread ID of the response thread(read) available for the CPU */
425 TISCI_SEC_PROXY_MAIN_0_R5_3_READ_RESPONSE_THREAD_ID,
426 /** Thread ID of the notification thread(read) available for the CPU */
427 TISCI_SEC_PROXY_MAIN_0_R5_3_READ_NOTIFY_THREAD_ID,
428 /** Notification Interrupt Number. */
429 CSLR_R5FSS0_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_227
430 },
431 {
432 /** Context **/
433 SCICLIENT_NON_SECURE_CONTEXT,
434 /** CPU ID of the A53/A72/R5F/DSP */
435 TISCI_HOST_ID_MAIN_1_R5_0,
436 /** Thread ID of the high priority thread(write) allowed for the CPU */
437 TISCI_SEC_PROXY_MAIN_1_R5_0_WRITE_HIGH_PRIORITY_THREAD_ID,
438 /** Thread ID of the low priority thread(write) allowed for the CPU */
439 TISCI_SEC_PROXY_MAIN_1_R5_0_WRITE_LOW_PRIORITY_THREAD_ID,
440 /** Thread ID of the thread(write) for sending a notification to the firmware */
441 TISCI_SEC_PROXY_MAIN_1_R5_0_WRITE_NOTIFY_RESP_THREAD_ID,
442 /** Thread ID of the response thread(read) available for the CPU */
443 TISCI_SEC_PROXY_MAIN_1_R5_0_READ_RESPONSE_THREAD_ID,
444 /** Thread ID of the notification thread(read) available for the CPU */
445 TISCI_SEC_PROXY_MAIN_1_R5_0_READ_NOTIFY_THREAD_ID,
446 /** Notification Interrupt Number. */
447 CSLR_R5FSS1_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_257
448 },
449 {
450 /** Context **/
451 SCICLIENT_SECURE_CONTEXT,
452 /** CPU ID of the A53/A72/R5F/DSP */
453 TISCI_HOST_ID_MAIN_1_R5_1,
454 /** Thread ID of the high priority thread(write) allowed for the CPU */
455 TISCI_SEC_PROXY_MAIN_1_R5_1_WRITE_HIGH_PRIORITY_THREAD_ID,
456 /** Thread ID of the low priority thread(write) allowed for the CPU */
457 TISCI_SEC_PROXY_MAIN_1_R5_1_WRITE_LOW_PRIORITY_THREAD_ID,
458 /** Thread ID of the thread(write) for sending a notification to the firmware */
459 TISCI_SEC_PROXY_MAIN_1_R5_1_WRITE_NOTIFY_RESP_THREAD_ID,
460 /** Thread ID of the response thread(read) available for the CPU */
461 TISCI_SEC_PROXY_MAIN_1_R5_1_READ_RESPONSE_THREAD_ID,
462 /** Thread ID of the notification thread(read) available for the CPU */
463 TISCI_SEC_PROXY_MAIN_1_R5_1_READ_NOTIFY_THREAD_ID,
464 /** Notification Interrupt Number. */
465 CSLR_R5FSS1_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_259
466 },
467 {
468 /** Context **/
469 SCICLIENT_NON_SECURE_CONTEXT,
470 /** CPU ID of the A53/A72/R5F/DSP */
471 TISCI_HOST_ID_MAIN_1_R5_2,
472 /** Thread ID of the high priority thread(write) allowed for the CPU */
473 TISCI_SEC_PROXY_MAIN_1_R5_2_WRITE_HIGH_PRIORITY_THREAD_ID,
474 /** Thread ID of the low priority thread(write) allowed for the CPU */
475 TISCI_SEC_PROXY_MAIN_1_R5_2_WRITE_LOW_PRIORITY_THREAD_ID,
476 /** Thread ID of the thread(write) for sending a notification to the firmware */
477 TISCI_SEC_PROXY_MAIN_1_R5_2_WRITE_NOTIFY_RESP_THREAD_ID,
478 /** Thread ID of the response thread(read) available for the CPU */
479 TISCI_SEC_PROXY_MAIN_1_R5_2_READ_RESPONSE_THREAD_ID,
480 /** Thread ID of the notification thread(read) available for the CPU */
481 TISCI_SEC_PROXY_MAIN_1_R5_2_READ_NOTIFY_THREAD_ID,
482 /** Notification Interrupt Number. */
483 CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_289
484 },
485 {
486 /** Context **/
487 SCICLIENT_SECURE_CONTEXT,
488 /** CPU ID of the A53/A72/R5F/DSP */
489 TISCI_HOST_ID_MAIN_1_R5_3,
490 /** Thread ID of the high priority thread(write) allowed for the CPU */
491 TISCI_SEC_PROXY_MAIN_1_R5_3_WRITE_HIGH_PRIORITY_THREAD_ID,
492 /** Thread ID of the low priority thread(write) allowed for the CPU */
493 TISCI_SEC_PROXY_MAIN_1_R5_3_WRITE_LOW_PRIORITY_THREAD_ID,
494 /** Thread ID of the thread(write) for sending a notification to the firmware */
495 TISCI_SEC_PROXY_MAIN_1_R5_3_WRITE_NOTIFY_RESP_THREAD_ID,
496 /** Thread ID of the response thread(read) available for the CPU */
497 TISCI_SEC_PROXY_MAIN_1_R5_3_READ_RESPONSE_THREAD_ID,
498 /** Thread ID of the notification thread(read) available for the CPU */
499 TISCI_SEC_PROXY_MAIN_1_R5_3_READ_NOTIFY_THREAD_ID,
500 /** Notification Interrupt Number. */
501 CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_291
502 },
503 {
504 /** Context **/
505 SCICLIENT_NON_SECURE_CONTEXT,
506 /** CPU ID of the A53/A72/R5F/DSP */
507 TISCI_HOST_ID_ICSSG_0,
508 /** Thread ID of the high priority thread(write) allowed for the CPU */
509 TISCI_SEC_PROXY_ICSSG_0_WRITE_HIGH_PRIORITY_THREAD_ID,
510 /** Thread ID of the low priority thread(write) allowed for the CPU */
511 TISCI_SEC_PROXY_ICSSG_0_WRITE_LOW_PRIORITY_THREAD_ID,
512 /** Thread ID of the thread(write) for sending a notification to the firmware */
513 TISCI_SEC_PROXY_ICSSG_0_WRITE_NOTIFY_RESP_THREAD_ID,
514 /** Thread ID of the response thread(read) available for the CPU */
515 TISCI_SEC_PROXY_ICSSG_0_READ_RESPONSE_THREAD_ID,
516 /** Thread ID of the notification thread(read) available for the CPU */
517 TISCI_SEC_PROXY_ICSSG_0_READ_NOTIFY_THREAD_ID,
518 /** Notification Interrupt Number. */
519 0
520 }
521 };