7ba0faed8c654a455128c060f8c500d63f4d6674
[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / V2 / sciclient_defaultBoardcfg_rm.c
1 /*
2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 * Copyright (c) 2020, Texas Instruments Incorporated
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
33 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35 /**
36 * \file V2/sciclient_defaultBoardcfg.c
37 *
38 * \brief File containing the boardcfg default data structure to
39 * send TISCI_MSG_BOARD_CONFIG message.
40 *
41 */
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 #include <ti/drv/sciclient/soc/sysfw/include/j7200/tisci_hosts.h>
47 #include <ti/drv/sciclient/soc/sysfw/include/j7200/tisci_boardcfg_constraints.h>
48 #include <ti/drv/sciclient/soc/sysfw/include/j7200/tisci_devices.h>
49 #include <ti/drv/sciclient/soc/V2/sciclient_defaultBoardcfg.h>
51 /* ========================================================================== */
52 /* Global Variables */
53 /* ========================================================================== */
55 #if defined (BUILD_MCU1_0)
56 const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
57 __attribute__(( aligned(128), section(".boardcfg_data") )) =
58 {
59 .rm_boardcfg = {
60 .rev = {
61 .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
62 .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
63 },
64 .host_cfg = {
65 .subhdr = {
66 .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
67 .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
68 },
69 .host_cfg_entries = {
70 {
71 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
72 .allowed_atype = 0b101010,
73 .allowed_qos = 0xAAAA,
74 .allowed_orderid = 0xAAAAAAAA,
75 .allowed_priority = 0xAAAA,
76 .allowed_sched_priority = 0xAA
77 },
78 {
79 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
80 .allowed_atype = 0b101010,
81 .allowed_qos = 0xAAAA,
82 .allowed_orderid = 0xAAAAAAAA,
83 .allowed_priority = 0xAAAA,
84 .allowed_sched_priority = 0xAA
85 },
86 {
87 .host_id = TISCI_HOST_ID_A72_2,
88 .allowed_atype = 0b101010,
89 .allowed_qos = 0xAAAA,
90 .allowed_orderid = 0xAAAAAAAA,
91 .allowed_priority = 0xAAAA,
92 .allowed_sched_priority = 0xAA
93 },
94 {
95 .host_id = TISCI_HOST_ID_A72_3,
96 .allowed_atype = 0b101010,
97 .allowed_qos = 0xAAAA,
98 .allowed_orderid = 0xAAAAAAAA,
99 .allowed_priority = 0xAAAA,
100 .allowed_sched_priority = 0xAA
101 },
102 {
103 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
104 .allowed_atype = 0b101010,
105 .allowed_qos = 0xAAAA,
106 .allowed_orderid = 0xAAAAAAAA,
107 .allowed_priority = 0xAAAA,
108 .allowed_sched_priority = 0xAA
109 },
110 {
111 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
112 .allowed_atype = 0b101010,
113 .allowed_qos = 0xAAAA,
114 .allowed_orderid = 0xAAAAAAAA,
115 .allowed_priority = 0xAAAA,
116 .allowed_sched_priority = 0xAA
117 },
118 },
119 },
120 .resasg = {
121 .subhdr = {
122 .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
123 .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
124 },
125 .resasg_entries_size = 292 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
126 },
127 },
128 .resasg_entries = {
129 {
130 .num_resource = 32,
131 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_LVL_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
132 .start_resource = 0,
133 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
134 },
135 {
136 .num_resource = 32,
137 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_LVL_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
138 .start_resource = 0,
139 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
140 },
141 {
142 .num_resource = 32,
143 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_LVL_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
144 .start_resource = 32,
145 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
146 },
147 {
148 .num_resource = 24,
149 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_PLS_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
150 .start_resource = 0,
151 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
152 },
153 {
154 .num_resource = 24,
155 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_PLS_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
156 .start_resource = 0,
157 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
158 },
159 {
160 .num_resource = 24,
161 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_PLS_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
162 .start_resource = 24,
163 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
164 },
165 {
166 .num_resource = 8,
167 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
168 .start_resource = 0,
169 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
170 },
171 {
172 .num_resource = 8,
173 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
174 .start_resource = 0,
175 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
176 },
177 {
178 .num_resource = 8,
179 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
180 .start_resource = 8,
181 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
182 },
183 {
184 .num_resource = 8,
185 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
186 .start_resource = 16,
187 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
188 },
189 {
190 .num_resource = 8,
191 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
192 .start_resource = 24,
193 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
194 },
195 {
196 .num_resource = 16,
197 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
198 .start_resource = 32,
199 .host_id = TISCI_HOST_ID_A72_2,
200 },
201 {
202 .num_resource = 16,
203 .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
204 .start_resource = 48,
205 .host_id = TISCI_HOST_ID_A72_3,
206 },
207 {
208 .num_resource = 48,
209 .type = TISCI_RESASG_UTYPE (TISCI_DEV_TIMESYNC_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
210 .start_resource = 0,
211 .host_id = TISCI_HOST_ID_ALL,
212 },
213 {
214 .num_resource = 8,
215 .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
216 .start_resource = 0,
217 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
218 },
219 {
220 .num_resource = 8,
221 .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
222 .start_resource = 0,
223 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
224 },
225 {
226 .num_resource = 8,
227 .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
228 .start_resource = 8,
229 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
230 },
231 {
232 .num_resource = 8,
233 .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
234 .start_resource = 16,
235 .host_id = TISCI_HOST_ID_A72_2,
236 },
237 {
238 .num_resource = 8,
239 .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
240 .start_resource = 24,
241 .host_id = TISCI_HOST_ID_A72_3,
242 },
243 {
244 .num_resource = 64,
245 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
246 .start_resource = 0,
247 .host_id = TISCI_HOST_ID_ALL,
248 },
249 {
250 .num_resource = 1024,
251 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
252 .start_resource = 20480,
253 .host_id = TISCI_HOST_ID_ALL,
254 },
255 {
256 .num_resource = 64,
257 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTA_1, TISCI_RESASG_SUBTYPE_IA_VINT),
258 .start_resource = 0,
259 .host_id = TISCI_HOST_ID_ALL,
260 },
261 {
262 .num_resource = 1024,
263 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTA_1, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
264 .start_resource = 22528,
265 .host_id = TISCI_HOST_ID_ALL,
266 },
267 {
268 .num_resource = 86,
269 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
270 .start_resource = 18,
271 .host_id = TISCI_HOST_ID_A72_2,
272 },
273 {
274 .num_resource = 32,
275 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
276 .start_resource = 104,
277 .host_id = TISCI_HOST_ID_A72_3,
278 },
279 {
280 .num_resource = 16,
281 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
282 .start_resource = 136,
283 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
284 },
285 {
286 .num_resource = 16,
287 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
288 .start_resource = 136,
289 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
290 },
291 {
292 .num_resource = 16,
293 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
294 .start_resource = 152,
295 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
296 },
297 {
298 .num_resource = 32,
299 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
300 .start_resource = 168,
301 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
302 },
303 {
304 .num_resource = 24,
305 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
306 .start_resource = 200,
307 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
308 },
309 {
310 .num_resource = 32,
311 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
312 .start_resource = 224,
313 .host_id = TISCI_HOST_ID_ALL,
314 },
315 {
316 .num_resource = 1024,
317 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
318 .start_resource = 18,
319 .host_id = TISCI_HOST_ID_A72_2,
320 },
321 {
322 .num_resource = 512,
323 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
324 .start_resource = 1042,
325 .host_id = TISCI_HOST_ID_A72_3,
326 },
327 {
328 .num_resource = 128,
329 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
330 .start_resource = 1554,
331 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
332 },
333 {
334 .num_resource = 128,
335 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
336 .start_resource = 1554,
337 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
338 },
339 {
340 .num_resource = 128,
341 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
342 .start_resource = 1682,
343 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
344 },
345 {
346 .num_resource = 256,
347 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
348 .start_resource = 1810,
349 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
350 },
351 {
352 .num_resource = 512,
353 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
354 .start_resource = 2066,
355 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
356 },
357 {
358 .num_resource = 2030,
359 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
360 .start_resource = 2578,
361 .host_id = TISCI_HOST_ID_ALL,
362 },
363 {
364 .num_resource = 4,
365 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
366 .start_resource = 0,
367 .host_id = TISCI_HOST_ID_A72_2,
368 },
369 {
370 .num_resource = 4,
371 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
372 .start_resource = 4,
373 .host_id = TISCI_HOST_ID_A72_3,
374 },
375 {
376 .num_resource = 4,
377 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
378 .start_resource = 8,
379 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
380 },
381 {
382 .num_resource = 4,
383 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
384 .start_resource = 8,
385 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
386 },
387 {
388 .num_resource = 4,
389 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
390 .start_resource = 12,
391 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
392 },
393 {
394 .num_resource = 16,
395 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
396 .start_resource = 16,
397 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
398 },
399 {
400 .num_resource = 16,
401 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
402 .start_resource = 32,
403 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
404 },
405 {
406 .num_resource = 16,
407 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_PROXY_0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
408 .start_resource = 48,
409 .host_id = TISCI_HOST_ID_ALL,
410 },
411 {
412 .num_resource = 1,
413 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
414 .start_resource = 0,
415 .host_id = TISCI_HOST_ID_ALL,
416 },
417 {
418 .num_resource = 200,
419 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
420 .start_resource = 120,
421 .host_id = TISCI_HOST_ID_A72_2,
422 },
423 {
424 .num_resource = 40,
425 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
426 .start_resource = 320,
427 .host_id = TISCI_HOST_ID_A72_3,
428 },
429 {
430 .num_resource = 32,
431 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
432 .start_resource = 360,
433 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
434 },
435 {
436 .num_resource = 32,
437 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
438 .start_resource = 360,
439 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
440 },
441 {
442 .num_resource = 32,
443 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
444 .start_resource = 392,
445 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
446 },
447 {
448 .num_resource = 256,
449 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
450 .start_resource = 424,
451 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
452 },
453 {
454 .num_resource = 256,
455 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
456 .start_resource = 680,
457 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
458 },
459 {
460 .num_resource = 38,
461 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GP),
462 .start_resource = 936,
463 .host_id = TISCI_HOST_ID_ALL,
464 },
465 {
466 .num_resource = 4,
467 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
468 .start_resource = 64,
469 .host_id = TISCI_HOST_ID_A72_2,
470 },
471 {
472 .num_resource = 2,
473 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
474 .start_resource = 68,
475 .host_id = TISCI_HOST_ID_A72_3,
476 },
477 {
478 .num_resource = 2,
479 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
480 .start_resource = 70,
481 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
482 },
483 {
484 .num_resource = 2,
485 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
486 .start_resource = 70,
487 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
488 },
489 {
490 .num_resource = 2,
491 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
492 .start_resource = 72,
493 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
494 },
495 {
496 .num_resource = 2,
497 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
498 .start_resource = 74,
499 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
500 },
501 {
502 .num_resource = 2,
503 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
504 .start_resource = 76,
505 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
506 },
507 {
508 .num_resource = 20,
509 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
510 .start_resource = 78,
511 .host_id = TISCI_HOST_ID_A72_2,
512 },
513 {
514 .num_resource = 4,
515 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
516 .start_resource = 98,
517 .host_id = TISCI_HOST_ID_A72_3,
518 },
519 {
520 .num_resource = 8,
521 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
522 .start_resource = 102,
523 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
524 },
525 {
526 .num_resource = 8,
527 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
528 .start_resource = 110,
529 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
530 },
531 {
532 .num_resource = 2,
533 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
534 .start_resource = 118,
535 .host_id = TISCI_HOST_ID_ALL,
536 },
537 {
538 .num_resource = 4,
539 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
540 .start_resource = 4,
541 .host_id = TISCI_HOST_ID_A72_2,
542 },
543 {
544 .num_resource = 2,
545 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
546 .start_resource = 8,
547 .host_id = TISCI_HOST_ID_A72_3,
548 },
549 {
550 .num_resource = 2,
551 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
552 .start_resource = 10,
553 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
554 },
555 {
556 .num_resource = 2,
557 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
558 .start_resource = 10,
559 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
560 },
561 {
562 .num_resource = 2,
563 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
564 .start_resource = 12,
565 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
566 },
567 {
568 .num_resource = 2,
569 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
570 .start_resource = 14,
571 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
572 },
573 {
574 .num_resource = 2,
575 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
576 .start_resource = 16,
577 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
578 },
579 {
580 .num_resource = 20,
581 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
582 .start_resource = 18,
583 .host_id = TISCI_HOST_ID_A72_2,
584 },
585 {
586 .num_resource = 4,
587 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
588 .start_resource = 38,
589 .host_id = TISCI_HOST_ID_A72_3,
590 },
591 {
592 .num_resource = 8,
593 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
594 .start_resource = 42,
595 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
596 },
597 {
598 .num_resource = 8,
599 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
600 .start_resource = 50,
601 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
602 },
603 {
604 .num_resource = 2,
605 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
606 .start_resource = 58,
607 .host_id = TISCI_HOST_ID_ALL,
608 },
609 {
610 .num_resource = 0,
611 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
612 .start_resource = 62,
613 .host_id = TISCI_HOST_ID_A72_2,
614 },
615 {
616 .num_resource = 1,
617 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
618 .start_resource = 62,
619 .host_id = TISCI_HOST_ID_A72_2,
620 },
621 {
622 .num_resource = 0,
623 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
624 .start_resource = 62,
625 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
626 },
627 {
628 .num_resource = 1,
629 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
630 .start_resource = 63,
631 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
632 },
633 {
634 .num_resource = 0,
635 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_UH),
636 .start_resource = 60,
637 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
638 },
639 {
640 .num_resource = 2,
641 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_UH),
642 .start_resource = 60,
643 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
644 },
645 {
646 .num_resource = 0,
647 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
648 .start_resource = 2,
649 .host_id = TISCI_HOST_ID_A72_2,
650 },
651 {
652 .num_resource = 1,
653 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
654 .start_resource = 2,
655 .host_id = TISCI_HOST_ID_A72_2,
656 },
657 {
658 .num_resource = 0,
659 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
660 .start_resource = 2,
661 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
662 },
663 {
664 .num_resource = 1,
665 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
666 .start_resource = 3,
667 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
668 },
669 {
670 .num_resource = 0,
671 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_UH),
672 .start_resource = 0,
673 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
674 },
675 {
676 .num_resource = 2,
677 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_UH),
678 .start_resource = 0,
679 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
680 },
681 {
682 .num_resource = 1,
683 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
684 .start_resource = 2,
685 .host_id = TISCI_HOST_ID_A72_2,
686 },
687 {
688 .num_resource = 1,
689 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
690 .start_resource = 3,
691 .host_id = TISCI_HOST_ID_A72_3,
692 },
693 {
694 .num_resource = 3,
695 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
696 .start_resource = 0,
697 .host_id = TISCI_HOST_ID_A72_2,
698 },
699 {
700 .num_resource = 2,
701 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
702 .start_resource = 3,
703 .host_id = TISCI_HOST_ID_A72_3,
704 },
705 {
706 .num_resource = 1,
707 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
708 .start_resource = 5,
709 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
710 },
711 {
712 .num_resource = 1,
713 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
714 .start_resource = 5,
715 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
716 },
717 {
718 .num_resource = 1,
719 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
720 .start_resource = 6,
721 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
722 },
723 {
724 .num_resource = 16,
725 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
726 .start_resource = 7,
727 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
728 },
729 {
730 .num_resource = 8,
731 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
732 .start_resource = 23,
733 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
734 },
735 {
736 .num_resource = 1,
737 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
738 .start_resource = 31,
739 .host_id = TISCI_HOST_ID_ALL,
740 },
741 {
742 .num_resource = 8,
743 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
744 .start_resource = 60,
745 .host_id = TISCI_HOST_ID_A72_2,
746 },
747 {
748 .num_resource = 8,
749 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
750 .start_resource = 68,
751 .host_id = TISCI_HOST_ID_A72_3,
752 },
753 {
754 .num_resource = 8,
755 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
756 .start_resource = 76,
757 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
758 },
759 {
760 .num_resource = 66,
761 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
762 .start_resource = 84,
763 .host_id = TISCI_HOST_ID_ALL,
764 },
765 {
766 .num_resource = 1,
767 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
768 .start_resource = 0,
769 .host_id = TISCI_HOST_ID_ALL,
770 },
771 {
772 .num_resource = 1024,
773 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
774 .start_resource = 49152,
775 .host_id = TISCI_HOST_ID_ALL,
776 },
777 {
778 .num_resource = 1,
779 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
780 .start_resource = 0,
781 .host_id = TISCI_HOST_ID_ALL,
782 },
783 {
784 .num_resource = 4,
785 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
786 .start_resource = 4,
787 .host_id = TISCI_HOST_ID_A72_2,
788 },
789 {
790 .num_resource = 2,
791 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
792 .start_resource = 8,
793 .host_id = TISCI_HOST_ID_A72_3,
794 },
795 {
796 .num_resource = 2,
797 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
798 .start_resource = 10,
799 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
800 },
801 {
802 .num_resource = 2,
803 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
804 .start_resource = 10,
805 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
806 },
807 {
808 .num_resource = 2,
809 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
810 .start_resource = 12,
811 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
812 },
813 {
814 .num_resource = 2,
815 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
816 .start_resource = 14,
817 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
818 },
819 {
820 .num_resource = 2,
821 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
822 .start_resource = 16,
823 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
824 },
825 {
826 .num_resource = 20,
827 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
828 .start_resource = 18,
829 .host_id = TISCI_HOST_ID_A72_2,
830 },
831 {
832 .num_resource = 4,
833 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
834 .start_resource = 38,
835 .host_id = TISCI_HOST_ID_A72_3,
836 },
837 {
838 .num_resource = 8,
839 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
840 .start_resource = 42,
841 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
842 },
843 {
844 .num_resource = 8,
845 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
846 .start_resource = 50,
847 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
848 },
849 {
850 .num_resource = 2,
851 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
852 .start_resource = 58,
853 .host_id = TISCI_HOST_ID_ALL,
854 },
855 {
856 .num_resource = 0,
857 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
858 .start_resource = 2,
859 .host_id = TISCI_HOST_ID_A72_2,
860 },
861 {
862 .num_resource = 1,
863 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
864 .start_resource = 2,
865 .host_id = TISCI_HOST_ID_A72_2,
866 },
867 {
868 .num_resource = 0,
869 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
870 .start_resource = 2,
871 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
872 },
873 {
874 .num_resource = 1,
875 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
876 .start_resource = 3,
877 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
878 },
879 {
880 .num_resource = 0,
881 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
882 .start_resource = 0,
883 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
884 },
885 {
886 .num_resource = 2,
887 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
888 .start_resource = 0,
889 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
890 },
891 {
892 .num_resource = 4,
893 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
894 .start_resource = 4,
895 .host_id = TISCI_HOST_ID_A72_2,
896 },
897 {
898 .num_resource = 2,
899 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
900 .start_resource = 8,
901 .host_id = TISCI_HOST_ID_A72_3,
902 },
903 {
904 .num_resource = 2,
905 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
906 .start_resource = 10,
907 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
908 },
909 {
910 .num_resource = 2,
911 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
912 .start_resource = 10,
913 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
914 },
915 {
916 .num_resource = 2,
917 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
918 .start_resource = 12,
919 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
920 },
921 {
922 .num_resource = 2,
923 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
924 .start_resource = 14,
925 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
926 },
927 {
928 .num_resource = 2,
929 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
930 .start_resource = 16,
931 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
932 },
933 {
934 .num_resource = 20,
935 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
936 .start_resource = 18,
937 .host_id = TISCI_HOST_ID_A72_2,
938 },
939 {
940 .num_resource = 4,
941 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
942 .start_resource = 38,
943 .host_id = TISCI_HOST_ID_A72_3,
944 },
945 {
946 .num_resource = 8,
947 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
948 .start_resource = 42,
949 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
950 },
951 {
952 .num_resource = 8,
953 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
954 .start_resource = 50,
955 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
956 },
957 {
958 .num_resource = 2,
959 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
960 .start_resource = 58,
961 .host_id = TISCI_HOST_ID_ALL,
962 },
963 {
964 .num_resource = 0,
965 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
966 .start_resource = 2,
967 .host_id = TISCI_HOST_ID_A72_2,
968 },
969 {
970 .num_resource = 1,
971 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
972 .start_resource = 2,
973 .host_id = TISCI_HOST_ID_A72_2,
974 },
975 {
976 .num_resource = 0,
977 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
978 .start_resource = 2,
979 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
980 },
981 {
982 .num_resource = 1,
983 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
984 .start_resource = 3,
985 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
986 },
987 {
988 .num_resource = 0,
989 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
990 .start_resource = 0,
991 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
992 },
993 {
994 .num_resource = 2,
995 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
996 .start_resource = 0,
997 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
998 },
999 {
1000 .num_resource = 128,
1001 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1002 .start_resource = 10,
1003 .host_id = TISCI_HOST_ID_A72_2,
1004 },
1005 {
1006 .num_resource = 54,
1007 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1008 .start_resource = 138,
1009 .host_id = TISCI_HOST_ID_A72_3,
1010 },
1011 {
1012 .num_resource = 28,
1013 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1014 .start_resource = 196,
1015 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1016 },
1017 {
1018 .num_resource = 28,
1019 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1020 .start_resource = 228,
1021 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1022 },
1023 {
1024 .num_resource = 4,
1025 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1026 .start_resource = 400,
1027 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1028 },
1029 {
1030 .num_resource = 4,
1031 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1032 .start_resource = 400,
1033 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1034 },
1035 {
1036 .num_resource = 4,
1037 .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_INTR_ROUTER_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1038 .start_resource = 404,
1039 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1040 },
1041 {
1042 .num_resource = 25,
1043 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1044 .start_resource = 15,
1045 .host_id = TISCI_HOST_ID_A72_2,
1046 },
1047 {
1048 .num_resource = 16,
1049 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1050 .start_resource = 47,
1051 .host_id = TISCI_HOST_ID_A72_3,
1052 },
1053 {
1054 .num_resource = 64,
1055 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1056 .start_resource = 63,
1057 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1058 },
1059 {
1060 .num_resource = 64,
1061 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1062 .start_resource = 63,
1063 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1064 },
1065 {
1066 .num_resource = 32,
1067 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1068 .start_resource = 127,
1069 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1070 },
1071 {
1072 .num_resource = 16,
1073 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1074 .start_resource = 159,
1075 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1076 },
1077 {
1078 .num_resource = 16,
1079 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1080 .start_resource = 175,
1081 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1082 },
1083 {
1084 .num_resource = 65,
1085 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_IA_VINT),
1086 .start_resource = 191,
1087 .host_id = TISCI_HOST_ID_ALL,
1088 },
1089 {
1090 .num_resource = 121,
1091 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1092 .start_resource = 16399,
1093 .host_id = TISCI_HOST_ID_A72_2,
1094 },
1095 {
1096 .num_resource = 128,
1097 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1098 .start_resource = 16527,
1099 .host_id = TISCI_HOST_ID_A72_3,
1100 },
1101 {
1102 .num_resource = 256,
1103 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1104 .start_resource = 16655,
1105 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1106 },
1107 {
1108 .num_resource = 256,
1109 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1110 .start_resource = 16655,
1111 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1112 },
1113 {
1114 .num_resource = 128,
1115 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1116 .start_resource = 16911,
1117 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1118 },
1119 {
1120 .num_resource = 128,
1121 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1122 .start_resource = 17039,
1123 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1124 },
1125 {
1126 .num_resource = 128,
1127 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1128 .start_resource = 17167,
1129 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1130 },
1131 {
1132 .num_resource = 625,
1133 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1134 .start_resource = 17295,
1135 .host_id = TISCI_HOST_ID_ALL,
1136 },
1137 {
1138 .num_resource = 8,
1139 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1140 .start_resource = 1,
1141 .host_id = TISCI_HOST_ID_A72_2,
1142 },
1143 {
1144 .num_resource = 4,
1145 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1146 .start_resource = 9,
1147 .host_id = TISCI_HOST_ID_A72_3,
1148 },
1149 {
1150 .num_resource = 16,
1151 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1152 .start_resource = 13,
1153 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1154 },
1155 {
1156 .num_resource = 16,
1157 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1158 .start_resource = 13,
1159 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1160 },
1161 {
1162 .num_resource = 16,
1163 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1164 .start_resource = 29,
1165 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1166 },
1167 {
1168 .num_resource = 8,
1169 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1170 .start_resource = 45,
1171 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1172 },
1173 {
1174 .num_resource = 8,
1175 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1176 .start_resource = 53,
1177 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1178 },
1179 {
1180 .num_resource = 3,
1181 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
1182 .start_resource = 61,
1183 .host_id = TISCI_HOST_ID_ALL,
1184 },
1185 {
1186 .num_resource = 1,
1187 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
1188 .start_resource = 0,
1189 .host_id = TISCI_HOST_ID_ALL,
1190 },
1191 {
1192 .num_resource = 32,
1193 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1194 .start_resource = 96,
1195 .host_id = TISCI_HOST_ID_A72_2,
1196 },
1197 {
1198 .num_resource = 16,
1199 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1200 .start_resource = 128,
1201 .host_id = TISCI_HOST_ID_A72_3,
1202 },
1203 {
1204 .num_resource = 32,
1205 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1206 .start_resource = 144,
1207 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1208 },
1209 {
1210 .num_resource = 32,
1211 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1212 .start_resource = 144,
1213 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1214 },
1215 {
1216 .num_resource = 32,
1217 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1218 .start_resource = 176,
1219 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1220 },
1221 {
1222 .num_resource = 16,
1223 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1224 .start_resource = 208,
1225 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1226 },
1227 {
1228 .num_resource = 16,
1229 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1230 .start_resource = 224,
1231 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1232 },
1233 {
1234 .num_resource = 12,
1235 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
1236 .start_resource = 240,
1237 .host_id = TISCI_HOST_ID_ALL,
1238 },
1239 {
1240 .num_resource = 3,
1241 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1242 .start_resource = 50,
1243 .host_id = TISCI_HOST_ID_A72_2,
1244 },
1245 {
1246 .num_resource = 2,
1247 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1248 .start_resource = 53,
1249 .host_id = TISCI_HOST_ID_A72_3,
1250 },
1251 {
1252 .num_resource = 2,
1253 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1254 .start_resource = 55,
1255 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1256 },
1257 {
1258 .num_resource = 2,
1259 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1260 .start_resource = 55,
1261 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1262 },
1263 {
1264 .num_resource = 2,
1265 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1266 .start_resource = 57,
1267 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1268 },
1269 {
1270 .num_resource = 2,
1271 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1272 .start_resource = 59,
1273 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1274 },
1275 {
1276 .num_resource = 2,
1277 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1278 .start_resource = 61,
1279 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1280 },
1281 {
1282 .num_resource = 9,
1283 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1284 .start_resource = 63,
1285 .host_id = TISCI_HOST_ID_A72_2,
1286 },
1287 {
1288 .num_resource = 4,
1289 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1290 .start_resource = 72,
1291 .host_id = TISCI_HOST_ID_A72_3,
1292 },
1293 {
1294 .num_resource = 4,
1295 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1296 .start_resource = 76,
1297 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1298 },
1299 {
1300 .num_resource = 4,
1301 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1302 .start_resource = 76,
1303 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1304 },
1305 {
1306 .num_resource = 4,
1307 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1308 .start_resource = 80,
1309 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1310 },
1311 {
1312 .num_resource = 4,
1313 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1314 .start_resource = 84,
1315 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1316 },
1317 {
1318 .num_resource = 4,
1319 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1320 .start_resource = 88,
1321 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1322 },
1323 {
1324 .num_resource = 1,
1325 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
1326 .start_resource = 92,
1327 .host_id = TISCI_HOST_ID_ALL,
1328 },
1329 {
1330 .num_resource = 3,
1331 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1332 .start_resource = 2,
1333 .host_id = TISCI_HOST_ID_A72_2,
1334 },
1335 {
1336 .num_resource = 2,
1337 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1338 .start_resource = 5,
1339 .host_id = TISCI_HOST_ID_A72_3,
1340 },
1341 {
1342 .num_resource = 2,
1343 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1344 .start_resource = 7,
1345 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1346 },
1347 {
1348 .num_resource = 2,
1349 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1350 .start_resource = 7,
1351 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1352 },
1353 {
1354 .num_resource = 2,
1355 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1356 .start_resource = 9,
1357 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1358 },
1359 {
1360 .num_resource = 2,
1361 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1362 .start_resource = 11,
1363 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1364 },
1365 {
1366 .num_resource = 2,
1367 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1368 .start_resource = 13,
1369 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1370 },
1371 {
1372 .num_resource = 9,
1373 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1374 .start_resource = 15,
1375 .host_id = TISCI_HOST_ID_A72_2,
1376 },
1377 {
1378 .num_resource = 4,
1379 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1380 .start_resource = 24,
1381 .host_id = TISCI_HOST_ID_A72_3,
1382 },
1383 {
1384 .num_resource = 4,
1385 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1386 .start_resource = 28,
1387 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1388 },
1389 {
1390 .num_resource = 4,
1391 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1392 .start_resource = 28,
1393 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1394 },
1395 {
1396 .num_resource = 4,
1397 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1398 .start_resource = 32,
1399 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1400 },
1401 {
1402 .num_resource = 4,
1403 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1404 .start_resource = 36,
1405 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1406 },
1407 {
1408 .num_resource = 4,
1409 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1410 .start_resource = 40,
1411 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1412 },
1413 {
1414 .num_resource = 2,
1415 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
1416 .start_resource = 44,
1417 .host_id = TISCI_HOST_ID_ALL,
1418 },
1419 {
1420 .num_resource = 0,
1421 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1422 .start_resource = 48,
1423 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1424 },
1425 {
1426 .num_resource = 0,
1427 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1428 .start_resource = 48,
1429 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1430 },
1431 {
1432 .num_resource = 0,
1433 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1434 .start_resource = 48,
1435 .host_id = TISCI_HOST_ID_A72_2,
1436 },
1437 {
1438 .num_resource = 1,
1439 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1440 .start_resource = 48,
1441 .host_id = TISCI_HOST_ID_A72_2,
1442 },
1443 {
1444 .num_resource = 1,
1445 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1446 .start_resource = 49,
1447 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1448 },
1449 {
1450 .num_resource = 1,
1451 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
1452 .start_resource = 49,
1453 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1454 },
1455 {
1456 .num_resource = 0,
1457 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1458 .start_resource = 0,
1459 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1460 },
1461 {
1462 .num_resource = 0,
1463 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1464 .start_resource = 0,
1465 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1466 },
1467 {
1468 .num_resource = 0,
1469 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1470 .start_resource = 0,
1471 .host_id = TISCI_HOST_ID_A72_2,
1472 },
1473 {
1474 .num_resource = 1,
1475 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1476 .start_resource = 0,
1477 .host_id = TISCI_HOST_ID_A72_2,
1478 },
1479 {
1480 .num_resource = 1,
1481 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1482 .start_resource = 1,
1483 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1484 },
1485 {
1486 .num_resource = 1,
1487 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
1488 .start_resource = 1,
1489 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1490 },
1491 {
1492 .num_resource = 1,
1493 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
1494 .start_resource = 2,
1495 .host_id = TISCI_HOST_ID_A72_2,
1496 },
1497 {
1498 .num_resource = 1,
1499 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
1500 .start_resource = 3,
1501 .host_id = TISCI_HOST_ID_A72_3,
1502 },
1503 {
1504 .num_resource = 3,
1505 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1506 .start_resource = 0,
1507 .host_id = TISCI_HOST_ID_A72_2,
1508 },
1509 {
1510 .num_resource = 2,
1511 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1512 .start_resource = 3,
1513 .host_id = TISCI_HOST_ID_A72_3,
1514 },
1515 {
1516 .num_resource = 6,
1517 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1518 .start_resource = 5,
1519 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1520 },
1521 {
1522 .num_resource = 6,
1523 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1524 .start_resource = 11,
1525 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1526 },
1527 {
1528 .num_resource = 5,
1529 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1530 .start_resource = 17,
1531 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1532 },
1533 {
1534 .num_resource = 5,
1535 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1536 .start_resource = 22,
1537 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1538 },
1539 {
1540 .num_resource = 5,
1541 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
1542 .start_resource = 27,
1543 .host_id = TISCI_HOST_ID_ALL,
1544 },
1545 {
1546 .num_resource = 8,
1547 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1548 .start_resource = 48,
1549 .host_id = TISCI_HOST_ID_A72_2,
1550 },
1551 {
1552 .num_resource = 4,
1553 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1554 .start_resource = 56,
1555 .host_id = TISCI_HOST_ID_A72_3,
1556 },
1557 {
1558 .num_resource = 8,
1559 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1560 .start_resource = 60,
1561 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1562 },
1563 {
1564 .num_resource = 8,
1565 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1566 .start_resource = 60,
1567 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1568 },
1569 {
1570 .num_resource = 4,
1571 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1572 .start_resource = 68,
1573 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1574 },
1575 {
1576 .num_resource = 8,
1577 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1578 .start_resource = 72,
1579 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1580 },
1581 {
1582 .num_resource = 4,
1583 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1584 .start_resource = 80,
1585 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1586 },
1587 {
1588 .num_resource = 12,
1589 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1590 .start_resource = 84,
1591 .host_id = TISCI_HOST_ID_ALL,
1592 },
1593 {
1594 .num_resource = 1,
1595 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
1596 .start_resource = 0,
1597 .host_id = TISCI_HOST_ID_ALL,
1598 },
1599 {
1600 .num_resource = 256,
1601 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
1602 .start_resource = 56320,
1603 .host_id = TISCI_HOST_ID_ALL,
1604 },
1605 {
1606 .num_resource = 1,
1607 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
1608 .start_resource = 0,
1609 .host_id = TISCI_HOST_ID_ALL,
1610 },
1611 {
1612 .num_resource = 3,
1613 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1614 .start_resource = 2,
1615 .host_id = TISCI_HOST_ID_A72_2,
1616 },
1617 {
1618 .num_resource = 2,
1619 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1620 .start_resource = 5,
1621 .host_id = TISCI_HOST_ID_A72_3,
1622 },
1623 {
1624 .num_resource = 2,
1625 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1626 .start_resource = 7,
1627 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1628 },
1629 {
1630 .num_resource = 2,
1631 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1632 .start_resource = 7,
1633 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1634 },
1635 {
1636 .num_resource = 2,
1637 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1638 .start_resource = 9,
1639 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1640 },
1641 {
1642 .num_resource = 2,
1643 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1644 .start_resource = 11,
1645 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1646 },
1647 {
1648 .num_resource = 2,
1649 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1650 .start_resource = 13,
1651 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1652 },
1653 {
1654 .num_resource = 9,
1655 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1656 .start_resource = 15,
1657 .host_id = TISCI_HOST_ID_A72_2,
1658 },
1659 {
1660 .num_resource = 4,
1661 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1662 .start_resource = 24,
1663 .host_id = TISCI_HOST_ID_A72_3,
1664 },
1665 {
1666 .num_resource = 4,
1667 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1668 .start_resource = 28,
1669 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1670 },
1671 {
1672 .num_resource = 4,
1673 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1674 .start_resource = 28,
1675 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1676 },
1677 {
1678 .num_resource = 4,
1679 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1680 .start_resource = 32,
1681 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1682 },
1683 {
1684 .num_resource = 4,
1685 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1686 .start_resource = 36,
1687 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1688 },
1689 {
1690 .num_resource = 4,
1691 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1692 .start_resource = 40,
1693 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1694 },
1695 {
1696 .num_resource = 1,
1697 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
1698 .start_resource = 44,
1699 .host_id = TISCI_HOST_ID_ALL,
1700 },
1701 {
1702 .num_resource = 0,
1703 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1704 .start_resource = 0,
1705 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1706 },
1707 {
1708 .num_resource = 0,
1709 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1710 .start_resource = 0,
1711 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1712 },
1713 {
1714 .num_resource = 0,
1715 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1716 .start_resource = 0,
1717 .host_id = TISCI_HOST_ID_A72_2,
1718 },
1719 {
1720 .num_resource = 1,
1721 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1722 .start_resource = 0,
1723 .host_id = TISCI_HOST_ID_A72_2,
1724 },
1725 {
1726 .num_resource = 1,
1727 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1728 .start_resource = 1,
1729 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1730 },
1731 {
1732 .num_resource = 1,
1733 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1734 .start_resource = 1,
1735 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1736 },
1737 {
1738 .num_resource = 3,
1739 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1740 .start_resource = 2,
1741 .host_id = TISCI_HOST_ID_A72_2,
1742 },
1743 {
1744 .num_resource = 2,
1745 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1746 .start_resource = 5,
1747 .host_id = TISCI_HOST_ID_A72_3,
1748 },
1749 {
1750 .num_resource = 2,
1751 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1752 .start_resource = 7,
1753 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1754 },
1755 {
1756 .num_resource = 2,
1757 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1758 .start_resource = 7,
1759 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1760 },
1761 {
1762 .num_resource = 2,
1763 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1764 .start_resource = 9,
1765 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1766 },
1767 {
1768 .num_resource = 2,
1769 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1770 .start_resource = 11,
1771 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1772 },
1773 {
1774 .num_resource = 2,
1775 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1776 .start_resource = 13,
1777 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1778 },
1779 {
1780 .num_resource = 9,
1781 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1782 .start_resource = 15,
1783 .host_id = TISCI_HOST_ID_A72_2,
1784 },
1785 {
1786 .num_resource = 4,
1787 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1788 .start_resource = 24,
1789 .host_id = TISCI_HOST_ID_A72_3,
1790 },
1791 {
1792 .num_resource = 4,
1793 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1794 .start_resource = 28,
1795 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1796 },
1797 {
1798 .num_resource = 4,
1799 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1800 .start_resource = 28,
1801 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1802 },
1803 {
1804 .num_resource = 4,
1805 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1806 .start_resource = 32,
1807 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1808 },
1809 {
1810 .num_resource = 4,
1811 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1812 .start_resource = 36,
1813 .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
1814 },
1815 {
1816 .num_resource = 4,
1817 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1818 .start_resource = 40,
1819 .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
1820 },
1821 {
1822 .num_resource = 2,
1823 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
1824 .start_resource = 44,
1825 .host_id = TISCI_HOST_ID_ALL,
1826 },
1827 {
1828 .num_resource = 0,
1829 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1830 .start_resource = 0,
1831 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1832 },
1833 {
1834 .num_resource = 0,
1835 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1836 .start_resource = 0,
1837 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1838 },
1839 {
1840 .num_resource = 0,
1841 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1842 .start_resource = 0,
1843 .host_id = TISCI_HOST_ID_A72_2,
1844 },
1845 {
1846 .num_resource = 1,
1847 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1848 .start_resource = 0,
1849 .host_id = TISCI_HOST_ID_A72_2,
1850 },
1851 {
1852 .num_resource = 1,
1853 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1854 .start_resource = 1,
1855 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1856 },
1857 {
1858 .num_resource = 1,
1859 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1860 .start_resource = 1,
1861 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1862 },
1863 {
1864 .num_resource = 21,
1865 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_INTR_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1866 .start_resource = 11,
1867 .host_id = TISCI_HOST_ID_MCU_0_R5_0,
1868 },
1869 {
1870 .num_resource = 21,
1871 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_INTR_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1872 .start_resource = 11,
1873 .host_id = TISCI_HOST_ID_MCU_0_R5_1,
1874 },
1875 {
1876 .num_resource = 28,
1877 .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_INTR_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
1878 .start_resource = 36,
1879 .host_id = TISCI_HOST_ID_MCU_0_R5_2,
1880 },
1881 }
1882 };
1883 #endif