PDK-9368: j721s2: Sciclient/Sciserver fixes to match RM/PM data
[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / V4 / sciclient_irq_rm.c
1 /*
2  * Copyright (c) 2021, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
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8  *
9  * *  Redistributions of source code must retain the above copyright
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11  *
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13  *    notice, this list of conditions and the following disclaimer in the
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15  *
16  * *  Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
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31  */
32 /**
33  *  \file V4/sciclient_irq_rm.c
34  *
35  *  \brief File containing the J7 Family specific interrupt management data for
36  *         RM.
37  *
38  */
39 /* ========================================================================== */
40 /*                             Include Files                                  */
41 /* ========================================================================== */
43 #include <ti/drv/sciclient/src/sciclient/sciclient_rm_priv.h>
44 #include <ti/drv/sciclient/soc/V4/sciclient_irq_rm.h>
46 /* ========================================================================== */
47 /*                            Global Variables                                */
48 /* ========================================================================== */
50 #if defined (SOC_J721S2)
51 uint8_t vint_usage_count_NAVSS0_MODSS_INTA_0[64] = {0};
52 uint8_t vint_usage_count_NAVSS0_MODSS_INTA_1[64] = {0};
53 uint8_t vint_usage_count_NAVSS0_UDMASS_INTA_0[256] = {0};
54 uint8_t vint_usage_count_MCU_NAVSS0_INTA_0[256] = {0};
55 uint8_t vint_usage_count_MCU_SA3_SS0_INTAGGR_0[8] = {0};
56 static struct Sciclient_rmIaUsedMapping rom_usage_MCU_NAVSS0_UDMASS_INTA_0[5U] = {
57     {
58         .event = 16404U,
59         .cleared = false,
60     },
61     {
62         .event = 16405U,
63         .cleared = false,
64     },
65     {
66         .event = 16406U,
67         .cleared = false,
68     },
69     {
70         .event = 16407U,
71         .cleared = false,
72     },
73     {
74         .event = 16414U,
75         .cleared = false,
76     },
77 };
79 struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST] =
80 {
81     {
82         .dev_id             = TISCI_DEV_NAVSS0_MODSS_INTA_0,
83         .imap               = 0x30900000,
84         .sevt_offset        = 20480u,
85         .n_sevt             = 1024u,
86         .n_vint             = 64,
87         .vint_usage_count   = &vint_usage_count_NAVSS0_MODSS_INTA_0[0],
88         .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
89         .rom_usage          = NULL,
90         .n_rom_usage        = 0U,
91     },
92     {
93         .dev_id             = TISCI_DEV_NAVSS0_MODSS_INTA_1,
94         .imap               = 0x30908000,
95         .sevt_offset        = 22528u,
96         .n_sevt             = 1024u,
97         .n_vint             = 64,
98         .vint_usage_count   = &vint_usage_count_NAVSS0_MODSS_INTA_1[0],
99         .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
100         .rom_usage          = NULL,
101         .n_rom_usage        = 0U,
102     },
103     {
104         .dev_id             = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
105         .imap               = 0x30940000,
106         .sevt_offset        = 0u,
107         .n_sevt             = 4608u,
108         .n_vint             = 256,
109         .vint_usage_count   = &vint_usage_count_NAVSS0_UDMASS_INTA_0[0],
110         .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
111         .rom_usage          = NULL,
112         .n_rom_usage        = 0U,
113     },
114     {
115         .dev_id             = TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0,
116         .imap               = 0x28560000,
117         .sevt_offset        = 16384u,
118         .n_sevt             = 1536u,
119         .n_vint             = 256,
120         .vint_usage_count   = &vint_usage_count_MCU_NAVSS0_INTA_0[0],
121         .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
122         .rom_usage          = &rom_usage_MCU_NAVSS0_UDMASS_INTA_0[0U],
123         .n_rom_usage        = 5,
124     },
125     {
126         .dev_id             = TISCI_DEV_MCU_SA3_SS0_INTAGGR_0,
127         .imap               = 0x44809000,
128         .sevt_offset        = 0u,
129         .n_sevt             = 100u,
130         .n_vint             = 8,
131         .vint_usage_count   = &vint_usage_count_MCU_SA3_SS0_INTAGGR_0[0],
132         .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
133         .rom_usage          = NULL,
134         .n_rom_usage        = 0U,
135     }
136 };
138 static struct Sciclient_rmIrUsedMapping rom_usage_MAIN2MCU_LVL_INTRTR0[1U] = {
139     {
140         .inp_start = 28U,
141         .outp_start = 32U,
142         .length = 2U,
143         .cleared = false,
144         .opCleared = false,
145     },
146 };
147 static struct Sciclient_rmIrUsedMapping rom_usage_MCU_NAVSS0_INTR_ROUTER_0[1U] = {
148     {
149         .inp_start = 1U,
150         .outp_start = 0U,
151         .length = 4U,
152         .cleared = false,
153         .opCleared = false,
154     },
155 };
157 struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST] =
159     {
160         .dev_id         = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
161         .cfg            = 0xa10000,
162         .n_inp          = 320u,
163         .n_outp         = 64u,
164         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
165         .rom_usage      = &rom_usage_MAIN2MCU_LVL_INTRTR0[0U],
166         .n_rom_usage    = 2,
167     },
168     {
169         .dev_id         = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
170         .cfg            = 0xa20000,
171         .n_inp          = 112u,
172         .n_outp         = 48u,
173         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
174         .rom_usage      = NULL,
175         .n_rom_usage    = 0U,
176     },
177     {
178         .dev_id         = TISCI_DEV_TIMESYNC_INTRTR0,
179         .cfg            = 0xa40000,
180         .n_inp          = 56u,
181         .n_outp         = 48u,
182         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
183         .rom_usage      = NULL,
184         .n_rom_usage    = 0U,
185     },
186     {
187         .dev_id         = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
188         .cfg            = 0x42200000,
189         .n_inp          = 120u,
190         .n_outp         = 32u,
191         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
192         .rom_usage      = NULL,
193         .n_rom_usage    = 0U,
194     },
195     {
196         .dev_id         = TISCI_DEV_GPIOMUX_INTRTR0,
197         .cfg            = 0xa00000,
198         .n_inp          = 180u,
199         .n_outp         = 64u,
200         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
201         .rom_usage      = NULL,
202         .n_rom_usage    = 0U,
203     },
204     {
205         .dev_id         = TISCI_DEV_CMPEVENT_INTRTR0,
206         .cfg            = 0xa30000,
207         .n_inp          = 16u,
208         .n_outp         = 16u,
209         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
210         .rom_usage      = NULL,
211         .n_rom_usage    = 0U,
212     },
213     {
214         .dev_id         = TISCI_DEV_NAVSS0_INTR_0,
215         .cfg            = 0x310e0000,
216         .n_inp          = 442u,
217         .n_outp         = 512u,
218         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
219         .rom_usage      = NULL,
220         .n_rom_usage    = 0U,
221     },
222     {
223         .dev_id         = TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0,
224         .cfg            = 0x28540000,
225         .n_inp          = 261u,
226         .n_outp         = 64u,
227         .inp0_mapping   = SCICLIENT_RM_IR_MAPPING_FREE,
228         .rom_usage      = &rom_usage_MCU_NAVSS0_INTR_ROUTER_0[0U],
229         .n_rom_usage    = 1,
230     },
231 };
233 #endif
235 /* IRQ Tree definition */
237 #if defined (SOC_J721S2)
239 /* Start of CPSW1 interface definition */
240 const struct Sciclient_rmIrqIf CPSW1_cpts_comp_0_0_to_CMPEVENT_INTRTR0_in_11_11 = {
241         .lbase = 0,
242         .len = 1,
243         .rid = TISCI_DEV_CMPEVENT_INTRTR0,
244         .rbase = 11,
245 };
246 const struct Sciclient_rmIrqIf CPSW1_cpts_genf0_1_1_to_TIMESYNC_INTRTR0_in_18_18 = {
247         .lbase = 1,
248         .len = 1,
249         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
250         .rbase = 18,
251 };
252 const struct Sciclient_rmIrqIf CPSW1_cpts_genf1_2_2_to_TIMESYNC_INTRTR0_in_19_19 = {
253         .lbase = 2,
254         .len = 1,
255         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
256         .rbase = 19,
257 };
258 const struct Sciclient_rmIrqIf CPSW1_cpts_sync_3_3_to_TIMESYNC_INTRTR0_in_39_39 = {
259         .lbase = 3,
260         .len = 1,
261         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
262         .rbase = 39,
263 };
264 const struct Sciclient_rmIrqIf CPSW1_stat_pend_6_6_to_MAIN2MCU_LVL_INTRTR0_in_70_70 = {
265         .lbase = 6,
266         .len = 1,
267         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
268         .rbase = 70,
269 };
270 const struct Sciclient_rmIrqIf CPSW1_mdio_pend_5_5_to_MAIN2MCU_LVL_INTRTR0_in_71_71 = {
271         .lbase = 5,
272         .len = 1,
273         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
274         .rbase = 71,
275 };
276 const struct Sciclient_rmIrqIf CPSW1_evnt_pend_4_4_to_MAIN2MCU_LVL_INTRTR0_in_72_72 = {
277         .lbase = 4,
278         .len = 1,
279         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
280         .rbase = 72,
281 };
282 const struct Sciclient_rmIrqIf * const tisci_if_CPSW1[] = {
283         &CPSW1_cpts_comp_0_0_to_CMPEVENT_INTRTR0_in_11_11,
284         &CPSW1_cpts_genf0_1_1_to_TIMESYNC_INTRTR0_in_18_18,
285         &CPSW1_cpts_genf1_2_2_to_TIMESYNC_INTRTR0_in_19_19,
286         &CPSW1_cpts_sync_3_3_to_TIMESYNC_INTRTR0_in_39_39,
287         &CPSW1_stat_pend_6_6_to_MAIN2MCU_LVL_INTRTR0_in_70_70,
288         &CPSW1_mdio_pend_5_5_to_MAIN2MCU_LVL_INTRTR0_in_71_71,
289         &CPSW1_evnt_pend_4_4_to_MAIN2MCU_LVL_INTRTR0_in_72_72,
290 };
291 static const struct Sciclient_rmIrqNode tisci_irq_CPSW1 = {
292         .id = TISCI_DEV_CPSW1,
293         .n_if = 7,
294         .p_if = &tisci_if_CPSW1[0],
295 };
297 /* Start of MCU_CPSW0 interface definition */
298 const struct Sciclient_rmIrqIf MCU_CPSW0_cpts_comp_0_0_to_CMPEVENT_INTRTR0_in_10_10 = {
299         .lbase = 0,
300         .len = 1,
301         .rid = TISCI_DEV_CMPEVENT_INTRTR0,
302         .rbase = 10,
303 };
304 const struct Sciclient_rmIrqIf MCU_CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTRTR0_in_16_16 = {
305         .lbase = 1,
306         .len = 1,
307         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
308         .rbase = 16,
309 };
310 const struct Sciclient_rmIrqIf MCU_CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTRTR0_in_17_17 = {
311         .lbase = 2,
312         .len = 1,
313         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
314         .rbase = 17,
315 };
316 const struct Sciclient_rmIrqIf MCU_CPSW0_cpts_sync_3_3_to_TIMESYNC_INTRTR0_in_38_38 = {
317         .lbase = 3,
318         .len = 1,
319         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
320         .rbase = 38,
321 };
322 const struct Sciclient_rmIrqIf * const tisci_if_MCU_CPSW0[] = {
323         &MCU_CPSW0_cpts_comp_0_0_to_CMPEVENT_INTRTR0_in_10_10,
324         &MCU_CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTRTR0_in_16_16,
325         &MCU_CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTRTR0_in_17_17,
326         &MCU_CPSW0_cpts_sync_3_3_to_TIMESYNC_INTRTR0_in_38_38,
327 };
328 static const struct Sciclient_rmIrqNode tisci_irq_MCU_CPSW0 = {
329         .id = TISCI_DEV_MCU_CPSW0,
330         .n_if = 4,
331         .p_if = &tisci_if_MCU_CPSW0[0],
332 };
334 /* Start of CSI_RX_IF0 interface definition */
335 const struct Sciclient_rmIrqIf CSI_RX_IF0_csi_irq_1_1_to_MAIN2MCU_LVL_INTRTR0_in_254_254 = {
336         .lbase = 1,
337         .len = 1,
338         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
339         .rbase = 254,
340 };
341 const struct Sciclient_rmIrqIf CSI_RX_IF0_csi_err_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_255_255 = {
342         .lbase = 0,
343         .len = 1,
344         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
345         .rbase = 255,
346 };
347 const struct Sciclient_rmIrqIf CSI_RX_IF0_csi_level_2_2_to_MAIN2MCU_LVL_INTRTR0_in_256_256 = {
348         .lbase = 2,
349         .len = 1,
350         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
351         .rbase = 256,
352 };
353 const struct Sciclient_rmIrqIf * const tisci_if_CSI_RX_IF0[] = {
354         &CSI_RX_IF0_csi_irq_1_1_to_MAIN2MCU_LVL_INTRTR0_in_254_254,
355         &CSI_RX_IF0_csi_err_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_255_255,
356         &CSI_RX_IF0_csi_level_2_2_to_MAIN2MCU_LVL_INTRTR0_in_256_256,
357 };
358 static const struct Sciclient_rmIrqNode tisci_irq_CSI_RX_IF0 = {
359         .id = TISCI_DEV_CSI_RX_IF0,
360         .n_if = 3,
361         .p_if = &tisci_if_CSI_RX_IF0[0],
362 };
364 /* Start of CSI_RX_IF1 interface definition */
365 const struct Sciclient_rmIrqIf CSI_RX_IF1_csi_irq_1_1_to_MAIN2MCU_LVL_INTRTR0_in_257_257 = {
366         .lbase = 1,
367         .len = 1,
368         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
369         .rbase = 257,
370 };
371 const struct Sciclient_rmIrqIf CSI_RX_IF1_csi_err_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_258_258 = {
372         .lbase = 0,
373         .len = 1,
374         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
375         .rbase = 258,
376 };
377 const struct Sciclient_rmIrqIf CSI_RX_IF1_csi_level_2_2_to_MAIN2MCU_LVL_INTRTR0_in_259_259 = {
378         .lbase = 2,
379         .len = 1,
380         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
381         .rbase = 259,
382 };
383 const struct Sciclient_rmIrqIf * const tisci_if_CSI_RX_IF1[] = {
384         &CSI_RX_IF1_csi_irq_1_1_to_MAIN2MCU_LVL_INTRTR0_in_257_257,
385         &CSI_RX_IF1_csi_err_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_258_258,
386         &CSI_RX_IF1_csi_level_2_2_to_MAIN2MCU_LVL_INTRTR0_in_259_259,
387 };
388 static const struct Sciclient_rmIrqNode tisci_irq_CSI_RX_IF1 = {
389         .id = TISCI_DEV_CSI_RX_IF1,
390         .n_if = 3,
391         .p_if = &tisci_if_CSI_RX_IF1[0],
392 };
394 /* Start of CSI_TX_IF_V2_0 interface definition */
395 const struct Sciclient_rmIrqIf CSI_TX_IF_V2_0_csi_interrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_250_250 = {
396         .lbase = 0,
397         .len = 1,
398         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
399         .rbase = 250,
400 };
401 const struct Sciclient_rmIrqIf CSI_TX_IF_V2_0_csi_level_1_1_to_MAIN2MCU_LVL_INTRTR0_in_251_251 = {
402         .lbase = 1,
403         .len = 1,
404         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
405         .rbase = 251,
406 };
407 const struct Sciclient_rmIrqIf * const tisci_if_CSI_TX_IF_V2_0[] = {
408         &CSI_TX_IF_V2_0_csi_interrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_250_250,
409         &CSI_TX_IF_V2_0_csi_level_1_1_to_MAIN2MCU_LVL_INTRTR0_in_251_251,
410 };
411 static const struct Sciclient_rmIrqNode tisci_irq_CSI_TX_IF_V2_0 = {
412         .id = TISCI_DEV_CSI_TX_IF_V2_0,
413         .n_if = 2,
414         .p_if = &tisci_if_CSI_TX_IF_V2_0[0],
415 };
417 /* Start of CSI_TX_IF_V2_1 interface definition */
418 const struct Sciclient_rmIrqIf CSI_TX_IF_V2_1_csi_interrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_248_248 = {
419         .lbase = 0,
420         .len = 1,
421         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
422         .rbase = 248,
423 };
424 const struct Sciclient_rmIrqIf CSI_TX_IF_V2_1_csi_level_1_1_to_MAIN2MCU_LVL_INTRTR0_in_249_249 = {
425         .lbase = 1,
426         .len = 1,
427         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
428         .rbase = 249,
429 };
430 const struct Sciclient_rmIrqIf * const tisci_if_CSI_TX_IF_V2_1[] = {
431         &CSI_TX_IF_V2_1_csi_interrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_248_248,
432         &CSI_TX_IF_V2_1_csi_level_1_1_to_MAIN2MCU_LVL_INTRTR0_in_249_249,
433 };
434 static const struct Sciclient_rmIrqNode tisci_irq_CSI_TX_IF_V2_1 = {
435         .id = TISCI_DEV_CSI_TX_IF_V2_1,
436         .n_if = 2,
437         .p_if = &tisci_if_CSI_TX_IF_V2_1[0],
438 };
440 /* Start of DCC0 interface definition */
441 const struct Sciclient_rmIrqIf DCC0_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_88_88 = {
442         .lbase = 0,
443         .len = 1,
444         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
445         .rbase = 88,
446 };
447 const struct Sciclient_rmIrqIf * const tisci_if_DCC0[] = {
448         &DCC0_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_88_88,
449 };
450 static const struct Sciclient_rmIrqNode tisci_irq_DCC0 = {
451         .id = TISCI_DEV_DCC0,
452         .n_if = 1,
453         .p_if = &tisci_if_DCC0[0],
454 };
456 /* Start of DCC1 interface definition */
457 const struct Sciclient_rmIrqIf DCC1_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_89_89 = {
458         .lbase = 0,
459         .len = 1,
460         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
461         .rbase = 89,
462 };
463 const struct Sciclient_rmIrqIf * const tisci_if_DCC1[] = {
464         &DCC1_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_89_89,
465 };
466 static const struct Sciclient_rmIrqNode tisci_irq_DCC1 = {
467         .id = TISCI_DEV_DCC1,
468         .n_if = 1,
469         .p_if = &tisci_if_DCC1[0],
470 };
472 /* Start of DCC2 interface definition */
473 const struct Sciclient_rmIrqIf DCC2_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_90_90 = {
474         .lbase = 0,
475         .len = 1,
476         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
477         .rbase = 90,
478 };
479 const struct Sciclient_rmIrqIf * const tisci_if_DCC2[] = {
480         &DCC2_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_90_90,
481 };
482 static const struct Sciclient_rmIrqNode tisci_irq_DCC2 = {
483         .id = TISCI_DEV_DCC2,
484         .n_if = 1,
485         .p_if = &tisci_if_DCC2[0],
486 };
488 /* Start of DCC3 interface definition */
489 const struct Sciclient_rmIrqIf DCC3_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_91_91 = {
490         .lbase = 0,
491         .len = 1,
492         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
493         .rbase = 91,
494 };
495 const struct Sciclient_rmIrqIf * const tisci_if_DCC3[] = {
496         &DCC3_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_91_91,
497 };
498 static const struct Sciclient_rmIrqNode tisci_irq_DCC3 = {
499         .id = TISCI_DEV_DCC3,
500         .n_if = 1,
501         .p_if = &tisci_if_DCC3[0],
502 };
504 /* Start of DCC4 interface definition */
505 const struct Sciclient_rmIrqIf DCC4_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_92_92 = {
506         .lbase = 0,
507         .len = 1,
508         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
509         .rbase = 92,
510 };
511 const struct Sciclient_rmIrqIf * const tisci_if_DCC4[] = {
512         &DCC4_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_92_92,
513 };
514 static const struct Sciclient_rmIrqNode tisci_irq_DCC4 = {
515         .id = TISCI_DEV_DCC4,
516         .n_if = 1,
517         .p_if = &tisci_if_DCC4[0],
518 };
520 /* Start of DCC5 interface definition */
521 const struct Sciclient_rmIrqIf DCC5_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_93_93 = {
522         .lbase = 0,
523         .len = 1,
524         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
525         .rbase = 93,
526 };
527 const struct Sciclient_rmIrqIf * const tisci_if_DCC5[] = {
528         &DCC5_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_93_93,
529 };
530 static const struct Sciclient_rmIrqNode tisci_irq_DCC5 = {
531         .id = TISCI_DEV_DCC5,
532         .n_if = 1,
533         .p_if = &tisci_if_DCC5[0],
534 };
536 /* Start of DCC6 interface definition */
537 const struct Sciclient_rmIrqIf DCC6_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_94_94 = {
538         .lbase = 0,
539         .len = 1,
540         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
541         .rbase = 94,
542 };
543 const struct Sciclient_rmIrqIf * const tisci_if_DCC6[] = {
544         &DCC6_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_94_94,
545 };
546 static const struct Sciclient_rmIrqNode tisci_irq_DCC6 = {
547         .id = TISCI_DEV_DCC6,
548         .n_if = 1,
549         .p_if = &tisci_if_DCC6[0],
550 };
552 /* Start of DCC7 interface definition */
553 const struct Sciclient_rmIrqIf DCC7_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_95_95 = {
554         .lbase = 0,
555         .len = 1,
556         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
557         .rbase = 95,
558 };
559 const struct Sciclient_rmIrqIf * const tisci_if_DCC7[] = {
560         &DCC7_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_95_95,
561 };
562 static const struct Sciclient_rmIrqNode tisci_irq_DCC7 = {
563         .id = TISCI_DEV_DCC7,
564         .n_if = 1,
565         .p_if = &tisci_if_DCC7[0],
566 };
568 /* Start of DCC8 interface definition */
569 const struct Sciclient_rmIrqIf DCC8_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_208_208 = {
570         .lbase = 0,
571         .len = 1,
572         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
573         .rbase = 208,
574 };
575 const struct Sciclient_rmIrqIf * const tisci_if_DCC8[] = {
576         &DCC8_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_208_208,
577 };
578 static const struct Sciclient_rmIrqNode tisci_irq_DCC8 = {
579         .id = TISCI_DEV_DCC8,
580         .n_if = 1,
581         .p_if = &tisci_if_DCC8[0],
582 };
584 /* Start of DCC9 interface definition */
585 const struct Sciclient_rmIrqIf DCC9_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_209_209 = {
586         .lbase = 0,
587         .len = 1,
588         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
589         .rbase = 209,
590 };
591 const struct Sciclient_rmIrqIf * const tisci_if_DCC9[] = {
592         &DCC9_intr_done_level_0_0_to_MAIN2MCU_LVL_INTRTR0_in_209_209,
593 };
594 static const struct Sciclient_rmIrqNode tisci_irq_DCC9 = {
595         .id = TISCI_DEV_DCC9,
596         .n_if = 1,
597         .p_if = &tisci_if_DCC9[0],
598 };
600 /* Start of DMPAC0_INTD_0 interface definition */
601 const struct Sciclient_rmIrqIf DMPAC0_INTD_0_system_intr_level_0_1_to_MAIN2MCU_LVL_INTRTR0_in_268_269 = {
602         .lbase = 0,
603         .len = 2,
604         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
605         .rbase = 268,
606 };
607 const struct Sciclient_rmIrqIf * const tisci_if_DMPAC0_INTD_0[] = {
608         &DMPAC0_INTD_0_system_intr_level_0_1_to_MAIN2MCU_LVL_INTRTR0_in_268_269,
609 };
610 static const struct Sciclient_rmIrqNode tisci_irq_DMPAC0_INTD_0 = {
611         .id = TISCI_DEV_DMPAC0_INTD_0,
612         .n_if = 1,
613         .p_if = &tisci_if_DMPAC0_INTD_0[0],
614 };
616 /* Start of GTC0 interface definition */
617 const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_INTRTR0_in_1_1 = {
618         .lbase = 0,
619         .len = 1,
620         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
621         .rbase = 1,
622 };
623 const struct Sciclient_rmIrqIf * const tisci_if_GTC0[] = {
624         &GTC0_gtc_push_event_0_0_to_TIMESYNC_INTRTR0_in_1_1,
625 };
626 static const struct Sciclient_rmIrqNode tisci_irq_GTC0 = {
627         .id = TISCI_DEV_GTC0,
628         .n_if = 1,
629         .p_if = &tisci_if_GTC0[0],
630 };
632 /* Start of TIMER0 interface definition */
633 const struct Sciclient_rmIrqIf TIMER0_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_108_108 = {
634         .lbase = 0,
635         .len = 1,
636         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
637         .rbase = 108,
638 };
639 const struct Sciclient_rmIrqIf * const tisci_if_TIMER0[] = {
640         &TIMER0_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_108_108,
641 };
642 static const struct Sciclient_rmIrqNode tisci_irq_TIMER0 = {
643         .id = TISCI_DEV_TIMER0,
644         .n_if = 1,
645         .p_if = &tisci_if_TIMER0[0],
646 };
648 /* Start of TIMER1 interface definition */
649 const struct Sciclient_rmIrqIf TIMER1_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_109_109 = {
650         .lbase = 0,
651         .len = 1,
652         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
653         .rbase = 109,
654 };
655 const struct Sciclient_rmIrqIf * const tisci_if_TIMER1[] = {
656         &TIMER1_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_109_109,
657 };
658 static const struct Sciclient_rmIrqNode tisci_irq_TIMER1 = {
659         .id = TISCI_DEV_TIMER1,
660         .n_if = 1,
661         .p_if = &tisci_if_TIMER1[0],
662 };
664 /* Start of TIMER2 interface definition */
665 const struct Sciclient_rmIrqIf TIMER2_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_110_110 = {
666         .lbase = 0,
667         .len = 1,
668         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
669         .rbase = 110,
670 };
671 const struct Sciclient_rmIrqIf * const tisci_if_TIMER2[] = {
672         &TIMER2_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_110_110,
673 };
674 static const struct Sciclient_rmIrqNode tisci_irq_TIMER2 = {
675         .id = TISCI_DEV_TIMER2,
676         .n_if = 1,
677         .p_if = &tisci_if_TIMER2[0],
678 };
680 /* Start of TIMER3 interface definition */
681 const struct Sciclient_rmIrqIf TIMER3_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_111_111 = {
682         .lbase = 0,
683         .len = 1,
684         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
685         .rbase = 111,
686 };
687 const struct Sciclient_rmIrqIf * const tisci_if_TIMER3[] = {
688         &TIMER3_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_111_111,
689 };
690 static const struct Sciclient_rmIrqNode tisci_irq_TIMER3 = {
691         .id = TISCI_DEV_TIMER3,
692         .n_if = 1,
693         .p_if = &tisci_if_TIMER3[0],
694 };
696 /* Start of TIMER4 interface definition */
697 const struct Sciclient_rmIrqIf TIMER4_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_112_112 = {
698         .lbase = 0,
699         .len = 1,
700         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
701         .rbase = 112,
702 };
703 const struct Sciclient_rmIrqIf * const tisci_if_TIMER4[] = {
704         &TIMER4_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_112_112,
705 };
706 static const struct Sciclient_rmIrqNode tisci_irq_TIMER4 = {
707         .id = TISCI_DEV_TIMER4,
708         .n_if = 1,
709         .p_if = &tisci_if_TIMER4[0],
710 };
712 /* Start of TIMER5 interface definition */
713 const struct Sciclient_rmIrqIf TIMER5_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_113_113 = {
714         .lbase = 0,
715         .len = 1,
716         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
717         .rbase = 113,
718 };
719 const struct Sciclient_rmIrqIf * const tisci_if_TIMER5[] = {
720         &TIMER5_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_113_113,
721 };
722 static const struct Sciclient_rmIrqNode tisci_irq_TIMER5 = {
723         .id = TISCI_DEV_TIMER5,
724         .n_if = 1,
725         .p_if = &tisci_if_TIMER5[0],
726 };
728 /* Start of TIMER6 interface definition */
729 const struct Sciclient_rmIrqIf TIMER6_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_114_114 = {
730         .lbase = 0,
731         .len = 1,
732         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
733         .rbase = 114,
734 };
735 const struct Sciclient_rmIrqIf * const tisci_if_TIMER6[] = {
736         &TIMER6_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_114_114,
737 };
738 static const struct Sciclient_rmIrqNode tisci_irq_TIMER6 = {
739         .id = TISCI_DEV_TIMER6,
740         .n_if = 1,
741         .p_if = &tisci_if_TIMER6[0],
742 };
744 /* Start of TIMER7 interface definition */
745 const struct Sciclient_rmIrqIf TIMER7_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_115_115 = {
746         .lbase = 0,
747         .len = 1,
748         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
749         .rbase = 115,
750 };
751 const struct Sciclient_rmIrqIf * const tisci_if_TIMER7[] = {
752         &TIMER7_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_115_115,
753 };
754 static const struct Sciclient_rmIrqNode tisci_irq_TIMER7 = {
755         .id = TISCI_DEV_TIMER7,
756         .n_if = 1,
757         .p_if = &tisci_if_TIMER7[0],
758 };
760 /* Start of TIMER8 interface definition */
761 const struct Sciclient_rmIrqIf TIMER8_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_116_116 = {
762         .lbase = 0,
763         .len = 1,
764         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
765         .rbase = 116,
766 };
767 const struct Sciclient_rmIrqIf * const tisci_if_TIMER8[] = {
768         &TIMER8_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_116_116,
769 };
770 static const struct Sciclient_rmIrqNode tisci_irq_TIMER8 = {
771         .id = TISCI_DEV_TIMER8,
772         .n_if = 1,
773         .p_if = &tisci_if_TIMER8[0],
774 };
776 /* Start of TIMER9 interface definition */
777 const struct Sciclient_rmIrqIf TIMER9_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_117_117 = {
778         .lbase = 0,
779         .len = 1,
780         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
781         .rbase = 117,
782 };
783 const struct Sciclient_rmIrqIf * const tisci_if_TIMER9[] = {
784         &TIMER9_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_117_117,
785 };
786 static const struct Sciclient_rmIrqNode tisci_irq_TIMER9 = {
787         .id = TISCI_DEV_TIMER9,
788         .n_if = 1,
789         .p_if = &tisci_if_TIMER9[0],
790 };
792 /* Start of TIMER10 interface definition */
793 const struct Sciclient_rmIrqIf TIMER10_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_118_118 = {
794         .lbase = 0,
795         .len = 1,
796         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
797         .rbase = 118,
798 };
799 const struct Sciclient_rmIrqIf * const tisci_if_TIMER10[] = {
800         &TIMER10_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_118_118,
801 };
802 static const struct Sciclient_rmIrqNode tisci_irq_TIMER10 = {
803         .id = TISCI_DEV_TIMER10,
804         .n_if = 1,
805         .p_if = &tisci_if_TIMER10[0],
806 };
808 /* Start of TIMER11 interface definition */
809 const struct Sciclient_rmIrqIf TIMER11_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_119_119 = {
810         .lbase = 0,
811         .len = 1,
812         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
813         .rbase = 119,
814 };
815 const struct Sciclient_rmIrqIf * const tisci_if_TIMER11[] = {
816         &TIMER11_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_119_119,
817 };
818 static const struct Sciclient_rmIrqNode tisci_irq_TIMER11 = {
819         .id = TISCI_DEV_TIMER11,
820         .n_if = 1,
821         .p_if = &tisci_if_TIMER11[0],
822 };
824 /* Start of TIMER12 interface definition */
825 const struct Sciclient_rmIrqIf TIMER12_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_120_120 = {
826         .lbase = 0,
827         .len = 1,
828         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
829         .rbase = 120,
830 };
831 const struct Sciclient_rmIrqIf * const tisci_if_TIMER12[] = {
832         &TIMER12_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_120_120,
833 };
834 static const struct Sciclient_rmIrqNode tisci_irq_TIMER12 = {
835         .id = TISCI_DEV_TIMER12,
836         .n_if = 1,
837         .p_if = &tisci_if_TIMER12[0],
838 };
840 /* Start of TIMER13 interface definition */
841 const struct Sciclient_rmIrqIf TIMER13_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_121_121 = {
842         .lbase = 0,
843         .len = 1,
844         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
845         .rbase = 121,
846 };
847 const struct Sciclient_rmIrqIf * const tisci_if_TIMER13[] = {
848         &TIMER13_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_121_121,
849 };
850 static const struct Sciclient_rmIrqNode tisci_irq_TIMER13 = {
851         .id = TISCI_DEV_TIMER13,
852         .n_if = 1,
853         .p_if = &tisci_if_TIMER13[0],
854 };
856 /* Start of TIMER14 interface definition */
857 const struct Sciclient_rmIrqIf TIMER14_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_122_122 = {
858         .lbase = 0,
859         .len = 1,
860         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
861         .rbase = 122,
862 };
863 const struct Sciclient_rmIrqIf TIMER14_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_2_2 = {
864         .lbase = 1,
865         .len = 1,
866         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
867         .rbase = 2,
868 };
869 const struct Sciclient_rmIrqIf * const tisci_if_TIMER14[] = {
870         &TIMER14_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_122_122,
871         &TIMER14_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_2_2,
872 };
873 static const struct Sciclient_rmIrqNode tisci_irq_TIMER14 = {
874         .id = TISCI_DEV_TIMER14,
875         .n_if = 2,
876         .p_if = &tisci_if_TIMER14[0],
877 };
879 /* Start of TIMER15 interface definition */
880 const struct Sciclient_rmIrqIf TIMER15_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_123_123 = {
881         .lbase = 0,
882         .len = 1,
883         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
884         .rbase = 123,
885 };
886 const struct Sciclient_rmIrqIf TIMER15_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_3_3 = {
887         .lbase = 1,
888         .len = 1,
889         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
890         .rbase = 3,
891 };
892 const struct Sciclient_rmIrqIf * const tisci_if_TIMER15[] = {
893         &TIMER15_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_123_123,
894         &TIMER15_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_3_3,
895 };
896 static const struct Sciclient_rmIrqNode tisci_irq_TIMER15 = {
897         .id = TISCI_DEV_TIMER15,
898         .n_if = 2,
899         .p_if = &tisci_if_TIMER15[0],
900 };
902 /* Start of TIMER16 interface definition */
903 const struct Sciclient_rmIrqIf TIMER16_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_124_124 = {
904         .lbase = 0,
905         .len = 1,
906         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
907         .rbase = 124,
908 };
909 const struct Sciclient_rmIrqIf TIMER16_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_40_40 = {
910         .lbase = 1,
911         .len = 1,
912         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
913         .rbase = 40,
914 };
915 const struct Sciclient_rmIrqIf * const tisci_if_TIMER16[] = {
916         &TIMER16_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_124_124,
917         &TIMER16_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_40_40,
918 };
919 static const struct Sciclient_rmIrqNode tisci_irq_TIMER16 = {
920         .id = TISCI_DEV_TIMER16,
921         .n_if = 2,
922         .p_if = &tisci_if_TIMER16[0],
923 };
925 /* Start of TIMER17 interface definition */
926 const struct Sciclient_rmIrqIf TIMER17_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_125_125 = {
927         .lbase = 0,
928         .len = 1,
929         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
930         .rbase = 125,
931 };
932 const struct Sciclient_rmIrqIf TIMER17_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_41_41 = {
933         .lbase = 1,
934         .len = 1,
935         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
936         .rbase = 41,
937 };
938 const struct Sciclient_rmIrqIf * const tisci_if_TIMER17[] = {
939         &TIMER17_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_125_125,
940         &TIMER17_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_41_41,
941 };
942 static const struct Sciclient_rmIrqNode tisci_irq_TIMER17 = {
943         .id = TISCI_DEV_TIMER17,
944         .n_if = 2,
945         .p_if = &tisci_if_TIMER17[0],
946 };
948 /* Start of TIMER18 interface definition */
949 const struct Sciclient_rmIrqIf TIMER18_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_126_126 = {
950         .lbase = 0,
951         .len = 1,
952         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
953         .rbase = 126,
954 };
955 const struct Sciclient_rmIrqIf TIMER18_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_42_42 = {
956         .lbase = 1,
957         .len = 1,
958         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
959         .rbase = 42,
960 };
961 const struct Sciclient_rmIrqIf * const tisci_if_TIMER18[] = {
962         &TIMER18_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_126_126,
963         &TIMER18_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_42_42,
964 };
965 static const struct Sciclient_rmIrqNode tisci_irq_TIMER18 = {
966         .id = TISCI_DEV_TIMER18,
967         .n_if = 2,
968         .p_if = &tisci_if_TIMER18[0],
969 };
971 /* Start of TIMER19 interface definition */
972 const struct Sciclient_rmIrqIf TIMER19_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_127_127 = {
973         .lbase = 0,
974         .len = 1,
975         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
976         .rbase = 127,
977 };
978 const struct Sciclient_rmIrqIf TIMER19_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_43_43 = {
979         .lbase = 1,
980         .len = 1,
981         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
982         .rbase = 43,
983 };
984 const struct Sciclient_rmIrqIf * const tisci_if_TIMER19[] = {
985         &TIMER19_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_127_127,
986         &TIMER19_timer_pwm_1_1_to_TIMESYNC_INTRTR0_in_43_43,
987 };
988 static const struct Sciclient_rmIrqNode tisci_irq_TIMER19 = {
989         .id = TISCI_DEV_TIMER19,
990         .n_if = 2,
991         .p_if = &tisci_if_TIMER19[0],
992 };
994 /* Start of ECAP0 interface definition */
995 const struct Sciclient_rmIrqIf ECAP0_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_17_17 = {
996         .lbase = 0,
997         .len = 1,
998         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
999         .rbase = 17,
1000 };
1001 const struct Sciclient_rmIrqIf * const tisci_if_ECAP0[] = {
1002         &ECAP0_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_17_17,
1003 };
1004 static const struct Sciclient_rmIrqNode tisci_irq_ECAP0 = {
1005         .id = TISCI_DEV_ECAP0,
1006         .n_if = 1,
1007         .p_if = &tisci_if_ECAP0[0],
1008 };
1010 /* Start of ECAP1 interface definition */
1011 const struct Sciclient_rmIrqIf ECAP1_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_18_18 = {
1012         .lbase = 0,
1013         .len = 1,
1014         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1015         .rbase = 18,
1016 };
1017 const struct Sciclient_rmIrqIf * const tisci_if_ECAP1[] = {
1018         &ECAP1_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_18_18,
1019 };
1020 static const struct Sciclient_rmIrqNode tisci_irq_ECAP1 = {
1021         .id = TISCI_DEV_ECAP1,
1022         .n_if = 1,
1023         .p_if = &tisci_if_ECAP1[0],
1024 };
1026 /* Start of ECAP2 interface definition */
1027 const struct Sciclient_rmIrqIf ECAP2_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_19_19 = {
1028         .lbase = 0,
1029         .len = 1,
1030         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1031         .rbase = 19,
1032 };
1033 const struct Sciclient_rmIrqIf * const tisci_if_ECAP2[] = {
1034         &ECAP2_ecap_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_19_19,
1035 };
1036 static const struct Sciclient_rmIrqNode tisci_irq_ECAP2 = {
1037         .id = TISCI_DEV_ECAP2,
1038         .n_if = 1,
1039         .p_if = &tisci_if_ECAP2[0],
1040 };
1042 /* Start of ELM0 interface definition */
1043 const struct Sciclient_rmIrqIf ELM0_elm_porocpsinterrupt_lvl_0_0_to_MAIN2MCU_LVL_INTRTR0_in_7_7 = {
1044         .lbase = 0,
1045         .len = 1,
1046         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1047         .rbase = 7,
1048 };
1049 const struct Sciclient_rmIrqIf * const tisci_if_ELM0[] = {
1050         &ELM0_elm_porocpsinterrupt_lvl_0_0_to_MAIN2MCU_LVL_INTRTR0_in_7_7,
1051 };
1052 static const struct Sciclient_rmIrqNode tisci_irq_ELM0 = {
1053         .id = TISCI_DEV_ELM0,
1054         .n_if = 1,
1055         .p_if = &tisci_if_ELM0[0],
1056 };
1058 /* Start of MMCSD0 interface definition */
1059 const struct Sciclient_rmIrqIf MMCSD0_emmcss_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_28_28 = {
1060         .lbase = 0,
1061         .len = 1,
1062         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1063         .rbase = 28,
1064 };
1065 const struct Sciclient_rmIrqIf * const tisci_if_MMCSD0[] = {
1066         &MMCSD0_emmcss_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_28_28,
1067 };
1068 static const struct Sciclient_rmIrqNode tisci_irq_MMCSD0 = {
1069         .id = TISCI_DEV_MMCSD0,
1070         .n_if = 1,
1071         .p_if = &tisci_if_MMCSD0[0],
1072 };
1074 /* Start of MMCSD1 interface definition */
1075 const struct Sciclient_rmIrqIf MMCSD1_emmcsdss_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_29_29 = {
1076         .lbase = 0,
1077         .len = 1,
1078         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1079         .rbase = 29,
1080 };
1081 const struct Sciclient_rmIrqIf * const tisci_if_MMCSD1[] = {
1082         &MMCSD1_emmcsdss_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_29_29,
1083 };
1084 static const struct Sciclient_rmIrqNode tisci_irq_MMCSD1 = {
1085         .id = TISCI_DEV_MMCSD1,
1086         .n_if = 1,
1087         .p_if = &tisci_if_MMCSD1[0],
1088 };
1090 /* Start of EQEP0 interface definition */
1091 const struct Sciclient_rmIrqIf EQEP0_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_14_14 = {
1092         .lbase = 0,
1093         .len = 1,
1094         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1095         .rbase = 14,
1096 };
1097 const struct Sciclient_rmIrqIf * const tisci_if_EQEP0[] = {
1098         &EQEP0_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_14_14,
1099 };
1100 static const struct Sciclient_rmIrqNode tisci_irq_EQEP0 = {
1101         .id = TISCI_DEV_EQEP0,
1102         .n_if = 1,
1103         .p_if = &tisci_if_EQEP0[0],
1104 };
1106 /* Start of EQEP1 interface definition */
1107 const struct Sciclient_rmIrqIf EQEP1_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_15_15 = {
1108         .lbase = 0,
1109         .len = 1,
1110         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1111         .rbase = 15,
1112 };
1113 const struct Sciclient_rmIrqIf * const tisci_if_EQEP1[] = {
1114         &EQEP1_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_15_15,
1115 };
1116 static const struct Sciclient_rmIrqNode tisci_irq_EQEP1 = {
1117         .id = TISCI_DEV_EQEP1,
1118         .n_if = 1,
1119         .p_if = &tisci_if_EQEP1[0],
1120 };
1122 /* Start of EQEP2 interface definition */
1123 const struct Sciclient_rmIrqIf EQEP2_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_16_16 = {
1124         .lbase = 0,
1125         .len = 1,
1126         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1127         .rbase = 16,
1128 };
1129 const struct Sciclient_rmIrqIf * const tisci_if_EQEP2[] = {
1130         &EQEP2_eqep_int_0_0_to_MAIN2MCU_PLS_INTRTR0_in_16_16,
1131 };
1132 static const struct Sciclient_rmIrqNode tisci_irq_EQEP2 = {
1133         .id = TISCI_DEV_EQEP2,
1134         .n_if = 1,
1135         .p_if = &tisci_if_EQEP2[0],
1136 };
1138 /* Start of GPIO0 interface definition */
1139 const struct Sciclient_rmIrqIf GPIO0_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_145_152 = {
1140         .lbase = 0,
1141         .len = 8,
1142         .rid = TISCI_DEV_GPIOMUX_INTRTR0,
1143         .rbase = 145,
1144 };
1145 const struct Sciclient_rmIrqIf * const tisci_if_GPIO0[] = {
1146         &GPIO0_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_145_152,
1147 };
1148 static const struct Sciclient_rmIrqNode tisci_irq_GPIO0 = {
1149         .id = TISCI_DEV_GPIO0,
1150         .n_if = 1,
1151         .p_if = &tisci_if_GPIO0[0],
1152 };
1154 /* Start of GPIO2 interface definition */
1155 const struct Sciclient_rmIrqIf GPIO2_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_154_161 = {
1156         .lbase = 0,
1157         .len = 8,
1158         .rid = TISCI_DEV_GPIOMUX_INTRTR0,
1159         .rbase = 154,
1160 };
1161 const struct Sciclient_rmIrqIf * const tisci_if_GPIO2[] = {
1162         &GPIO2_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_154_161,
1163 };
1164 static const struct Sciclient_rmIrqNode tisci_irq_GPIO2 = {
1165         .id = TISCI_DEV_GPIO2,
1166         .n_if = 1,
1167         .p_if = &tisci_if_GPIO2[0],
1168 };
1170 /* Start of GPIO4 interface definition */
1171 const struct Sciclient_rmIrqIf GPIO4_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_163_170 = {
1172         .lbase = 0,
1173         .len = 8,
1174         .rid = TISCI_DEV_GPIOMUX_INTRTR0,
1175         .rbase = 163,
1176 };
1177 const struct Sciclient_rmIrqIf * const tisci_if_GPIO4[] = {
1178         &GPIO4_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_163_170,
1179 };
1180 static const struct Sciclient_rmIrqNode tisci_irq_GPIO4 = {
1181         .id = TISCI_DEV_GPIO4,
1182         .n_if = 1,
1183         .p_if = &tisci_if_GPIO4[0],
1184 };
1186 /* Start of GPIO6 interface definition */
1187 const struct Sciclient_rmIrqIf GPIO6_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_172_179 = {
1188         .lbase = 0,
1189         .len = 8,
1190         .rid = TISCI_DEV_GPIOMUX_INTRTR0,
1191         .rbase = 172,
1192 };
1193 const struct Sciclient_rmIrqIf * const tisci_if_GPIO6[] = {
1194         &GPIO6_gpio_bank_0_7_to_GPIOMUX_INTRTR0_in_172_179,
1195 };
1196 static const struct Sciclient_rmIrqNode tisci_irq_GPIO6 = {
1197         .id = TISCI_DEV_GPIO6,
1198         .n_if = 1,
1199         .p_if = &tisci_if_GPIO6[0],
1200 };
1202 /* Start of WKUP_GPIO0 interface definition */
1203 const struct Sciclient_rmIrqIf WKUP_GPIO0_gpio_bank_0_5_to_WKUP_GPIOMUX_INTRTR0_in_103_108 = {
1204         .lbase = 0,
1205         .len = 6,
1206         .rid = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
1207         .rbase = 103,
1208 };
1209 const struct Sciclient_rmIrqIf * const tisci_if_WKUP_GPIO0[] = {
1210         &WKUP_GPIO0_gpio_bank_0_5_to_WKUP_GPIOMUX_INTRTR0_in_103_108,
1211 };
1212 static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIO0 = {
1213         .id = TISCI_DEV_WKUP_GPIO0,
1214         .n_if = 1,
1215         .p_if = &tisci_if_WKUP_GPIO0[0],
1216 };
1218 /* Start of WKUP_GPIO1 interface definition */
1219 const struct Sciclient_rmIrqIf WKUP_GPIO1_gpio_bank_0_5_to_WKUP_GPIOMUX_INTRTR0_in_112_117 = {
1220         .lbase = 0,
1221         .len = 6,
1222         .rid = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
1223         .rbase = 112,
1224 };
1225 const struct Sciclient_rmIrqIf * const tisci_if_WKUP_GPIO1[] = {
1226         &WKUP_GPIO1_gpio_bank_0_5_to_WKUP_GPIOMUX_INTRTR0_in_112_117,
1227 };
1228 static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIO1 = {
1229         .id = TISCI_DEV_WKUP_GPIO1,
1230         .n_if = 1,
1231         .p_if = &tisci_if_WKUP_GPIO1[0],
1232 };
1234 /* Start of GPMC0 interface definition */
1235 const struct Sciclient_rmIrqIf GPMC0_gpmc_sinterrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_8_8 = {
1236         .lbase = 0,
1237         .len = 1,
1238         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1239         .rbase = 8,
1240 };
1241 const struct Sciclient_rmIrqIf * const tisci_if_GPMC0[] = {
1242         &GPMC0_gpmc_sinterrupt_0_0_to_MAIN2MCU_LVL_INTRTR0_in_8_8,
1243 };
1244 static const struct Sciclient_rmIrqNode tisci_irq_GPMC0 = {
1245         .id = TISCI_DEV_GPMC0,
1246         .n_if = 1,
1247         .p_if = &tisci_if_GPMC0[0],
1248 };
1250 /* Start of MAIN2MCU_LVL_INTRTR0 interface definition */
1251 const struct Sciclient_rmIrqIf MAIN2MCU_LVL_INTRTR0_outl_0_63_to_MCU_R5FSS0_CORE0_intr_160_223 = {
1252         .lbase = 0,
1253         .len = 64,
1254         .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
1255         .rbase = 160,
1256 };
1257 const struct Sciclient_rmIrqIf MAIN2MCU_LVL_INTRTR0_outl_0_63_to_MCU_R5FSS0_CORE1_intr_160_223 = {
1258         .lbase = 0,
1259         .len = 64,
1260         .rid = TISCI_DEV_MCU_R5FSS0_CORE1,
1261         .rbase = 160,
1262 };
1263 const struct Sciclient_rmIrqIf MAIN2MCU_LVL_INTRTR0_outl_56_63_to_WKUP_TIFS0_nvic_64_71 = {
1264         .lbase = 56,
1265         .len = 8,
1266         .rid = TISCI_DEV_WKUP_TIFS0,
1267         .rbase = 64,
1268 };
1269 const struct Sciclient_rmIrqIf MAIN2MCU_LVL_INTRTR0_outl_56_63_to_WKUP_HSM0_nvic_64_71 = {
1270         .lbase = 56,
1271         .len = 8,
1272         .rid = TISCI_DEV_WKUP_HSM0,
1273         .rbase = 64,
1274 };
1275 const struct Sciclient_rmIrqIf * const tisci_if_MAIN2MCU_LVL_INTRTR0[] = {
1276         &MAIN2MCU_LVL_INTRTR0_outl_0_63_to_MCU_R5FSS0_CORE0_intr_160_223,
1277         &MAIN2MCU_LVL_INTRTR0_outl_0_63_to_MCU_R5FSS0_CORE1_intr_160_223,
1278         &MAIN2MCU_LVL_INTRTR0_outl_56_63_to_WKUP_TIFS0_nvic_64_71,
1279         &MAIN2MCU_LVL_INTRTR0_outl_56_63_to_WKUP_HSM0_nvic_64_71,
1280 };
1281 static const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_LVL_INTRTR0 = {
1282         .id = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1283         .n_if = 4,
1284         .p_if = &tisci_if_MAIN2MCU_LVL_INTRTR0[0],
1285 };
1287 /* Start of MAIN2MCU_PLS_INTRTR0 interface definition */
1288 const struct Sciclient_rmIrqIf MAIN2MCU_PLS_INTRTR0_outp_0_47_to_MCU_R5FSS0_CORE0_intr_224_271 = {
1289         .lbase = 0,
1290         .len = 48,
1291         .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
1292         .rbase = 224,
1293 };
1294 const struct Sciclient_rmIrqIf MAIN2MCU_PLS_INTRTR0_outp_0_47_to_MCU_R5FSS0_CORE1_intr_224_271 = {
1295         .lbase = 0,
1296         .len = 48,
1297         .rid = TISCI_DEV_MCU_R5FSS0_CORE1,
1298         .rbase = 224,
1299 };
1300 const struct Sciclient_rmIrqIf MAIN2MCU_PLS_INTRTR0_outp_40_47_to_WKUP_TIFS0_nvic_72_79 = {
1301         .lbase = 40,
1302         .len = 8,
1303         .rid = TISCI_DEV_WKUP_TIFS0,
1304         .rbase = 72,
1305 };
1306 const struct Sciclient_rmIrqIf MAIN2MCU_PLS_INTRTR0_outp_40_47_to_WKUP_HSM0_nvic_72_79 = {
1307         .lbase = 40,
1308         .len = 8,
1309         .rid = TISCI_DEV_WKUP_HSM0,
1310         .rbase = 72,
1311 };
1312 const struct Sciclient_rmIrqIf * const tisci_if_MAIN2MCU_PLS_INTRTR0[] = {
1313         &MAIN2MCU_PLS_INTRTR0_outp_0_47_to_MCU_R5FSS0_CORE0_intr_224_271,
1314         &MAIN2MCU_PLS_INTRTR0_outp_0_47_to_MCU_R5FSS0_CORE1_intr_224_271,
1315         &MAIN2MCU_PLS_INTRTR0_outp_40_47_to_WKUP_TIFS0_nvic_72_79,
1316         &MAIN2MCU_PLS_INTRTR0_outp_40_47_to_WKUP_HSM0_nvic_72_79,
1317 };
1318 static const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_PLS_INTRTR0 = {
1319         .id = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1320         .n_if = 4,
1321         .p_if = &tisci_if_MAIN2MCU_PLS_INTRTR0[0],
1322 };
1324 /* Start of TIMESYNC_INTRTR0 interface definition */
1325 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_0_0_to_NAVSS0_cpts0_hw1_push_0_0 = {
1326         .lbase = 0,
1327         .len = 1,
1328         .rid = TISCI_DEV_NAVSS0,
1329         .rbase = 0,
1330 };
1331 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_1_1_to_NAVSS0_cpts0_hw2_push_1_1 = {
1332         .lbase = 1,
1333         .len = 1,
1334         .rid = TISCI_DEV_NAVSS0,
1335         .rbase = 1,
1336 };
1337 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_2_2_to_NAVSS0_cpts0_hw3_push_2_2 = {
1338         .lbase = 2,
1339         .len = 1,
1340         .rid = TISCI_DEV_NAVSS0,
1341         .rbase = 2,
1342 };
1343 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_3_3_to_NAVSS0_cpts0_hw4_push_3_3 = {
1344         .lbase = 3,
1345         .len = 1,
1346         .rid = TISCI_DEV_NAVSS0,
1347         .rbase = 3,
1348 };
1349 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_4_4_to_NAVSS0_cpts0_hw5_push_4_4 = {
1350         .lbase = 4,
1351         .len = 1,
1352         .rid = TISCI_DEV_NAVSS0,
1353         .rbase = 4,
1354 };
1355 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_5_5_to_NAVSS0_cpts0_hw6_push_5_5 = {
1356         .lbase = 5,
1357         .len = 1,
1358         .rid = TISCI_DEV_NAVSS0,
1359         .rbase = 5,
1360 };
1361 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_6_6_to_NAVSS0_cpts0_hw7_push_6_6 = {
1362         .lbase = 6,
1363         .len = 1,
1364         .rid = TISCI_DEV_NAVSS0,
1365         .rbase = 6,
1366 };
1367 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_7_7_to_NAVSS0_cpts0_hw8_push_7_7 = {
1368         .lbase = 7,
1369         .len = 1,
1370         .rid = TISCI_DEV_NAVSS0,
1371         .rbase = 7,
1372 };
1373 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_21_21_to_PCIE1_pcie_cpts_hw2_push_0_0 = {
1374         .lbase = 21,
1375         .len = 1,
1376         .rid = TISCI_DEV_PCIE1,
1377         .rbase = 0,
1378 };
1379 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_24_24_to_MCU_CPSW0_cpts_hw3_push_0_0 = {
1380         .lbase = 24,
1381         .len = 1,
1382         .rid = TISCI_DEV_MCU_CPSW0,
1383         .rbase = 0,
1384 };
1385 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_25_25_to_MCU_CPSW0_cpts_hw4_push_1_1 = {
1386         .lbase = 25,
1387         .len = 1,
1388         .rid = TISCI_DEV_MCU_CPSW0,
1389         .rbase = 1,
1390 };
1391 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_38_38_to_CPSW1_cpts_hw3_push_0_0 = {
1392         .lbase = 38,
1393         .len = 1,
1394         .rid = TISCI_DEV_CPSW1,
1395         .rbase = 0,
1396 };
1397 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_39_39_to_CPSW1_cpts_hw4_push_1_1 = {
1398         .lbase = 39,
1399         .len = 1,
1400         .rid = TISCI_DEV_CPSW1,
1401         .rbase = 1,
1402 };
1403 const struct Sciclient_rmIrqIf TIMESYNC_INTRTR0_outl_40_47_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_100_107 = {
1404         .lbase = 40,
1405         .len = 8,
1406         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
1407         .rbase = 100,
1408 };
1409 const struct Sciclient_rmIrqIf * const tisci_if_TIMESYNC_INTRTR0[] = {
1410         &TIMESYNC_INTRTR0_outl_0_0_to_NAVSS0_cpts0_hw1_push_0_0,
1411         &TIMESYNC_INTRTR0_outl_1_1_to_NAVSS0_cpts0_hw2_push_1_1,
1412         &TIMESYNC_INTRTR0_outl_2_2_to_NAVSS0_cpts0_hw3_push_2_2,
1413         &TIMESYNC_INTRTR0_outl_3_3_to_NAVSS0_cpts0_hw4_push_3_3,
1414         &TIMESYNC_INTRTR0_outl_4_4_to_NAVSS0_cpts0_hw5_push_4_4,
1415         &TIMESYNC_INTRTR0_outl_5_5_to_NAVSS0_cpts0_hw6_push_5_5,
1416         &TIMESYNC_INTRTR0_outl_6_6_to_NAVSS0_cpts0_hw7_push_6_6,
1417         &TIMESYNC_INTRTR0_outl_7_7_to_NAVSS0_cpts0_hw8_push_7_7,
1418         &TIMESYNC_INTRTR0_outl_21_21_to_PCIE1_pcie_cpts_hw2_push_0_0,
1419         &TIMESYNC_INTRTR0_outl_24_24_to_MCU_CPSW0_cpts_hw3_push_0_0,
1420         &TIMESYNC_INTRTR0_outl_25_25_to_MCU_CPSW0_cpts_hw4_push_1_1,
1421         &TIMESYNC_INTRTR0_outl_38_38_to_CPSW1_cpts_hw3_push_0_0,
1422         &TIMESYNC_INTRTR0_outl_39_39_to_CPSW1_cpts_hw4_push_1_1,
1423         &TIMESYNC_INTRTR0_outl_40_47_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_100_107,
1424 };
1425 static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_INTRTR0 = {
1426         .id = TISCI_DEV_TIMESYNC_INTRTR0,
1427         .n_if = 14,
1428         .p_if = &tisci_if_TIMESYNC_INTRTR0[0],
1429 };
1431 /* Start of WKUP_GPIOMUX_INTRTR0 interface definition */
1432 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_0_15_to_MCU_R5FSS0_CORE0_intr_124_139 = {
1433         .lbase = 0,
1434         .len = 16,
1435         .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
1436         .rbase = 124,
1437 };
1438 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_0_15_to_MCU_R5FSS0_CORE1_intr_124_139 = {
1439         .lbase = 0,
1440         .len = 16,
1441         .rid = TISCI_DEV_MCU_R5FSS0_CORE1,
1442         .rbase = 124,
1443 };
1444 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_0_11_to_WKUP_TIFS0_nvic_184_195 = {
1445         .lbase = 0,
1446         .len = 12,
1447         .rid = TISCI_DEV_WKUP_TIFS0,
1448         .rbase = 184,
1449 };
1450 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_0_11_to_WKUP_HSM0_nvic_184_195 = {
1451         .lbase = 0,
1452         .len = 12,
1453         .rid = TISCI_DEV_WKUP_HSM0,
1454         .rbase = 184,
1455 };
1456 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event0_120_127 = {
1457         .lbase = 8,
1458         .len = 8,
1459         .rid = TISCI_DEV_WKUP_ESM0,
1460         .rbase = 120,
1461 };
1462 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event1_128_135 = {
1463         .lbase = 8,
1464         .len = 8,
1465         .rid = TISCI_DEV_WKUP_ESM0,
1466         .rbase = 128,
1467 };
1468 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event2_136_143 = {
1469         .lbase = 8,
1470         .len = 8,
1471         .rid = TISCI_DEV_WKUP_ESM0,
1472         .rbase = 136,
1473 };
1474 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_12_19_to_MCU_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_4_11 = {
1475         .lbase = 12,
1476         .len = 8,
1477         .rid = TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1478         .rbase = 4,
1479 };
1480 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_960_975 = {
1481         .lbase = 16,
1482         .len = 16,
1483         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
1484         .rbase = 960,
1485 };
1486 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_COMPUTE_CLUSTER0_GIC500SS_spi_928_943 = {
1487         .lbase = 16,
1488         .len = 16,
1489         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
1490         .rbase = 928,
1491 };
1492 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE0_intr_488_503 = {
1493         .lbase = 16,
1494         .len = 16,
1495         .rid = TISCI_DEV_R5FSS0_CORE0,
1496         .rbase = 488,
1497 };
1498 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE1_intr_488_503 = {
1499         .lbase = 16,
1500         .len = 16,
1501         .rid = TISCI_DEV_R5FSS0_CORE1,
1502         .rbase = 488,
1503 };
1504 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE0_intr_488_503 = {
1505         .lbase = 16,
1506         .len = 16,
1507         .rid = TISCI_DEV_R5FSS1_CORE0,
1508         .rbase = 488,
1509 };
1510 const struct Sciclient_rmIrqIf WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE1_intr_488_503 = {
1511         .lbase = 16,
1512         .len = 16,
1513         .rid = TISCI_DEV_R5FSS1_CORE1,
1514         .rbase = 488,
1515 };
1516 const struct Sciclient_rmIrqIf * const tisci_if_WKUP_GPIOMUX_INTRTR0[] = {
1517         &WKUP_GPIOMUX_INTRTR0_outp_0_15_to_MCU_R5FSS0_CORE0_intr_124_139,
1518         &WKUP_GPIOMUX_INTRTR0_outp_0_15_to_MCU_R5FSS0_CORE1_intr_124_139,
1519         &WKUP_GPIOMUX_INTRTR0_outp_0_11_to_WKUP_TIFS0_nvic_184_195,
1520         &WKUP_GPIOMUX_INTRTR0_outp_0_11_to_WKUP_HSM0_nvic_184_195,
1521         &WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event0_120_127,
1522         &WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event1_128_135,
1523         &WKUP_GPIOMUX_INTRTR0_outp_8_15_to_WKUP_ESM0_esm_pls_event2_136_143,
1524         &WKUP_GPIOMUX_INTRTR0_outp_12_19_to_MCU_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_4_11,
1525         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_960_975,
1526         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_COMPUTE_CLUSTER0_GIC500SS_spi_928_943,
1527         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE0_intr_488_503,
1528         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE1_intr_488_503,
1529         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE0_intr_488_503,
1530         &WKUP_GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE1_intr_488_503,
1531 };
1532 static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIOMUX_INTRTR0 = {
1533         .id = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
1534         .n_if = 14,
1535         .p_if = &tisci_if_WKUP_GPIOMUX_INTRTR0[0],
1536 };
1538 /* Start of J7AEP_GPU_BXS464_WRAP0 interface definition */
1539 const struct Sciclient_rmIrqIf J7AEP_GPU_BXS464_WRAP0_gpu_pwrctrl_req_0_0_to_MAIN2MCU_LVL_INTRTR0_in_316_316 = {
1540         .lbase = 0,
1541         .len = 1,
1542         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1543         .rbase = 316,
1544 };
1545 const struct Sciclient_rmIrqIf * const tisci_if_J7AEP_GPU_BXS464_WRAP0[] = {
1546         &J7AEP_GPU_BXS464_WRAP0_gpu_pwrctrl_req_0_0_to_MAIN2MCU_LVL_INTRTR0_in_316_316,
1547 };
1548 static const struct Sciclient_rmIrqNode tisci_irq_J7AEP_GPU_BXS464_WRAP0 = {
1549         .id = TISCI_DEV_J7AEP_GPU_BXS464_WRAP0,
1550         .n_if = 1,
1551         .p_if = &tisci_if_J7AEP_GPU_BXS464_WRAP0[0],
1552 };
1554 /* Start of J7AEP_GPU_BXS464_WRAP0_COMMON_0 interface definition */
1555 const struct Sciclient_rmIrqIf J7AEP_GPU_BXS464_WRAP0_COMMON_0_os_irq_0_3_to_MAIN2MCU_LVL_INTRTR0_in_312_315 = {
1556         .lbase = 0,
1557         .len = 4,
1558         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1559         .rbase = 312,
1560 };
1561 const struct Sciclient_rmIrqIf * const tisci_if_J7AEP_GPU_BXS464_WRAP0_COMMON_0[] = {
1562         &J7AEP_GPU_BXS464_WRAP0_COMMON_0_os_irq_0_3_to_MAIN2MCU_LVL_INTRTR0_in_312_315,
1563 };
1564 static const struct Sciclient_rmIrqNode tisci_irq_J7AEP_GPU_BXS464_WRAP0_COMMON_0 = {
1565         .id = TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_COMMON_0,
1566         .n_if = 1,
1567         .p_if = &tisci_if_J7AEP_GPU_BXS464_WRAP0_COMMON_0[0],
1568 };
1570 /* Start of DDR0 interface definition */
1571 const struct Sciclient_rmIrqIf DDR0_ddrss_pll_freq_change_req_2_2_to_MAIN2MCU_LVL_INTRTR0_in_9_9 = {
1572         .lbase = 2,
1573         .len = 1,
1574         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1575         .rbase = 9,
1576 };
1577 const struct Sciclient_rmIrqIf DDR0_ddrss_controller_0_0_to_MAIN2MCU_LVL_INTRTR0_in_10_10 = {
1578         .lbase = 0,
1579         .len = 1,
1580         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1581         .rbase = 10,
1582 };
1583 const struct Sciclient_rmIrqIf DDR0_ddrss_v2a_other_err_lvl_3_3_to_MAIN2MCU_LVL_INTRTR0_in_11_11 = {
1584         .lbase = 3,
1585         .len = 1,
1586         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1587         .rbase = 11,
1588 };
1589 const struct Sciclient_rmIrqIf DDR0_ddrss_hs_phy_global_error_1_1_to_MAIN2MCU_LVL_INTRTR0_in_12_12 = {
1590         .lbase = 1,
1591         .len = 1,
1592         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1593         .rbase = 12,
1594 };
1595 const struct Sciclient_rmIrqIf * const tisci_if_DDR0[] = {
1596         &DDR0_ddrss_pll_freq_change_req_2_2_to_MAIN2MCU_LVL_INTRTR0_in_9_9,
1597         &DDR0_ddrss_controller_0_0_to_MAIN2MCU_LVL_INTRTR0_in_10_10,
1598         &DDR0_ddrss_v2a_other_err_lvl_3_3_to_MAIN2MCU_LVL_INTRTR0_in_11_11,
1599         &DDR0_ddrss_hs_phy_global_error_1_1_to_MAIN2MCU_LVL_INTRTR0_in_12_12,
1600 };
1601 static const struct Sciclient_rmIrqNode tisci_irq_DDR0 = {
1602         .id = TISCI_DEV_DDR0,
1603         .n_if = 4,
1604         .p_if = &tisci_if_DDR0[0],
1605 };
1607 /* Start of DDR1 interface definition */
1608 const struct Sciclient_rmIrqIf DDR1_ddrss_pll_freq_change_req_2_2_to_MAIN2MCU_LVL_INTRTR0_in_63_63 = {
1609         .lbase = 2,
1610         .len = 1,
1611         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1612         .rbase = 63,
1613 };
1614 const struct Sciclient_rmIrqIf DDR1_ddrss_controller_0_0_to_MAIN2MCU_LVL_INTRTR0_in_64_64 = {
1615         .lbase = 0,
1616         .len = 1,
1617         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1618         .rbase = 64,
1619 };
1620 const struct Sciclient_rmIrqIf DDR1_ddrss_v2a_other_err_lvl_3_3_to_MAIN2MCU_LVL_INTRTR0_in_65_65 = {
1621         .lbase = 3,
1622         .len = 1,
1623         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1624         .rbase = 65,
1625 };
1626 const struct Sciclient_rmIrqIf DDR1_ddrss_hs_phy_global_error_1_1_to_MAIN2MCU_LVL_INTRTR0_in_66_66 = {
1627         .lbase = 1,
1628         .len = 1,
1629         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1630         .rbase = 66,
1631 };
1632 const struct Sciclient_rmIrqIf * const tisci_if_DDR1[] = {
1633         &DDR1_ddrss_pll_freq_change_req_2_2_to_MAIN2MCU_LVL_INTRTR0_in_63_63,
1634         &DDR1_ddrss_controller_0_0_to_MAIN2MCU_LVL_INTRTR0_in_64_64,
1635         &DDR1_ddrss_v2a_other_err_lvl_3_3_to_MAIN2MCU_LVL_INTRTR0_in_65_65,
1636         &DDR1_ddrss_hs_phy_global_error_1_1_to_MAIN2MCU_LVL_INTRTR0_in_66_66,
1637 };
1638 static const struct Sciclient_rmIrqNode tisci_irq_DDR1 = {
1639         .id = TISCI_DEV_DDR1,
1640         .n_if = 4,
1641         .p_if = &tisci_if_DDR1[0],
1642 };
1644 /* Start of UART0 interface definition */
1645 const struct Sciclient_rmIrqIf UART0_usart_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_96_96 = {
1646         .lbase = 0,
1647         .len = 1,
1648         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1649         .rbase = 96,
1650 };
1651 const struct Sciclient_rmIrqIf * const tisci_if_UART0[] = {
1652         &UART0_usart_irq_0_0_to_MAIN2MCU_LVL_INTRTR0_in_96_96,
1653 };
1654 static const struct Sciclient_rmIrqNode tisci_irq_UART0 = {
1655         .id = TISCI_DEV_UART0,
1656         .n_if = 1,
1657         .p_if = &tisci_if_UART0[0],
1658 };
1660 /* Start of GPIOMUX_INTRTR0 interface definition */
1661 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event0_664_671 = {
1662         .lbase = 0,
1663         .len = 8,
1664         .rid = TISCI_DEV_ESM0,
1665         .rbase = 664,
1666 };
1667 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event1_672_679 = {
1668         .lbase = 0,
1669         .len = 8,
1670         .rid = TISCI_DEV_ESM0,
1671         .rbase = 672,
1672 };
1673 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event2_680_687 = {
1674         .lbase = 0,
1675         .len = 8,
1676         .rid = TISCI_DEV_ESM0,
1677         .rbase = 680,
1678 };
1679 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_31_to_MAIN2MCU_PLS_INTRTR0_in_64_95 = {
1680         .lbase = 0,
1681         .len = 32,
1682         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1683         .rbase = 64,
1684 };
1685 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE0_intr_176_191 = {
1686         .lbase = 16,
1687         .len = 16,
1688         .rid = TISCI_DEV_R5FSS0_CORE0,
1689         .rbase = 176,
1690 };
1691 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_15_to_R5FSS0_CORE0_intr_396_411 = {
1692         .lbase = 0,
1693         .len = 16,
1694         .rid = TISCI_DEV_R5FSS0_CORE0,
1695         .rbase = 396,
1696 };
1697 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE1_intr_176_191 = {
1698         .lbase = 16,
1699         .len = 16,
1700         .rid = TISCI_DEV_R5FSS0_CORE1,
1701         .rbase = 176,
1702 };
1703 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_15_to_R5FSS0_CORE1_intr_396_411 = {
1704         .lbase = 0,
1705         .len = 16,
1706         .rid = TISCI_DEV_R5FSS0_CORE1,
1707         .rbase = 396,
1708 };
1709 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE0_intr_176_191 = {
1710         .lbase = 16,
1711         .len = 16,
1712         .rid = TISCI_DEV_R5FSS1_CORE0,
1713         .rbase = 176,
1714 };
1715 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_15_to_R5FSS1_CORE0_intr_396_411 = {
1716         .lbase = 0,
1717         .len = 16,
1718         .rid = TISCI_DEV_R5FSS1_CORE0,
1719         .rbase = 396,
1720 };
1721 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE1_intr_176_191 = {
1722         .lbase = 16,
1723         .len = 16,
1724         .rid = TISCI_DEV_R5FSS1_CORE1,
1725         .rbase = 176,
1726 };
1727 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_0_15_to_R5FSS1_CORE1_intr_396_411 = {
1728         .lbase = 0,
1729         .len = 16,
1730         .rid = TISCI_DEV_R5FSS1_CORE1,
1731         .rbase = 396,
1732 };
1733 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_8_63_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_392_447 = {
1734         .lbase = 8,
1735         .len = 56,
1736         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
1737         .rbase = 392,
1738 };
1739 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_8_63_to_COMPUTE_CLUSTER0_GIC500SS_spi_360_415 = {
1740         .lbase = 8,
1741         .len = 56,
1742         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
1743         .rbase = 360,
1744 };
1745 const struct Sciclient_rmIrqIf GPIOMUX_INTRTR0_outp_16_31_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_116_131 = {
1746         .lbase = 16,
1747         .len = 16,
1748         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
1749         .rbase = 116,
1750 };
1751 const struct Sciclient_rmIrqIf * const tisci_if_GPIOMUX_INTRTR0[] = {
1752         &GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event0_664_671,
1753         &GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event1_672_679,
1754         &GPIOMUX_INTRTR0_outp_0_7_to_ESM0_esm_pls_event2_680_687,
1755         &GPIOMUX_INTRTR0_outp_0_31_to_MAIN2MCU_PLS_INTRTR0_in_64_95,
1756         &GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE0_intr_176_191,
1757         &GPIOMUX_INTRTR0_outp_0_15_to_R5FSS0_CORE0_intr_396_411,
1758         &GPIOMUX_INTRTR0_outp_16_31_to_R5FSS0_CORE1_intr_176_191,
1759         &GPIOMUX_INTRTR0_outp_0_15_to_R5FSS0_CORE1_intr_396_411,
1760         &GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE0_intr_176_191,
1761         &GPIOMUX_INTRTR0_outp_0_15_to_R5FSS1_CORE0_intr_396_411,
1762         &GPIOMUX_INTRTR0_outp_16_31_to_R5FSS1_CORE1_intr_176_191,
1763         &GPIOMUX_INTRTR0_outp_0_15_to_R5FSS1_CORE1_intr_396_411,
1764         &GPIOMUX_INTRTR0_outp_8_63_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_392_447,
1765         &GPIOMUX_INTRTR0_outp_8_63_to_COMPUTE_CLUSTER0_GIC500SS_spi_360_415,
1766         &GPIOMUX_INTRTR0_outp_16_31_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_116_131,
1767 };
1768 static const struct Sciclient_rmIrqNode tisci_irq_GPIOMUX_INTRTR0 = {
1769         .id = TISCI_DEV_GPIOMUX_INTRTR0,
1770         .n_if = 15,
1771         .p_if = &tisci_if_GPIOMUX_INTRTR0[0],
1772 };
1774 /* Start of CMPEVENT_INTRTR0 interface definition */
1775 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_0_3_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_544_547 = {
1776         .lbase = 0,
1777         .len = 4,
1778         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
1779         .rbase = 544,
1780 };
1781 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_0_3_to_COMPUTE_CLUSTER0_GIC500SS_spi_512_515 = {
1782         .lbase = 0,
1783         .len = 4,
1784         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
1785         .rbase = 512,
1786 };
1787 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_4_7_to_MAIN2MCU_PLS_INTRTR0_in_96_99 = {
1788         .lbase = 4,
1789         .len = 4,
1790         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1791         .rbase = 96,
1792 };
1793 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_8_11_to_R5FSS0_CORE0_intr_326_329 = {
1794         .lbase = 8,
1795         .len = 4,
1796         .rid = TISCI_DEV_R5FSS0_CORE0,
1797         .rbase = 326,
1798 };
1799 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_8_11_to_R5FSS0_CORE1_intr_326_329 = {
1800         .lbase = 8,
1801         .len = 4,
1802         .rid = TISCI_DEV_R5FSS0_CORE1,
1803         .rbase = 326,
1804 };
1805 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_8_11_to_R5FSS1_CORE0_intr_326_329 = {
1806         .lbase = 8,
1807         .len = 4,
1808         .rid = TISCI_DEV_R5FSS1_CORE0,
1809         .rbase = 326,
1810 };
1811 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_8_11_to_R5FSS1_CORE1_intr_326_329 = {
1812         .lbase = 8,
1813         .len = 4,
1814         .rid = TISCI_DEV_R5FSS1_CORE1,
1815         .rbase = 326,
1816 };
1817 const struct Sciclient_rmIrqIf CMPEVENT_INTRTR0_outp_12_15_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_108_111 = {
1818         .lbase = 12,
1819         .len = 4,
1820         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
1821         .rbase = 108,
1822 };
1823 const struct Sciclient_rmIrqIf * const tisci_if_CMPEVENT_INTRTR0[] = {
1824         &CMPEVENT_INTRTR0_outp_0_3_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_544_547,
1825         &CMPEVENT_INTRTR0_outp_0_3_to_COMPUTE_CLUSTER0_GIC500SS_spi_512_515,
1826         &CMPEVENT_INTRTR0_outp_4_7_to_MAIN2MCU_PLS_INTRTR0_in_96_99,
1827         &CMPEVENT_INTRTR0_outp_8_11_to_R5FSS0_CORE0_intr_326_329,
1828         &CMPEVENT_INTRTR0_outp_8_11_to_R5FSS0_CORE1_intr_326_329,
1829         &CMPEVENT_INTRTR0_outp_8_11_to_R5FSS1_CORE0_intr_326_329,
1830         &CMPEVENT_INTRTR0_outp_8_11_to_R5FSS1_CORE1_intr_326_329,
1831         &CMPEVENT_INTRTR0_outp_12_15_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_108_111,
1832 };
1833 static const struct Sciclient_rmIrqNode tisci_irq_CMPEVENT_INTRTR0 = {
1834         .id = TISCI_DEV_CMPEVENT_INTRTR0,
1835         .n_if = 8,
1836         .p_if = &tisci_if_CMPEVENT_INTRTR0[0],
1837 };
1839 /* Start of DSS_DSI0 interface definition */
1840 const struct Sciclient_rmIrqIf DSS_DSI0_dsi_0_func_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_224_224 = {
1841         .lbase = 0,
1842         .len = 1,
1843         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1844         .rbase = 224,
1845 };
1846 const struct Sciclient_rmIrqIf * const tisci_if_DSS_DSI0[] = {
1847         &DSS_DSI0_dsi_0_func_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_224_224,
1848 };
1849 static const struct Sciclient_rmIrqNode tisci_irq_DSS_DSI0 = {
1850         .id = TISCI_DEV_DSS_DSI0,
1851         .n_if = 1,
1852         .p_if = &tisci_if_DSS_DSI0[0],
1853 };
1855 /* Start of DSS_DSI1 interface definition */
1856 const struct Sciclient_rmIrqIf DSS_DSI1_dsi_0_func_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_225_225 = {
1857         .lbase = 0,
1858         .len = 1,
1859         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1860         .rbase = 225,
1861 };
1862 const struct Sciclient_rmIrqIf * const tisci_if_DSS_DSI1[] = {
1863         &DSS_DSI1_dsi_0_func_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_225_225,
1864 };
1865 static const struct Sciclient_rmIrqNode tisci_irq_DSS_DSI1 = {
1866         .id = TISCI_DEV_DSS_DSI1,
1867         .n_if = 1,
1868         .p_if = &tisci_if_DSS_DSI1[0],
1869 };
1871 /* Start of DSS_EDP0 interface definition */
1872 const struct Sciclient_rmIrqIf DSS_EDP0_intr_0_3_to_MAIN2MCU_LVL_INTRTR0_in_238_241 = {
1873         .lbase = 0,
1874         .len = 4,
1875         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1876         .rbase = 238,
1877 };
1878 const struct Sciclient_rmIrqIf * const tisci_if_DSS_EDP0[] = {
1879         &DSS_EDP0_intr_0_3_to_MAIN2MCU_LVL_INTRTR0_in_238_241,
1880 };
1881 static const struct Sciclient_rmIrqNode tisci_irq_DSS_EDP0 = {
1882         .id = TISCI_DEV_DSS_EDP0,
1883         .n_if = 1,
1884         .p_if = &tisci_if_DSS_EDP0[0],
1885 };
1887 /* Start of DSS0 interface definition */
1888 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_func_irq_proc0_0_0_to_MAIN2MCU_LVL_INTRTR0_in_226_226 = {
1889         .lbase = 0,
1890         .len = 1,
1891         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1892         .rbase = 226,
1893 };
1894 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_func_irq_proc1_1_1_to_MAIN2MCU_LVL_INTRTR0_in_227_227 = {
1895         .lbase = 1,
1896         .len = 1,
1897         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1898         .rbase = 227,
1899 };
1900 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_secure_irq_proc0_4_4_to_MAIN2MCU_LVL_INTRTR0_in_228_228 = {
1901         .lbase = 4,
1902         .len = 1,
1903         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1904         .rbase = 228,
1905 };
1906 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_secure_irq_proc1_5_5_to_MAIN2MCU_LVL_INTRTR0_in_229_229 = {
1907         .lbase = 5,
1908         .len = 1,
1909         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1910         .rbase = 229,
1911 };
1912 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_safety_error_irq_proc0_2_2_to_MAIN2MCU_LVL_INTRTR0_in_230_230 = {
1913         .lbase = 2,
1914         .len = 1,
1915         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1916         .rbase = 230,
1917 };
1918 const struct Sciclient_rmIrqIf DSS0_dss_inst0_dispc_safety_error_irq_proc1_3_3_to_MAIN2MCU_LVL_INTRTR0_in_231_231 = {
1919         .lbase = 3,
1920         .len = 1,
1921         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
1922         .rbase = 231,
1923 };
1924 const struct Sciclient_rmIrqIf * const tisci_if_DSS0[] = {
1925         &DSS0_dss_inst0_dispc_func_irq_proc0_0_0_to_MAIN2MCU_LVL_INTRTR0_in_226_226,
1926         &DSS0_dss_inst0_dispc_func_irq_proc1_1_1_to_MAIN2MCU_LVL_INTRTR0_in_227_227,
1927         &DSS0_dss_inst0_dispc_secure_irq_proc0_4_4_to_MAIN2MCU_LVL_INTRTR0_in_228_228,
1928         &DSS0_dss_inst0_dispc_secure_irq_proc1_5_5_to_MAIN2MCU_LVL_INTRTR0_in_229_229,
1929         &DSS0_dss_inst0_dispc_safety_error_irq_proc0_2_2_to_MAIN2MCU_LVL_INTRTR0_in_230_230,
1930         &DSS0_dss_inst0_dispc_safety_error_irq_proc1_3_3_to_MAIN2MCU_LVL_INTRTR0_in_231_231,
1931 };
1932 static const struct Sciclient_rmIrqNode tisci_irq_DSS0 = {
1933         .id = TISCI_DEV_DSS0,
1934         .n_if = 6,
1935         .p_if = &tisci_if_DSS0[0],
1936 };
1938 /* Start of EPWM0 interface definition */
1939 const struct Sciclient_rmIrqIf EPWM0_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_2_2 = {
1940         .lbase = 0,
1941         .len = 1,
1942         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1943         .rbase = 2,
1944 };
1945 const struct Sciclient_rmIrqIf EPWM0_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_8_8 = {
1946         .lbase = 1,
1947         .len = 1,
1948         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1949         .rbase = 8,
1950 };
1951 const struct Sciclient_rmIrqIf * const tisci_if_EPWM0[] = {
1952         &EPWM0_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_2_2,
1953         &EPWM0_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_8_8,
1954 };
1955 static const struct Sciclient_rmIrqNode tisci_irq_EPWM0 = {
1956         .id = TISCI_DEV_EPWM0,
1957         .n_if = 2,
1958         .p_if = &tisci_if_EPWM0[0],
1959 };
1961 /* Start of EPWM1 interface definition */
1962 const struct Sciclient_rmIrqIf EPWM1_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_3_3 = {
1963         .lbase = 0,
1964         .len = 1,
1965         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1966         .rbase = 3,
1967 };
1968 const struct Sciclient_rmIrqIf EPWM1_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_9_9 = {
1969         .lbase = 1,
1970         .len = 1,
1971         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1972         .rbase = 9,
1973 };
1974 const struct Sciclient_rmIrqIf * const tisci_if_EPWM1[] = {
1975         &EPWM1_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_3_3,
1976         &EPWM1_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_9_9,
1977 };
1978 static const struct Sciclient_rmIrqNode tisci_irq_EPWM1 = {
1979         .id = TISCI_DEV_EPWM1,
1980         .n_if = 2,
1981         .p_if = &tisci_if_EPWM1[0],
1982 };
1984 /* Start of EPWM2 interface definition */
1985 const struct Sciclient_rmIrqIf EPWM2_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_4_4 = {
1986         .lbase = 0,
1987         .len = 1,
1988         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1989         .rbase = 4,
1990 };
1991 const struct Sciclient_rmIrqIf EPWM2_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_10_10 = {
1992         .lbase = 1,
1993         .len = 1,
1994         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
1995         .rbase = 10,
1996 };
1997 const struct Sciclient_rmIrqIf * const tisci_if_EPWM2[] = {
1998         &EPWM2_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_4_4,
1999         &EPWM2_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_10_10,
2000 };
2001 static const struct Sciclient_rmIrqNode tisci_irq_EPWM2 = {
2002         .id = TISCI_DEV_EPWM2,
2003         .n_if = 2,
2004         .p_if = &tisci_if_EPWM2[0],
2005 };
2007 /* Start of EPWM3 interface definition */
2008 const struct Sciclient_rmIrqIf EPWM3_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_5_5 = {
2009         .lbase = 0,
2010         .len = 1,
2011         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2012         .rbase = 5,
2013 };
2014 const struct Sciclient_rmIrqIf EPWM3_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_11_11 = {
2015         .lbase = 1,
2016         .len = 1,
2017         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2018         .rbase = 11,
2019 };
2020 const struct Sciclient_rmIrqIf * const tisci_if_EPWM3[] = {
2021         &EPWM3_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_5_5,
2022         &EPWM3_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_11_11,
2023 };
2024 static const struct Sciclient_rmIrqNode tisci_irq_EPWM3 = {
2025         .id = TISCI_DEV_EPWM3,
2026         .n_if = 2,
2027         .p_if = &tisci_if_EPWM3[0],
2028 };
2030 /* Start of EPWM4 interface definition */
2031 const struct Sciclient_rmIrqIf EPWM4_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_6_6 = {
2032         .lbase = 0,
2033         .len = 1,
2034         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2035         .rbase = 6,
2036 };
2037 const struct Sciclient_rmIrqIf EPWM4_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_12_12 = {
2038         .lbase = 1,
2039         .len = 1,
2040         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2041         .rbase = 12,
2042 };
2043 const struct Sciclient_rmIrqIf * const tisci_if_EPWM4[] = {
2044         &EPWM4_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_6_6,
2045         &EPWM4_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_12_12,
2046 };
2047 static const struct Sciclient_rmIrqNode tisci_irq_EPWM4 = {
2048         .id = TISCI_DEV_EPWM4,
2049         .n_if = 2,
2050         .p_if = &tisci_if_EPWM4[0],
2051 };
2053 /* Start of EPWM5 interface definition */
2054 const struct Sciclient_rmIrqIf EPWM5_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_7_7 = {
2055         .lbase = 0,
2056         .len = 1,
2057         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2058         .rbase = 7,
2059 };
2060 const struct Sciclient_rmIrqIf EPWM5_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_13_13 = {
2061         .lbase = 1,
2062         .len = 1,
2063         .rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
2064         .rbase = 13,
2065 };
2066 const struct Sciclient_rmIrqIf * const tisci_if_EPWM5[] = {
2067         &EPWM5_epwm_etint_0_0_to_MAIN2MCU_PLS_INTRTR0_in_7_7,
2068         &EPWM5_epwm_tripzint_1_1_to_MAIN2MCU_PLS_INTRTR0_in_13_13,
2069 };
2070 static const struct Sciclient_rmIrqNode tisci_irq_EPWM5 = {
2071         .id = TISCI_DEV_EPWM5,
2072         .n_if = 2,
2073         .p_if = &tisci_if_EPWM5[0],
2074 };
2076 /* Start of K3_VPU_WAVE521CL0 interface definition */
2077 const struct Sciclient_rmIrqIf K3_VPU_WAVE521CL0_vpu_wave521cl_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_263_263 = {
2078         .lbase = 0,
2079         .len = 1,
2080         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2081         .rbase = 263,
2082 };
2083 const struct Sciclient_rmIrqIf * const tisci_if_K3_VPU_WAVE521CL0[] = {
2084         &K3_VPU_WAVE521CL0_vpu_wave521cl_intr_0_0_to_MAIN2MCU_LVL_INTRTR0_in_263_263,
2085 };
2086 static const struct Sciclient_rmIrqNode tisci_irq_K3_VPU_WAVE521CL0 = {
2087         .id = TISCI_DEV_K3_VPU_WAVE521CL0,
2088         .n_if = 1,
2089         .p_if = &tisci_if_K3_VPU_WAVE521CL0[0],
2090 };
2092 /* Start of MCAN0 interface definition */
2093 const struct Sciclient_rmIrqIf MCAN0_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_16_17 = {
2094         .lbase = 1,
2095         .len = 2,
2096         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2097         .rbase = 16,
2098 };
2099 const struct Sciclient_rmIrqIf MCAN0_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_18_18 = {
2100         .lbase = 0,
2101         .len = 1,
2102         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2103         .rbase = 18,
2104 };
2105 const struct Sciclient_rmIrqIf * const tisci_if_MCAN0[] = {
2106         &MCAN0_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_16_17,
2107         &MCAN0_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_18_18,
2108 };
2109 static const struct Sciclient_rmIrqNode tisci_irq_MCAN0 = {
2110         .id = TISCI_DEV_MCAN0,
2111         .n_if = 2,
2112         .p_if = &tisci_if_MCAN0[0],
2113 };
2115 /* Start of MCAN1 interface definition */
2116 const struct Sciclient_rmIrqIf MCAN1_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_19_20 = {
2117         .lbase = 1,
2118         .len = 2,
2119         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2120         .rbase = 19,
2121 };
2122 const struct Sciclient_rmIrqIf MCAN1_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_21_21 = {
2123         .lbase = 0,
2124         .len = 1,
2125         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2126         .rbase = 21,
2127 };
2128 const struct Sciclient_rmIrqIf * const tisci_if_MCAN1[] = {
2129         &MCAN1_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_19_20,
2130         &MCAN1_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_21_21,
2131 };
2132 static const struct Sciclient_rmIrqNode tisci_irq_MCAN1 = {
2133         .id = TISCI_DEV_MCAN1,
2134         .n_if = 2,
2135         .p_if = &tisci_if_MCAN1[0],
2136 };
2138 /* Start of MCAN2 interface definition */
2139 const struct Sciclient_rmIrqIf MCAN2_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_22_23 = {
2140         .lbase = 1,
2141         .len = 2,
2142         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2143         .rbase = 22,
2144 };
2145 const struct Sciclient_rmIrqIf MCAN2_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_24_24 = {
2146         .lbase = 0,
2147         .len = 1,
2148         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2149         .rbase = 24,
2150 };
2151 const struct Sciclient_rmIrqIf * const tisci_if_MCAN2[] = {
2152         &MCAN2_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_22_23,
2153         &MCAN2_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_24_24,
2154 };
2155 static const struct Sciclient_rmIrqNode tisci_irq_MCAN2 = {
2156         .id = TISCI_DEV_MCAN2,
2157         .n_if = 2,
2158         .p_if = &tisci_if_MCAN2[0],
2159 };
2161 /* Start of MCAN3 interface definition */
2162 const struct Sciclient_rmIrqIf MCAN3_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_25_26 = {
2163         .lbase = 1,
2164         .len = 2,
2165         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2166         .rbase = 25,
2167 };
2168 const struct Sciclient_rmIrqIf MCAN3_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_27_27 = {
2169         .lbase = 0,
2170         .len = 1,
2171         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2172         .rbase = 27,
2173 };
2174 const struct Sciclient_rmIrqIf * const tisci_if_MCAN3[] = {
2175         &MCAN3_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_25_26,
2176         &MCAN3_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_27_27,
2177 };
2178 static const struct Sciclient_rmIrqNode tisci_irq_MCAN3 = {
2179         .id = TISCI_DEV_MCAN3,
2180         .n_if = 2,
2181         .p_if = &tisci_if_MCAN3[0],
2182 };
2184 /* Start of MCAN4 interface definition */
2185 const struct Sciclient_rmIrqIf MCAN4_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_278_279 = {
2186         .lbase = 1,
2187         .len = 2,
2188         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2189         .rbase = 278,
2190 };
2191 const struct Sciclient_rmIrqIf MCAN4_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_280_280 = {
2192         .lbase = 0,
2193         .len = 1,
2194         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2195         .rbase = 280,
2196 };
2197 const struct Sciclient_rmIrqIf * const tisci_if_MCAN4[] = {
2198         &MCAN4_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_278_279,
2199         &MCAN4_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_280_280,
2200 };
2201 static const struct Sciclient_rmIrqNode tisci_irq_MCAN4 = {
2202         .id = TISCI_DEV_MCAN4,
2203         .n_if = 2,
2204         .p_if = &tisci_if_MCAN4[0],
2205 };
2207 /* Start of MCAN5 interface definition */
2208 const struct Sciclient_rmIrqIf MCAN5_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_281_282 = {
2209         .lbase = 1,
2210         .len = 2,
2211         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2212         .rbase = 281,
2213 };
2214 const struct Sciclient_rmIrqIf MCAN5_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_283_283 = {
2215         .lbase = 0,
2216         .len = 1,
2217         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2218         .rbase = 283,
2219 };
2220 const struct Sciclient_rmIrqIf * const tisci_if_MCAN5[] = {
2221         &MCAN5_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_281_282,
2222         &MCAN5_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_283_283,
2223 };
2224 static const struct Sciclient_rmIrqNode tisci_irq_MCAN5 = {
2225         .id = TISCI_DEV_MCAN5,
2226         .n_if = 2,
2227         .p_if = &tisci_if_MCAN5[0],
2228 };
2230 /* Start of MCAN6 interface definition */
2231 const struct Sciclient_rmIrqIf MCAN6_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_284_285 = {
2232         .lbase = 1,
2233         .len = 2,
2234         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2235         .rbase = 284,
2236 };
2237 const struct Sciclient_rmIrqIf MCAN6_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_286_286 = {
2238         .lbase = 0,
2239         .len = 1,
2240         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2241         .rbase = 286,
2242 };
2243 const struct Sciclient_rmIrqIf * const tisci_if_MCAN6[] = {
2244         &MCAN6_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_284_285,
2245         &MCAN6_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_286_286,
2246 };
2247 static const struct Sciclient_rmIrqNode tisci_irq_MCAN6 = {
2248         .id = TISCI_DEV_MCAN6,
2249         .n_if = 2,
2250         .p_if = &tisci_if_MCAN6[0],
2251 };
2253 /* Start of MCAN7 interface definition */
2254 const struct Sciclient_rmIrqIf MCAN7_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_287_288 = {
2255         .lbase = 1,
2256         .len = 2,
2257         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2258         .rbase = 287,
2259 };
2260 const struct Sciclient_rmIrqIf MCAN7_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_289_289 = {
2261         .lbase = 0,
2262         .len = 1,
2263         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2264         .rbase = 289,
2265 };
2266 const struct Sciclient_rmIrqIf * const tisci_if_MCAN7[] = {
2267         &MCAN7_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_287_288,
2268         &MCAN7_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_289_289,
2269 };
2270 static const struct Sciclient_rmIrqNode tisci_irq_MCAN7 = {
2271         .id = TISCI_DEV_MCAN7,
2272         .n_if = 2,
2273         .p_if = &tisci_if_MCAN7[0],
2274 };
2276 /* Start of MCAN8 interface definition */
2277 const struct Sciclient_rmIrqIf MCAN8_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_290_291 = {
2278         .lbase = 1,
2279         .len = 2,
2280         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2281         .rbase = 290,
2282 };
2283 const struct Sciclient_rmIrqIf MCAN8_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_292_292 = {
2284         .lbase = 0,
2285         .len = 1,
2286         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2287         .rbase = 292,
2288 };
2289 const struct Sciclient_rmIrqIf * const tisci_if_MCAN8[] = {
2290         &MCAN8_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_290_291,
2291         &MCAN8_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_292_292,
2292 };
2293 static const struct Sciclient_rmIrqNode tisci_irq_MCAN8 = {
2294         .id = TISCI_DEV_MCAN8,
2295         .n_if = 2,
2296         .p_if = &tisci_if_MCAN8[0],
2297 };
2299 /* Start of MCAN9 interface definition */
2300 const struct Sciclient_rmIrqIf MCAN9_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_293_294 = {
2301         .lbase = 1,
2302         .len = 2,
2303         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2304         .rbase = 293,
2305 };
2306 const struct Sciclient_rmIrqIf MCAN9_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_295_295 = {
2307         .lbase = 0,
2308         .len = 1,
2309         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2310         .rbase = 295,
2311 };
2312 const struct Sciclient_rmIrqIf * const tisci_if_MCAN9[] = {
2313         &MCAN9_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_293_294,
2314         &MCAN9_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_295_295,
2315 };
2316 static const struct Sciclient_rmIrqNode tisci_irq_MCAN9 = {
2317         .id = TISCI_DEV_MCAN9,
2318         .n_if = 2,
2319         .p_if = &tisci_if_MCAN9[0],
2320 };
2322 /* Start of MCAN10 interface definition */
2323 const struct Sciclient_rmIrqIf MCAN10_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_296_297 = {
2324         .lbase = 1,
2325         .len = 2,
2326         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2327         .rbase = 296,
2328 };
2329 const struct Sciclient_rmIrqIf MCAN10_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_298_298 = {
2330         .lbase = 0,
2331         .len = 1,
2332         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2333         .rbase = 298,
2334 };
2335 const struct Sciclient_rmIrqIf * const tisci_if_MCAN10[] = {
2336         &MCAN10_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_296_297,
2337         &MCAN10_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_298_298,
2338 };
2339 static const struct Sciclient_rmIrqNode tisci_irq_MCAN10 = {
2340         .id = TISCI_DEV_MCAN10,
2341         .n_if = 2,
2342         .p_if = &tisci_if_MCAN10[0],
2343 };
2345 /* Start of MCAN11 interface definition */
2346 const struct Sciclient_rmIrqIf MCAN11_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_299_300 = {
2347         .lbase = 1,
2348         .len = 2,
2349         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2350         .rbase = 299,
2351 };
2352 const struct Sciclient_rmIrqIf MCAN11_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_301_301 = {
2353         .lbase = 0,
2354         .len = 1,
2355         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2356         .rbase = 301,
2357 };
2358 const struct Sciclient_rmIrqIf * const tisci_if_MCAN11[] = {
2359         &MCAN11_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_299_300,
2360         &MCAN11_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_301_301,
2361 };
2362 static const struct Sciclient_rmIrqNode tisci_irq_MCAN11 = {
2363         .id = TISCI_DEV_MCAN11,
2364         .n_if = 2,
2365         .p_if = &tisci_if_MCAN11[0],
2366 };
2368 /* Start of MCAN12 interface definition */
2369 const struct Sciclient_rmIrqIf MCAN12_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_302_303 = {
2370         .lbase = 1,
2371         .len = 2,
2372         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2373         .rbase = 302,
2374 };
2375 const struct Sciclient_rmIrqIf MCAN12_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_304_304 = {
2376         .lbase = 0,
2377         .len = 1,
2378         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2379         .rbase = 304,
2380 };
2381 const struct Sciclient_rmIrqIf * const tisci_if_MCAN12[] = {
2382         &MCAN12_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_302_303,
2383         &MCAN12_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_304_304,
2384 };
2385 static const struct Sciclient_rmIrqNode tisci_irq_MCAN12 = {
2386         .id = TISCI_DEV_MCAN12,
2387         .n_if = 2,
2388         .p_if = &tisci_if_MCAN12[0],
2389 };
2391 /* Start of MCAN13 interface definition */
2392 const struct Sciclient_rmIrqIf MCAN13_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_305_306 = {
2393         .lbase = 1,
2394         .len = 2,
2395         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2396         .rbase = 305,
2397 };
2398 const struct Sciclient_rmIrqIf MCAN13_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_307_307 = {
2399         .lbase = 0,
2400         .len = 1,
2401         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2402         .rbase = 307,
2403 };
2404 const struct Sciclient_rmIrqIf * const tisci_if_MCAN13[] = {
2405         &MCAN13_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_305_306,
2406         &MCAN13_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_307_307,
2407 };
2408 static const struct Sciclient_rmIrqNode tisci_irq_MCAN13 = {
2409         .id = TISCI_DEV_MCAN13,
2410         .n_if = 2,
2411         .p_if = &tisci_if_MCAN13[0],
2412 };
2414 /* Start of MCAN14 interface definition */
2415 const struct Sciclient_rmIrqIf MCAN14_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_160_161 = {
2416         .lbase = 1,
2417         .len = 2,
2418         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2419         .rbase = 160,
2420 };
2421 const struct Sciclient_rmIrqIf MCAN14_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_162_162 = {
2422         .lbase = 0,
2423         .len = 1,
2424         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2425         .rbase = 162,
2426 };
2427 const struct Sciclient_rmIrqIf * const tisci_if_MCAN14[] = {
2428         &MCAN14_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_160_161,
2429         &MCAN14_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_162_162,
2430 };
2431 static const struct Sciclient_rmIrqNode tisci_irq_MCAN14 = {
2432         .id = TISCI_DEV_MCAN14,
2433         .n_if = 2,
2434         .p_if = &tisci_if_MCAN14[0],
2435 };
2437 /* Start of MCAN15 interface definition */
2438 const struct Sciclient_rmIrqIf MCAN15_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_163_164 = {
2439         .lbase = 1,
2440         .len = 2,
2441         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2442         .rbase = 163,
2443 };
2444 const struct Sciclient_rmIrqIf MCAN15_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_165_165 = {
2445         .lbase = 0,
2446         .len = 1,
2447         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2448         .rbase = 165,
2449 };
2450 const struct Sciclient_rmIrqIf * const tisci_if_MCAN15[] = {
2451         &MCAN15_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_163_164,
2452         &MCAN15_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_165_165,
2453 };
2454 static const struct Sciclient_rmIrqNode tisci_irq_MCAN15 = {
2455         .id = TISCI_DEV_MCAN15,
2456         .n_if = 2,
2457         .p_if = &tisci_if_MCAN15[0],
2458 };
2460 /* Start of MCAN16 interface definition */
2461 const struct Sciclient_rmIrqIf MCAN16_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_170_171 = {
2462         .lbase = 1,
2463         .len = 2,
2464         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2465         .rbase = 170,
2466 };
2467 const struct Sciclient_rmIrqIf MCAN16_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_172_172 = {
2468         .lbase = 0,
2469         .len = 1,
2470         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2471         .rbase = 172,
2472 };
2473 const struct Sciclient_rmIrqIf * const tisci_if_MCAN16[] = {
2474         &MCAN16_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_170_171,
2475         &MCAN16_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_172_172,
2476 };
2477 static const struct Sciclient_rmIrqNode tisci_irq_MCAN16 = {
2478         .id = TISCI_DEV_MCAN16,
2479         .n_if = 2,
2480         .p_if = &tisci_if_MCAN16[0],
2481 };
2483 /* Start of MCAN17 interface definition */
2484 const struct Sciclient_rmIrqIf MCAN17_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_173_174 = {
2485         .lbase = 1,
2486         .len = 2,
2487         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2488         .rbase = 173,
2489 };
2490 const struct Sciclient_rmIrqIf MCAN17_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_175_175 = {
2491         .lbase = 0,
2492         .len = 1,
2493         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2494         .rbase = 175,
2495 };
2496 const struct Sciclient_rmIrqIf * const tisci_if_MCAN17[] = {
2497         &MCAN17_mcanss_mcan_lvl_int_1_2_to_MAIN2MCU_LVL_INTRTR0_in_173_174,
2498         &MCAN17_mcanss_ext_ts_rollover_lvl_int_0_0_to_MAIN2MCU_LVL_INTRTR0_in_175_175,
2499 };
2500 static const struct Sciclient_rmIrqNode tisci_irq_MCAN17 = {
2501         .id = TISCI_DEV_MCAN17,
2502         .n_if = 2,
2503         .p_if = &tisci_if_MCAN17[0],
2504 };
2506 /* Start of MCASP0 interface definition */
2507 const struct Sciclient_rmIrqIf MCASP0_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_176_176 = {
2508         .lbase = 1,
2509         .len = 1,
2510         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2511         .rbase = 176,
2512 };
2513 const struct Sciclient_rmIrqIf MCASP0_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_177_177 = {
2514         .lbase = 0,
2515         .len = 1,
2516         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2517         .rbase = 177,
2518 };
2519 const struct Sciclient_rmIrqIf * const tisci_if_MCASP0[] = {
2520         &MCASP0_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_176_176,
2521         &MCASP0_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_177_177,
2522 };
2523 static const struct Sciclient_rmIrqNode tisci_irq_MCASP0 = {
2524         .id = TISCI_DEV_MCASP0,
2525         .n_if = 2,
2526         .p_if = &tisci_if_MCASP0[0],
2527 };
2529 /* Start of MCASP1 interface definition */
2530 const struct Sciclient_rmIrqIf MCASP1_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_178_178 = {
2531         .lbase = 1,
2532         .len = 1,
2533         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2534         .rbase = 178,
2535 };
2536 const struct Sciclient_rmIrqIf MCASP1_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_179_179 = {
2537         .lbase = 0,
2538         .len = 1,
2539         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2540         .rbase = 179,
2541 };
2542 const struct Sciclient_rmIrqIf * const tisci_if_MCASP1[] = {
2543         &MCASP1_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_178_178,
2544         &MCASP1_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_179_179,
2545 };
2546 static const struct Sciclient_rmIrqNode tisci_irq_MCASP1 = {
2547         .id = TISCI_DEV_MCASP1,
2548         .n_if = 2,
2549         .p_if = &tisci_if_MCASP1[0],
2550 };
2552 /* Start of MCASP2 interface definition */
2553 const struct Sciclient_rmIrqIf MCASP2_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_180_180 = {
2554         .lbase = 1,
2555         .len = 1,
2556         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2557         .rbase = 180,
2558 };
2559 const struct Sciclient_rmIrqIf MCASP2_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_181_181 = {
2560         .lbase = 0,
2561         .len = 1,
2562         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2563         .rbase = 181,
2564 };
2565 const struct Sciclient_rmIrqIf * const tisci_if_MCASP2[] = {
2566         &MCASP2_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_180_180,
2567         &MCASP2_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_181_181,
2568 };
2569 static const struct Sciclient_rmIrqNode tisci_irq_MCASP2 = {
2570         .id = TISCI_DEV_MCASP2,
2571         .n_if = 2,
2572         .p_if = &tisci_if_MCASP2[0],
2573 };
2575 /* Start of MCASP3 interface definition */
2576 const struct Sciclient_rmIrqIf MCASP3_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_182_182 = {
2577         .lbase = 1,
2578         .len = 1,
2579         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2580         .rbase = 182,
2581 };
2582 const struct Sciclient_rmIrqIf MCASP3_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_183_183 = {
2583         .lbase = 0,
2584         .len = 1,
2585         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2586         .rbase = 183,
2587 };
2588 const struct Sciclient_rmIrqIf * const tisci_if_MCASP3[] = {
2589         &MCASP3_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_182_182,
2590         &MCASP3_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_183_183,
2591 };
2592 static const struct Sciclient_rmIrqNode tisci_irq_MCASP3 = {
2593         .id = TISCI_DEV_MCASP3,
2594         .n_if = 2,
2595         .p_if = &tisci_if_MCASP3[0],
2596 };
2598 /* Start of MCASP4 interface definition */
2599 const struct Sciclient_rmIrqIf MCASP4_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_184_184 = {
2600         .lbase = 1,
2601         .len = 1,
2602         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2603         .rbase = 184,
2604 };
2605 const struct Sciclient_rmIrqIf MCASP4_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_185_185 = {
2606         .lbase = 0,
2607         .len = 1,
2608         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2609         .rbase = 185,
2610 };
2611 const struct Sciclient_rmIrqIf * const tisci_if_MCASP4[] = {
2612         &MCASP4_xmit_intr_pend_1_1_to_MAIN2MCU_LVL_INTRTR0_in_184_184,
2613         &MCASP4_rec_intr_pend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_185_185,
2614 };
2615 static const struct Sciclient_rmIrqNode tisci_irq_MCASP4 = {
2616         .id = TISCI_DEV_MCASP4,
2617         .n_if = 2,
2618         .p_if = &tisci_if_MCASP4[0],
2619 };
2621 /* Start of I2C0 interface definition */
2622 const struct Sciclient_rmIrqIf I2C0_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_56_56 = {
2623         .lbase = 0,
2624         .len = 1,
2625         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2626         .rbase = 56,
2627 };
2628 const struct Sciclient_rmIrqIf * const tisci_if_I2C0[] = {
2629         &I2C0_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_56_56,
2630 };
2631 static const struct Sciclient_rmIrqNode tisci_irq_I2C0 = {
2632         .id = TISCI_DEV_I2C0,
2633         .n_if = 1,
2634         .p_if = &tisci_if_I2C0[0],
2635 };
2637 /* Start of I2C1 interface definition */
2638 const struct Sciclient_rmIrqIf I2C1_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_57_57 = {
2639         .lbase = 0,
2640         .len = 1,
2641         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2642         .rbase = 57,
2643 };
2644 const struct Sciclient_rmIrqIf * const tisci_if_I2C1[] = {
2645         &I2C1_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_57_57,
2646 };
2647 static const struct Sciclient_rmIrqNode tisci_irq_I2C1 = {
2648         .id = TISCI_DEV_I2C1,
2649         .n_if = 1,
2650         .p_if = &tisci_if_I2C1[0],
2651 };
2653 /* Start of I2C2 interface definition */
2654 const struct Sciclient_rmIrqIf I2C2_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_58_58 = {
2655         .lbase = 0,
2656         .len = 1,
2657         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2658         .rbase = 58,
2659 };
2660 const struct Sciclient_rmIrqIf * const tisci_if_I2C2[] = {
2661         &I2C2_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_58_58,
2662 };
2663 static const struct Sciclient_rmIrqNode tisci_irq_I2C2 = {
2664         .id = TISCI_DEV_I2C2,
2665         .n_if = 1,
2666         .p_if = &tisci_if_I2C2[0],
2667 };
2669 /* Start of I2C3 interface definition */
2670 const struct Sciclient_rmIrqIf I2C3_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_59_59 = {
2671         .lbase = 0,
2672         .len = 1,
2673         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2674         .rbase = 59,
2675 };
2676 const struct Sciclient_rmIrqIf * const tisci_if_I2C3[] = {
2677         &I2C3_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_59_59,
2678 };
2679 static const struct Sciclient_rmIrqNode tisci_irq_I2C3 = {
2680         .id = TISCI_DEV_I2C3,
2681         .n_if = 1,
2682         .p_if = &tisci_if_I2C3[0],
2683 };
2685 /* Start of I2C4 interface definition */
2686 const struct Sciclient_rmIrqIf I2C4_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_60_60 = {
2687         .lbase = 0,
2688         .len = 1,
2689         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2690         .rbase = 60,
2691 };
2692 const struct Sciclient_rmIrqIf * const tisci_if_I2C4[] = {
2693         &I2C4_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_60_60,
2694 };
2695 static const struct Sciclient_rmIrqNode tisci_irq_I2C4 = {
2696         .id = TISCI_DEV_I2C4,
2697         .n_if = 1,
2698         .p_if = &tisci_if_I2C4[0],
2699 };
2701 /* Start of I2C5 interface definition */
2702 const struct Sciclient_rmIrqIf I2C5_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_61_61 = {
2703         .lbase = 0,
2704         .len = 1,
2705         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2706         .rbase = 61,
2707 };
2708 const struct Sciclient_rmIrqIf * const tisci_if_I2C5[] = {
2709         &I2C5_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_61_61,
2710 };
2711 static const struct Sciclient_rmIrqNode tisci_irq_I2C5 = {
2712         .id = TISCI_DEV_I2C5,
2713         .n_if = 1,
2714         .p_if = &tisci_if_I2C5[0],
2715 };
2717 /* Start of I2C6 interface definition */
2718 const struct Sciclient_rmIrqIf I2C6_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_62_62 = {
2719         .lbase = 0,
2720         .len = 1,
2721         .rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
2722         .rbase = 62,
2723 };
2724 const struct Sciclient_rmIrqIf * const tisci_if_I2C6[] = {
2725         &I2C6_pointrpend_0_0_to_MAIN2MCU_LVL_INTRTR0_in_62_62,
2726 };
2727 static const struct Sciclient_rmIrqNode tisci_irq_I2C6 = {
2728         .id = TISCI_DEV_I2C6,
2729         .n_if = 1,
2730         .p_if = &tisci_if_I2C6[0],
2731 };
2733 /* Start of NAVSS0 interface definition */
2734 const struct Sciclient_rmIrqIf NAVSS0_cpts0_comp_0_0_to_CMPEVENT_INTRTR0_in_8_8 = {
2735         .lbase = 0,
2736         .len = 1,
2737         .rid = TISCI_DEV_CMPEVENT_INTRTR0,
2738         .rbase = 8,
2739 };
2740 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf0_1_1_to_TIMESYNC_INTRTR0_in_4_4 = {
2741         .lbase = 1,
2742         .len = 1,
2743         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2744         .rbase = 4,
2745 };
2746 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf1_2_2_to_TIMESYNC_INTRTR0_in_5_5 = {
2747         .lbase = 2,
2748         .len = 1,
2749         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2750         .rbase = 5,
2751 };
2752 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf2_3_3_to_TIMESYNC_INTRTR0_in_6_6 = {
2753         .lbase = 3,
2754         .len = 1,
2755         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2756         .rbase = 6,
2757 };
2758 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf3_4_4_to_TIMESYNC_INTRTR0_in_7_7 = {
2759         .lbase = 4,
2760         .len = 1,
2761         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2762         .rbase = 7,
2763 };
2764 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf4_5_5_to_TIMESYNC_INTRTR0_in_8_8 = {
2765         .lbase = 5,
2766         .len = 1,
2767         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2768         .rbase = 8,
2769 };
2770 const struct Sciclient_rmIrqIf NAVSS0_cpts0_genf5_6_6_to_TIMESYNC_INTRTR0_in_9_9 = {
2771         .lbase = 6,
2772         .len = 1,
2773         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2774         .rbase = 9,
2775 };
2776 const struct Sciclient_rmIrqIf NAVSS0_cpts0_sync_7_7_to_TIMESYNC_INTRTR0_in_36_36 = {
2777         .lbase = 7,
2778         .len = 1,
2779         .rid = TISCI_DEV_TIMESYNC_INTRTR0,
2780         .rbase = 36,
2781 };
2782 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0[] = {
2783         &NAVSS0_cpts0_comp_0_0_to_CMPEVENT_INTRTR0_in_8_8,
2784         &NAVSS0_cpts0_genf0_1_1_to_TIMESYNC_INTRTR0_in_4_4,
2785         &NAVSS0_cpts0_genf1_2_2_to_TIMESYNC_INTRTR0_in_5_5,
2786         &NAVSS0_cpts0_genf2_3_3_to_TIMESYNC_INTRTR0_in_6_6,
2787         &NAVSS0_cpts0_genf3_4_4_to_TIMESYNC_INTRTR0_in_7_7,
2788         &NAVSS0_cpts0_genf4_5_5_to_TIMESYNC_INTRTR0_in_8_8,
2789         &NAVSS0_cpts0_genf5_6_6_to_TIMESYNC_INTRTR0_in_9_9,
2790         &NAVSS0_cpts0_sync_7_7_to_TIMESYNC_INTRTR0_in_36_36,
2791 };
2792 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0 = {
2793         .id = TISCI_DEV_NAVSS0,
2794         .n_if = 8,
2795         .p_if = &tisci_if_NAVSS0[0],
2796 };
2798 /* Start of NAVSS0_CPTS_0 interface definition */
2799 const struct Sciclient_rmIrqIf NAVSS0_CPTS_0_event_pend_intr_0_0_to_NAVSS0_INTR_0_in_intr_391_391 = {
2800         .lbase = 0,
2801         .len = 1,
2802         .rid = TISCI_DEV_NAVSS0_INTR_0,
2803         .rbase = 391,
2804 };
2805 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_CPTS_0[] = {
2806         &NAVSS0_CPTS_0_event_pend_intr_0_0_to_NAVSS0_INTR_0_in_intr_391_391,
2807 };
2808 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_CPTS_0 = {
2809         .id = TISCI_DEV_NAVSS0_CPTS_0,
2810         .n_if = 1,
2811         .p_if = &tisci_if_NAVSS0_CPTS_0[0],
2812 };
2814 /* Start of NAVSS0_INTR_0 interface definition */
2815 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_0_63_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_64_127 = {
2816         .lbase = 0,
2817         .len = 64,
2818         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
2819         .rbase = 64,
2820 };
2821 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_64_127_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_448_511 = {
2822         .lbase = 64,
2823         .len = 64,
2824         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
2825         .rbase = 448,
2826 };
2827 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_128_191_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_672_735 = {
2828         .lbase = 128,
2829         .len = 64,
2830         .rid = TISCI_DEV_COMPUTE_CLUSTER0_CLEC,
2831         .rbase = 672,
2832 };
2833 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_0_63_to_COMPUTE_CLUSTER0_GIC500SS_spi_32_95 = {
2834         .lbase = 0,
2835         .len = 64,
2836         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
2837         .rbase = 32,
2838 };
2839 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_64_127_to_COMPUTE_CLUSTER0_GIC500SS_spi_416_479 = {
2840         .lbase = 64,
2841         .len = 64,
2842         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
2843         .rbase = 416,
2844 };
2845 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_128_191_to_COMPUTE_CLUSTER0_GIC500SS_spi_640_703 = {
2846         .lbase = 128,
2847         .len = 64,
2848         .rid = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS,
2849         .rbase = 640,
2850 };
2851 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_192_223_to_R5FSS0_CORE0_intr_224_255 = {
2852         .lbase = 192,
2853         .len = 32,
2854         .rid = TISCI_DEV_R5FSS0_CORE0,
2855         .rbase = 224,
2856 };
2857 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_224_255_to_R5FSS0_CORE1_intr_224_255 = {
2858         .lbase = 224,
2859         .len = 32,
2860         .rid = TISCI_DEV_R5FSS0_CORE1,
2861         .rbase = 224,
2862 };
2863 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_256_287_to_R5FSS1_CORE0_intr_224_255 = {
2864         .lbase = 256,
2865         .len = 32,
2866         .rid = TISCI_DEV_R5FSS1_CORE0,
2867         .rbase = 224,
2868 };
2869 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_288_319_to_R5FSS1_CORE1_intr_224_255 = {
2870         .lbase = 288,
2871         .len = 32,
2872         .rid = TISCI_DEV_R5FSS1_CORE1,
2873         .rbase = 224,
2874 };
2875 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_400_407_to_MCU_R5FSS0_CORE0_intr_376_383 = {
2876         .lbase = 400,
2877         .len = 8,
2878         .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
2879         .rbase = 376,
2880 };
2881 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_400_407_to_MCU_R5FSS0_CORE1_intr_376_383 = {
2882         .lbase = 400,
2883         .len = 8,
2884         .rid = TISCI_DEV_MCU_R5FSS0_CORE1,
2885         .rbase = 376,
2886 };
2887 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_408_439_to_VUSR_DUAL0_v0_vusr_in_int_0_31 = {
2888         .lbase = 408,
2889         .len = 32,
2890         .rid = TISCI_DEV_VUSR_DUAL0,
2891         .rbase = 0,
2892 };
2893 const struct Sciclient_rmIrqIf NAVSS0_INTR_0_outl_intr_408_439_to_VUSR_DUAL0_v1_vusr_in_int_32_63 = {
2894         .lbase = 408,
2895         .len = 32,
2896         .rid = TISCI_DEV_VUSR_DUAL0,
2897         .rbase = 32,
2898 };
2899 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_INTR_0[] = {
2900         &NAVSS0_INTR_0_outl_intr_0_63_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_64_127,
2901         &NAVSS0_INTR_0_outl_intr_64_127_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_448_511,
2902         &NAVSS0_INTR_0_outl_intr_128_191_to_COMPUTE_CLUSTER0_CLEC_soc_events_in_672_735,
2903         &NAVSS0_INTR_0_outl_intr_0_63_to_COMPUTE_CLUSTER0_GIC500SS_spi_32_95,
2904         &NAVSS0_INTR_0_outl_intr_64_127_to_COMPUTE_CLUSTER0_GIC500SS_spi_416_479,
2905         &NAVSS0_INTR_0_outl_intr_128_191_to_COMPUTE_CLUSTER0_GIC500SS_spi_640_703,
2906         &NAVSS0_INTR_0_outl_intr_192_223_to_R5FSS0_CORE0_intr_224_255,
2907         &NAVSS0_INTR_0_outl_intr_224_255_to_R5FSS0_CORE1_intr_224_255,
2908         &NAVSS0_INTR_0_outl_intr_256_287_to_R5FSS1_CORE0_intr_224_255,
2909         &NAVSS0_INTR_0_outl_intr_288_319_to_R5FSS1_CORE1_intr_224_255,
2910         &NAVSS0_INTR_0_outl_intr_400_407_to_MCU_R5FSS0_CORE0_intr_376_383,
2911         &NAVSS0_INTR_0_outl_intr_400_407_to_MCU_R5FSS0_CORE1_intr_376_383,
2912         &NAVSS0_INTR_0_outl_intr_408_439_to_VUSR_DUAL0_v0_vusr_in_int_0_31,
2913         &NAVSS0_INTR_0_outl_intr_408_439_to_VUSR_DUAL0_v1_vusr_in_int_32_63,
2914 };
2915 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_INTR_0 = {
2916         .id = TISCI_DEV_NAVSS0_INTR_0,
2917         .n_if = 14,
2918         .p_if = &tisci_if_NAVSS0_INTR_0[0],
2919 };
2921 /* Start of NAVSS0_MAILBOX1_0 interface definition */
2922 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_0_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_484_487 = {
2923         .lbase = 0,
2924         .len = 4,
2925         .rid = TISCI_DEV_NAVSS0_INTR_0,
2926         .rbase = 484,
2927 };
2928 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_0_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_4_7 = {
2929         .lbase = 0,
2930         .len = 4,
2931         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
2932         .rbase = 4,
2933 };
2934 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_0[] = {
2935         &NAVSS0_MAILBOX1_0_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_484_487,
2936         &NAVSS0_MAILBOX1_0_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_4_7,
2937 };
2938 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_0 = {
2939         .id = TISCI_DEV_NAVSS0_MAILBOX1_0,
2940         .n_if = 2,
2941         .p_if = &tisci_if_NAVSS0_MAILBOX1_0[0],
2942 };
2944 /* Start of NAVSS0_MAILBOX1_1 interface definition */
2945 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_1_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_480_483 = {
2946         .lbase = 0,
2947         .len = 4,
2948         .rid = TISCI_DEV_NAVSS0_INTR_0,
2949         .rbase = 480,
2950 };
2951 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_1_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_8_11 = {
2952         .lbase = 0,
2953         .len = 4,
2954         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
2955         .rbase = 8,
2956 };
2957 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_1[] = {
2958         &NAVSS0_MAILBOX1_1_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_480_483,
2959         &NAVSS0_MAILBOX1_1_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_8_11,
2960 };
2961 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_1 = {
2962         .id = TISCI_DEV_NAVSS0_MAILBOX1_1,
2963         .n_if = 2,
2964         .p_if = &tisci_if_NAVSS0_MAILBOX1_1[0],
2965 };
2967 /* Start of NAVSS0_MAILBOX1_2 interface definition */
2968 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_2_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_476_479 = {
2969         .lbase = 0,
2970         .len = 4,
2971         .rid = TISCI_DEV_NAVSS0_INTR_0,
2972         .rbase = 476,
2973 };
2974 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_2_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_12_15 = {
2975         .lbase = 0,
2976         .len = 4,
2977         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
2978         .rbase = 12,
2979 };
2980 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_2[] = {
2981         &NAVSS0_MAILBOX1_2_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_476_479,
2982         &NAVSS0_MAILBOX1_2_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_12_15,
2983 };
2984 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_2 = {
2985         .id = TISCI_DEV_NAVSS0_MAILBOX1_2,
2986         .n_if = 2,
2987         .p_if = &tisci_if_NAVSS0_MAILBOX1_2[0],
2988 };
2990 /* Start of NAVSS0_MAILBOX1_3 interface definition */
2991 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_3_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_472_475 = {
2992         .lbase = 0,
2993         .len = 4,
2994         .rid = TISCI_DEV_NAVSS0_INTR_0,
2995         .rbase = 472,
2996 };
2997 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_3_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_16_19 = {
2998         .lbase = 0,
2999         .len = 4,
3000         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3001         .rbase = 16,
3002 };
3003 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_3[] = {
3004         &NAVSS0_MAILBOX1_3_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_472_475,
3005         &NAVSS0_MAILBOX1_3_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_16_19,
3006 };
3007 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_3 = {
3008         .id = TISCI_DEV_NAVSS0_MAILBOX1_3,
3009         .n_if = 2,
3010         .p_if = &tisci_if_NAVSS0_MAILBOX1_3[0],
3011 };
3013 /* Start of NAVSS0_MAILBOX1_4 interface definition */
3014 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_4_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_468_471 = {
3015         .lbase = 0,
3016         .len = 4,
3017         .rid = TISCI_DEV_NAVSS0_INTR_0,
3018         .rbase = 468,
3019 };
3020 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_4_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_20_23 = {
3021         .lbase = 0,
3022         .len = 4,
3023         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3024         .rbase = 20,
3025 };
3026 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_4[] = {
3027         &NAVSS0_MAILBOX1_4_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_468_471,
3028         &NAVSS0_MAILBOX1_4_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_20_23,
3029 };
3030 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_4 = {
3031         .id = TISCI_DEV_NAVSS0_MAILBOX1_4,
3032         .n_if = 2,
3033         .p_if = &tisci_if_NAVSS0_MAILBOX1_4[0],
3034 };
3036 /* Start of NAVSS0_MAILBOX1_5 interface definition */
3037 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_5_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_464_467 = {
3038         .lbase = 0,
3039         .len = 4,
3040         .rid = TISCI_DEV_NAVSS0_INTR_0,
3041         .rbase = 464,
3042 };
3043 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_5_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_24_27 = {
3044         .lbase = 0,
3045         .len = 4,
3046         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3047         .rbase = 24,
3048 };
3049 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_5[] = {
3050         &NAVSS0_MAILBOX1_5_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_464_467,
3051         &NAVSS0_MAILBOX1_5_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_24_27,
3052 };
3053 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_5 = {
3054         .id = TISCI_DEV_NAVSS0_MAILBOX1_5,
3055         .n_if = 2,
3056         .p_if = &tisci_if_NAVSS0_MAILBOX1_5[0],
3057 };
3059 /* Start of NAVSS0_MAILBOX1_6 interface definition */
3060 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_6_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_460_463 = {
3061         .lbase = 0,
3062         .len = 4,
3063         .rid = TISCI_DEV_NAVSS0_INTR_0,
3064         .rbase = 460,
3065 };
3066 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_6_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_28_31 = {
3067         .lbase = 0,
3068         .len = 4,
3069         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3070         .rbase = 28,
3071 };
3072 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_6[] = {
3073         &NAVSS0_MAILBOX1_6_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_460_463,
3074         &NAVSS0_MAILBOX1_6_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_28_31,
3075 };
3076 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_6 = {
3077         .id = TISCI_DEV_NAVSS0_MAILBOX1_6,
3078         .n_if = 2,
3079         .p_if = &tisci_if_NAVSS0_MAILBOX1_6[0],
3080 };
3082 /* Start of NAVSS0_MAILBOX1_7 interface definition */
3083 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_7_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_456_459 = {
3084         .lbase = 0,
3085         .len = 4,
3086         .rid = TISCI_DEV_NAVSS0_INTR_0,
3087         .rbase = 456,
3088 };
3089 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_7_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_32_35 = {
3090         .lbase = 0,
3091         .len = 4,
3092         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3093         .rbase = 32,
3094 };
3095 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_7[] = {
3096         &NAVSS0_MAILBOX1_7_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_456_459,
3097         &NAVSS0_MAILBOX1_7_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_32_35,
3098 };
3099 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_7 = {
3100         .id = TISCI_DEV_NAVSS0_MAILBOX1_7,
3101         .n_if = 2,
3102         .p_if = &tisci_if_NAVSS0_MAILBOX1_7[0],
3103 };
3105 /* Start of NAVSS0_MAILBOX1_8 interface definition */
3106 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_8_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_452_455 = {
3107         .lbase = 0,
3108         .len = 4,
3109         .rid = TISCI_DEV_NAVSS0_INTR_0,
3110         .rbase = 452,
3111 };
3112 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_8_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_36_39 = {
3113         .lbase = 0,
3114         .len = 4,
3115         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3116         .rbase = 36,
3117 };
3118 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_8[] = {
3119         &NAVSS0_MAILBOX1_8_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_452_455,
3120         &NAVSS0_MAILBOX1_8_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_36_39,
3121 };
3122 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_8 = {
3123         .id = TISCI_DEV_NAVSS0_MAILBOX1_8,
3124         .n_if = 2,
3125         .p_if = &tisci_if_NAVSS0_MAILBOX1_8[0],
3126 };
3128 /* Start of NAVSS0_MAILBOX1_9 interface definition */
3129 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_9_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_448_451 = {
3130         .lbase = 0,
3131         .len = 4,
3132         .rid = TISCI_DEV_NAVSS0_INTR_0,
3133         .rbase = 448,
3134 };
3135 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_9_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_40_43 = {
3136         .lbase = 0,
3137         .len = 4,
3138         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3139         .rbase = 40,
3140 };
3141 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_9[] = {
3142         &NAVSS0_MAILBOX1_9_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_448_451,
3143         &NAVSS0_MAILBOX1_9_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_40_43,
3144 };
3145 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_9 = {
3146         .id = TISCI_DEV_NAVSS0_MAILBOX1_9,
3147         .n_if = 2,
3148         .p_if = &tisci_if_NAVSS0_MAILBOX1_9[0],
3149 };
3151 /* Start of NAVSS0_MAILBOX1_10 interface definition */
3152 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_10_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_444_447 = {
3153         .lbase = 0,
3154         .len = 4,
3155         .rid = TISCI_DEV_NAVSS0_INTR_0,
3156         .rbase = 444,
3157 };
3158 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_10_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_44_47 = {
3159         .lbase = 0,
3160         .len = 4,
3161         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3162         .rbase = 44,
3163 };
3164 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_10[] = {
3165         &NAVSS0_MAILBOX1_10_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_444_447,
3166         &NAVSS0_MAILBOX1_10_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_44_47,
3167 };
3168 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_10 = {
3169         .id = TISCI_DEV_NAVSS0_MAILBOX1_10,
3170         .n_if = 2,
3171         .p_if = &tisci_if_NAVSS0_MAILBOX1_10[0],
3172 };
3174 /* Start of NAVSS0_MAILBOX1_11 interface definition */
3175 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_11_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_440_443 = {
3176         .lbase = 0,
3177         .len = 4,
3178         .rid = TISCI_DEV_NAVSS0_INTR_0,
3179         .rbase = 440,
3180 };
3181 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX1_11_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_48_51 = {
3182         .lbase = 0,
3183         .len = 4,
3184         .rid = TISCI_DEV_NAVSS0_UDMASS_INTA_0,
3185         .rbase = 48,
3186 };
3187 const struct Sciclient_rmIrqIf * const tisci_if_NAVSS0_MAILBOX1_11[] = {
3188         &NAVSS0_MAILBOX1_11_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_440_443,
3189         &NAVSS0_MAILBOX1_11_pend_intr_0_3_to_NAVSS0_UDMASS_INTA_0_intaggr_levi_pend_48_51,
3190 };
3191 static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0_MAILBOX1_11 = {
3192         .id = TISCI_DEV_NAVSS0_MAILBOX1_11,
3193         .n_if = 2,
3194         .p_if = &tisci_if_NAVSS0_MAILBOX1_11[0],
3195 };
3197 /* Start of NAVSS0_MAILBOX_0 interface definition */
3198 const struct Sciclient_rmIrqIf NAVSS0_MAILBOX_0_pend_intr_0_3_to_NAVSS0_INTR_0_in_intr_436_439 = {
3199         .lbase = 0,
3200         .len = 4,
3201         .rid = TISCI_DEV_NAVSS0_INTR_0,
3202         .rbase = 436,