[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / binaries / scripts / sysfw_boardcfg_rules.json
1 {
2 "comment": "Python struct module (https://docs.python.org/2/library/struct.html#module-struct) format codes and validation rules for the board configuration structures",
3 "format_rules": {
4 "boardcfg_substructure_header": {
5 "magic": {
6 "fmt": "H"
7 },
8 "size": {
9 "fmt": "H"
10 }
11 },
12 "boardcfg_abi_rev": {
13 "boardcfg_abi_maj": {
14 "fmt": "B"
15 },
16 "boardcfg_abi_min": {
17 "fmt": "B"
18 }
19 },
20 "boardcfg_rm_host_cfg_entry": {
21 "host_id": {
22 "fmt": "B"
23 },
24 "allowed_atype": {
25 "fmt": "B"
26 },
27 "allowed_qos": {
28 "fmt": "H"
29 },
30 "allowed_orderid": {
31 "fmt": "I"
32 },
33 "allowed_priority": {
34 "fmt": "H"
35 },
36 "allowed_sched_priority": {
37 "fmt": "B"
38 }
39 },
40 "boardcfg_rm_host_cfg": {
41 "subhdr": {
42 "fmt": "boardcfg_substructure_header",
43 "value": {
44 "magic": "0x4c41",
45 "size": "boardcfg_rm_host_cfg"
46 }
47 },
48 "host_cfg_entries": {
49 "fmt": "boardcfg_rm_host_cfg_entry",
50 "elements": 32
51 }
52 },
53 "boardcfg_rm_resasg_entry": {
54 "start_resource": {
55 "fmt": "H"
56 },
57 "num_resource": {
58 "fmt": "H"
59 },
60 "type": {
61 "fmt": "H"
62 },
63 "host_id": {
64 "fmt": "B"
65 },
66 "reserved": {
67 "fmt": "B"
68 }
69 },
70 "boardcfg_rm_resasg": {
71 "subhdr": {
72 "fmt": "boardcfg_substructure_header",
73 "value": {
74 "magic": "0x7b25",
75 "size": "boardcfg_rm_resasg"
76 }
77 },
78 "resasg_entries_size": {
79 "fmt": "H"
80 },
81 "reserved": {
82 "fmt": "H"
83 },
84 "resasg_entries": {
85 "fmt": "boardcfg_rm_resasg_entry",
86 "validator": "boardcfg_rm_resasg_entry",
87 "size_bytes": "resasg_entries_size",
88 "incomplete_type": "",
89 "sort_order": [
90 "type",
91 "start_resource"
92 ]
93 }
94 },
95 "boardcfg_rm": {
96 "rev": {
97 "fmt": "boardcfg_abi_rev"
98 },
99 "host_cfg": {
100 "fmt": "boardcfg_rm_host_cfg"
101 },
102 "resasg": {
103 "fmt": "boardcfg_substructure_header"
104 }
105 },
106 "boardcfg_pm": {
107 "rev": {
108 "fmt": "boardcfg_abi_rev"
109 }
110 },
111 "boardcfg_control": {
112 "subhdr": {
113 "fmt": "boardcfg_substructure_header",
114 "value": {
115 "magic": "0xc1d3",
116 "size": "boardcfg_control"
117 }
118 },
119 "main_isolation_enable": {
120 "fmt": "?"
121 },
122 "main_isolation_hostid": {
123 "fmt": "H"
124 }
125 },
126 "boardcfg_secproxy": {
127 "subhdr": {
128 "fmt": "boardcfg_substructure_header",
129 "value": {
130 "magic": "0x1207",
131 "size": "boardcfg_secproxy"
132 }
133 },
134 "scaling_factor": {
135 "fmt": "B"
136 },
137 "scaling_profile": {
138 "fmt": "B"
139 },
140 "disable_main_nav_secure_proxy": {
141 "fmt": "B"
142 }
143 },
144 "boardcfg_msmc": {
145 "subhdr": {
146 "fmt": "boardcfg_substructure_header",
147 "value": {
148 "magic": "0xa5c3",
149 "size": "boardcfg_msmc"
150 }
151 },
152 "msmc_cache_size": {
153 "fmt": "B"
154 }
155 },
156 "boardcfg_proc_acl_entry": {
157 "processor_id": {
158 "fmt": "B"
159 },
160 "proc_access_master": {
161 "fmt": "B"
162 },
163 "proc_access_secondary": {
164 "fmt": "B",
165 "elements": 3
166 }
167 },
168 "boardcfg_proc_acl": {
169 "subhdr": {
170 "fmt": "boardcfg_substructure_header",
171 "value": {
172 "magic": "0xf1ea",
173 "size": "boardcfg_proc_acl"
174 }
175 },
176 "boardcfg_proc_acl_entry": {
177 "fmt": "boardcfg_proc_acl_entry",
178 "elements": 32
179 }
180 },
181 "boardcfg_host_hierarchy_entry": {
182 "host_id": {
183 "fmt": "B"
184 },
185 "supervisor_host_id": {
186 "fmt": "B"
187 }
188 },
189 "boardcfg_host_hierarchy": {
190 "subhdr": {
191 "fmt": "boardcfg_substructure_header",
192 "value": {
193 "magic": "0x8d27",
194 "size": "boardcfg_host_hierarchy"
195 }
196 },
197 "host_hierarchy_entries": {
198 "fmt": "boardcfg_host_hierarchy_entry",
199 "elements": 32
200 }
201 },
202 "boardcfg_extended_otp_entry": {
203 "host_id": {
204 "fmt": "B"
205 },
206 "host_perms": {
207 "fmt": "B"
208 }
209 },
210 "boardcfg_extended_otp": {
211 "subhdr": {
212 "fmt": "boardcfg_substructure_header",
213 "value": {
214 "magic": "0x4081",
215 "size": "boardcfg_extended_otp"
216 }
217 },
218 "otp_entry": {
219 "fmt": "boardcfg_extended_otp_entry",
220 "elements": 32
221 },
222 "write_host_id": {
223 "fmt": "B"
224 }
225 },
226 "boardcfg_dkek": {
227 "subhdr": {
228 "fmt": "boardcfg_substructure_header",
229 "value": {
230 "magic": "0x5170",
231 "size": "boardcfg_dkek"
232 }
233 },
234 "allowed_hosts": {
235 "fmt": "B",
236 "elements": 4
237 },
238 "allow_dkek_export_tisci": {
239 "fmt": "B"
240 },
241 "rsvd": {
242 "fmt": "B",
243 "elements": 3
244 }
245 },
246 "boardcfg_sec": {
247 "rev": {
248 "fmt": "boardcfg_abi_rev"
249 },
250 "processor_acl_list": {
251 "fmt": "boardcfg_proc_acl"
252 },
253 "host_hierarchy": {
254 "fmt": "boardcfg_host_hierarchy"
255 },
256 "otp_config": {
257 "fmt": "boardcfg_extended_otp"
258 },
259 "dkek_config": {
260 "fmt": "boardcfg_dkek"
261 }
262 },
263 "boardcfg_orderid": {
264 "allowed": {
265 "fmt": "I"
266 }
267 },
268 "boardcfg_dbg_cfg": {
269 "subhdr": {
270 "fmt": "boardcfg_substructure_header",
271 "value": {
272 "magic": "0x020c",
273 "size": "boardcfg_dbg_cfg"
274 }
275 },
276 "trace_dst_enables": {
277 "fmt": "H"
278 },
279 "trace_src_enables": {
280 "fmt": "H"
281 }
282 },
283 "boardcfg": {
284 "rev": {
285 "fmt": "boardcfg_abi_rev"
286 },
287 "control": {
288 "fmt": "boardcfg_control"
289 },
290 "secproxy": {
291 "fmt": "boardcfg_secproxy"
292 },
293 "msmc": {
294 "fmt": "boardcfg_msmc"
295 },
296 "debug_cfg": {
297 "fmt": "boardcfg_dbg_cfg"
298 }
299 }
300 },
301 "validation_rules": {
302 "boardcfg_rm_resasg_entry": {
303 "comment": "values array contain each resources valid range AFTER accounting for DMSC reserved resources",
304 "am6": {
305 "values": [
306 {
307 "name": "RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
308 "type": 192,
309 "start_resource": 0,
310 "num_resource": 32
311 },
312 {
313 "name": "RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
314 "type": 6208,
315 "start_resource": 0,
316 "num_resource": 64
317 },
318 {
319 "name": "RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
320 "type": 6272,
321 "start_resource": 0,
322 "num_resource": 48
323 },
324 {
325 "name": "RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
326 "type": 6400,
327 "start_resource": 0,
328 "num_resource": 32
329 },
330 {
331 "name": "RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
332 "type": 9280,
333 "start_resource": 0,
334 "num_resource": 40
335 },
336 {
337 "name": "RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
338 "type": 9984,
339 "start_resource": 0,
340 "num_resource": 16
341 },
342 {
343 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_IA_VINT)",
344 "type": 11466,
345 "start_resource": 16,
346 "num_resource": 240
347 },
348 {
349 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
350 "type": 11469,
351 "start_resource": 16,
352 "num_resource": 4592
353 },
354 {
355 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_IA_VINT)",
356 "type": 11530,
357 "start_resource": 0,
358 "num_resource": 64
359 },
360 {
361 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
362 "type": 11533,
363 "start_resource": 20480,
364 "num_resource": 1024
365 },
366 {
367 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_IA_VINT)",
368 "type": 11594,
369 "start_resource": 0,
370 "num_resource": 64
371 },
372 {
373 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
374 "type": 11597,
375 "start_resource": 22528,
376 "num_resource": 1024
377 },
378 {
379 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
380 "type": 11648,
381 "start_resource": 16,
382 "num_resource": 136
383 },
384 {
385 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_PROXY0, RESASG_SUBTYPE_PROXY_PROXIES)",
386 "type": 11840,
387 "start_resource": 1,
388 "num_resource": 63
389 },
390 {
391 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES)",
392 "type": 11968,
393 "start_resource": 0,
394 "num_resource": 1
395 },
396 {
397 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP)",
398 "type": 11969,
399 "start_resource": 304,
400 "num_resource": 464
401 },
402 {
403 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX)",
404 "type": 11970,
405 "start_resource": 160,
406 "num_resource": 142
407 },
408 {
409 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX)",
410 "type": 11971,
411 "start_resource": 8,
412 "num_resource": 112
413 },
414 {
415 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT)",
416 "type": 11972,
417 "start_resource": 120,
418 "num_resource": 32
419 },
420 {
421 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
422 "type": 11973,
423 "start_resource": 154,
424 "num_resource": 6
425 },
426 {
427 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
428 "type": 11975,
429 "start_resource": 1,
430 "num_resource": 7
431 },
432 {
433 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_VIRTID)",
434 "type": 11978,
435 "start_resource": 0,
436 "num_resource": 4096
437 },
438 {
439 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_MONITORS)",
440 "type": 11979,
441 "start_resource": 0,
442 "num_resource": 32
443 },
444 {
445 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
446 "type": 12032,
447 "start_resource": 150,
448 "num_resource": 150
449 },
450 {
451 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
452 "type": 12033,
453 "start_resource": 0,
454 "num_resource": 1
455 },
456 {
457 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
458 "type": 12034,
459 "start_resource": 49152,
460 "num_resource": 1024
461 },
462 {
463 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
464 "type": 12035,
465 "start_resource": 0,
466 "num_resource": 1
467 },
468 {
469 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
470 "type": 12042,
471 "start_resource": 8,
472 "num_resource": 142
473 },
474 {
475 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
476 "type": 12043,
477 "start_resource": 2,
478 "num_resource": 6
479 },
480 {
481 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
482 "type": 12045,
483 "start_resource": 8,
484 "num_resource": 112
485 },
486 {
487 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_ECHAN)",
488 "type": 12046,
489 "start_resource": 120,
490 "num_resource": 32
491 },
492 {
493 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
494 "type": 12047,
495 "start_resource": 1,
496 "num_resource": 7
497 },
498 {
499 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_IA_VINT)",
500 "type": 12106,
501 "start_resource": 8,
502 "num_resource": 248
503 },
504 {
505 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
506 "type": 12109,
507 "start_resource": 16392,
508 "num_resource": 1528
509 },
510 {
511 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
512 "type": 12160,
513 "start_resource": 4,
514 "num_resource": 28
515 },
516 {
517 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
518 "type": 12160,
519 "start_resource": 36,
520 "num_resource": 28
521 },
522 {
523 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_PROXY0, RESASG_SUBTYPE_PROXY_PROXIES)",
524 "type": 12224,
525 "start_resource": 0,
526 "num_resource": 64
527 },
528 {
529 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
530 "type": 12416,
531 "start_resource": 48,
532 "num_resource": 48
533 },
534 {
535 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
536 "type": 12417,
537 "start_resource": 0,
538 "num_resource": 1
539 },
540 {
541 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
542 "type": 12418,
543 "start_resource": 56320,
544 "num_resource": 256
545 },
546 {
547 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
548 "type": 12419,
549 "start_resource": 0,
550 "num_resource": 1
551 },
552 {
553 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
554 "type": 12426,
555 "start_resource": 2,
556 "num_resource": 46
557 },
558 {
559 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
560 "type": 12427,
561 "start_resource": 0,
562 "num_resource": 2
563 },
564 {
565 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
566 "type": 12429,
567 "start_resource": 2,
568 "num_resource": 46
569 },
570 {
571 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
572 "type": 12431,
573 "start_resource": 0,
574 "num_resource": 2
575 },
576 {
577 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES)",
578 "type": 12480,
579 "start_resource": 0,
580 "num_resource": 1
581 },
582 {
583 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP)",
584 "type": 12481,
585 "start_resource": 96,
586 "num_resource": 160
587 },
588 {
589 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX)",
590 "type": 12482,
591 "start_resource": 50,
592 "num_resource": 46
593 },
594 {
595 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX)",
596 "type": 12483,
597 "start_resource": 2,
598 "num_resource": 46
599 },
600 {
601 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
602 "type": 12485,
603 "start_resource": 48,
604 "num_resource": 2
605 },
606 {
607 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
608 "type": 12487,
609 "start_resource": 0,
610 "num_resource": 2
611 },
612 {
613 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_VIRTID)",
614 "type": 12490,
615 "start_resource": 0,
616 "num_resource": 4096
617 },
618 {
619 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_MONITORS)",
620 "type": 12491,
621 "start_resource": 0,
622 "num_resource": 32
623 }
624 ],
625 "constraints": [
626 {
627 "max_resource_entries": 104
628 }
629 ]
630 },
631 "am65x_sr2": {
632 "values": [
633 {
634 "name": "RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
635 "type": 192,
636 "start_resource": 0,
637 "num_resource": 32
638 },
639 {
640 "name": "RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
641 "type": 6208,
642 "start_resource": 0,
643 "num_resource": 64
644 },
645 {
646 "name": "RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
647 "type": 6272,
648 "start_resource": 0,
649 "num_resource": 48
650 },
651 {
652 "name": "RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
653 "type": 6400,
654 "start_resource": 0,
655 "num_resource": 32
656 },
657 {
658 "name": "RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
659 "type": 9280,
660 "start_resource": 0,
661 "num_resource": 40
662 },
663 {
664 "name": "RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
665 "type": 9984,
666 "start_resource": 0,
667 "num_resource": 16
668 },
669 {
670 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_IA_VINT)",
671 "type": 11466,
672 "start_resource": 16,
673 "num_resource": 240
674 },
675 {
676 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
677 "type": 11469,
678 "start_resource": 16,
679 "num_resource": 4592
680 },
681 {
682 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_IA_VINT)",
683 "type": 11530,
684 "start_resource": 0,
685 "num_resource": 64
686 },
687 {
688 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
689 "type": 11533,
690 "start_resource": 20480,
691 "num_resource": 1024
692 },
693 {
694 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_IA_VINT)",
695 "type": 11594,
696 "start_resource": 0,
697 "num_resource": 64
698 },
699 {
700 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
701 "type": 11597,
702 "start_resource": 22528,
703 "num_resource": 1024
704 },
705 {
706 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
707 "type": 11648,
708 "start_resource": 16,
709 "num_resource": 136
710 },
711 {
712 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_PROXY0, RESASG_SUBTYPE_PROXY_PROXIES)",
713 "type": 11840,
714 "start_resource": 1,
715 "num_resource": 63
716 },
717 {
718 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES)",
719 "type": 11968,
720 "start_resource": 0,
721 "num_resource": 1
722 },
723 {
724 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP)",
725 "type": 11969,
726 "start_resource": 304,
727 "num_resource": 464
728 },
729 {
730 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX)",
731 "type": 11970,
732 "start_resource": 160,
733 "num_resource": 142
734 },
735 {
736 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX)",
737 "type": 11971,
738 "start_resource": 8,
739 "num_resource": 112
740 },
741 {
742 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT)",
743 "type": 11972,
744 "start_resource": 120,
745 "num_resource": 32
746 },
747 {
748 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
749 "type": 11973,
750 "start_resource": 154,
751 "num_resource": 6
752 },
753 {
754 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
755 "type": 11975,
756 "start_resource": 1,
757 "num_resource": 7
758 },
759 {
760 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_VIRTID)",
761 "type": 11978,
762 "start_resource": 0,
763 "num_resource": 4096
764 },
765 {
766 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_MONITORS)",
767 "type": 11979,
768 "start_resource": 0,
769 "num_resource": 32
770 },
771 {
772 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
773 "type": 12032,
774 "start_resource": 150,
775 "num_resource": 150
776 },
777 {
778 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
779 "type": 12033,
780 "start_resource": 0,
781 "num_resource": 1
782 },
783 {
784 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
785 "type": 12034,
786 "start_resource": 49152,
787 "num_resource": 1024
788 },
789 {
790 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
791 "type": 12035,
792 "start_resource": 0,
793 "num_resource": 1
794 },
795 {
796 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
797 "type": 12042,
798 "start_resource": 8,
799 "num_resource": 142
800 },
801 {
802 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
803 "type": 12043,
804 "start_resource": 2,
805 "num_resource": 6
806 },
807 {
808 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
809 "type": 12045,
810 "start_resource": 8,
811 "num_resource": 112
812 },
813 {
814 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_ECHAN)",
815 "type": 12046,
816 "start_resource": 120,
817 "num_resource": 32
818 },
819 {
820 "name": "RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
821 "type": 12047,
822 "start_resource": 1,
823 "num_resource": 7
824 },
825 {
826 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_IA_VINT)",
827 "type": 12106,
828 "start_resource": 8,
829 "num_resource": 248
830 },
831 {
832 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
833 "type": 12109,
834 "start_resource": 16392,
835 "num_resource": 1528
836 },
837 {
838 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
839 "type": 12160,
840 "start_resource": 4,
841 "num_resource": 28
842 },
843 {
844 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
845 "type": 12160,
846 "start_resource": 36,
847 "num_resource": 28
848 },
849 {
850 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_PROXY0, RESASG_SUBTYPE_PROXY_PROXIES)",
851 "type": 12224,
852 "start_resource": 0,
853 "num_resource": 64
854 },
855 {
856 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
857 "type": 12416,
858 "start_resource": 48,
859 "num_resource": 48
860 },
861 {
862 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
863 "type": 12417,
864 "start_resource": 0,
865 "num_resource": 1
866 },
867 {
868 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
869 "type": 12418,
870 "start_resource": 56320,
871 "num_resource": 256
872 },
873 {
874 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
875 "type": 12419,
876 "start_resource": 0,
877 "num_resource": 1
878 },
879 {
880 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
881 "type": 12426,
882 "start_resource": 2,
883 "num_resource": 46
884 },
885 {
886 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
887 "type": 12427,
888 "start_resource": 0,
889 "num_resource": 2
890 },
891 {
892 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
893 "type": 12429,
894 "start_resource": 2,
895 "num_resource": 46
896 },
897 {
898 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
899 "type": 12431,
900 "start_resource": 0,
901 "num_resource": 2
902 },
903 {
904 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES)",
905 "type": 12480,
906 "start_resource": 0,
907 "num_resource": 1
908 },
909 {
910 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP)",
911 "type": 12481,
912 "start_resource": 96,
913 "num_resource": 160
914 },
915 {
916 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX)",
917 "type": 12482,
918 "start_resource": 50,
919 "num_resource": 46
920 },
921 {
922 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX)",
923 "type": 12483,
924 "start_resource": 2,
925 "num_resource": 46
926 },
927 {
928 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
929 "type": 12485,
930 "start_resource": 48,
931 "num_resource": 2
932 },
933 {
934 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
935 "type": 12487,
936 "start_resource": 0,
937 "num_resource": 2
938 },
939 {
940 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_VIRTID)",
941 "type": 12490,
942 "start_resource": 0,
943 "num_resource": 4096
944 },
945 {
946 "name": "RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_MONITORS)",
947 "type": 12491,
948 "start_resource": 0,
949 "num_resource": 32
950 }
951 ],
952 "constraints": [
953 {
954 "max_resource_entries": 104
955 }
956 ]
957 },
958 "j721e": {
959 "values": [
960 {
961 "name": "RESASG_UTYPE(J721E_DEV_C66SS0_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
962 "type": 7744,
963 "start_resource": 4,
964 "num_resource": 93
965 },
966 {
967 "name": "RESASG_UTYPE(J721E_DEV_C66SS1_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
968 "type": 7808,
969 "start_resource": 4,
970 "num_resource": 93
971 },
972 {
973 "name": "RESASG_UTYPE(J721E_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
974 "type": 7872,
975 "start_resource": 0,
976 "num_resource": 32
977 },
978 {
979 "name": "RESASG_UTYPE(J721E_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
980 "type": 8192,
981 "start_resource": 0,
982 "num_resource": 64
983 },
984 {
985 "name": "RESASG_UTYPE(J721E_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
986 "type": 8320,
987 "start_resource": 0,
988 "num_resource": 48
989 },
990 {
991 "name": "RESASG_UTYPE(J721E_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
992 "type": 8384,
993 "start_resource": 0,
994 "num_resource": 64
995 },
996 {
997 "name": "RESASG_UTYPE(J721E_DEV_R5FSS0_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
998 "type": 8576,
999 "start_resource": 0,
1000 "num_resource": 256
1001 },
1002 {
1003 "name": "RESASG_UTYPE(J721E_DEV_R5FSS1_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
1004 "type": 8640,
1005 "start_resource": 0,
1006 "num_resource": 256
1007 },
1008 {
1009 "name": "RESASG_UTYPE(J721E_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
1010 "type": 8704,
1011 "start_resource": 0,
1012 "num_resource": 48
1013 },
1014 {
1015 "name": "RESASG_UTYPE(J721E_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT)",
1016 "type": 8768,
1017 "start_resource": 0,
1018 "num_resource": 32
1019 },
1020 {
1021 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_MODSS_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1022 "type": 13258,
1023 "start_resource": 0,
1024 "num_resource": 64
1025 },
1026 {
1027 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_MODSS_INTAGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
1028 "type": 13261,
1029 "start_resource": 20480,
1030 "num_resource": 1024
1031 },
1032 {
1033 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_MODSS_INTAGGR_1, RESASG_SUBTYPE_IA_VINT)",
1034 "type": 13322,
1035 "start_resource": 0,
1036 "num_resource": 64
1037 },
1038 {
1039 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_MODSS_INTAGGR_1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
1040 "type": 13325,
1041 "start_resource": 22528,
1042 "num_resource": 1024
1043 },
1044 {
1045 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMASS_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1046 "type": 13386,
1047 "start_resource": 38,
1048 "num_resource": 218
1049 },
1050 {
1051 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMASS_INTAGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
1052 "type": 13389,
1053 "start_resource": 38,
1054 "num_resource": 4570
1055 },
1056 {
1057 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_PROXY_0, RESASG_SUBTYPE_PROXY_PROXIES)",
1058 "type": 13440,
1059 "start_resource": 0,
1060 "num_resource": 64
1061 },
1062 {
1063 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_ERROR_OES)",
1064 "type": 13504,
1065 "start_resource": 0,
1066 "num_resource": 1
1067 },
1068 {
1069 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_GP)",
1070 "type": 13505,
1071 "start_resource": 440,
1072 "num_resource": 534
1073 },
1074 {
1075 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_RX)",
1076 "type": 13506,
1077 "start_resource": 316,
1078 "num_resource": 124
1079 },
1080 {
1081 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX)",
1082 "type": 13507,
1083 "start_resource": 16,
1084 "num_resource": 124
1085 },
1086 {
1087 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT)",
1088 "type": 13508,
1089 "start_resource": 140,
1090 "num_resource": 160
1091 },
1092 {
1093 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
1094 "type": 13509,
1095 "start_resource": 304,
1096 "num_resource": 12
1097 },
1098 {
1099 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_RX_UH)",
1100 "type": 13510,
1101 "start_resource": 300,
1102 "num_resource": 4
1103 },
1104 {
1105 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
1106 "type": 13511,
1107 "start_resource": 4,
1108 "num_resource": 12
1109 },
1110 {
1111 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX_UH)",
1112 "type": 13512,
1113 "start_resource": 0,
1114 "num_resource": 4
1115 },
1116 {
1117 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_VIRTID)",
1118 "type": 13514,
1119 "start_resource": 0,
1120 "num_resource": 4096
1121 },
1122 {
1123 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_MONITORS)",
1124 "type": 13515,
1125 "start_resource": 0,
1126 "num_resource": 32
1127 },
1128 {
1129 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
1130 "type": 13568,
1131 "start_resource": 140,
1132 "num_resource": 160
1133 },
1134 {
1135 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
1136 "type": 13569,
1137 "start_resource": 0,
1138 "num_resource": 1
1139 },
1140 {
1141 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
1142 "type": 13570,
1143 "start_resource": 49152,
1144 "num_resource": 1024
1145 },
1146 {
1147 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
1148 "type": 13571,
1149 "start_resource": 0,
1150 "num_resource": 1
1151 },
1152 {
1153 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
1154 "type": 13578,
1155 "start_resource": 16,
1156 "num_resource": 124
1157 },
1158 {
1159 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
1160 "type": 13579,
1161 "start_resource": 4,
1162 "num_resource": 12
1163 },
1164 {
1165 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_UHCHAN)",
1166 "type": 13580,
1167 "start_resource": 0,
1168 "num_resource": 4
1169 },
1170 {
1171 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
1172 "type": 13581,
1173 "start_resource": 16,
1174 "num_resource": 124
1175 },
1176 {
1177 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_ECHAN)",
1178 "type": 13582,
1179 "start_resource": 140,
1180 "num_resource": 160
1181 },
1182 {
1183 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
1184 "type": 13583,
1185 "start_resource": 4,
1186 "num_resource": 12
1187 },
1188 {
1189 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_UHCHAN)",
1190 "type": 13584,
1191 "start_resource": 0,
1192 "num_resource": 4
1193 },
1194 {
1195 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1196 "type": 13632,
1197 "start_resource": 10,
1198 "num_resource": 178
1199 },
1200 {
1201 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1202 "type": 13632,
1203 "start_resource": 196,
1204 "num_resource": 28
1205 },
1206 {
1207 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1208 "type": 13632,
1209 "start_resource": 228,
1210 "num_resource": 28
1211 },
1212 {
1213 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1214 "type": 13632,
1215 "start_resource": 260,
1216 "num_resource": 28
1217 },
1218 {
1219 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1220 "type": 13632,
1221 "start_resource": 292,
1222 "num_resource": 52
1223 },
1224 {
1225 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1226 "type": 13632,
1227 "start_resource": 348,
1228 "num_resource": 28
1229 },
1230 {
1231 "name": "RESASG_UTYPE(J721E_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1232 "type": 13632,
1233 "start_resource": 380,
1234 "num_resource": 132
1235 },
1236 {
1237 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1238 "type": 14922,
1239 "start_resource": 8,
1240 "num_resource": 248
1241 },
1242 {
1243 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_INTAGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
1244 "type": 14925,
1245 "start_resource": 16392,
1246 "num_resource": 1528
1247 },
1248 {
1249 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_PROXY_0, RESASG_SUBTYPE_PROXY_PROXIES)",
1250 "type": 14976,
1251 "start_resource": 1,
1252 "num_resource": 63
1253 },
1254 {
1255 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_ERROR_OES)",
1256 "type": 15040,
1257 "start_resource": 0,
1258 "num_resource": 1
1259 },
1260 {
1261 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_GP)",
1262 "type": 15041,
1263 "start_resource": 96,
1264 "num_resource": 156
1265 },
1266 {
1267 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_RX)",
1268 "type": 15042,
1269 "start_resource": 50,
1270 "num_resource": 43
1271 },
1272 {
1273 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX)",
1274 "type": 15043,
1275 "start_resource": 2,
1276 "num_resource": 44
1277 },
1278 {
1279 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_RX_H)",
1280 "type": 15045,
1281 "start_resource": 48,
1282 "num_resource": 2
1283 },
1284 {
1285 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_UDMAP_TX_H)",
1286 "type": 15047,
1287 "start_resource": 0,
1288 "num_resource": 2
1289 },
1290 {
1291 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_VIRTID)",
1292 "type": 15050,
1293 "start_resource": 0,
1294 "num_resource": 4096
1295 },
1296 {
1297 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_RINGACC_0, RESASG_SUBTYPE_RA_MONITORS)",
1298 "type": 15051,
1299 "start_resource": 0,
1300 "num_resource": 32
1301 },
1302 {
1303 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON)",
1304 "type": 15104,
1305 "start_resource": 48,
1306 "num_resource": 48
1307 },
1308 {
1309 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES)",
1310 "type": 15105,
1311 "start_resource": 0,
1312 "num_resource": 1
1313 },
1314 {
1315 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
1316 "type": 15106,
1317 "start_resource": 56320,
1318 "num_resource": 256
1319 },
1320 {
1321 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
1322 "type": 15107,
1323 "start_resource": 0,
1324 "num_resource": 1
1325 },
1326 {
1327 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_CHAN)",
1328 "type": 15114,
1329 "start_resource": 2,
1330 "num_resource": 43
1331 },
1332 {
1333 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_RX_HCHAN)",
1334 "type": 15115,
1335 "start_resource": 0,
1336 "num_resource": 2
1337 },
1338 {
1339 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_CHAN)",
1340 "type": 15117,
1341 "start_resource": 2,
1342 "num_resource": 44
1343 },
1344 {
1345 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_UDMAP_0, RESASG_SUBTYPE_UDMAP_TX_HCHAN)",
1346 "type": 15119,
1347 "start_resource": 0,
1348 "num_resource": 2
1349 },
1350 {
1351 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1352 "type": 15168,
1353 "start_resource": 4,
1354 "num_resource": 28
1355 },
1356 {
1357 "name": "RESASG_UTYPE(J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT)",
1358 "type": 15168,
1359 "start_resource": 36,
1360 "num_resource": 28
1361 }
1362 ],
1363 "constraints": [
1364 {
1365 "max_resource_entries": 420
1366 }
1367 ]
1368 },
1369 "am64x": {
1370 "values": [
1371 {
1372 "name": "RESASG_UTYPE(AM64X_DEV_CMP_EVENT_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
1373 "type": 64,
1374 "start_resource": 0,
1375 "num_resource": 43
1376 },
1377 {
1378 "name": "RESASG_UTYPE(AM64X_DEV_MAIN_GPIOMUX_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
1379 "type": 192,
1380 "start_resource": 0,
1381 "num_resource": 54
1382 },
1383 {
1384 "name": "RESASG_UTYPE(AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
1385 "type": 320,
1386 "start_resource": 0,
1387 "num_resource": 12
1388 },
1389 {
1390 "name": "RESASG_UTYPE(AM64X_DEV_TIMESYNC_EVENT_INTROUTER0, RESASG_SUBTYPE_IR_OUTPUT)",
1391 "type": 384,
1392 "start_resource": 0,
1393 "num_resource": 41
1394 },
1395 {
1396 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_RA_ERROR_OES)",
1397 "type": 1664,
1398 "start_resource": 0,
1399 "num_resource": 1
1400 },
1401 {
1402 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER)",
1403 "type": 1666,
1404 "start_resource": 50176,
1405 "num_resource": 136
1406 },
1407 {
1408 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
1409 "type": 1667,
1410 "start_resource": 0,
1411 "num_resource": 1
1412 },
1413 {
1414 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN)",
1415 "type": 1677,
1416 "start_resource": 0,
1417 "num_resource": 28
1418 },
1419 {
1420 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN)",
1421 "type": 1678,
1422 "start_resource": 48,
1423 "num_resource": 20
1424 },
1425 {
1426 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN)",
1427 "type": 1679,
1428 "start_resource": 28,
1429 "num_resource": 20
1430 },
1431 {
1432 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN)",
1433 "type": 1696,
1434 "start_resource": 0,
1435 "num_resource": 28
1436 },
1437 {
1438 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN)",
1439 "type": 1697,
1440 "start_resource": 0,
1441 "num_resource": 20
1442 },
1443 {
1444 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_BCDMA_0, RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN)",
1445 "type": 1698,
1446 "start_resource": 0,
1447 "num_resource": 20
1448 },
1449 {
1450 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1451 "type": 1802,
1452 "start_resource": 4,
1453 "num_resource": 36
1454 },
1455 {
1456 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1457 "type": 1802,
1458 "start_resource": 44,
1459 "num_resource": 44
1460 },
1461 {
1462 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1463 "type": 1802,
1464 "start_resource": 92,
1465 "num_resource": 44
1466 },
1467 {
1468 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_VINT)",
1469 "type": 1802,
1470 "start_resource": 139,
1471 "num_resource": 45
1472 },
1473 {
1474 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT)",
1475 "type": 1805,
1476 "start_resource": 15,
1477 "num_resource": 1521
1478 },
1479 {
1480 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES)",
1481 "type": 1807,
1482 "start_resource": 0,
1483 "num_resource": 1024
1484 },
1485 {
1486 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES)",
1487 "type": 1808,
1488 "start_resource": 4096,
1489 "num_resource": 42
1490 },
1491 {
1492 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES)",
1493 "type": 1809,
1494 "start_resource": 4608,
1495 "num_resource": 112
1496 },
1497 {
1498 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES)",
1499 "type": 1810,
1500 "start_resource": 5120,
1501 "num_resource": 29
1502 },
1503 {
1504 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES)",
1505 "type": 1811,
1506 "start_resource": 5632,
1507 "num_resource": 176
1508 },
1509 {
1510 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES)",
1511 "type": 1812,
1512 "start_resource": 6144,
1513 "num_resource": 176
1514 },
1515 {
1516 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES)",
1517 "type": 1813,
1518 "start_resource": 6656,
1519 "num_resource": 176
1520 },
1521 {
1522 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES)",
1523 "type": 1814,
1524 "start_resource": 8192,
1525 "num_resource": 28
1526 },
1527 {
1528 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES)",
1529 "type": 1815,
1530 "start_resource": 8704,
1531 "num_resource": 28
1532 },
1533 {
1534 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES)",
1535 "type": 1816,
1536 "start_resource": 9216,
1537 "num_resource": 28
1538 },
1539 {
1540 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES)",
1541 "type": 1817,
1542 "start_resource": 9728,
1543 "num_resource": 20
1544 },
1545 {
1546 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES)",
1547 "type": 1818,
1548 "start_resource": 10240,
1549 "num_resource": 20
1550 },
1551 {
1552 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES)",
1553 "type": 1819,
1554 "start_resource": 10752,
1555 "num_resource": 20
1556 },
1557 {
1558 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES)",
1559 "type": 1820,
1560 "start_resource": 11264,
1561 "num_resource": 20
1562 },
1563 {
1564 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES)",
1565 "type": 1821,
1566 "start_resource": 11776,
1567 "num_resource": 20
1568 },
1569 {
1570 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_INTAGGR_0, RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES)",
1571 "type": 1822,
1572 "start_resource": 12288,
1573 "num_resource": 20
1574 },
1575 {
1576 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_RA_ERROR_OES)",
1577 "type": 1920,
1578 "start_resource": 0,
1579 "num_resource": 1
1580 },
1581 {
1582 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG)",
1583 "type": 1923,
1584 "start_resource": 0,
1585 "num_resource": 1
1586 },
1587 {
1588 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN)",
1589 "type": 1936,
1590 "start_resource": 0,
1591 "num_resource": 16
1592 },
1593 {
1594 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN)",
1595 "type": 1937,
1596 "start_resource": 16,
1597 "num_resource": 64
1598 },
1599 {
1600 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN)",
1601 "type": 1938,
1602 "start_resource": 81,
1603 "num_resource": 7
1604 },
1605 {
1606 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN)",
1607 "type": 1939,
1608 "start_resource": 88,
1609 "num_resource": 8
1610 },
1611 {
1612 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN)",
1613 "type": 1940,
1614 "start_resource": 96,
1615 "num_resource": 8
1616 },
1617 {
1618 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN)",
1619 "type": 1941,
1620 "start_resource": 104,
1621 "num_resource": 8
1622 },
1623 {
1624 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN)",
1625 "type": 1942,
1626 "start_resource": 112,
1627 "num_resource": 16
1628 },
1629 {
1630 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN)",
1631 "type": 1943,
1632 "start_resource": 128,
1633 "num_resource": 16
1634 },
1635 {
1636 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN)",
1637 "type": 1944,
1638 "start_resource": 145,
1639 "num_resource": 7
1640 },
1641 {
1642 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN)",
1643 "type": 1945,
1644 "start_resource": 144,
1645 "num_resource": 8
1646 },
1647 {
1648 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN)",
1649 "type": 1946,
1650 "start_resource": 152,
1651 "num_resource": 8
1652 },
1653 {
1654 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN)",
1655 "type": 1947,
1656 "start_resource": 152,
1657 "num_resource": 8
1658 },
1659 {
1660 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN)",
1661 "type": 1948,
1662 "start_resource": 160,
1663 "num_resource": 64
1664 },
1665 {
1666 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN)",
1667 "type": 1949,
1668 "start_resource": 224,
1669 "num_resource": 64
1670 },
1671 {
1672 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN)",
1673 "type": 1955,
1674 "start_resource": 0,
1675 "num_resource": 16
1676 },
1677 {
1678 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN)",
1679 "type": 1956,
1680 "start_resource": 16,
1681 "num_resource": 8
1682 },
1683 {
1684 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN)",
1685 "type": 1957,
1686 "start_resource": 25,
1687 "num_resource": 0
1688 },
1689 {
1690 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN)",
1691 "type": 1958,
1692 "start_resource": 25,
1693 "num_resource": 1
1694 },
1695 {
1696 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN)",
1697 "type": 1959,
1698 "start_resource": 26,
1699 "num_resource": 8
1700 },
1701 {
1702 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN)",
1703 "type": 1960,
1704 "start_resource": 34,
1705 "num_resource": 8
1706 },
1707 {
1708 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN)",
1709 "type": 1961,
1710 "start_resource": 0,
1711 "num_resource": 16
1712 },
1713 {
1714 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN)",
1715 "type": 1962,
1716 "start_resource": 0,
1717 "num_resource": 16
1718 },
1719 {
1720 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN)",
1721 "type": 1963,
1722 "start_resource": 16,
1723 "num_resource": 1
1724 },
1725 {
1726 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN)",
1727 "type": 1964,
1728 "start_resource": 16,
1729 "num_resource": 16
1730 },
1731 {
1732 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN)",
1733 "type": 1965,
1734 "start_resource": 18,
1735 "num_resource": 0
1736 },
1737 {
1738 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN)",
1739 "type": 1966,
1740 "start_resource": 32,
1741 "num_resource": 8
1742 },
1743 {
1744 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN)",
1745 "type": 1967,
1746 "start_resource": 19,
1747 "num_resource": 0
1748 },
1749 {
1750 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN)",
1751 "type": 1968,
1752 "start_resource": 32,
1753 "num_resource": 8
1754 },
1755 {
1756 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN)",
1757 "type": 1969,
1758 "start_resource": 19,
1759 "num_resource": 1
1760 },
1761 {
1762 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN)",
1763 "type": 1970,
1764 "start_resource": 40,
1765 "num_resource": 8
1766 },
1767 {
1768 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN)",
1769 "type": 1971,
1770 "start_resource": 20,
1771 "num_resource": 1
1772 },
1773 {
1774 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN)",
1775 "type": 1972,
1776 "start_resource": 40,
1777 "num_resource": 8
1778 },
1779 {
1780 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN)",
1781 "type": 1973,
1782 "start_resource": 21,
1783 "num_resource": 4
1784 },
1785 {
1786 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN)",
1787 "type": 1974,
1788 "start_resource": 48,
1789 "num_resource": 64
1790 },
1791 {
1792 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN)",
1793 "type": 1975,
1794 "start_resource": 25,
1795 "num_resource": 4
1796 },
1797 {
1798 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_PKTDMA_0, RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN)",
1799 "type": 1976,
1800 "start_resource": 112,
1801 "num_resource": 64
1802 },
1803 {
1804 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_RINGACC_0, RESASG_SUBTYPE_RA_ERROR_OES)",
1805 "type": 2112,
1806 "start_resource": 0,
1807 "num_resource": 1
1808 },
1809 {
1810 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_RINGACC_0, RESASG_SUBTYPE_RA_VIRTID)",
1811 "type": 2122,
1812 "start_resource": 0,
1813 "num_resource": 4096
1814 },
1815 {
1816 "name": "RESASG_UTYPE(AM64X_DEV_DMASS0_RINGACC_0, RESASG_SUBTYPE_RA_GENERIC_IPC)",
1817 "type": 2124,
1818 "start_resource": 20,
1819 "num_resource": 12
1820 }
1821 ],
1822 "constraints": [
1823 {
1824 "max_resource_entries": 144
1825 }
1826 ]
1827 }
1828 }
1829 }
1830 }