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113 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
114 <li class="toctree-l4"><a class="reference internal" href="#processor-boot-api-description">Processor Boot API Description</a></li>
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175 <div class="section" id="processor-boot-management-tisci-description">
176 <h1>Processor Boot Management TISCI Description<a class="headerlink" href="#processor-boot-management-tisci-description" title="Permalink to this headline">¶</a></h1>
177 <div class="section" id="introduction">
178 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
179 <p>This chapter provides information about the messaging APIs for the processor
180 boot control. APIs are divided into the following two sets:</p>
181 <ul class="simple">
182 <li>Book keeping APIs - Meant to control access to allow a reasonable usage
183 scenario of processors.</li>
184 <li>Processor Control APIs - Meant to be the actual Processor Core controls.</li>
185 </ul>
186 <p>Book Keeping APIs:</p>
187 <table border="1" class="docutils">
188 <colgroup>
189 <col width="22%" />
190 <col width="78%" />
191 </colgroup>
192 <thead valign="bottom">
193 <tr class="row-odd"><th class="head">TISCI Message ID</th>
194 <th class="head">Message Name</th>
195 </tr>
196 </thead>
197 <tbody valign="top">
198 <tr class="row-even"><td>0xC000</td>
199 <td><a class="reference internal" href="#proc-boot-request-processor"><span class="std std-ref">TISCI_MSG_PROC_REQUEST</span></a>.</td>
200 </tr>
201 <tr class="row-odd"><td>0xC001</td>
202 <td><a class="reference internal" href="#proc-boot-release-processor"><span class="std std-ref">TISCI_MSG_PROC_RELEASE</span></a>.</td>
203 </tr>
204 <tr class="row-even"><td>0xC005</td>
205 <td><a class="reference internal" href="#proc-boot-handover-processor"><span class="std std-ref">TISCI_MSG_PROC_HANDOVER</span></a>.</td>
206 </tr>
207 </tbody>
208 </table>
209 <p>Processor Control APIs:</p>
210 <table border="1" class="docutils">
211 <colgroup>
212 <col width="17%" />
213 <col width="83%" />
214 </colgroup>
215 <thead valign="bottom">
216 <tr class="row-odd"><th class="head">TISCI Message ID</th>
217 <th class="head">Message Name</th>
218 </tr>
219 </thead>
220 <tbody valign="top">
221 <tr class="row-even"><td>0xC100</td>
222 <td><a class="reference internal" href="#proc-boot-set-processor-configuration"><span class="std std-ref">TISCI_MSG_PROC_SET_CONFIG</span></a></td>
223 </tr>
224 <tr class="row-odd"><td>0xC101</td>
225 <td><a class="reference internal" href="#proc-boot-set-processor-control"><span class="std std-ref">TISCI_MSG_PROC_SET_CONTROL</span></a></td>
226 </tr>
227 <tr class="row-even"><td>0xC120</td>
228 <td><a class="reference internal" href="#proc-boot-authenticate-image-and-configure-processor"><span class="std std-ref">TISCI_MSG_PROC_AUTH_BOOT</span></a></td>
229 </tr>
230 <tr class="row-odd"><td>0xC400</td>
231 <td><a class="reference internal" href="#proc-boot-get-processor-status"><span class="std std-ref">TISCI_MSG_PROC_GET_STATUS</span></a></td>
232 </tr>
233 <tr class="row-even"><td>0xC401</td>
234 <td><a class="reference internal" href="#proc-boot-wait-processor-status"><span class="std std-ref">TISCI_MSG_PROC_WAIT_STATUS</span></a></td>
235 </tr>
236 </tbody>
237 </table>
238 <p>The APIs use the overall concepts explained in the following sections.</p>
239 <div class="section" id="id-definition">
240 <h3>ID definition<a class="headerlink" href="#id-definition" title="Permalink to this headline">¶</a></h3>
241 <p>To help identify the various entities invovled, the following IDs are involved:</p>
242 <ul class="simple">
243 <li>HOST_ID is the concept of identifying processing entities (SoC specific)</li>
244 <li>PROC_ID is the specific hardware processor instance involved (SoC specific)</li>
245 </ul>
246 </div>
247 <div class="section" id="access-control-definition">
248 <h3>Access control definition<a class="headerlink" href="#access-control-definition" title="Permalink to this headline">¶</a></h3>
249 <p>Access control is enforced via the Book keeping APIs. The basic definition of access is as follows:</p>
250 <ul class="simple">
251 <li>We identify a requester (just like rest of TISCI) using Host ID (or plain Host).</li>
252 <li>By default, we permit all processors to be controlled by any other Host (no policing).</li>
253 <li>Board configuration provides: per PROC_ID, a limited list of “permitted host IDs”
254 which are permitted to control a processor. BUT with the following conditions:<ul>
255 <li>Only one host can control a processor at a time</li>
256 <li>A host(with control) can hand over control of a processor to another host
257 in the permitted list.</li>
258 <li>“recovery master” host id is identified in board cfg and this host can
259 override the ownership already established.</li>
260 </ul>
261 </li>
262 </ul>
263 <p>In addition, ONLY a secure host can request for an authenticated image access.</p>
264 <p>API access control will be as follows:</p>
265 <ul class="simple">
266 <li>request_processor: Only one host can get control from access list. However,
267 “recovery master” host can override previously allocated master.</li>
268 <li>handover_processor: Only the host with current control of the processor.</li>
269 <li>release_processor: Only the host with current control of the processor.</li>
270 <li>set_processor_config: Only the host with current control of the processor.</li>
271 <li>get_processor_config: Any host within the access control list.</li>
272 <li>set_processor_control: Only the host with current control of the processor.</li>
273 <li>get_processor_control: Any host within the access control list.</li>
274 <li>authenticate_and_start_image: Only a <em>secure</em> host with current
275 control of the processor.</li>
276 <li>set_processor_suspend_ready: Only the host with current control of
277 processor can report that the processor is ready to suspend</li>
278 <li>get_processor_wake_reason: Any host within the access control list.</li>
279 </ul>
280 </div>
281 <div class="section" id="sequencing-of-apis">
282 <h3>Sequencing of APIs<a class="headerlink" href="#sequencing-of-apis" title="Permalink to this headline">¶</a></h3>
283 <p>The boot APIs must be used in correct sequence with the device and clock APIs to
284 be operational. This sequence would be specific to the processor involved.</p>
285 <p>Rationale: by encoding the sequence of processor boot along with boot
286 configuration API will complicate management of processors, since the
287 operational requirements are extremely varied. Some processors need the boot
288 configuration done, clocked, and specific MMU/RAT configuration be done prior to
289 be released from reset. Many of the operations may require interaction with
290 specific processor internals that is hard to make generic and usecase
291 independent.</p>
292 </div>
293 <div class="section" id="example-usage-of-apis">
294 <h3>Example usage of APIs<a class="headerlink" href="#example-usage-of-apis" title="Permalink to this headline">¶</a></h3>
295 <p>Example 1: Boot a processor from one core and let it self manage:</p>
296 <ol class="arabic simple">
297 <li>Boot host: (optionally) PM apis to control clock and hold processor in
298 reset. This might be necessary for some processors to get the boot
299 vector registers to be accessible in the first place.</li>
300 <li>Boot host: request_processor</li>
301 <li>Boot host: set_processor_config -> set bootvector</li>
302 <li>Alternatively call authenticate and start image API.</li>
303 <li>Boot host: handover_processor -> give control to ‘processor host’</li>
304 <li>Boot host: PM apis to control clock and release processor from reset.
305 ‘processor host’ gets active. It is probably better to release the processor
306 from reset after handover, in case the ‘processor host’ tries to do
307 additional operations. however this depends on usecase - use a sane
308 judgement as to how to sequence the APIs.</li>
309 <li>Processor host: (continues to boot and do other TISCI APIs permitted)</li>
310 <li>Processor host: set_processor_suspend_ready -> ready to suspend</li>
311 <li>Processor WFI Wakeup:</li>
312 <li>Processor host: get_processor_wake_reason -> get reason for wakeup.
313 …. until all operations are complete…</li>
314 <li>Processor host: set_processor_suspend_ready -> state it is going down</li>
315 <li>Processor host: release_processor -> Mark no longer required</li>
316 <li>Processor WFI (NOTE: a processor cannot switch off it’s own clocks -> so
317 in case of a self managed processor shutdown sequence, it will need
318 System firmware to help do the last stages of operation - typically
319 this will involve either shutdown OR reset sequence).</li>
320 </ol>
321 <p>Example 2: Boot a processor from one core and recover from another core:</p>
322 <ol class="arabic simple">
323 <li>Boot host: request_processor</li>
324 <li>Boot host: set_processor_config -> set bootvector</li>
325 <li>Boot host: handover_processor -> give control to ‘processor host’</li>
326 <li>Boot host: PM apis to control clock and release processor boot host dies</li>
327 <li>Recovery Host: request_processor</li>
328 <li>Recovery Host: set_processor_config -> force power off</li>
329 <li>Recovery Host: PM apis to control clock and force power off of processor</li>
330 <li>Recovery Host: Additional cleanup API calls …. Restoration sequence….</li>
331 </ol>
332 </div>
333 </div>
334 <div class="section" id="processor-boot-api-description">
335 <h2>Processor Boot API Description<a class="headerlink" href="#processor-boot-api-description" title="Permalink to this headline">¶</a></h2>
336 <p>This Section goes into details on the various APIs involved for processor control</p>
337 <div class="admonition note">
338 <p class="first admonition-title">Note</p>
339 <p class="last">Reference <a class="reference internal" href="../../5_soc_doc/index.html#pub-soc-family-doc"><span class="std std-ref">Chapter 5: SoC Family Specific Documentation</span></a> to see Host IDs and Processor IDs for
340 your SoC.</p>
341 </div>
342 <div class="section" id="book-keeping-apis">
343 <h3>Book Keeping APIs<a class="headerlink" href="#book-keeping-apis" title="Permalink to this headline">¶</a></h3>
344 <p>These are the top level APIs that provide access control knobs for
345 <a class="reference internal" href="#proc-boot-processor-control-apis"><span class="std std-ref">processor operation APIs</span></a> to be valid.</p>
346 <div class="section" id="tisci-msg-proc-request-request-processor">
347 <span id="proc-boot-request-processor"></span><h4>TISCI_MSG_PROC_REQUEST - Request Processor<a class="headerlink" href="#tisci-msg-proc-request-request-processor" title="Permalink to this headline">¶</a></h4>
348 <p><strong>Usage</strong>:</p>
349 <table border="1" class="docutils">
350 <colgroup>
351 <col width="75%" />
352 <col width="25%" />
353 </colgroup>
354 <tbody valign="top">
355 <tr class="row-odd"><td><strong>Message Type</strong></td>
356 <td>Normal</td>
357 </tr>
358 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
359 <td>No</td>
360 </tr>
361 </tbody>
362 </table>
363 <p><strong>TISCI Message ID</strong></p>
364 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_REQUEST</span>          <span class="pre">(0xC000U)</span></code></p>
365 <p>Message to get a Processor</p>
366 </p>
367 <p><p><strong>struct tisci_msg_proc_request_req</strong></p>
368 <p>Request for physical processor control request</p>
369 <table border="1" class="docutils">
370 <colgroup>
371 <col width="9%" />
372 <col width="13%" />
373 <col width="78%" />
374 </colgroup>
375 <thead valign="bottom">
376 <tr class="row-odd"><th class="head">Parameter</th>
377 <th class="head">Type</th>
378 <th class="head">Description</th>
379 </tr>
380 </thead>
381 <tbody valign="top">
382 <tr class="row-even"><td>hdr</td>
383 <td>struct tisci_header</td>
384 <td>Generic TISCI message header.</td>
385 </tr>
386 <tr class="row-odd"><td>processor_id</td>
387 <td>u8</td>
388 <td>Specifies a Processor ID. See the SoC Family Specific Documentation Chapter of the TISCI User Guide for accepted values.</td>
389 </tr>
390 </tbody>
391 </table>
392 <p>Provides a means for either the “recovery master” host or another host
393 in the permitted access list to request for a physical processor control.</p>
394 </p>
395 <p><p><strong>struct tisci_msg_proc_request_resp</strong></p>
396 <p>Request for physical processor control response</p>
397 <table border="1" class="docutils">
398 <colgroup>
399 <col width="20%" />
400 <col width="32%" />
401 <col width="48%" />
402 </colgroup>
403 <thead valign="bottom">
404 <tr class="row-odd"><th class="head">Parameter</th>
405 <th class="head">Type</th>
406 <th class="head">Description</th>
407 </tr>
408 </thead>
409 <tbody valign="top">
410 <tr class="row-even"><td>hdr</td>
411 <td>struct tisci_header</td>
412 <td>Generic TISCI message header.</td>
413 </tr>
414 </tbody>
415 </table>
416 <p>Although this message is essentially empty and contains only a header
417 a full data structure is created for consistency in implementation.
418 ACK response: The processor access is permitted for the host if
419 processor is un-claimed AND host is permitted to control the
420 processor OR if the host is the recovery master.
421 NAK response: The processor access is not permitted.</p>
422 </p>
423 </div>
424 <div class="section" id="tisci-msg-proc-release-release-processor">
425 <span id="proc-boot-release-processor"></span><h4>TISCI_MSG_PROC_RELEASE - Release Processor<a class="headerlink" href="#tisci-msg-proc-release-release-processor" title="Permalink to this headline">¶</a></h4>
426 <p><strong>Usage</strong>:</p>
427 <table border="1" class="docutils">
428 <colgroup>
429 <col width="75%" />
430 <col width="25%" />
431 </colgroup>
432 <tbody valign="top">
433 <tr class="row-odd"><td><strong>Message Type</strong></td>
434 <td>Normal</td>
435 </tr>
436 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
437 <td>No</td>
438 </tr>
439 </tbody>
440 </table>
441 <p><strong>TISCI Message ID</strong></p>
442 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_RELEASE</span>          <span class="pre">(0xC001U)</span></code></p>
443 <p>Message to release a Processor</p>
444 </p>
445 <p><p><strong>struct tisci_msg_proc_release_req</strong></p>
446 <p>Release physical processor control request</p>
447 <table border="1" class="docutils">
448 <colgroup>
449 <col width="21%" />
450 <col width="32%" />
451 <col width="47%" />
452 </colgroup>
453 <thead valign="bottom">
454 <tr class="row-odd"><th class="head">Parameter</th>
455 <th class="head">Type</th>
456 <th class="head">Description</th>
457 </tr>
458 </thead>
459 <tbody valign="top">
460 <tr class="row-even"><td>hdr</td>
461 <td>struct tisci_header</td>
462 <td>Generic TISCI message header.</td>
463 </tr>
464 <tr class="row-odd"><td>processor_id</td>
465 <td>u8</td>
466 <td>ID of processor to release.</td>
467 </tr>
468 </tbody>
469 </table>
470 <p>Provides a means for the host with current control to relinquish a
471 physical processor control.</p>
472 </p>
473 <p><p><strong>struct tisci_msg_proc_release_resp</strong></p>
474 <p>Release physical processor control response</p>
475 <table border="1" class="docutils">
476 <colgroup>
477 <col width="20%" />
478 <col width="32%" />
479 <col width="48%" />
480 </colgroup>
481 <thead valign="bottom">
482 <tr class="row-odd"><th class="head">Parameter</th>
483 <th class="head">Type</th>
484 <th class="head">Description</th>
485 </tr>
486 </thead>
487 <tbody valign="top">
488 <tr class="row-even"><td>hdr</td>
489 <td>struct tisci_header</td>
490 <td>Generic TISCI message header.</td>
491 </tr>
492 </tbody>
493 </table>
494 <p>Although this message is essentially empty and contains only a header
495 a full data structure is created for consistency in implementation.
496 ACK Response: The host had control over the processor and is
497 confirmed to be released to “free pool”.
498 NAK Response: The processor access is not permitted.</p>
499 </p>
500 </div>
501 <div class="section" id="tisci-msg-proc-handover-handover-processor">
502 <span id="proc-boot-handover-processor"></span><h4>TISCI_MSG_PROC_HANDOVER - Handover Processor<a class="headerlink" href="#tisci-msg-proc-handover-handover-processor" title="Permalink to this headline">¶</a></h4>
503 <p><strong>Usage</strong>:</p>
504 <table border="1" class="docutils">
505 <colgroup>
506 <col width="75%" />
507 <col width="25%" />
508 </colgroup>
509 <tbody valign="top">
510 <tr class="row-odd"><td><strong>Message Type</strong></td>
511 <td>Normal</td>
512 </tr>
513 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
514 <td>No</td>
515 </tr>
516 </tbody>
517 </table>
518 <p><strong>TISCI Message ID</strong></p>
519 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_HANDOVER</span>          <span class="pre">(0xC005U)</span></code></p>
520 <p>Message to handover a Processor</p>
521 </p>
522 <p><p><strong>struct tisci_msg_proc_handover_req</strong></p>
523 <p>Request to handover control of a processor to another host if permitted.</p>
524 <table border="1" class="docutils">
525 <colgroup>
526 <col width="17%" />
527 <col width="25%" />
528 <col width="58%" />
529 </colgroup>
530 <thead valign="bottom">
531 <tr class="row-odd"><th class="head">Parameter</th>
532 <th class="head">Type</th>
533 <th class="head">Description</th>
534 </tr>
535 </thead>
536 <tbody valign="top">
537 <tr class="row-even"><td>hdr</td>
538 <td>struct tisci_header</td>
539 <td>Generic TISCI message header.</td>
540 </tr>
541 <tr class="row-odd"><td>processor_id</td>
542 <td>u8</td>
543 <td>Specifies a Processor ID.</td>
544 </tr>
545 <tr class="row-even"><td>host_id</td>
546 <td>u8</td>
547 <td>Specifies the new host to hand over control to.</td>
548 </tr>
549 </tbody>
550 </table>
551 <p>Provides a means for the host with current control to relinquish a
552 physical processor control to another host in the permitted list.</p>
553 </p>
554 <p><p><strong>struct tisci_msg_proc_handover_resp</strong></p>
555 <p>Response to handover of control of a processor to another host if permitted.</p>
556 <table border="1" class="docutils">
557 <colgroup>
558 <col width="20%" />
559 <col width="32%" />
560 <col width="48%" />
561 </colgroup>
562 <thead valign="bottom">
563 <tr class="row-odd"><th class="head">Parameter</th>
564 <th class="head">Type</th>
565 <th class="head">Description</th>
566 </tr>
567 </thead>
568 <tbody valign="top">
569 <tr class="row-even"><td>hdr</td>
570 <td>struct tisci_header</td>
571 <td>Generic TISCI message header.</td>
572 </tr>
573 </tbody>
574 </table>
575 <p>Although this message is essentially empty and contains only a header
576 a full data structure is created for consistency in implementation.
577 ACK Response: The host had control over the processor and is
578 confirmed to be released to “free pool”.
579 NAK Response: The processor access is not permitted.</p>
580 </p>
581 </div>
582 </div>
583 <div class="section" id="processor-control-apis">
584 <span id="proc-boot-processor-control-apis"></span><h3>Processor Control APIs<a class="headerlink" href="#processor-control-apis" title="Permalink to this headline">¶</a></h3>
585 <p>These are granular control APIs for control of the processor state themselves.
586 These APIs need to be used in conjunction with standard Power Management APIs.</p>
587 <div class="admonition note">
588 <p class="first admonition-title">Note</p>
589 <p class="last">Not all APIs are supported for all processors. See <a class="reference internal" href="#proc-boot-flags"><span class="std std-ref">Processor Specific Flags</span></a>
590 for core specific flags (implies the applicable APIs are valid for that type of
591 core).</p>
592 </div>
593 <div class="section" id="tisci-msg-proc-set-config-set-processor-configuration">
594 <span id="proc-boot-set-processor-configuration"></span><h4>TISCI_MSG_PROC_SET_CONFIG - Set Processor Configuration<a class="headerlink" href="#tisci-msg-proc-set-config-set-processor-configuration" title="Permalink to this headline">¶</a></h4>
595 <p><strong>Purpose</strong>: Provides a means for the host with current control to do the base
596 configuration of the processor.</p>
597 <p><strong>Usage</strong>:</p>
598 <table border="1" class="docutils">
599 <colgroup>
600 <col width="75%" />
601 <col width="25%" />
602 </colgroup>
603 <tbody valign="top">
604 <tr class="row-odd"><td><strong>Message Type</strong></td>
605 <td>Normal</td>
606 </tr>
607 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
608 <td>No</td>
609 </tr>
610 </tbody>
611 </table>
612 <p><strong>TISCI Message ID</strong></p>
613 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_SET_CONFIG</span>          <span class="pre">(0xC100U)</span></code></p>
614 <p>Message to Set the processor configuration</p>
615 </p>
616 <p><p><strong>struct tisci_msg_proc_set_config_req</strong></p>
617 <p>Processor Boot Configuration</p>
618 <table border="1" class="docutils">
619 <colgroup>
620 <col width="14%" />
621 <col width="13%" />
622 <col width="73%" />
623 </colgroup>
624 <thead valign="bottom">
625 <tr class="row-odd"><th class="head">Parameter</th>
626 <th class="head">Type</th>
627 <th class="head">Description</th>
628 </tr>
629 </thead>
630 <tbody valign="top">
631 <tr class="row-even"><td>hdr</td>
632 <td>struct tisci_header</td>
633 <td>Message header</td>
634 </tr>
635 <tr class="row-odd"><td>processor_id</td>
636 <td>u8</td>
637 <td>ID of processor</td>
638 </tr>
639 <tr class="row-even"><td>bootvector_lo</td>
640 <td>u32</td>
641 <td>Lower 32bit (Little Endian) of boot vector</td>
642 </tr>
643 <tr class="row-odd"><td>bootvector_hi</td>
644 <td>u32</td>
645 <td>Higher 32bit (Little Endian) of boot vector</td>
646 </tr>
647 <tr class="row-even"><td>config_flags_1_set</td>
648 <td>u32</td>
649 <td>Optional Processor specific Config Flags to set. Setting a bit here implies required bit has to be set to 1.</td>
650 </tr>
651 <tr class="row-odd"><td>config_flags_1_clear</td>
652 <td>u32</td>
653 <td>Optional Processor specific Config Flags to clear. Setting a bit here implies required bit has to be cleared to 0.</td>
654 </tr>
655 </tbody>
656 </table>
657 </p>
658 <div class="admonition note">
659 <p class="first admonition-title">Note</p>
660 <p class="last">Boot vector address and config are processor specific configurations. This
661 may be done in separate invocations as required in processor specific startup
662 sequence.</p>
663 </div>
664 <p><p><strong>struct tisci_msg_proc_set_config_resp</strong></p>
665 <p>Response to Processor Boot Configuration message.</p>
666 <table border="1" class="docutils">
667 <colgroup>
668 <col width="20%" />
669 <col width="32%" />
670 <col width="48%" />
671 </colgroup>
672 <thead valign="bottom">
673 <tr class="row-odd"><th class="head">Parameter</th>
674 <th class="head">Type</th>
675 <th class="head">Description</th>
676 </tr>
677 </thead>
678 <tbody valign="top">
679 <tr class="row-even"><td>hdr</td>
680 <td>struct tisci_header</td>
681 <td>Generic TISCI message header.</td>
682 </tr>
683 </tbody>
684 </table>
685 <p>Although this message is essentially empty and contains only a header
686 a full data structure is created for consistency in implementation.
687 ACK Response: The host had control over the processor and requested
688 operation is successful
689 NAK Response: The processor access is not permitted or the operation failed.</p>
690 </p>
691 <div class="admonition attention">
692 <p class="first admonition-title">Attention</p>
693 <p class="last">Reason for failure is NOT provided to prevent security attacks by
694 scan. If permitted, System firmware logs shall provide relevant failure
695 information.</p>
696 </div>
697 </div>
698 <div class="section" id="tisci-msg-proc-set-control-set-processor-control-flags">
699 <span id="proc-boot-set-processor-control"></span><h4>TISCI_MSG_PROC_SET_CONTROL - Set Processor Control Flags<a class="headerlink" href="#tisci-msg-proc-set-control-set-processor-control-flags" title="Permalink to this headline">¶</a></h4>
700 <p><strong>Purpose</strong>: Provides a means for the host with current control to setup limited
701 control flags in specific cases.</p>
702 <p><strong>Usage</strong>:</p>
703 <table border="1" class="docutils">
704 <colgroup>
705 <col width="75%" />
706 <col width="25%" />
707 </colgroup>
708 <tbody valign="top">
709 <tr class="row-odd"><td><strong>Message Type</strong></td>
710 <td>Normal</td>
711 </tr>
712 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
713 <td>No</td>
714 </tr>
715 </tbody>
716 </table>
717 <p><strong>TISCI Message ID</strong></p>
718 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_SET_CONTROL</span>          <span class="pre">(0xC101U)</span></code></p>
719 <p>Message to Set the processor control</p>
720 </p>
721 <p><p><strong>struct tisci_msg_proc_set_control_req</strong></p>
722 <p>Optional processor specific message for sequence control</p>
723 <table border="1" class="docutils">
724 <colgroup>
725 <col width="14%" />
726 <col width="13%" />
727 <col width="73%" />
728 </colgroup>
729 <thead valign="bottom">
730 <tr class="row-odd"><th class="head">Parameter</th>
731 <th class="head">Type</th>
732 <th class="head">Description</th>
733 </tr>
734 </thead>
735 <tbody valign="top">
736 <tr class="row-even"><td>hdr</td>
737 <td>struct tisci_header</td>
738 <td>Message header</td>
739 </tr>
740 <tr class="row-odd"><td>processor_id</td>
741 <td>u8</td>
742 <td>ID of processor</td>
743 </tr>
744 <tr class="row-even"><td>control_flags_1_set</td>
745 <td>u32</td>
746 <td>Optional Processor specific Control Flags to set. Setting a bit here implies required bit has to be set to 1.</td>
747 </tr>
748 <tr class="row-odd"><td>control_flags_1_clear</td>
749 <td>u32</td>
750 <td>Optional Processor specific Control Flags to clear. Setting a bit here implies required bit has to be cleared to 0.</td>
751 </tr>
752 </tbody>
753 </table>
754 </p>
755 <p><p><strong>struct tisci_msg_proc_set_control_resp</strong></p>
756 <p>Response to optional processor specific message for sequence control</p>
757 <table border="1" class="docutils">
758 <colgroup>
759 <col width="20%" />
760 <col width="32%" />
761 <col width="48%" />
762 </colgroup>
763 <thead valign="bottom">
764 <tr class="row-odd"><th class="head">Parameter</th>
765 <th class="head">Type</th>
766 <th class="head">Description</th>
767 </tr>
768 </thead>
769 <tbody valign="top">
770 <tr class="row-even"><td>hdr</td>
771 <td>struct tisci_header</td>
772 <td>Generic TISCI message header.</td>
773 </tr>
774 </tbody>
775 </table>
776 <p>Although this message is essentially empty and contains only a header
777 a full data structure is created for consistency in implementation.
778 ACK Response: The host had control over the processor and requested
779 operation is successful
780 NAK Response: The processor access is not permitted or the operation failed.</p>
781 </p>
782 <div class="admonition attention">
783 <p class="first admonition-title">Attention</p>
784 <p class="last">Reason for failure is NOT provided to prevent security attacks by
785 scan. If permitted, System firmware logs shall provide relevant failure
786 information.</p>
787 </div>
788 </div>
789 <div class="section" id="tisci-msg-proc-auth-boot-authenticate-image-and-configure-processor">
790 <span id="proc-boot-authenticate-image-and-configure-processor"></span><h4>TISCI_MSG_PROC_AUTH_BOOT - Authenticate Image and Configure Processor<a class="headerlink" href="#tisci-msg-proc-auth-boot-authenticate-image-and-configure-processor" title="Permalink to this headline">¶</a></h4>
791 <p><strong>Purpose</strong>: Provides a means for the host with current control to do the following:</p>
792 <ul class="simple">
793 <li>Authenticate and load a binary using the certificate provided information</li>
794 <li>Use certificate information also to setup critical processor specific
795 flags which is similar to
796 <a class="reference internal" href="#proc-boot-set-processor-configuration"><span class="std std-ref">Set Processor Configuration</span></a>.</li>
797 </ul>
798 <p><strong>Usage</strong>:</p>
799 <table border="1" class="docutils">
800 <colgroup>
801 <col width="75%" />
802 <col width="25%" />
803 </colgroup>
804 <tbody valign="top">
805 <tr class="row-odd"><td><strong>Message Type</strong></td>
806 <td>Normal</td>
807 </tr>
808 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
809 <td>No</td>
810 </tr>
811 </tbody>
812 </table>
813 <p><strong>TISCI Message ID</strong></p>
814 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_AUTH_BOOT</span>          <span class="pre">(0xC120U)</span></code></p>
815 <p>Message to do authenticated boot configuration of a processor</p>
816 </p>
817 <p><p><strong>struct tisci_msg_proc_auth_boot_req</strong></p>
818 <p>Authenticate and start image</p>
819 <table border="1" class="docutils">
820 <colgroup>
821 <col width="27%" />
822 <col width="23%" />
823 <col width="50%" />
824 </colgroup>
825 <thead valign="bottom">
826 <tr class="row-odd"><th class="head">Parameter</th>
827 <th class="head">Type</th>
828 <th class="head">Description</th>
829 </tr>
830 </thead>
831 <tbody valign="top">
832 <tr class="row-even"><td>hdr</td>
833 <td>struct tisci_header</td>
834 <td>Message header</td>
835 </tr>
836 <tr class="row-odd"><td>certificate_address_lo</td>
837 <td>u32</td>
838 <td>Lower 32bit (Little Endian) of certificate</td>
839 </tr>
840 <tr class="row-even"><td>certificate_address_hi</td>
841 <td>u32</td>
842 <td>Higher 32bit (Little Endian) of certificate</td>
843 </tr>
844 </tbody>
845 </table>
846 </p>
847 <div class="admonition attention">
848 <p class="first admonition-title">Attention</p>
849 <ul class="last simple">
850 <li>The certificate itself shall contain relevant information about the
851 processor flags and configuration information.</li>
852 <li>ONLY secure hosts are permitted to invoke this API in addition to
853 being part of the access control list.</li>
854 <li>See Hosts description for the corresponding SoC to identify which hosts
855 are secure and which are not.</li>
856 </ul>
857 </div>
858 <div class="admonition attention">
859 <p class="first admonition-title">Attention</p>
860 <p class="last">Please see <a class="reference internal" href="sec_cert_format.html"><span class="doc">Security X509 Certificate Documentation</span></a> for certificate format.</p>
861 </div>
862 <p><p><strong>struct tisci_msg_proc_auth_boot_resp</strong></p>
863 <p>Response to authenticate and start image request</p>
864 <table border="1" class="docutils">
865 <colgroup>
866 <col width="23%" />
867 <col width="27%" />
868 <col width="50%" />
869 </colgroup>
870 <thead valign="bottom">
871 <tr class="row-odd"><th class="head">Parameter</th>
872 <th class="head">Type</th>
873 <th class="head">Description</th>
874 </tr>
875 </thead>
876 <tbody valign="top">
877 <tr class="row-even"><td>hdr</td>
878 <td>struct tisci_header</td>
879 <td>Generic TISCI message header.</td>
880 </tr>
881 <tr class="row-odd"><td>image_address_lo</td>
882 <td>u32</td>
883 <td>Lower 32bit (Little Endian) of image</td>
884 </tr>
885 <tr class="row-even"><td>image_address_hi</td>
886 <td>u32</td>
887 <td>Higher 32bit (Little Endian) of image</td>
888 </tr>
889 <tr class="row-odd"><td>image_size</td>
890 <td>u32</td>
891 <td>Size of the binary</td>
892 </tr>
893 </tbody>
894 </table>
895 <p>ACK Response: The host had control over the processor and requested
896 operation is successful
897 NAK Response: The processor access is not permitted or the operation failed.
898 IMPORTANT: Reason for failure is NOT provided to prevent security attacks
899 by scan. If permitted, System firmware logs shall provide relevant failure
900 information.</p>
901 </p>
902 <div class="admonition attention">
903 <p class="first admonition-title">Attention</p>
904 <p class="last">Reason for failure is NOT provided to prevent security attacks by
905 scan. If permitted, System firmware logs shall provide relevant failure
906 information.</p>
907 </div>
908 </div>
909 <div class="section" id="tisci-msg-proc-get-status-get-processor-status">
910 <span id="proc-boot-get-processor-status"></span><h4>TISCI_MSG_PROC_GET_STATUS - Get Processor Status<a class="headerlink" href="#tisci-msg-proc-get-status-get-processor-status" title="Permalink to this headline">¶</a></h4>
911 <p><strong>Purpose</strong>: Provides a means for hosts in the permitted list to get the status
912 of a physical processor. This is required for the hosts to sequence events in
913 the correct order</p>
914 <p><strong>Usage</strong>:</p>
915 <table border="1" class="docutils">
916 <colgroup>
917 <col width="75%" />
918 <col width="25%" />
919 </colgroup>
920 <tbody valign="top">
921 <tr class="row-odd"><td><strong>Message Type</strong></td>
922 <td>Normal</td>
923 </tr>
924 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
925 <td>No</td>
926 </tr>
927 </tbody>
928 </table>
929 <p><strong>TISCI Message ID</strong></p>
930 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_GET_STATUS</span>          <span class="pre">(0xC400U)</span></code></p>
931 <p>Message to Get the processor status</p>
932 </p>
933 <p><p><strong>struct tisci_msg_proc_get_status_req</strong></p>
934 <p>Processor Status request</p>
935 <table border="1" class="docutils">
936 <colgroup>
937 <col width="27%" />
938 <col width="40%" />
939 <col width="33%" />
940 </colgroup>
941 <thead valign="bottom">
942 <tr class="row-odd"><th class="head">Parameter</th>
943 <th class="head">Type</th>
944 <th class="head">Description</th>
945 </tr>
946 </thead>
947 <tbody valign="top">
948 <tr class="row-even"><td>hdr</td>
949 <td>struct tisci_header</td>
950 <td>Message header</td>
951 </tr>
952 <tr class="row-odd"><td>processor_id</td>
953 <td>u8</td>
954 <td>ID of processor</td>
955 </tr>
956 </tbody>
957 </table>
958 </p>
959 <p><p><strong>struct tisci_msg_proc_get_status_resp</strong></p>
960 <p>Processor Status Response</p>
961 <table border="1" class="docutils">
962 <colgroup>
963 <col width="20%" />
964 <col width="25%" />
965 <col width="55%" />
966 </colgroup>
967 <thead valign="bottom">
968 <tr class="row-odd"><th class="head">Parameter</th>
969 <th class="head">Type</th>
970 <th class="head">Description</th>
971 </tr>
972 </thead>
973 <tbody valign="top">
974 <tr class="row-even"><td>hdr</td>
975 <td>struct tisci_header</td>
976 <td>Message header</td>
977 </tr>
978 <tr class="row-odd"><td>processor_id</td>
979 <td>u8</td>
980 <td>ID of processor</td>
981 </tr>
982 <tr class="row-even"><td>bootvector_lo</td>
983 <td>u32</td>
984 <td>Lower 32bit (Little Endian) of boot vector</td>
985 </tr>
986 <tr class="row-odd"><td>bootvector_hi</td>
987 <td>u32</td>
988 <td>Higher 32bit (Little Endian) of boot vector</td>
989 </tr>
990 <tr class="row-even"><td>config_flags_1</td>
991 <td>u32</td>
992 <td>Optional Processor specific Config Flags set</td>
993 </tr>
994 <tr class="row-odd"><td>control_flags_1</td>
995 <td>u32</td>
996 <td>Optional Processor specific Control Flags set</td>
997 </tr>
998 <tr class="row-even"><td>status_flags_1</td>
999 <td>u32</td>
1000 <td>Optional Processor specific Status Flags set</td>
1001 </tr>
1002 </tbody>
1003 </table>
1004 <p>ACK Response: The host had control over the processor and requested
1005 operation is successful
1006 NAK Response: The processor access is not permitted or the operation failed.
1007 IMPORTANT: Reason for failure is NOT provided to prevent security attacks
1008 by scan. If permitted, System firmware logs shall provide relevant failure
1009 information.</p>
1010 </p>
1011 <div class="admonition attention">
1012 <p class="first admonition-title">Attention</p>
1013 <p class="last">Reason for failure is NOT provided to prevent security attacks by
1014 scan. If permitted, System firmware logs shall provide relevant failure
1015 information.</p>
1016 </div>
1017 </div>
1018 <div class="section" id="tisci-msg-proc-wait-status-wait-for-processor-status">
1019 <span id="proc-boot-wait-processor-status"></span><h4>TISCI_MSG_PROC_WAIT_STATUS - Wait for Processor Status<a class="headerlink" href="#tisci-msg-proc-wait-status-wait-for-processor-status" title="Permalink to this headline">¶</a></h4>
1020 <p><strong>Purpose</strong>: Provides a means for hosts in the permitted list to wait for the
1021 status of a physical processor.</p>
1022 <div class="admonition warning">
1023 <p class="first admonition-title">Warning</p>
1024 <p>This API that has impact on firmware performance and is typically
1025 only required for the hosts to sequence events in the correct order
1026 when executing from the processor itself. In short, avoid if possible.</p>
1027 <p class="last">The worst case delay could be upto:
1028 (register operations and code overheads) +
1029 num_wait_iterations(255) * delay_per_iteration_us(255) +
1030 delay_before_iteration_loop_start_us (255) =
1031 65.280 milli seconds + (register operations and code overheads)</p>
1032 </div>
1033 <p><strong>Usage</strong>:</p>
1034 <table border="1" class="docutils">
1035 <colgroup>
1036 <col width="75%" />
1037 <col width="25%" />
1038 </colgroup>
1039 <tbody valign="top">
1040 <tr class="row-odd"><td><strong>Message Type</strong></td>
1041 <td>Normal</td>
1042 </tr>
1043 <tr class="row-even"><td><strong>Secure Queue Only?</strong></td>
1044 <td>No</td>
1045 </tr>
1046 </tbody>
1047 </table>
1048 <p><strong>TISCI Message ID</strong></p>
1049 <p><p><code class="docutils literal"><span class="pre">TISCI_MSG_PROC_WAIT_STATUS</span>          <span class="pre">(0xC401U)</span></code></p>
1050 <p>Message to Wait for processor status</p>
1051 </p>
1052 <p><p><strong>struct tisci_msg_proc_status_wait_req</strong></p>
1053 <p>Processor Status Wait</p>
1054 <table border="1" class="docutils">
1055 <colgroup>
1056 <col width="10%" />
1057 <col width="6%" />
1058 <col width="84%" />
1059 </colgroup>
1060 <thead valign="bottom">
1061 <tr class="row-odd"><th class="head">Parameter</th>
1062 <th class="head">Type</th>
1063 <th class="head">Description</th>
1064 </tr>
1065 </thead>
1066 <tbody valign="top">
1067 <tr class="row-even"><td>hdr</td>
1068 <td>struct tisci_header</td>
1069 <td>Message header</td>
1070 </tr>
1071 <tr class="row-odd"><td>processor_id</td>
1072 <td>u8</td>
1073 <td>ID of processor</td>
1074 </tr>
1075 <tr class="row-even"><td>num_wait_iterations</td>
1076 <td>u8</td>
1077 <td>1-255, Total number of iterations we will check before we will timeout and give up</td>
1078 </tr>
1079 <tr class="row-odd"><td>num_match_iterations</td>
1080 <td>u8</td>
1081 <td>1-255, How many iterations should we have continued status to account for status bits glitching. This is to make sure that match occurs for consecutive checks. This implies that the worst case should consider that the stable time should at the worst be num_wait_iterations num_match_iterations to prevent timeout.</td>
1082 </tr>
1083 <tr class="row-even"><td>delay_per_iteration_us</td>
1084 <td>u8</td>
1085 <td>0-255, Specifies how long to wait (in micro seconds) between each status checks. This is the minimum duration, and overhead of register reads and checks are on top of this and can vary based on varied conditions.</td>
1086 </tr>
1087 <tr class="row-odd"><td>delay_before_iteration_loop_start_us</td>
1088 <td>u8</td>
1089 <td>0-255, Specifies how long to wait (in micro seconds) before the very first check in the first iteration of status check loop. This is the minimum duration, and overhead of register reads and checks are</td>
1090 </tr>
1091 <tr class="row-even"><td>status_flags_1_set_all_wait</td>
1092 <td>u32</td>
1093 <td>If non-zero, Specifies that all bits of the status matching this field requested MUST be ‘1’.</td>
1094 </tr>
1095 <tr class="row-odd"><td>status_flags_1_set_any_wait</td>
1096 <td>u32</td>
1097 <td>If non-zero, Specifies that at least one of the bits matching this field requested MUST be ‘1’.</td>
1098 </tr>
1099 <tr class="row-even"><td>status_flags_1_clr_all_wait</td>
1100 <td>u32</td>
1101 <td>If non-zero, Specifies that all bits of the status matching this field requested MUST be ‘0’.</td>
1102 </tr>
1103 <tr class="row-odd"><td>status_flags_1_clr_any_wait</td>
1104 <td>u32</td>
1105 <td>If non-zero, Specifies that at least one of the bits matching this field requested MUST be ‘0’.</td>
1106 </tr>
1107 </tbody>
1108 </table>
1109 </p>
1110 <p><p><strong>struct tisci_msg_proc_status_wait_resp</strong></p>
1111 <p>Processor Status Wait Response</p>
1112 <table border="1" class="docutils">
1113 <colgroup>
1114 <col width="20%" />
1115 <col width="32%" />
1116 <col width="48%" />
1117 </colgroup>
1118 <thead valign="bottom">
1119 <tr class="row-odd"><th class="head">Parameter</th>
1120 <th class="head">Type</th>
1121 <th class="head">Description</th>
1122 </tr>
1123 </thead>
1124 <tbody valign="top">
1125 <tr class="row-even"><td>hdr</td>
1126 <td>struct tisci_header</td>
1127 <td>Generic TISCI message header.</td>
1128 </tr>
1129 </tbody>
1130 </table>
1131 <p>Although this message is essentially empty and contains only a header
1132 a full data structure is created for consistency in implementation.
1133 ACK Response: The status requested was achieved within the constraints provided in request.
1134 NAK Response: The processor access is not permitted or operation failed or timedout.</p>
1135 </p>
1136 <div class="admonition warning">
1137 <p class="first admonition-title">Warning</p>
1138 <p>At least one of status_flags_1_set_all_wait, status_flags_1_set_any_wait,
1139 status_flags_1_clr_all_wait or status_flags_1_clr_any_wait must be
1140 requested.</p>
1141 <p class="last">Flags and sequences desired are very specific to processor and SoC involved. Please
1142 refer to appropriate documentation for accurate sequencing and status information.</p>
1143 </div>
1144 <div class="admonition note">
1145 <p class="first admonition-title">Note</p>
1146 <p>A trivial example for a hypothetical processor status wait could have the parameters as follows:</p>
1147 <div class="last highlight-bash"><div class="highlight"><pre><span></span><span class="c1"># No optional bits to be set</span>
1148 <span class="nv">status_flags_1_set_all_wait</span> <span class="o">=</span> <span class="m">0</span>
1150 <span class="c1"># Either WFI OR WFE to be set as 1</span>
1151 <span class="nv">status_flags_1_set_any_wait</span> <span class="o">=</span> WFI <span class="p">|</span> WFE
1153 <span class="c1"># CLK_STOP must be to be cleared</span>
1154 <span class="nv">status_flags_1_clr_all_wait</span> <span class="o">=</span> CLK_STOP
1156 <span class="c1"># No optional status bits to be cleared</span>
1157 <span class="nv">status_flags_1_clr_any_wait</span> <span class="o">=</span> <span class="m">0</span>
1159 <span class="c1"># Check status every ~2 us</span>
1160 <span class="nv">delay_per_iteration_us</span> <span class="o">=</span> <span class="m">2</span>
1162 <span class="c1"># Do not wait to start checks</span>
1163 <span class="nv">delay_before_iteration_loop_start_us</span> <span class="o">=</span> <span class="m">0</span>
1165 <span class="c1"># Check for 10 times before timing out</span>
1166 <span class="nv">num_wait_iterations</span> <span class="o">=</span> <span class="m">10</span>
1168 <span class="c1"># Must match at least for 2 consecutive iterations</span>
1169 <span class="nv">num_match_iterations</span> <span class="o">=</span> <span class="m">2</span>
1170 </pre></div>
1171 </div>
1172 </div>
1173 <div class="admonition attention">
1174 <p class="first admonition-title">Attention</p>
1175 <p class="last">Reason for failure is NOT provided to prevent security attacks by
1176 scan. If permitted, System firmware logs shall provide relevant failure
1177 information.</p>
1178 </div>
1179 </div>
1180 </div>
1181 <div class="section" id="generic-processor-flags">
1182 <span id="proc-boot-flags"></span><h3>Generic Processor Flags<a class="headerlink" href="#generic-processor-flags" title="Permalink to this headline">¶</a></h3>
1183 <ul class="simple">
1184 <li>config_flags_1 Field Reserved for Generic usage</li>
1185 </ul>
1186 <table border="1" class="docutils">
1187 <colgroup>
1188 <col width="17%" />
1189 <col width="10%" />
1190 <col width="73%" />
1191 </colgroup>
1192 <thead valign="bottom">
1193 <tr class="row-odd"><th class="head">Flag Name</th>
1194 <th class="head">Bit Offset</th>
1195 <th class="head">Description</th>
1196 </tr>
1197 </thead>
1198 <tbody valign="top">
1199 <tr class="row-even"><td>GEN_IGN_BOOTVECTOR</td>
1200 <td>28</td>
1201 <td>Valid only for <a class="reference internal" href="#proc-boot-set-processor-configuration"><span class="std std-ref">config_flags_1_clear</span></a>
1202 Flag indicating that SYSFW should not use the bootvector_lo and bootvector_hi fields
1203 in the tisci_msg_proc_set_config_req structure.</td>
1204 </tr>
1205 </tbody>
1206 </table>
1207 </div>
1208 <div class="section" id="processor-specific-flags">
1209 <h3>Processor Specific Flags<a class="headerlink" href="#processor-specific-flags" title="Permalink to this headline">¶</a></h3>
1210 <p>This section lists the flags that are specific to each processor types. These
1211 flags apply to the <a class="reference internal" href="#proc-boot-processor-control-apis"><span class="std std-ref">processor control APIs</span></a>.</p>
1212 <div class="admonition note">
1213 <p class="first admonition-title">Note</p>
1214 <p class="last">The System Firmware does not modify the silicon defaults unless the specific message
1215 to update the processor config/control flags is received.</p>
1216 </div>
1217 <div class="section" id="armv8">
1218 <h4>ARMV8<a class="headerlink" href="#armv8" title="Permalink to this headline">¶</a></h4>
1219 <ul class="simple">
1220 <li>config_flags_1 Fields</li>
1221 </ul>
1222 <table border="1" class="docutils">
1223 <colgroup>
1224 <col width="18%" />
1225 <col width="17%" />
1226 <col width="65%" />
1227 </colgroup>
1228 <thead valign="bottom">
1229 <tr class="row-odd"><th class="head">Flag Name</th>
1230 <th class="head">Bit Offset</th>
1231 <th class="head">Description</th>
1232 </tr>
1233 </thead>
1234 <tbody valign="top">
1235 <tr class="row-even"><td>DBG_EN</td>
1236 <td>0</td>
1237 <td>invasive Debug</td>
1238 </tr>
1239 <tr class="row-odd"><td>DBG_NIDEN</td>
1240 <td>1</td>
1241 <td>Non-invasive Debug</td>
1242 </tr>
1243 <tr class="row-even"><td>DBG_SPIDEN</td>
1244 <td>2</td>
1245 <td>Secure invasive Debug</td>
1246 </tr>
1247 <tr class="row-odd"><td>DBG_SPNIDEN</td>
1248 <td>3</td>
1249 <td>Secure Non-invasive Debug</td>
1250 </tr>
1251 <tr class="row-even"><td>ARCH32</td>
1252 <td>8</td>
1253 <td>32bit mode (if disabled, implies 64 bit mode)</td>
1254 </tr>
1255 </tbody>
1256 </table>
1257 <ul class="simple">
1258 <li>control_flags_1 Fields:</li>
1259 </ul>
1260 <table border="1" class="docutils">
1261 <colgroup>
1262 <col width="13%" />
1263 <col width="13%" />
1264 <col width="74%" />
1265 </colgroup>
1266 <thead valign="bottom">
1267 <tr class="row-odd"><th class="head">Flag Name</th>
1268 <th class="head">Bit Offset</th>
1269 <th class="head">Description</th>
1270 </tr>
1271 </thead>
1272 <tbody valign="top">
1273 <tr class="row-even"><td>ACINACTM</td>
1274 <td>0</td>
1275 <td>Snoop coherency interface state</td>
1276 </tr>
1277 <tr class="row-odd"><td>AINACTS</td>
1278 <td>1</td>
1279 <td>ACP interface state</td>
1280 </tr>
1281 <tr class="row-even"><td>L2FLUSHREQ</td>
1282 <td>8</td>
1283 <td>SoC level L2 Flush Request - See L2FLUSH_DONE status for completion</td>
1284 </tr>
1285 </tbody>
1286 </table>
1287 <div class="admonition note">
1288 <p class="first admonition-title">Note</p>
1289 <p class="last">Please refer to SoC Technical Reference Manual and
1290 <a class="reference external" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500e/CACJFAJC.html">ARM Technical Reference</a>
1291 for information on sequencing required for startup and shutdown of CPUs in a cluster.
1292 Applying these flags to any CPU in a cluster affects the corresponding cluster.</p>
1293 </div>
1294 <ul class="simple">
1295 <li>status_flags_1 Fields</li>
1296 </ul>
1297 <table border="1" class="docutils">
1298 <colgroup>
1299 <col width="19%" />
1300 <col width="16%" />
1301 <col width="65%" />
1302 </colgroup>
1303 <thead valign="bottom">
1304 <tr class="row-odd"><th class="head">Flag Name</th>
1305 <th class="head">Bit Offset</th>
1306 <th class="head">Description</th>
1307 </tr>
1308 </thead>
1309 <tbody valign="top">
1310 <tr class="row-even"><td>WFE</td>
1311 <td>0</td>
1312 <td>Set if the core is in WFE state</td>
1313 </tr>
1314 <tr class="row-odd"><td>WFI</td>
1315 <td>1</td>
1316 <td>Set if the core is in WFI state</td>
1317 </tr>
1318 <tr class="row-even"><td>L2FLUSH_DONE</td>
1319 <td>4</td>
1320 <td>Set if the cluster’s L2 flush done is complete</td>
1321 </tr>
1322 <tr class="row-odd"><td>STANDBYWFIL2</td>
1323 <td>5</td>
1324 <td>Set if the cluster’s L2 WFI is achieved</td>
1325 </tr>
1326 </tbody>
1327 </table>
1328 </div>
1329 <div class="section" id="arm-r5">
1330 <h4>ARM R5<a class="headerlink" href="#arm-r5" title="Permalink to this headline">¶</a></h4>
1331 <ul class="simple">
1332 <li>config_flags_1 Fields</li>
1333 </ul>
1334 <table border="1" class="docutils">
1335 <colgroup>
1336 <col width="10%" />
1337 <col width="9%" />
1338 <col width="81%" />
1339 </colgroup>
1340 <thead valign="bottom">
1341 <tr class="row-odd"><th class="head">Flag Name</th>
1342 <th class="head">Bit Offset</th>
1343 <th class="head">Description</th>
1344 </tr>
1345 </thead>
1346 <tbody valign="top">
1347 <tr class="row-even"><td>DBG_EN</td>
1348 <td>0</td>
1349 <td>invasive Debug</td>
1350 </tr>
1351 <tr class="row-odd"><td>DBG_NIDEN</td>
1352 <td>1</td>
1353 <td>Non-invasive Debug</td>
1354 </tr>
1355 <tr class="row-even"><td>LOCKSTEP</td>
1356 <td>8</td>
1357 <td>On Write - Enable Lockstep (if permitted) - (1: Lockstep enabled, 0 - Lockstep disabled).
1358 On Read - Core Status - (1: Core in lockstep mode, 0 - Core in split mode)</td>
1359 </tr>
1360 <tr class="row-odd"><td>TE_INIT</td>
1361 <td>9</td>
1362 <td>Exception handling state at reset (0 - ARM, 1 - Thumb)</td>
1363 </tr>
1364 <tr class="row-even"><td>NMFI_EN</td>
1365 <td>10</td>
1366 <td>Enable Core Non-Maskable Fast Interrupts</td>
1367 </tr>
1368 <tr class="row-odd"><td>TCM_RSTBASE</td>
1369 <td>11</td>
1370 <td>Core A/BTCM Reset Base address Indicator (0 - BTCM located at address 0x0, 1 - ATCM located at address 0x0)</td>
1371 </tr>
1372 <tr class="row-even"><td>BTCM_EN</td>
1373 <td>12</td>
1374 <td>Enable Core BTCM RAM at reset</td>
1375 </tr>
1376 <tr class="row-odd"><td>ATCM_EN</td>
1377 <td>13</td>
1378 <td>Enable Core ATCM RAM at reset</td>
1379 </tr>
1380 <tr class="row-even"><td>MEM_INIT_DIS</td>
1381 <td>14</td>
1382 <td>Disables SRAM initialization (TCM, etc) at reset.
1383 (Not available on all devices. Please read TRM before trying to set this field.)
1384 (TRM Section to be referred to is: Chapter 5 (“Device Configuration”) ->
1385 Section 5.1 (“5.1 Control Module (CTRL_MMR)”) -> CTRLMMR_SEC_CLSTRx_CFG Register)</td>
1386 </tr>
1387 <tr class="row-odd"><td>SINGLE_CORE</td>
1388 <td>15</td>
1389 <td>Single / Dual CPU Mode CLSTR_CFG Value 0 = Both CPUs are enabled, 1 = CPU1 Core is disabled
1390 (Not available on all devices. Please read TRM before trying to set this field.)
1391 (TRM Section to be referred to is: Chapter 5 (“Device Configuration”) ->
1392 Section 5.1 (“5.1 Control Module (CTRL_MMR)”) -> CTRLMMR_SEC_CLSTRx_CFG Register)</td>
1393 </tr>
1394 </tbody>
1395 </table>
1396 <ul class="simple">
1397 <li>control_flags_1 Fields</li>
1398 </ul>
1399 <table border="1" class="docutils">
1400 <colgroup>
1401 <col width="8%" />
1402 <col width="9%" />
1403 <col width="83%" />
1404 </colgroup>
1405 <thead valign="bottom">
1406 <tr class="row-odd"><th class="head">Flag Name</th>
1407 <th class="head">Bit Offset</th>
1408 <th class="head">Description</th>
1409 </tr>
1410 </thead>
1411 <tbody valign="top">
1412 <tr class="row-even"><td>CORE_HALT</td>
1413 <td>0</td>
1414 <td>Halt Core</td>
1415 </tr>
1416 <tr class="row-odd"><td>R5_LPSC</td>
1417 <td>1</td>
1418 <td>Command for R5F LPSC Control (1 - LPSC ON, 0 - LPSC OFF)
1419 Reads will always return 0. You are expected to read the PM status via the PM message TISCI_MSG_GET_DEVICE
1420 This particular control is applicable only for J721E and J7200 devices (MCU_R5 only). This is done because
1421 the MCU R5F is running PM and RM and the MCU R5F cannot control its owner power down and power up.</td>
1422 </tr>
1423 <tr class="row-even"><td>R5 RESET</td>
1424 <td>2</td>
1425 <td>R5F Reset control command (1- Assert Reset, 0 - Deassert Reset)
1426 This particular control is applicable only for J721E and J7200 devices (MCU_R5 only). This is done because
1427 the MCU R5F is running PM and RM and the MCU R5F cannot control its owner power down and power up.</td>
1428 </tr>
1429 </tbody>
1430 </table>
1431 <p>The usage of R5_LPSC and R5_RESET is only for the MCU R5F. On the J721E and
1432 J7200 family of devices the RM and PM functions run on the MCU R5F. The MCU
1433 R5F cannot turn off and on its own self during a re-boot sequence which
1434 requires the following fundamental sequence of steps:</p>
1435 <ol class="arabic simple">
1436 <li>Wait for the R5F to hit WFI. (MCU at this point is running WFI and cannot run
1437 steps 2 and 3)</li>
1438 <li>Power off the R5F by writing to PSC registers.</li>
1439 <li>Power on the R5F by writing to PSC registers.</li>
1440 </ol>
1441 <p>In order to handle this the TIFS provides a special function for handling the LPSC
1442 control only for MCU R5F core 0 and core 1 which can enable performing the sequence
1443 of powering down and powering up the MCU R5Fs once the MCU R5F hits WFI.</p>
1444 <p>Similar to the LPSC control for power off and power on, the TIFS also controls the
1445 reset control for R5F LPSC reset controls as the MCU R5F cannot handle its own resets.</p>
1446 <p>For all other devices in the SoC the MCU R5F handles the LPSC configuration. For the
1447 devices like AM6 the TIFS, Power Management and Resource management run on the DMSC.
1448 Hence these controls are not applicable to these devices.</p>
1449 <ul class="simple">
1450 <li>status_flags_1 Fields</li>
1451 </ul>
1452 <table border="1" class="docutils">
1453 <colgroup>
1454 <col width="22%" />
1455 <col width="13%" />
1456 <col width="65%" />
1457 </colgroup>
1458 <thead valign="bottom">
1459 <tr class="row-odd"><th class="head">Flag Name</th>
1460 <th class="head">Bit Offset</th>
1461 <th class="head">Description</th>
1462 </tr>
1463 </thead>
1464 <tbody valign="top">
1465 <tr class="row-even"><td>WFE</td>
1466 <td>0</td>
1467 <td>Set if the core is in WFE state</td>
1468 </tr>
1469 <tr class="row-odd"><td>WFI</td>
1470 <td>1</td>
1471 <td>Set if the core is in WFI state</td>
1472 </tr>
1473 <tr class="row-even"><td>CLK_GATED</td>
1474 <td>2</td>
1475 <td>Core Clock Stopped due to WFI or WFE state</td>
1476 </tr>
1477 <tr class="row-odd"><td>LOCKSTEP_PERMITTED</td>
1478 <td>8</td>
1479 <td>Is Lockstep configuration permitted - 1: yes, 0 - no</td>
1480 </tr>
1481 <tr class="row-even"><td>SINGLECORE_ONLY</td>
1482 <td>9</td>
1483 <td>Is Single Core only configuration enabled - 1: yes, 0 - no</td>
1484 </tr>
1485 </tbody>
1486 </table>
1487 </div>
1488 <div class="section" id="c7x-dsp">
1489 <h4>C7x DSP<a class="headerlink" href="#c7x-dsp" title="Permalink to this headline">¶</a></h4>
1490 <ul class="simple">
1491 <li>config_flags_1 Fields</li>
1492 </ul>
1493 <table border="1" class="docutils">
1494 <colgroup>
1495 <col width="25%" />
1496 <col width="11%" />
1497 <col width="64%" />
1498 </colgroup>
1499 <thead valign="bottom">
1500 <tr class="row-odd"><th class="head">Flag Name</th>
1501 <th class="head">Bit Offset</th>
1502 <th class="head">Description</th>
1503 </tr>
1504 </thead>
1505 <tbody valign="top">
1506 <tr class="row-even"><td>L2_PIPELINE_LATENCY_VALUE</td>
1507 <td>0-3</td>
1508 <td>Set C7x Corepac L2 Pipeline latency. valid values: 1 to 5</td>
1509 </tr>
1510 <tr class="row-odd"><td>L2_ACCESS_LATENCY_VALUE</td>
1511 <td>4-7</td>
1512 <td>Set C7x Corepac L2 Access latency. valid values: 2 to 5</td>
1513 </tr>
1514 </tbody>
1515 </table>
1516 <ul class="simple">
1517 <li>control_flags_1 Fields</li>
1518 </ul>
1519 <p><strong>Not supported.</strong></p>
1520 <ul class="simple">
1521 <li>status_flags_1 Fields</li>
1522 </ul>
1523 <p><strong>Not supported.</strong></p>
1524 </div>
1525 <div class="section" id="c6x-dsp">
1526 <h4>C6x DSP<a class="headerlink" href="#c6x-dsp" title="Permalink to this headline">¶</a></h4>
1527 <ul class="simple">
1528 <li>config_flags_1 Fields</li>
1529 </ul>
1530 <table border="1" class="docutils">
1531 <colgroup>
1532 <col width="28%" />
1533 <col width="11%" />
1534 <col width="61%" />
1535 </colgroup>
1536 <thead valign="bottom">
1537 <tr class="row-odd"><th class="head">Flag Name</th>
1538 <th class="head">Bit Offset</th>
1539 <th class="head">Description</th>
1540 </tr>
1541 </thead>
1542 <tbody valign="top">
1543 <tr class="row-even"><td>SSCLK_MODE_DIV_CLK_MODE_VALUE</td>
1544 <td>0-2</td>
1545 <td>Controls the C66 clock rate for cluster logic and bus interfaces.
1546 (See warning note below)
1547 0x1 - Div2 clock mode.
1548 0x2 - Div3 clock mode.
1549 0x3 - Div4 clock mode.</td>
1550 </tr>
1551 </tbody>
1552 </table>
1553 <div class="admonition warning">
1554 <p class="first admonition-title">Warning</p>
1555 <p class="last">NOTE: Values of SSCLK_MODE_DIV_CLK_MODE_VALUE are TRM value + 1 for
1556 avoiding ‘0’ as a valid value which cannot be distinguished from values
1557 we are not attempting to set</p>
1558 </div>
1559 <ul class="simple">
1560 <li>control_flags_1 Fields</li>
1561 </ul>
1562 <p><strong>Not supported.</strong></p>
1563 <ul class="simple">
1564 <li>status_flags_1 Fields</li>
1565 </ul>
1566 <p><strong>Not supported.</strong></p>
1567 </div>
1568 <div class="section" id="arm-m4f">
1569 <h4>ARM M4F<a class="headerlink" href="#arm-m4f" title="Permalink to this headline">¶</a></h4>
1570 <div class="admonition warning">
1571 <p class="first admonition-title">Warning</p>
1572 <p class="last">NOTE: M4F always starts from 0x0 from internal TCM RAM. There is no
1573 specific bootvector configuration possible. We need to request the
1574 device with reset enabled and load the TCM RAM prior to releasing
1575 the reset to allow the processor to execute.</p>
1576 </div>
1577 <ul class="simple">
1578 <li>config_flags_1 Fields</li>
1579 </ul>
1580 <table border="1" class="docutils">
1581 <colgroup>
1582 <col width="10%" />
1583 <col width="9%" />
1584 <col width="81%" />
1585 </colgroup>
1586 <thead valign="bottom">
1587 <tr class="row-odd"><th class="head">Flag Name</th>
1588 <th class="head">Bit Offset</th>
1589 <th class="head">Description</th>
1590 </tr>
1591 </thead>
1592 <tbody valign="top">
1593 <tr class="row-even"><td>DBG_EN</td>
1594 <td>0</td>
1595 <td>invasive Debug</td>
1596 </tr>
1597 <tr class="row-odd"><td>DBG_NIDEN</td>
1598 <td>1</td>
1599 <td>Non-invasive Debug</td>
1600 </tr>
1601 </tbody>
1602 </table>
1603 <ul class="simple">
1604 <li>control_flags_1 Fields</li>
1605 </ul>
1606 <p><strong>Not supported.</strong></p>
1607 <ul class="simple">
1608 <li>status_flags_1 Fields</li>
1609 </ul>
1610 <table border="1" class="docutils">
1611 <colgroup>
1612 <col width="23%" />
1613 <col width="14%" />
1614 <col width="63%" />
1615 </colgroup>
1616 <thead valign="bottom">
1617 <tr class="row-odd"><th class="head">Flag Name</th>
1618 <th class="head">Bit Offset</th>
1619 <th class="head">Description</th>
1620 </tr>
1621 </thead>
1622 <tbody valign="top">
1623 <tr class="row-even"><td>WFI</td>
1624 <td>1</td>
1625 <td>Set if the core is in WFI state</td>
1626 </tr>
1627 </tbody>
1628 </table>
1629 </div>
1630 </div>
1631 </div>
1632 </div>
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1679 };
1680 </script>
1681 <script type="text/javascript" src="../../_static/jquery.js"></script>
1682 <script type="text/javascript" src="../../_static/underscore.js"></script>
1683 <script type="text/javascript" src="../../_static/doctools.js"></script>
1684 <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.1/MathJax.js?config=TeX-AMS-MML_HTMLorMML"></script>
1686 <script src="http://www.ti.com/assets/js/headerfooter/analytics.js" type="text/javascript" charset="utf-8"></script>
1692 <script type="text/javascript" src="../../_static/js/theme.js"></script>
1697 <script type="text/javascript">
1698 jQuery(function () {
1699 SphinxRtdTheme.StickyNav.enable();
1700 });
1702 var menuHeight = window.innerHeight;
1704 var contentOffset = $(".wy-nav-content-wrap").offset();
1705 var contentHeight = $(".wy-nav-content-wrap").height();
1706 var contentBottom = contentOffset.top + contentHeight;
1708 function setNavbarTop() {
1709 var scrollTop = $(window).scrollTop();
1710 var maxTop = scrollTop + menuHeight;
1712 // If past the header
1713 if (scrollTop > contentOffset.top && maxTop < contentBottom) {
1714 stickyTop = scrollTop - contentOffset.top;
1715 } else if (maxTop > contentBottom) {
1716 stickyTop = scrollTop - contentOffset.top - (maxTop - contentBottom);
1717 } else {
1718 stickyTop = 0;
1719 }
1721 $(".wy-nav-side").css("top", stickyTop);
1722 }
1724 $(document).ready(function() {
1725 setNavbarTop();
1726 $(window).scroll(function () {
1727 setNavbarTop();
1728 });
1730 $('body').on("mousewheel", function () {
1731 // Remove default behavior
1732 event.preventDefault();
1733 // Scroll without smoothing
1734 var wheelDelta = event.wheelDelta;
1735 var currentScrollPosition = window.pageYOffset;
1736 window.scrollTo(0, currentScrollPosition - wheelDelta);
1737 });
1738 });
1739 </script>
1742 </body>
1743 </html>